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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / nas_car / nas_core.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: nas_core.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef CORE_0
36
37module nas_core0 (
38
39 cid
40);
41
42input [2:0] cid;
43
44integer i;
45
46//----------------------------------------------------------
47
48//----------------------------------------------------------
49
50//----------------------------------------------------------
51//
52// THREAD 0
53//
54
55 nas_pipe0 t0 (
56 .mycid (cid),
57 .mytid (3'h0),
58
59// If GATESIM, instantiate "dummy" module with floating ports since unused.
60`ifdef GATESIM
61 .opcode () // this and all other ports are unconnected
62`else
63 .opcode ({`PROBES0.op_0_w}),
64 .PC_reg ({`PROBES0.pc_0_w}),
65 .Y_reg (`SPC0.exu0.rml.arch_yreg_tid0_ff),
66 .CCR_reg (`SPC0.exu0.ect.arch_ccr_tid0_lth),
67 .FPRS_reg (`SPC0.fgu.fac.fprs_tid0),
68 .FSR_reg (`SPC0.fgu.fad.fsr0_fx1[27:0]),
69 .ASI_reg (`SPC0.lsu.dcs.asi_state0),
70 .GSR_reg ({`SPC0.fgu.fgd.gsr0_mask_fx4[31:0], `SPC0.fgu.fpc.gsr0_11bits_fx4[10:0]}),
71 .TICK_CMPR_reg (`PROBES0.tick_cmpr_0),
72 .STICK_CMPR_reg (`PROBES0.stick_cmpr_0),
73 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_0),
74 .PSTATE_reg (`SPC0.tlu.tsd0.arch_pstate0),
75 .TL_reg (`SPC0.tlu.trl0.tl0),
76 .PIL_reg (`SPC0.tlu.trl0.pil0),
77 .TBA_reg (`SPC0.tlu.tsd0.tba0[47:15]),
78 .VER_reg (`SPC0.tlu.asi.hver_value), // static
79 .CWP_reg (`SPC0.exu0.rml.cwp_thr0),
80 .CANSAVE_reg (`SPC0.exu0.rml.cansave_thr0),
81 .CANRESTORE_reg (`SPC0.exu0.rml.canrestore_thr0),
82 .OTHERWIN_reg (`SPC0.exu0.rml.otherwin_thr0),
83 .WSTATE_reg (`SPC0.exu0.rml.wstate_thr0),
84 .CLEANWIN_reg (`SPC0.exu0.rml.cleanwin_thr0),
85 .rd_SOFTINT_reg (`SPC0.tlu.trl0.rd_softint0),
86 .SOFTINT_reg (`SPC0.tlu.trl0.softint0),
87 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec0),
88 .GL_reg (`SPC0.tlu.tlu_gl0),
89 .HPSTATE_reg (`SPC0.tlu.tsd0.arch_hpstate0),
90 .HTBA_reg (`SPC0.tlu.tsd0.htba0[47:14]),
91 .HINTP_reg (`SPC0.tlu.trl0.hintp0),
92
93 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_0[12:0]}),
94 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_0[12:0]}),
95 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_0[12:0]}),
96 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_0[12:0]}),
97 .LSU_CONTROL_reg ({29'd0,
98 `SPC0.lsu.dcs.wpt_mode_0[1:0],
99 `SPC0.lsu.dcs.wpt_mask_0[7:0],
100 `SPC0.lsu.dcs.wpt_enable_0[1:0],
101 18'd0,
102 `SPC0.lsu.dcs.spec_enable[0],
103 `SPC0.lsu.dcs.dmmu_enable[0],
104 `SPC0.lsu.dcs.immu_enable[0],
105 `SPC0.lsu.dcs.dc_enable[0],
106 `SPC0.lsu.dcs.ic_enable[0]}),
107 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.immu_tag_access_0[47:0]}),
108 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.dmmu_tag_access_0[47:0]}),
109 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint0[47:3],3'b00}),
110 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_0[47:0]),
111
112 .Trap_Entry_1 (`PROBES0.trap_entry_1_t0),
113 .Trap_Entry_2 (`PROBES0.trap_entry_2_t0),
114 .Trap_Entry_3 (`PROBES0.trap_entry_3_t0),
115 .Trap_Entry_4 (`PROBES0.trap_entry_4_t0),
116 .Trap_Entry_5 (`PROBES0.trap_entry_5_t0),
117 .Trap_Entry_6 (`PROBES0.trap_entry_6_t0),
118
119 .exu_valid (`PROBES0.ex_valid[0]),
120
121 .imul_valid (`PROBES0.imul_valid[0]),
122
123 .fp_valid (`PROBES0.fg_valid[0]),
124 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
125 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
126 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
127
128 .idiv_valid (`PROBES0.fgu_idiv_valid[0]),
129
130 .fdiv_valid (`PROBES0.fgu_fdiv_valid[0]),
131
132 .lsu_valid (`PROBES0.lsu_valid[0]),
133 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
134 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
135 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
136
137 .asi_valid (`PROBES0.asi_valid_fx5[0]),
138 .asi_in_progress (`PROBES0.asi_in_progress_fx4[0]),
139
140 .tlu_valid (`PROBES0.tlu_valid[0])
141`endif
142 );
143
144
145//----------------------------------------------------------
146//
147// THREAD 1
148//
149
150 nas_pipe0 t1 (
151 .mycid (cid),
152 .mytid (3'h1),
153
154// If GATESIM, instantiate "dummy" module with floating ports since unused.
155`ifdef GATESIM
156 .opcode () // this and all other ports are unconnected
157`else
158 .opcode ({`PROBES0.op_1_w}),
159 .PC_reg ({`PROBES0.pc_1_w}),
160 .Y_reg (`SPC0.exu0.rml.arch_yreg_tid1_ff),
161 .CCR_reg (`SPC0.exu0.ect.arch_ccr_tid1_lth),
162 .FPRS_reg (`SPC0.fgu.fac.fprs_tid1),
163 .FSR_reg (`SPC0.fgu.fad.fsr1_fx1[27:0]),
164 .ASI_reg (`SPC0.lsu.dcs.asi_state1),
165 .GSR_reg ({`SPC0.fgu.fgd.gsr1_mask_fx4[31:0], `SPC0.fgu.fpc.gsr1_11bits_fx4[10:0]}),
166 .TICK_CMPR_reg (`PROBES0.tick_cmpr_1),
167 .STICK_CMPR_reg (`PROBES0.stick_cmpr_1),
168 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_1),
169 .PSTATE_reg (`SPC0.tlu.tsd0.arch_pstate1),
170 .TL_reg (`SPC0.tlu.trl0.tl1),
171 .PIL_reg (`SPC0.tlu.trl0.pil1),
172 .TBA_reg (`SPC0.tlu.tsd0.tba1[47:15]),
173 .VER_reg (`SPC0.tlu.asi.hver_value), // static
174 .CWP_reg (`SPC0.exu0.rml.cwp_thr1),
175 .CANSAVE_reg (`SPC0.exu0.rml.cansave_thr1),
176 .CANRESTORE_reg (`SPC0.exu0.rml.canrestore_thr1),
177 .OTHERWIN_reg (`SPC0.exu0.rml.otherwin_thr1),
178 .WSTATE_reg (`SPC0.exu0.rml.wstate_thr1),
179 .CLEANWIN_reg (`SPC0.exu0.rml.cleanwin_thr1),
180 .rd_SOFTINT_reg (`SPC0.tlu.trl0.rd_softint1),
181 .SOFTINT_reg (`SPC0.tlu.trl0.softint1),
182 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec1),
183 .GL_reg (`SPC0.tlu.tlu_gl1),
184 .HPSTATE_reg (`SPC0.tlu.tsd0.arch_hpstate1),
185 .HTBA_reg (`SPC0.tlu.tsd0.htba1[47:14]),
186 .HINTP_reg (`SPC0.tlu.trl0.hintp1),
187
188 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_1[12:0]}),
189 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_1[12:0]}),
190 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_1[12:0]}),
191 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_1[12:0]}),
192 .LSU_CONTROL_reg ({29'd0,
193 `SPC0.lsu.dcs.wpt_mode_1[1:0],
194 `SPC0.lsu.dcs.wpt_mask_1[7:0],
195 `SPC0.lsu.dcs.wpt_enable_1[1:0],
196 18'd0,
197 `SPC0.lsu.dcs.spec_enable[1],
198 `SPC0.lsu.dcs.dmmu_enable[1],
199 `SPC0.lsu.dcs.immu_enable[1],
200 `SPC0.lsu.dcs.dc_enable[1],
201 `SPC0.lsu.dcs.ic_enable[1]}),
202 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.immu_tag_access_1[47:0]}),
203 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.dmmu_tag_access_1[47:0]}),
204 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint1[47:3],3'b00}),
205 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_1[47:0]),
206
207 .Trap_Entry_1 (`PROBES0.trap_entry_1_t1),
208 .Trap_Entry_2 (`PROBES0.trap_entry_2_t1),
209 .Trap_Entry_3 (`PROBES0.trap_entry_3_t1),
210 .Trap_Entry_4 (`PROBES0.trap_entry_4_t1),
211 .Trap_Entry_5 (`PROBES0.trap_entry_5_t1),
212 .Trap_Entry_6 (`PROBES0.trap_entry_6_t1),
213
214 .exu_valid (`PROBES0.ex_valid[1]),
215
216 .imul_valid (`PROBES0.imul_valid[1]),
217
218 .fp_valid (`PROBES0.fg_valid[1]),
219 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
220 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
221 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
222
223 .idiv_valid (`PROBES0.fgu_idiv_valid[1]),
224
225 .fdiv_valid (`PROBES0.fgu_fdiv_valid[1]),
226
227 .lsu_valid (`PROBES0.lsu_valid[1]),
228 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
229 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
230 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
231
232 .asi_valid (`PROBES0.asi_valid_fx5[1]),
233 .asi_in_progress (`PROBES0.asi_in_progress_fx4[1]),
234
235 .tlu_valid (`PROBES0.tlu_valid[1])
236`endif
237 );
238
239
240//----------------------------------------------------------
241//
242// THREAD 2
243//
244
245 nas_pipe0 t2 (
246 .mycid (cid),
247 .mytid (3'h2),
248
249// If GATESIM, instantiate "dummy" module with floating ports since unused.
250`ifdef GATESIM
251 .opcode () // this and all other ports are unconnected
252`else
253 .opcode ({`PROBES0.op_2_w}),
254 .PC_reg ({`PROBES0.pc_2_w}),
255 .Y_reg (`SPC0.exu0.rml.arch_yreg_tid2_ff),
256 .CCR_reg (`SPC0.exu0.ect.arch_ccr_tid2_lth),
257 .FPRS_reg (`SPC0.fgu.fac.fprs_tid2),
258 .FSR_reg (`SPC0.fgu.fad.fsr2_fx1[27:0]),
259 .ASI_reg (`SPC0.lsu.dcs.asi_state2),
260 .GSR_reg ({`SPC0.fgu.fgd.gsr2_mask_fx4[31:0], `SPC0.fgu.fpc.gsr2_11bits_fx4[10:0]}),
261 .TICK_CMPR_reg (`PROBES0.tick_cmpr_2),
262 .STICK_CMPR_reg (`PROBES0.stick_cmpr_2),
263 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_2),
264 .PSTATE_reg (`SPC0.tlu.tsd0.arch_pstate2),
265 .TL_reg (`SPC0.tlu.trl0.tl2),
266 .PIL_reg (`SPC0.tlu.trl0.pil2),
267 .TBA_reg (`SPC0.tlu.tsd0.tba2[47:15]),
268 .VER_reg (`SPC0.tlu.asi.hver_value), // static
269 .CWP_reg (`SPC0.exu0.rml.cwp_thr2),
270 .CANSAVE_reg (`SPC0.exu0.rml.cansave_thr2),
271 .CANRESTORE_reg (`SPC0.exu0.rml.canrestore_thr2),
272 .OTHERWIN_reg (`SPC0.exu0.rml.otherwin_thr2),
273 .WSTATE_reg (`SPC0.exu0.rml.wstate_thr2),
274 .CLEANWIN_reg (`SPC0.exu0.rml.cleanwin_thr2),
275 .rd_SOFTINT_reg (`SPC0.tlu.trl0.rd_softint2),
276 .SOFTINT_reg (`SPC0.tlu.trl0.softint2),
277 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec2),
278 .GL_reg (`SPC0.tlu.tlu_gl2),
279 .HPSTATE_reg (`SPC0.tlu.tsd0.arch_hpstate2),
280 .HTBA_reg (`SPC0.tlu.tsd0.htba2[47:14]),
281 .HINTP_reg (`SPC0.tlu.trl0.hintp2),
282
283 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_2[12:0]}),
284 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_2[12:0]}),
285 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_2[12:0]}),
286 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_2[12:0]}),
287 .LSU_CONTROL_reg ({29'd0,
288 `SPC0.lsu.dcs.wpt_mode_2[1:0],
289 `SPC0.lsu.dcs.wpt_mask_2[7:0],
290 `SPC0.lsu.dcs.wpt_enable_2[1:0],
291 18'd0,
292 `SPC0.lsu.dcs.spec_enable[2],
293 `SPC0.lsu.dcs.dmmu_enable[2],
294 `SPC0.lsu.dcs.immu_enable[2],
295 `SPC0.lsu.dcs.dc_enable[2],
296 `SPC0.lsu.dcs.ic_enable[2]}),
297 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.immu_tag_access_2[47:0]}),
298 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.dmmu_tag_access_2[47:0]}),
299 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint2[47:3],3'b00}),
300 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_2[47:0]),
301
302 .Trap_Entry_1 (`PROBES0.trap_entry_1_t2),
303 .Trap_Entry_2 (`PROBES0.trap_entry_2_t2),
304 .Trap_Entry_3 (`PROBES0.trap_entry_3_t2),
305 .Trap_Entry_4 (`PROBES0.trap_entry_4_t2),
306 .Trap_Entry_5 (`PROBES0.trap_entry_5_t2),
307 .Trap_Entry_6 (`PROBES0.trap_entry_6_t2),
308
309 .exu_valid (`PROBES0.ex_valid[2]),
310
311 .imul_valid (`PROBES0.imul_valid[2]),
312
313 .fp_valid (`PROBES0.fg_valid[2]),
314 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
315 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
316 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
317
318 .idiv_valid (`PROBES0.fgu_idiv_valid[2]),
319
320 .fdiv_valid (`PROBES0.fgu_fdiv_valid[2]),
321
322 .lsu_valid (`PROBES0.lsu_valid[2]),
323 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
324 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
325 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
326
327 .asi_valid (`PROBES0.asi_valid_fx5[2]),
328 .asi_in_progress (`PROBES0.asi_in_progress_fx4[2]),
329
330 .tlu_valid (`PROBES0.tlu_valid[2])
331`endif
332 );
333
334
335//----------------------------------------------------------
336//
337// THREAD 3
338//
339
340 nas_pipe0 t3 (
341 .mycid (cid),
342 .mytid (3'h3),
343
344// If GATESIM, instantiate "dummy" module with floating ports since unused.
345`ifdef GATESIM
346 .opcode () // this and all other ports are unconnected
347`else
348 .opcode ({`PROBES0.op_3_w}),
349 .PC_reg ({`PROBES0.pc_3_w}),
350 .Y_reg (`SPC0.exu0.rml.arch_yreg_tid3_ff),
351 .CCR_reg (`SPC0.exu0.ect.arch_ccr_tid3_lth),
352 .FPRS_reg (`SPC0.fgu.fac.fprs_tid3),
353 .FSR_reg (`SPC0.fgu.fad.fsr3_fx1[27:0]),
354 .ASI_reg (`SPC0.lsu.dcs.asi_state3),
355 .GSR_reg ({`SPC0.fgu.fgd.gsr3_mask_fx4[31:0], `SPC0.fgu.fpc.gsr3_11bits_fx4[10:0]}),
356 .TICK_CMPR_reg (`PROBES0.tick_cmpr_3),
357 .STICK_CMPR_reg (`PROBES0.stick_cmpr_3),
358 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_3),
359 .PSTATE_reg (`SPC0.tlu.tsd0.arch_pstate3),
360 .TL_reg (`SPC0.tlu.trl0.tl3),
361 .PIL_reg (`SPC0.tlu.trl0.pil3),
362 .TBA_reg (`SPC0.tlu.tsd0.tba3[47:15]),
363 .VER_reg (`SPC0.tlu.asi.hver_value), // static
364 .CWP_reg (`SPC0.exu0.rml.cwp_thr3),
365 .CANSAVE_reg (`SPC0.exu0.rml.cansave_thr3),
366 .CANRESTORE_reg (`SPC0.exu0.rml.canrestore_thr3),
367 .OTHERWIN_reg (`SPC0.exu0.rml.otherwin_thr3),
368 .WSTATE_reg (`SPC0.exu0.rml.wstate_thr3),
369 .CLEANWIN_reg (`SPC0.exu0.rml.cleanwin_thr3),
370 .rd_SOFTINT_reg (`SPC0.tlu.trl0.rd_softint3),
371 .SOFTINT_reg (`SPC0.tlu.trl0.softint3),
372 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec3),
373 .GL_reg (`SPC0.tlu.tlu_gl3),
374 .HPSTATE_reg (`SPC0.tlu.tsd0.arch_hpstate3),
375 .HTBA_reg (`SPC0.tlu.tsd0.htba3[47:14]),
376 .HINTP_reg (`SPC0.tlu.trl0.hintp3),
377
378 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_3[12:0]}),
379 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_3[12:0]}),
380 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_3[12:0]}),
381 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_3[12:0]}),
382 .LSU_CONTROL_reg ({29'd0,
383 `SPC0.lsu.dcs.wpt_mode_3[1:0],
384 `SPC0.lsu.dcs.wpt_mask_3[7:0],
385 `SPC0.lsu.dcs.wpt_enable_3[1:0],
386 18'd0,
387 `SPC0.lsu.dcs.spec_enable[3],
388 `SPC0.lsu.dcs.dmmu_enable[3],
389 `SPC0.lsu.dcs.immu_enable[3],
390 `SPC0.lsu.dcs.dc_enable[3],
391 `SPC0.lsu.dcs.ic_enable[3]}),
392 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.immu_tag_access_3[47:0]}),
393 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd0.dmmu_tag_access_3[47:0]}),
394 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint3[47:3],3'b00}),
395 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_3[47:0]),
396
397 .Trap_Entry_1 (`PROBES0.trap_entry_1_t3),
398 .Trap_Entry_2 (`PROBES0.trap_entry_2_t3),
399 .Trap_Entry_3 (`PROBES0.trap_entry_3_t3),
400 .Trap_Entry_4 (`PROBES0.trap_entry_4_t3),
401 .Trap_Entry_5 (`PROBES0.trap_entry_5_t3),
402 .Trap_Entry_6 (`PROBES0.trap_entry_6_t3),
403
404 .exu_valid (`PROBES0.ex_valid[3]),
405
406 .imul_valid (`PROBES0.imul_valid[3]),
407
408 .fp_valid (`PROBES0.fg_valid[3]),
409 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
410 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
411 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
412
413 .idiv_valid (`PROBES0.fgu_idiv_valid[3]),
414
415 .fdiv_valid (`PROBES0.fgu_fdiv_valid[3]),
416
417 .lsu_valid (`PROBES0.lsu_valid[3]),
418 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
419 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
420 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
421
422 .asi_valid (`PROBES0.asi_valid_fx5[3]),
423 .asi_in_progress (`PROBES0.asi_in_progress_fx4[3]),
424
425 .tlu_valid (`PROBES0.tlu_valid[3])
426`endif
427 );
428
429
430//----------------------------------------------------------
431//
432// THREAD 4
433//
434
435 nas_pipe0 t4 (
436 .mycid (cid),
437 .mytid (3'h4),
438
439// If GATESIM, instantiate "dummy" module with floating ports since unused.
440`ifdef GATESIM
441 .opcode () // this and all other ports are unconnected
442`else
443 .opcode ({`PROBES0.op_4_w}),
444 .PC_reg ({`PROBES0.pc_4_w}),
445 .Y_reg (`SPC0.exu1.rml.arch_yreg_tid0_ff),
446 .CCR_reg (`SPC0.exu1.ect.arch_ccr_tid0_lth),
447 .FPRS_reg (`SPC0.fgu.fac.fprs_tid4),
448 .FSR_reg (`SPC0.fgu.fad.fsr4_fx1[27:0]),
449 .ASI_reg (`SPC0.lsu.dcs.asi_state4),
450 .GSR_reg ({`SPC0.fgu.fgd.gsr4_mask_fx4[31:0], `SPC0.fgu.fpc.gsr4_11bits_fx4[10:0]}),
451 .TICK_CMPR_reg (`PROBES0.tick_cmpr_4),
452 .STICK_CMPR_reg (`PROBES0.stick_cmpr_4),
453 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_4),
454 .PSTATE_reg (`SPC0.tlu.tsd1.arch_pstate0),
455 .TL_reg (`SPC0.tlu.trl1.tl0),
456 .PIL_reg (`SPC0.tlu.trl1.pil0),
457 .TBA_reg (`SPC0.tlu.tsd1.tba0[47:15]),
458 .VER_reg (`SPC0.tlu.asi.hver_value), // static
459 .CWP_reg (`SPC0.exu1.rml.cwp_thr0),
460 .CANSAVE_reg (`SPC0.exu1.rml.cansave_thr0),
461 .CANRESTORE_reg (`SPC0.exu1.rml.canrestore_thr0),
462 .OTHERWIN_reg (`SPC0.exu1.rml.otherwin_thr0),
463 .WSTATE_reg (`SPC0.exu1.rml.wstate_thr0),
464 .CLEANWIN_reg (`SPC0.exu1.rml.cleanwin_thr0),
465 .rd_SOFTINT_reg (`SPC0.tlu.trl1.rd_softint0),
466 .SOFTINT_reg (`SPC0.tlu.trl1.softint0),
467 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec4),
468 .GL_reg (`SPC0.tlu.tlu_gl4),
469 .HPSTATE_reg (`SPC0.tlu.tsd1.arch_hpstate0),
470 .HTBA_reg (`SPC0.tlu.tsd1.htba0[47:14]),
471 .HINTP_reg (`SPC0.tlu.trl1.hintp0),
472
473 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_4[12:0]}),
474 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_4[12:0]}),
475 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_4[12:0]}),
476 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_4[12:0]}),
477 .LSU_CONTROL_reg ({29'd0,
478 `SPC0.lsu.dcs.wpt_mode_4[1:0],
479 `SPC0.lsu.dcs.wpt_mask_4[7:0],
480 `SPC0.lsu.dcs.wpt_enable_4[1:0],
481 18'd0,
482 `SPC0.lsu.dcs.spec_enable[4],
483 `SPC0.lsu.dcs.dmmu_enable[4],
484 `SPC0.lsu.dcs.immu_enable[4],
485 `SPC0.lsu.dcs.dc_enable[4],
486 `SPC0.lsu.dcs.ic_enable[4]}),
487 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.immu_tag_access_0[47:0]}),
488 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.dmmu_tag_access_0[47:0]}),
489 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint4[47:3],3'b00}),
490 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_4[47:0]),
491
492 .Trap_Entry_1 (`PROBES0.trap_entry_1_t4),
493 .Trap_Entry_2 (`PROBES0.trap_entry_2_t4),
494 .Trap_Entry_3 (`PROBES0.trap_entry_3_t4),
495 .Trap_Entry_4 (`PROBES0.trap_entry_4_t4),
496 .Trap_Entry_5 (`PROBES0.trap_entry_5_t4),
497 .Trap_Entry_6 (`PROBES0.trap_entry_6_t4),
498
499 .exu_valid (`PROBES0.ex_valid[4]),
500
501 .imul_valid (`PROBES0.imul_valid[4]),
502
503 .fp_valid (`PROBES0.fg_valid[4]),
504 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
505 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
506 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
507
508 .idiv_valid (`PROBES0.fgu_idiv_valid[4]),
509
510 .fdiv_valid (`PROBES0.fgu_fdiv_valid[4]),
511
512 .lsu_valid (`PROBES0.lsu_valid[4]),
513 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
514 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
515 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
516
517 .asi_valid (`PROBES0.asi_valid_fx5[4]),
518 .asi_in_progress (`PROBES0.asi_in_progress_fx4[4]),
519
520 .tlu_valid (`PROBES0.tlu_valid[4])
521`endif
522 );
523
524
525//----------------------------------------------------------
526//
527// THREAD 5
528//
529
530 nas_pipe0 t5 (
531 .mycid (cid),
532 .mytid (3'h5),
533
534// If GATESIM, instantiate "dummy" module with floating ports since unused.
535`ifdef GATESIM
536 .opcode () // this and all other ports are unconnected
537`else
538 .opcode ({`PROBES0.op_5_w}),
539 .PC_reg ({`PROBES0.pc_5_w}),
540 .Y_reg (`SPC0.exu1.rml.arch_yreg_tid1_ff),
541 .CCR_reg (`SPC0.exu1.ect.arch_ccr_tid1_lth),
542 .FPRS_reg (`SPC0.fgu.fac.fprs_tid5),
543 .FSR_reg (`SPC0.fgu.fad.fsr5_fx1[27:0]),
544 .ASI_reg (`SPC0.lsu.dcs.asi_state5),
545 .GSR_reg ({`SPC0.fgu.fgd.gsr5_mask_fx4[31:0], `SPC0.fgu.fpc.gsr5_11bits_fx4[10:0]}),
546 .TICK_CMPR_reg (`PROBES0.tick_cmpr_5),
547 .STICK_CMPR_reg (`PROBES0.stick_cmpr_5),
548 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_5),
549 .PSTATE_reg (`SPC0.tlu.tsd1.arch_pstate1),
550 .TL_reg (`SPC0.tlu.trl1.tl1),
551 .PIL_reg (`SPC0.tlu.trl1.pil1),
552 .TBA_reg (`SPC0.tlu.tsd1.tba1[47:15]),
553 .VER_reg (`SPC0.tlu.asi.hver_value), // static
554 .CWP_reg (`SPC0.exu1.rml.cwp_thr1),
555 .CANSAVE_reg (`SPC0.exu1.rml.cansave_thr1),
556 .CANRESTORE_reg (`SPC0.exu1.rml.canrestore_thr1),
557 .OTHERWIN_reg (`SPC0.exu1.rml.otherwin_thr1),
558 .WSTATE_reg (`SPC0.exu1.rml.wstate_thr1),
559 .CLEANWIN_reg (`SPC0.exu1.rml.cleanwin_thr1),
560 .rd_SOFTINT_reg (`SPC0.tlu.trl1.rd_softint1),
561 .SOFTINT_reg (`SPC0.tlu.trl1.softint1),
562 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec5),
563 .GL_reg (`SPC0.tlu.tlu_gl5),
564 .HPSTATE_reg (`SPC0.tlu.tsd1.arch_hpstate1),
565 .HTBA_reg (`SPC0.tlu.tsd1.htba1[47:14]),
566 .HINTP_reg (`SPC0.tlu.trl1.hintp1),
567
568 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_5[12:0]}),
569 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_5[12:0]}),
570 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_5[12:0]}),
571 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_5[12:0]}),
572 .LSU_CONTROL_reg ({29'd0,
573 `SPC0.lsu.dcs.wpt_mode_5[1:0],
574 `SPC0.lsu.dcs.wpt_mask_5[7:0],
575 `SPC0.lsu.dcs.wpt_enable_5[1:0],
576 18'd0,
577 `SPC0.lsu.dcs.spec_enable[5],
578 `SPC0.lsu.dcs.dmmu_enable[5],
579 `SPC0.lsu.dcs.immu_enable[5],
580 `SPC0.lsu.dcs.dc_enable[5],
581 `SPC0.lsu.dcs.ic_enable[5]}),
582 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.immu_tag_access_1[47:0]}),
583 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.dmmu_tag_access_1[47:0]}),
584 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint5[47:3],3'b00}),
585 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_5[47:0]),
586
587 .Trap_Entry_1 (`PROBES0.trap_entry_1_t5),
588 .Trap_Entry_2 (`PROBES0.trap_entry_2_t5),
589 .Trap_Entry_3 (`PROBES0.trap_entry_3_t5),
590 .Trap_Entry_4 (`PROBES0.trap_entry_4_t5),
591 .Trap_Entry_5 (`PROBES0.trap_entry_5_t5),
592 .Trap_Entry_6 (`PROBES0.trap_entry_6_t5),
593
594 .exu_valid (`PROBES0.ex_valid[5]),
595
596 .imul_valid (`PROBES0.imul_valid[5]),
597
598 .fp_valid (`PROBES0.fg_valid[5]),
599 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
600 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
601 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
602
603 .idiv_valid (`PROBES0.fgu_idiv_valid[5]),
604
605 .fdiv_valid (`PROBES0.fgu_fdiv_valid[5]),
606
607 .lsu_valid (`PROBES0.lsu_valid[5]),
608 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
609 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
610 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
611
612 .asi_valid (`PROBES0.asi_valid_fx5[5]),
613 .asi_in_progress (`PROBES0.asi_in_progress_fx4[5]),
614
615 .tlu_valid (`PROBES0.tlu_valid[5])
616`endif
617 );
618
619
620//----------------------------------------------------------
621//
622// THREAD 6
623//
624
625 nas_pipe0 t6 (
626 .mycid (cid),
627 .mytid (3'h6),
628
629// If GATESIM, instantiate "dummy" module with floating ports since unused.
630`ifdef GATESIM
631 .opcode () // this and all other ports are unconnected
632`else
633 .opcode ({`PROBES0.op_6_w}),
634 .PC_reg ({`PROBES0.pc_6_w}),
635 .Y_reg (`SPC0.exu1.rml.arch_yreg_tid2_ff),
636 .CCR_reg (`SPC0.exu1.ect.arch_ccr_tid2_lth),
637 .FPRS_reg (`SPC0.fgu.fac.fprs_tid6),
638 .FSR_reg (`SPC0.fgu.fad.fsr6_fx1[27:0]),
639 .ASI_reg (`SPC0.lsu.dcs.asi_state6),
640 .GSR_reg ({`SPC0.fgu.fgd.gsr6_mask_fx4[31:0], `SPC0.fgu.fpc.gsr6_11bits_fx4[10:0]}),
641 .TICK_CMPR_reg (`PROBES0.tick_cmpr_6),
642 .STICK_CMPR_reg (`PROBES0.stick_cmpr_6),
643 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_6),
644 .PSTATE_reg (`SPC0.tlu.tsd1.arch_pstate2),
645 .TL_reg (`SPC0.tlu.trl1.tl2),
646 .PIL_reg (`SPC0.tlu.trl1.pil2),
647 .TBA_reg (`SPC0.tlu.tsd1.tba2[47:15]),
648 .VER_reg (`SPC0.tlu.asi.hver_value), // static
649 .CWP_reg (`SPC0.exu1.rml.cwp_thr2),
650 .CANSAVE_reg (`SPC0.exu1.rml.cansave_thr2),
651 .CANRESTORE_reg (`SPC0.exu1.rml.canrestore_thr2),
652 .OTHERWIN_reg (`SPC0.exu1.rml.otherwin_thr2),
653 .WSTATE_reg (`SPC0.exu1.rml.wstate_thr2),
654 .CLEANWIN_reg (`SPC0.exu1.rml.cleanwin_thr2),
655 .rd_SOFTINT_reg (`SPC0.tlu.trl1.rd_softint2),
656 .SOFTINT_reg (`SPC0.tlu.trl1.softint2),
657 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec6),
658 .GL_reg (`SPC0.tlu.tlu_gl6),
659 .HPSTATE_reg (`SPC0.tlu.tsd1.arch_hpstate2),
660 .HTBA_reg (`SPC0.tlu.tsd1.htba2[47:14]),
661 .HINTP_reg (`SPC0.tlu.trl1.hintp2),
662
663 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_6[12:0]}),
664 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_6[12:0]}),
665 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_6[12:0]}),
666 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_6[12:0]}),
667 .LSU_CONTROL_reg ({29'd0,
668 `SPC0.lsu.dcs.wpt_mode_6[1:0],
669 `SPC0.lsu.dcs.wpt_mask_6[7:0],
670 `SPC0.lsu.dcs.wpt_enable_6[1:0],
671 18'd0,
672 `SPC0.lsu.dcs.spec_enable[6],
673 `SPC0.lsu.dcs.dmmu_enable[6],
674 `SPC0.lsu.dcs.immu_enable[6],
675 `SPC0.lsu.dcs.dc_enable[6],
676 `SPC0.lsu.dcs.ic_enable[6]}),
677 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.immu_tag_access_2[47:0]}),
678 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.dmmu_tag_access_2[47:0]}),
679 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint6[47:3],3'b00}),
680 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_6[47:0]),
681
682 .Trap_Entry_1 (`PROBES0.trap_entry_1_t6),
683 .Trap_Entry_2 (`PROBES0.trap_entry_2_t6),
684 .Trap_Entry_3 (`PROBES0.trap_entry_3_t6),
685 .Trap_Entry_4 (`PROBES0.trap_entry_4_t6),
686 .Trap_Entry_5 (`PROBES0.trap_entry_5_t6),
687 .Trap_Entry_6 (`PROBES0.trap_entry_6_t6),
688
689 .exu_valid (`PROBES0.ex_valid[6]),
690
691 .imul_valid (`PROBES0.imul_valid[6]),
692
693 .fp_valid (`PROBES0.fg_valid[6]),
694 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
695 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
696 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
697
698 .idiv_valid (`PROBES0.fgu_idiv_valid[6]),
699
700 .fdiv_valid (`PROBES0.fgu_fdiv_valid[6]),
701
702 .lsu_valid (`PROBES0.lsu_valid[6]),
703 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
704 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
705 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
706
707 .asi_valid (`PROBES0.asi_valid_fx5[6]),
708 .asi_in_progress (`PROBES0.asi_in_progress_fx4[6]),
709
710 .tlu_valid (`PROBES0.tlu_valid[6])
711`endif
712 );
713
714
715//----------------------------------------------------------
716//
717// THREAD 7
718//
719
720 nas_pipe0 t7 (
721 .mycid (cid),
722 .mytid (3'h7),
723
724// If GATESIM, instantiate "dummy" module with floating ports since unused.
725`ifdef GATESIM
726 .opcode () // this and all other ports are unconnected
727`else
728 .opcode ({`PROBES0.op_7_w}),
729 .PC_reg ({`PROBES0.pc_7_w}),
730 .Y_reg (`SPC0.exu1.rml.arch_yreg_tid3_ff),
731 .CCR_reg (`SPC0.exu1.ect.arch_ccr_tid3_lth),
732 .FPRS_reg (`SPC0.fgu.fac.fprs_tid7),
733 .FSR_reg (`SPC0.fgu.fad.fsr7_fx1[27:0]),
734 .ASI_reg (`SPC0.lsu.dcs.asi_state7),
735 .GSR_reg ({`SPC0.fgu.fgd.gsr7_mask_fx4[31:0], `SPC0.fgu.fpc.gsr7_11bits_fx4[10:0]}),
736 .TICK_CMPR_reg (`PROBES0.tick_cmpr_7),
737 .STICK_CMPR_reg (`PROBES0.stick_cmpr_7),
738 .HSTICK_CMPR_reg (`PROBES0.hstick_cmpr_7),
739 .PSTATE_reg (`SPC0.tlu.tsd1.arch_pstate3),
740 .TL_reg (`SPC0.tlu.trl1.tl3),
741 .PIL_reg (`SPC0.tlu.trl1.pil3),
742 .TBA_reg (`SPC0.tlu.tsd1.tba3[47:15]),
743 .VER_reg (`SPC0.tlu.asi.hver_value), // static
744 .CWP_reg (`SPC0.exu1.rml.cwp_thr3),
745 .CANSAVE_reg (`SPC0.exu1.rml.cansave_thr3),
746 .CANRESTORE_reg (`SPC0.exu1.rml.canrestore_thr3),
747 .OTHERWIN_reg (`SPC0.exu1.rml.otherwin_thr3),
748 .WSTATE_reg (`SPC0.exu1.rml.wstate_thr3),
749 .CLEANWIN_reg (`SPC0.exu1.rml.cleanwin_thr3),
750 .rd_SOFTINT_reg (`SPC0.tlu.trl1.rd_softint3),
751 .SOFTINT_reg (`SPC0.tlu.trl1.softint3),
752 .INTR_RECEIVE_reg (`SPC0.tlu.cth.int_rec7),
753 .GL_reg (`SPC0.tlu.tlu_gl7),
754 .HPSTATE_reg (`SPC0.tlu.tsd1.arch_hpstate3),
755 .HTBA_reg (`SPC0.tlu.tsd1.htba3[47:14]),
756 .HINTP_reg (`SPC0.tlu.trl1.hintp3),
757
758 .CTXT_PRIM_0_reg ({51'b0,`SPC0.lsu.dcs.p0ctxt_7[12:0]}),
759 .CTXT_SEC_0_reg ({51'b0,`SPC0.lsu.dcs.s0ctxt_7[12:0]}),
760 .CTXT_PRIM_1_reg ({51'b0,`SPC0.lsu.dcs.p1ctxt_7[12:0]}),
761 .CTXT_SEC_1_reg ({51'b0,`SPC0.lsu.dcs.s1ctxt_7[12:0]}),
762 .LSU_CONTROL_reg ({29'd0,
763 `SPC0.lsu.dcs.wpt_mode_7[1:0],
764 `SPC0.lsu.dcs.wpt_mask_7[7:0],
765 `SPC0.lsu.dcs.wpt_enable_7[1:0],
766 18'd0,
767 `SPC0.lsu.dcs.spec_enable[7],
768 `SPC0.lsu.dcs.dmmu_enable[7],
769 `SPC0.lsu.dcs.immu_enable[7],
770 `SPC0.lsu.dcs.dc_enable[7],
771 `SPC0.lsu.dcs.ic_enable[7]}),
772 .I_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.immu_tag_access_3[47:0]}),
773 .D_TAG_ACC_reg ({16'b0,`SPC0.mmu.asd1.dmmu_tag_access_3[47:0]}),
774 .WATCHPOINT_ADDR_reg ({16'b0,`SPC0.lsu.dcs.watchpoint7[47:3],3'b00}),
775 .DSFAR_reg (`SPC0.tlu.dfd.dsfar_7[47:0]),
776
777 .Trap_Entry_1 (`PROBES0.trap_entry_1_t7),
778 .Trap_Entry_2 (`PROBES0.trap_entry_2_t7),
779 .Trap_Entry_3 (`PROBES0.trap_entry_3_t7),
780 .Trap_Entry_4 (`PROBES0.trap_entry_4_t7),
781 .Trap_Entry_5 (`PROBES0.trap_entry_5_t7),
782 .Trap_Entry_6 (`PROBES0.trap_entry_6_t7),
783
784 .exu_valid (`PROBES0.ex_valid[7]),
785
786 .imul_valid (`PROBES0.imul_valid[7]),
787
788 .fp_valid (`PROBES0.fg_valid[7]),
789 .frf_w1_valid (`SPC0.fgu.frf.w1_valid),
790 .frf_w1_tid (`SPC0.fgu.frf.w1_tid),
791 .frf_w1_addr (`SPC0.fgu.frf.w1_addr),
792
793 .idiv_valid (`PROBES0.fgu_idiv_valid[7]),
794
795 .fdiv_valid (`PROBES0.fgu_fdiv_valid[7]),
796
797 .lsu_valid (`PROBES0.lsu_valid[7]),
798 .frf_w2_valid (`SPC0.fgu.frf.w2_valid),
799 .frf_w2_tid (`SPC0.fgu.frf.w2_tid),
800 .frf_w2_addr (`SPC0.fgu.frf.w2_addr),
801
802 .asi_valid (`PROBES0.asi_valid_fx5[7]),
803 .asi_in_progress (`PROBES0.asi_in_progress_fx4[7]),
804
805 .tlu_valid (`PROBES0.tlu_valid[7])
806`endif
807 );
808
809//----------------------------------------------------------
810
811
812//----------------------------------------------------------
813endmodule
814
815`endif
816
817`ifdef CORE_1
818
819module nas_core1 (
820
821 cid
822);
823
824input [2:0] cid;
825
826integer i;
827
828//----------------------------------------------------------
829
830//----------------------------------------------------------
831
832//----------------------------------------------------------
833//
834// THREAD 0
835//
836
837 nas_pipe1 t0 (
838 .mycid (cid),
839 .mytid (3'h0),
840
841// If GATESIM, instantiate "dummy" module with floating ports since unused.
842`ifdef GATESIM
843 .opcode () // this and all other ports are unconnected
844`else
845 .opcode ({`PROBES1.op_0_w}),
846 .PC_reg ({`PROBES1.pc_0_w}),
847 .Y_reg (`SPC1.exu0.rml.arch_yreg_tid0_ff),
848 .CCR_reg (`SPC1.exu0.ect.arch_ccr_tid0_lth),
849 .FPRS_reg (`SPC1.fgu.fac.fprs_tid0),
850 .FSR_reg (`SPC1.fgu.fad.fsr0_fx1[27:0]),
851 .ASI_reg (`SPC1.lsu.dcs.asi_state0),
852 .GSR_reg ({`SPC1.fgu.fgd.gsr0_mask_fx4[31:0], `SPC1.fgu.fpc.gsr0_11bits_fx4[10:0]}),
853 .TICK_CMPR_reg (`PROBES1.tick_cmpr_0),
854 .STICK_CMPR_reg (`PROBES1.stick_cmpr_0),
855 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_0),
856 .PSTATE_reg (`SPC1.tlu.tsd0.arch_pstate0),
857 .TL_reg (`SPC1.tlu.trl0.tl0),
858 .PIL_reg (`SPC1.tlu.trl0.pil0),
859 .TBA_reg (`SPC1.tlu.tsd0.tba0[47:15]),
860 .VER_reg (`SPC1.tlu.asi.hver_value), // static
861 .CWP_reg (`SPC1.exu0.rml.cwp_thr0),
862 .CANSAVE_reg (`SPC1.exu0.rml.cansave_thr0),
863 .CANRESTORE_reg (`SPC1.exu0.rml.canrestore_thr0),
864 .OTHERWIN_reg (`SPC1.exu0.rml.otherwin_thr0),
865 .WSTATE_reg (`SPC1.exu0.rml.wstate_thr0),
866 .CLEANWIN_reg (`SPC1.exu0.rml.cleanwin_thr0),
867 .rd_SOFTINT_reg (`SPC1.tlu.trl0.rd_softint0),
868 .SOFTINT_reg (`SPC1.tlu.trl0.softint0),
869 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec0),
870 .GL_reg (`SPC1.tlu.tlu_gl0),
871 .HPSTATE_reg (`SPC1.tlu.tsd0.arch_hpstate0),
872 .HTBA_reg (`SPC1.tlu.tsd0.htba0[47:14]),
873 .HINTP_reg (`SPC1.tlu.trl0.hintp0),
874
875 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_0[12:0]}),
876 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_0[12:0]}),
877 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_0[12:0]}),
878 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_0[12:0]}),
879 .LSU_CONTROL_reg ({29'd0,
880 `SPC1.lsu.dcs.wpt_mode_0[1:0],
881 `SPC1.lsu.dcs.wpt_mask_0[7:0],
882 `SPC1.lsu.dcs.wpt_enable_0[1:0],
883 18'd0,
884 `SPC1.lsu.dcs.spec_enable[0],
885 `SPC1.lsu.dcs.dmmu_enable[0],
886 `SPC1.lsu.dcs.immu_enable[0],
887 `SPC1.lsu.dcs.dc_enable[0],
888 `SPC1.lsu.dcs.ic_enable[0]}),
889 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.immu_tag_access_0[47:0]}),
890 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.dmmu_tag_access_0[47:0]}),
891 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint0[47:3],3'b00}),
892 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_0[47:0]),
893
894 .Trap_Entry_1 (`PROBES1.trap_entry_1_t0),
895 .Trap_Entry_2 (`PROBES1.trap_entry_2_t0),
896 .Trap_Entry_3 (`PROBES1.trap_entry_3_t0),
897 .Trap_Entry_4 (`PROBES1.trap_entry_4_t0),
898 .Trap_Entry_5 (`PROBES1.trap_entry_5_t0),
899 .Trap_Entry_6 (`PROBES1.trap_entry_6_t0),
900
901 .exu_valid (`PROBES1.ex_valid[0]),
902
903 .imul_valid (`PROBES1.imul_valid[0]),
904
905 .fp_valid (`PROBES1.fg_valid[0]),
906 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
907 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
908 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
909
910 .idiv_valid (`PROBES1.fgu_idiv_valid[0]),
911
912 .fdiv_valid (`PROBES1.fgu_fdiv_valid[0]),
913
914 .lsu_valid (`PROBES1.lsu_valid[0]),
915 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
916 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
917 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
918
919 .asi_valid (`PROBES1.asi_valid_fx5[0]),
920 .asi_in_progress (`PROBES1.asi_in_progress_fx4[0]),
921
922 .tlu_valid (`PROBES1.tlu_valid[0])
923`endif
924 );
925
926
927//----------------------------------------------------------
928//
929// THREAD 1
930//
931
932 nas_pipe1 t1 (
933 .mycid (cid),
934 .mytid (3'h1),
935
936// If GATESIM, instantiate "dummy" module with floating ports since unused.
937`ifdef GATESIM
938 .opcode () // this and all other ports are unconnected
939`else
940 .opcode ({`PROBES1.op_1_w}),
941 .PC_reg ({`PROBES1.pc_1_w}),
942 .Y_reg (`SPC1.exu0.rml.arch_yreg_tid1_ff),
943 .CCR_reg (`SPC1.exu0.ect.arch_ccr_tid1_lth),
944 .FPRS_reg (`SPC1.fgu.fac.fprs_tid1),
945 .FSR_reg (`SPC1.fgu.fad.fsr1_fx1[27:0]),
946 .ASI_reg (`SPC1.lsu.dcs.asi_state1),
947 .GSR_reg ({`SPC1.fgu.fgd.gsr1_mask_fx4[31:0], `SPC1.fgu.fpc.gsr1_11bits_fx4[10:0]}),
948 .TICK_CMPR_reg (`PROBES1.tick_cmpr_1),
949 .STICK_CMPR_reg (`PROBES1.stick_cmpr_1),
950 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_1),
951 .PSTATE_reg (`SPC1.tlu.tsd0.arch_pstate1),
952 .TL_reg (`SPC1.tlu.trl0.tl1),
953 .PIL_reg (`SPC1.tlu.trl0.pil1),
954 .TBA_reg (`SPC1.tlu.tsd0.tba1[47:15]),
955 .VER_reg (`SPC1.tlu.asi.hver_value), // static
956 .CWP_reg (`SPC1.exu0.rml.cwp_thr1),
957 .CANSAVE_reg (`SPC1.exu0.rml.cansave_thr1),
958 .CANRESTORE_reg (`SPC1.exu0.rml.canrestore_thr1),
959 .OTHERWIN_reg (`SPC1.exu0.rml.otherwin_thr1),
960 .WSTATE_reg (`SPC1.exu0.rml.wstate_thr1),
961 .CLEANWIN_reg (`SPC1.exu0.rml.cleanwin_thr1),
962 .rd_SOFTINT_reg (`SPC1.tlu.trl0.rd_softint1),
963 .SOFTINT_reg (`SPC1.tlu.trl0.softint1),
964 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec1),
965 .GL_reg (`SPC1.tlu.tlu_gl1),
966 .HPSTATE_reg (`SPC1.tlu.tsd0.arch_hpstate1),
967 .HTBA_reg (`SPC1.tlu.tsd0.htba1[47:14]),
968 .HINTP_reg (`SPC1.tlu.trl0.hintp1),
969
970 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_1[12:0]}),
971 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_1[12:0]}),
972 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_1[12:0]}),
973 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_1[12:0]}),
974 .LSU_CONTROL_reg ({29'd0,
975 `SPC1.lsu.dcs.wpt_mode_1[1:0],
976 `SPC1.lsu.dcs.wpt_mask_1[7:0],
977 `SPC1.lsu.dcs.wpt_enable_1[1:0],
978 18'd0,
979 `SPC1.lsu.dcs.spec_enable[1],
980 `SPC1.lsu.dcs.dmmu_enable[1],
981 `SPC1.lsu.dcs.immu_enable[1],
982 `SPC1.lsu.dcs.dc_enable[1],
983 `SPC1.lsu.dcs.ic_enable[1]}),
984 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.immu_tag_access_1[47:0]}),
985 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.dmmu_tag_access_1[47:0]}),
986 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint1[47:3],3'b00}),
987 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_1[47:0]),
988
989 .Trap_Entry_1 (`PROBES1.trap_entry_1_t1),
990 .Trap_Entry_2 (`PROBES1.trap_entry_2_t1),
991 .Trap_Entry_3 (`PROBES1.trap_entry_3_t1),
992 .Trap_Entry_4 (`PROBES1.trap_entry_4_t1),
993 .Trap_Entry_5 (`PROBES1.trap_entry_5_t1),
994 .Trap_Entry_6 (`PROBES1.trap_entry_6_t1),
995
996 .exu_valid (`PROBES1.ex_valid[1]),
997
998 .imul_valid (`PROBES1.imul_valid[1]),
999
1000 .fp_valid (`PROBES1.fg_valid[1]),
1001 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1002 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1003 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1004
1005 .idiv_valid (`PROBES1.fgu_idiv_valid[1]),
1006
1007 .fdiv_valid (`PROBES1.fgu_fdiv_valid[1]),
1008
1009 .lsu_valid (`PROBES1.lsu_valid[1]),
1010 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1011 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1012 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1013
1014 .asi_valid (`PROBES1.asi_valid_fx5[1]),
1015 .asi_in_progress (`PROBES1.asi_in_progress_fx4[1]),
1016
1017 .tlu_valid (`PROBES1.tlu_valid[1])
1018`endif
1019 );
1020
1021
1022//----------------------------------------------------------
1023//
1024// THREAD 2
1025//
1026
1027 nas_pipe1 t2 (
1028 .mycid (cid),
1029 .mytid (3'h2),
1030
1031// If GATESIM, instantiate "dummy" module with floating ports since unused.
1032`ifdef GATESIM
1033 .opcode () // this and all other ports are unconnected
1034`else
1035 .opcode ({`PROBES1.op_2_w}),
1036 .PC_reg ({`PROBES1.pc_2_w}),
1037 .Y_reg (`SPC1.exu0.rml.arch_yreg_tid2_ff),
1038 .CCR_reg (`SPC1.exu0.ect.arch_ccr_tid2_lth),
1039 .FPRS_reg (`SPC1.fgu.fac.fprs_tid2),
1040 .FSR_reg (`SPC1.fgu.fad.fsr2_fx1[27:0]),
1041 .ASI_reg (`SPC1.lsu.dcs.asi_state2),
1042 .GSR_reg ({`SPC1.fgu.fgd.gsr2_mask_fx4[31:0], `SPC1.fgu.fpc.gsr2_11bits_fx4[10:0]}),
1043 .TICK_CMPR_reg (`PROBES1.tick_cmpr_2),
1044 .STICK_CMPR_reg (`PROBES1.stick_cmpr_2),
1045 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_2),
1046 .PSTATE_reg (`SPC1.tlu.tsd0.arch_pstate2),
1047 .TL_reg (`SPC1.tlu.trl0.tl2),
1048 .PIL_reg (`SPC1.tlu.trl0.pil2),
1049 .TBA_reg (`SPC1.tlu.tsd0.tba2[47:15]),
1050 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1051 .CWP_reg (`SPC1.exu0.rml.cwp_thr2),
1052 .CANSAVE_reg (`SPC1.exu0.rml.cansave_thr2),
1053 .CANRESTORE_reg (`SPC1.exu0.rml.canrestore_thr2),
1054 .OTHERWIN_reg (`SPC1.exu0.rml.otherwin_thr2),
1055 .WSTATE_reg (`SPC1.exu0.rml.wstate_thr2),
1056 .CLEANWIN_reg (`SPC1.exu0.rml.cleanwin_thr2),
1057 .rd_SOFTINT_reg (`SPC1.tlu.trl0.rd_softint2),
1058 .SOFTINT_reg (`SPC1.tlu.trl0.softint2),
1059 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec2),
1060 .GL_reg (`SPC1.tlu.tlu_gl2),
1061 .HPSTATE_reg (`SPC1.tlu.tsd0.arch_hpstate2),
1062 .HTBA_reg (`SPC1.tlu.tsd0.htba2[47:14]),
1063 .HINTP_reg (`SPC1.tlu.trl0.hintp2),
1064
1065 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_2[12:0]}),
1066 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_2[12:0]}),
1067 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_2[12:0]}),
1068 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_2[12:0]}),
1069 .LSU_CONTROL_reg ({29'd0,
1070 `SPC1.lsu.dcs.wpt_mode_2[1:0],
1071 `SPC1.lsu.dcs.wpt_mask_2[7:0],
1072 `SPC1.lsu.dcs.wpt_enable_2[1:0],
1073 18'd0,
1074 `SPC1.lsu.dcs.spec_enable[2],
1075 `SPC1.lsu.dcs.dmmu_enable[2],
1076 `SPC1.lsu.dcs.immu_enable[2],
1077 `SPC1.lsu.dcs.dc_enable[2],
1078 `SPC1.lsu.dcs.ic_enable[2]}),
1079 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.immu_tag_access_2[47:0]}),
1080 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.dmmu_tag_access_2[47:0]}),
1081 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint2[47:3],3'b00}),
1082 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_2[47:0]),
1083
1084 .Trap_Entry_1 (`PROBES1.trap_entry_1_t2),
1085 .Trap_Entry_2 (`PROBES1.trap_entry_2_t2),
1086 .Trap_Entry_3 (`PROBES1.trap_entry_3_t2),
1087 .Trap_Entry_4 (`PROBES1.trap_entry_4_t2),
1088 .Trap_Entry_5 (`PROBES1.trap_entry_5_t2),
1089 .Trap_Entry_6 (`PROBES1.trap_entry_6_t2),
1090
1091 .exu_valid (`PROBES1.ex_valid[2]),
1092
1093 .imul_valid (`PROBES1.imul_valid[2]),
1094
1095 .fp_valid (`PROBES1.fg_valid[2]),
1096 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1097 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1098 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1099
1100 .idiv_valid (`PROBES1.fgu_idiv_valid[2]),
1101
1102 .fdiv_valid (`PROBES1.fgu_fdiv_valid[2]),
1103
1104 .lsu_valid (`PROBES1.lsu_valid[2]),
1105 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1106 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1107 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1108
1109 .asi_valid (`PROBES1.asi_valid_fx5[2]),
1110 .asi_in_progress (`PROBES1.asi_in_progress_fx4[2]),
1111
1112 .tlu_valid (`PROBES1.tlu_valid[2])
1113`endif
1114 );
1115
1116
1117//----------------------------------------------------------
1118//
1119// THREAD 3
1120//
1121
1122 nas_pipe1 t3 (
1123 .mycid (cid),
1124 .mytid (3'h3),
1125
1126// If GATESIM, instantiate "dummy" module with floating ports since unused.
1127`ifdef GATESIM
1128 .opcode () // this and all other ports are unconnected
1129`else
1130 .opcode ({`PROBES1.op_3_w}),
1131 .PC_reg ({`PROBES1.pc_3_w}),
1132 .Y_reg (`SPC1.exu0.rml.arch_yreg_tid3_ff),
1133 .CCR_reg (`SPC1.exu0.ect.arch_ccr_tid3_lth),
1134 .FPRS_reg (`SPC1.fgu.fac.fprs_tid3),
1135 .FSR_reg (`SPC1.fgu.fad.fsr3_fx1[27:0]),
1136 .ASI_reg (`SPC1.lsu.dcs.asi_state3),
1137 .GSR_reg ({`SPC1.fgu.fgd.gsr3_mask_fx4[31:0], `SPC1.fgu.fpc.gsr3_11bits_fx4[10:0]}),
1138 .TICK_CMPR_reg (`PROBES1.tick_cmpr_3),
1139 .STICK_CMPR_reg (`PROBES1.stick_cmpr_3),
1140 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_3),
1141 .PSTATE_reg (`SPC1.tlu.tsd0.arch_pstate3),
1142 .TL_reg (`SPC1.tlu.trl0.tl3),
1143 .PIL_reg (`SPC1.tlu.trl0.pil3),
1144 .TBA_reg (`SPC1.tlu.tsd0.tba3[47:15]),
1145 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1146 .CWP_reg (`SPC1.exu0.rml.cwp_thr3),
1147 .CANSAVE_reg (`SPC1.exu0.rml.cansave_thr3),
1148 .CANRESTORE_reg (`SPC1.exu0.rml.canrestore_thr3),
1149 .OTHERWIN_reg (`SPC1.exu0.rml.otherwin_thr3),
1150 .WSTATE_reg (`SPC1.exu0.rml.wstate_thr3),
1151 .CLEANWIN_reg (`SPC1.exu0.rml.cleanwin_thr3),
1152 .rd_SOFTINT_reg (`SPC1.tlu.trl0.rd_softint3),
1153 .SOFTINT_reg (`SPC1.tlu.trl0.softint3),
1154 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec3),
1155 .GL_reg (`SPC1.tlu.tlu_gl3),
1156 .HPSTATE_reg (`SPC1.tlu.tsd0.arch_hpstate3),
1157 .HTBA_reg (`SPC1.tlu.tsd0.htba3[47:14]),
1158 .HINTP_reg (`SPC1.tlu.trl0.hintp3),
1159
1160 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_3[12:0]}),
1161 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_3[12:0]}),
1162 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_3[12:0]}),
1163 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_3[12:0]}),
1164 .LSU_CONTROL_reg ({29'd0,
1165 `SPC1.lsu.dcs.wpt_mode_3[1:0],
1166 `SPC1.lsu.dcs.wpt_mask_3[7:0],
1167 `SPC1.lsu.dcs.wpt_enable_3[1:0],
1168 18'd0,
1169 `SPC1.lsu.dcs.spec_enable[3],
1170 `SPC1.lsu.dcs.dmmu_enable[3],
1171 `SPC1.lsu.dcs.immu_enable[3],
1172 `SPC1.lsu.dcs.dc_enable[3],
1173 `SPC1.lsu.dcs.ic_enable[3]}),
1174 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.immu_tag_access_3[47:0]}),
1175 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd0.dmmu_tag_access_3[47:0]}),
1176 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint3[47:3],3'b00}),
1177 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_3[47:0]),
1178
1179 .Trap_Entry_1 (`PROBES1.trap_entry_1_t3),
1180 .Trap_Entry_2 (`PROBES1.trap_entry_2_t3),
1181 .Trap_Entry_3 (`PROBES1.trap_entry_3_t3),
1182 .Trap_Entry_4 (`PROBES1.trap_entry_4_t3),
1183 .Trap_Entry_5 (`PROBES1.trap_entry_5_t3),
1184 .Trap_Entry_6 (`PROBES1.trap_entry_6_t3),
1185
1186 .exu_valid (`PROBES1.ex_valid[3]),
1187
1188 .imul_valid (`PROBES1.imul_valid[3]),
1189
1190 .fp_valid (`PROBES1.fg_valid[3]),
1191 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1192 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1193 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1194
1195 .idiv_valid (`PROBES1.fgu_idiv_valid[3]),
1196
1197 .fdiv_valid (`PROBES1.fgu_fdiv_valid[3]),
1198
1199 .lsu_valid (`PROBES1.lsu_valid[3]),
1200 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1201 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1202 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1203
1204 .asi_valid (`PROBES1.asi_valid_fx5[3]),
1205 .asi_in_progress (`PROBES1.asi_in_progress_fx4[3]),
1206
1207 .tlu_valid (`PROBES1.tlu_valid[3])
1208`endif
1209 );
1210
1211
1212//----------------------------------------------------------
1213//
1214// THREAD 4
1215//
1216
1217 nas_pipe1 t4 (
1218 .mycid (cid),
1219 .mytid (3'h4),
1220
1221// If GATESIM, instantiate "dummy" module with floating ports since unused.
1222`ifdef GATESIM
1223 .opcode () // this and all other ports are unconnected
1224`else
1225 .opcode ({`PROBES1.op_4_w}),
1226 .PC_reg ({`PROBES1.pc_4_w}),
1227 .Y_reg (`SPC1.exu1.rml.arch_yreg_tid0_ff),
1228 .CCR_reg (`SPC1.exu1.ect.arch_ccr_tid0_lth),
1229 .FPRS_reg (`SPC1.fgu.fac.fprs_tid4),
1230 .FSR_reg (`SPC1.fgu.fad.fsr4_fx1[27:0]),
1231 .ASI_reg (`SPC1.lsu.dcs.asi_state4),
1232 .GSR_reg ({`SPC1.fgu.fgd.gsr4_mask_fx4[31:0], `SPC1.fgu.fpc.gsr4_11bits_fx4[10:0]}),
1233 .TICK_CMPR_reg (`PROBES1.tick_cmpr_4),
1234 .STICK_CMPR_reg (`PROBES1.stick_cmpr_4),
1235 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_4),
1236 .PSTATE_reg (`SPC1.tlu.tsd1.arch_pstate0),
1237 .TL_reg (`SPC1.tlu.trl1.tl0),
1238 .PIL_reg (`SPC1.tlu.trl1.pil0),
1239 .TBA_reg (`SPC1.tlu.tsd1.tba0[47:15]),
1240 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1241 .CWP_reg (`SPC1.exu1.rml.cwp_thr0),
1242 .CANSAVE_reg (`SPC1.exu1.rml.cansave_thr0),
1243 .CANRESTORE_reg (`SPC1.exu1.rml.canrestore_thr0),
1244 .OTHERWIN_reg (`SPC1.exu1.rml.otherwin_thr0),
1245 .WSTATE_reg (`SPC1.exu1.rml.wstate_thr0),
1246 .CLEANWIN_reg (`SPC1.exu1.rml.cleanwin_thr0),
1247 .rd_SOFTINT_reg (`SPC1.tlu.trl1.rd_softint0),
1248 .SOFTINT_reg (`SPC1.tlu.trl1.softint0),
1249 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec4),
1250 .GL_reg (`SPC1.tlu.tlu_gl4),
1251 .HPSTATE_reg (`SPC1.tlu.tsd1.arch_hpstate0),
1252 .HTBA_reg (`SPC1.tlu.tsd1.htba0[47:14]),
1253 .HINTP_reg (`SPC1.tlu.trl1.hintp0),
1254
1255 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_4[12:0]}),
1256 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_4[12:0]}),
1257 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_4[12:0]}),
1258 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_4[12:0]}),
1259 .LSU_CONTROL_reg ({29'd0,
1260 `SPC1.lsu.dcs.wpt_mode_4[1:0],
1261 `SPC1.lsu.dcs.wpt_mask_4[7:0],
1262 `SPC1.lsu.dcs.wpt_enable_4[1:0],
1263 18'd0,
1264 `SPC1.lsu.dcs.spec_enable[4],
1265 `SPC1.lsu.dcs.dmmu_enable[4],
1266 `SPC1.lsu.dcs.immu_enable[4],
1267 `SPC1.lsu.dcs.dc_enable[4],
1268 `SPC1.lsu.dcs.ic_enable[4]}),
1269 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.immu_tag_access_0[47:0]}),
1270 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.dmmu_tag_access_0[47:0]}),
1271 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint4[47:3],3'b00}),
1272 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_4[47:0]),
1273
1274 .Trap_Entry_1 (`PROBES1.trap_entry_1_t4),
1275 .Trap_Entry_2 (`PROBES1.trap_entry_2_t4),
1276 .Trap_Entry_3 (`PROBES1.trap_entry_3_t4),
1277 .Trap_Entry_4 (`PROBES1.trap_entry_4_t4),
1278 .Trap_Entry_5 (`PROBES1.trap_entry_5_t4),
1279 .Trap_Entry_6 (`PROBES1.trap_entry_6_t4),
1280
1281 .exu_valid (`PROBES1.ex_valid[4]),
1282
1283 .imul_valid (`PROBES1.imul_valid[4]),
1284
1285 .fp_valid (`PROBES1.fg_valid[4]),
1286 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1287 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1288 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1289
1290 .idiv_valid (`PROBES1.fgu_idiv_valid[4]),
1291
1292 .fdiv_valid (`PROBES1.fgu_fdiv_valid[4]),
1293
1294 .lsu_valid (`PROBES1.lsu_valid[4]),
1295 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1296 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1297 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1298
1299 .asi_valid (`PROBES1.asi_valid_fx5[4]),
1300 .asi_in_progress (`PROBES1.asi_in_progress_fx4[4]),
1301
1302 .tlu_valid (`PROBES1.tlu_valid[4])
1303`endif
1304 );
1305
1306
1307//----------------------------------------------------------
1308//
1309// THREAD 5
1310//
1311
1312 nas_pipe1 t5 (
1313 .mycid (cid),
1314 .mytid (3'h5),
1315
1316// If GATESIM, instantiate "dummy" module with floating ports since unused.
1317`ifdef GATESIM
1318 .opcode () // this and all other ports are unconnected
1319`else
1320 .opcode ({`PROBES1.op_5_w}),
1321 .PC_reg ({`PROBES1.pc_5_w}),
1322 .Y_reg (`SPC1.exu1.rml.arch_yreg_tid1_ff),
1323 .CCR_reg (`SPC1.exu1.ect.arch_ccr_tid1_lth),
1324 .FPRS_reg (`SPC1.fgu.fac.fprs_tid5),
1325 .FSR_reg (`SPC1.fgu.fad.fsr5_fx1[27:0]),
1326 .ASI_reg (`SPC1.lsu.dcs.asi_state5),
1327 .GSR_reg ({`SPC1.fgu.fgd.gsr5_mask_fx4[31:0], `SPC1.fgu.fpc.gsr5_11bits_fx4[10:0]}),
1328 .TICK_CMPR_reg (`PROBES1.tick_cmpr_5),
1329 .STICK_CMPR_reg (`PROBES1.stick_cmpr_5),
1330 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_5),
1331 .PSTATE_reg (`SPC1.tlu.tsd1.arch_pstate1),
1332 .TL_reg (`SPC1.tlu.trl1.tl1),
1333 .PIL_reg (`SPC1.tlu.trl1.pil1),
1334 .TBA_reg (`SPC1.tlu.tsd1.tba1[47:15]),
1335 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1336 .CWP_reg (`SPC1.exu1.rml.cwp_thr1),
1337 .CANSAVE_reg (`SPC1.exu1.rml.cansave_thr1),
1338 .CANRESTORE_reg (`SPC1.exu1.rml.canrestore_thr1),
1339 .OTHERWIN_reg (`SPC1.exu1.rml.otherwin_thr1),
1340 .WSTATE_reg (`SPC1.exu1.rml.wstate_thr1),
1341 .CLEANWIN_reg (`SPC1.exu1.rml.cleanwin_thr1),
1342 .rd_SOFTINT_reg (`SPC1.tlu.trl1.rd_softint1),
1343 .SOFTINT_reg (`SPC1.tlu.trl1.softint1),
1344 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec5),
1345 .GL_reg (`SPC1.tlu.tlu_gl5),
1346 .HPSTATE_reg (`SPC1.tlu.tsd1.arch_hpstate1),
1347 .HTBA_reg (`SPC1.tlu.tsd1.htba1[47:14]),
1348 .HINTP_reg (`SPC1.tlu.trl1.hintp1),
1349
1350 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_5[12:0]}),
1351 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_5[12:0]}),
1352 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_5[12:0]}),
1353 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_5[12:0]}),
1354 .LSU_CONTROL_reg ({29'd0,
1355 `SPC1.lsu.dcs.wpt_mode_5[1:0],
1356 `SPC1.lsu.dcs.wpt_mask_5[7:0],
1357 `SPC1.lsu.dcs.wpt_enable_5[1:0],
1358 18'd0,
1359 `SPC1.lsu.dcs.spec_enable[5],
1360 `SPC1.lsu.dcs.dmmu_enable[5],
1361 `SPC1.lsu.dcs.immu_enable[5],
1362 `SPC1.lsu.dcs.dc_enable[5],
1363 `SPC1.lsu.dcs.ic_enable[5]}),
1364 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.immu_tag_access_1[47:0]}),
1365 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.dmmu_tag_access_1[47:0]}),
1366 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint5[47:3],3'b00}),
1367 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_5[47:0]),
1368
1369 .Trap_Entry_1 (`PROBES1.trap_entry_1_t5),
1370 .Trap_Entry_2 (`PROBES1.trap_entry_2_t5),
1371 .Trap_Entry_3 (`PROBES1.trap_entry_3_t5),
1372 .Trap_Entry_4 (`PROBES1.trap_entry_4_t5),
1373 .Trap_Entry_5 (`PROBES1.trap_entry_5_t5),
1374 .Trap_Entry_6 (`PROBES1.trap_entry_6_t5),
1375
1376 .exu_valid (`PROBES1.ex_valid[5]),
1377
1378 .imul_valid (`PROBES1.imul_valid[5]),
1379
1380 .fp_valid (`PROBES1.fg_valid[5]),
1381 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1382 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1383 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1384
1385 .idiv_valid (`PROBES1.fgu_idiv_valid[5]),
1386
1387 .fdiv_valid (`PROBES1.fgu_fdiv_valid[5]),
1388
1389 .lsu_valid (`PROBES1.lsu_valid[5]),
1390 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1391 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1392 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1393
1394 .asi_valid (`PROBES1.asi_valid_fx5[5]),
1395 .asi_in_progress (`PROBES1.asi_in_progress_fx4[5]),
1396
1397 .tlu_valid (`PROBES1.tlu_valid[5])
1398`endif
1399 );
1400
1401
1402//----------------------------------------------------------
1403//
1404// THREAD 6
1405//
1406
1407 nas_pipe1 t6 (
1408 .mycid (cid),
1409 .mytid (3'h6),
1410
1411// If GATESIM, instantiate "dummy" module with floating ports since unused.
1412`ifdef GATESIM
1413 .opcode () // this and all other ports are unconnected
1414`else
1415 .opcode ({`PROBES1.op_6_w}),
1416 .PC_reg ({`PROBES1.pc_6_w}),
1417 .Y_reg (`SPC1.exu1.rml.arch_yreg_tid2_ff),
1418 .CCR_reg (`SPC1.exu1.ect.arch_ccr_tid2_lth),
1419 .FPRS_reg (`SPC1.fgu.fac.fprs_tid6),
1420 .FSR_reg (`SPC1.fgu.fad.fsr6_fx1[27:0]),
1421 .ASI_reg (`SPC1.lsu.dcs.asi_state6),
1422 .GSR_reg ({`SPC1.fgu.fgd.gsr6_mask_fx4[31:0], `SPC1.fgu.fpc.gsr6_11bits_fx4[10:0]}),
1423 .TICK_CMPR_reg (`PROBES1.tick_cmpr_6),
1424 .STICK_CMPR_reg (`PROBES1.stick_cmpr_6),
1425 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_6),
1426 .PSTATE_reg (`SPC1.tlu.tsd1.arch_pstate2),
1427 .TL_reg (`SPC1.tlu.trl1.tl2),
1428 .PIL_reg (`SPC1.tlu.trl1.pil2),
1429 .TBA_reg (`SPC1.tlu.tsd1.tba2[47:15]),
1430 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1431 .CWP_reg (`SPC1.exu1.rml.cwp_thr2),
1432 .CANSAVE_reg (`SPC1.exu1.rml.cansave_thr2),
1433 .CANRESTORE_reg (`SPC1.exu1.rml.canrestore_thr2),
1434 .OTHERWIN_reg (`SPC1.exu1.rml.otherwin_thr2),
1435 .WSTATE_reg (`SPC1.exu1.rml.wstate_thr2),
1436 .CLEANWIN_reg (`SPC1.exu1.rml.cleanwin_thr2),
1437 .rd_SOFTINT_reg (`SPC1.tlu.trl1.rd_softint2),
1438 .SOFTINT_reg (`SPC1.tlu.trl1.softint2),
1439 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec6),
1440 .GL_reg (`SPC1.tlu.tlu_gl6),
1441 .HPSTATE_reg (`SPC1.tlu.tsd1.arch_hpstate2),
1442 .HTBA_reg (`SPC1.tlu.tsd1.htba2[47:14]),
1443 .HINTP_reg (`SPC1.tlu.trl1.hintp2),
1444
1445 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_6[12:0]}),
1446 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_6[12:0]}),
1447 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_6[12:0]}),
1448 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_6[12:0]}),
1449 .LSU_CONTROL_reg ({29'd0,
1450 `SPC1.lsu.dcs.wpt_mode_6[1:0],
1451 `SPC1.lsu.dcs.wpt_mask_6[7:0],
1452 `SPC1.lsu.dcs.wpt_enable_6[1:0],
1453 18'd0,
1454 `SPC1.lsu.dcs.spec_enable[6],
1455 `SPC1.lsu.dcs.dmmu_enable[6],
1456 `SPC1.lsu.dcs.immu_enable[6],
1457 `SPC1.lsu.dcs.dc_enable[6],
1458 `SPC1.lsu.dcs.ic_enable[6]}),
1459 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.immu_tag_access_2[47:0]}),
1460 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.dmmu_tag_access_2[47:0]}),
1461 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint6[47:3],3'b00}),
1462 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_6[47:0]),
1463
1464 .Trap_Entry_1 (`PROBES1.trap_entry_1_t6),
1465 .Trap_Entry_2 (`PROBES1.trap_entry_2_t6),
1466 .Trap_Entry_3 (`PROBES1.trap_entry_3_t6),
1467 .Trap_Entry_4 (`PROBES1.trap_entry_4_t6),
1468 .Trap_Entry_5 (`PROBES1.trap_entry_5_t6),
1469 .Trap_Entry_6 (`PROBES1.trap_entry_6_t6),
1470
1471 .exu_valid (`PROBES1.ex_valid[6]),
1472
1473 .imul_valid (`PROBES1.imul_valid[6]),
1474
1475 .fp_valid (`PROBES1.fg_valid[6]),
1476 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1477 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1478 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1479
1480 .idiv_valid (`PROBES1.fgu_idiv_valid[6]),
1481
1482 .fdiv_valid (`PROBES1.fgu_fdiv_valid[6]),
1483
1484 .lsu_valid (`PROBES1.lsu_valid[6]),
1485 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1486 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1487 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1488
1489 .asi_valid (`PROBES1.asi_valid_fx5[6]),
1490 .asi_in_progress (`PROBES1.asi_in_progress_fx4[6]),
1491
1492 .tlu_valid (`PROBES1.tlu_valid[6])
1493`endif
1494 );
1495
1496
1497//----------------------------------------------------------
1498//
1499// THREAD 7
1500//
1501
1502 nas_pipe1 t7 (
1503 .mycid (cid),
1504 .mytid (3'h7),
1505
1506// If GATESIM, instantiate "dummy" module with floating ports since unused.
1507`ifdef GATESIM
1508 .opcode () // this and all other ports are unconnected
1509`else
1510 .opcode ({`PROBES1.op_7_w}),
1511 .PC_reg ({`PROBES1.pc_7_w}),
1512 .Y_reg (`SPC1.exu1.rml.arch_yreg_tid3_ff),
1513 .CCR_reg (`SPC1.exu1.ect.arch_ccr_tid3_lth),
1514 .FPRS_reg (`SPC1.fgu.fac.fprs_tid7),
1515 .FSR_reg (`SPC1.fgu.fad.fsr7_fx1[27:0]),
1516 .ASI_reg (`SPC1.lsu.dcs.asi_state7),
1517 .GSR_reg ({`SPC1.fgu.fgd.gsr7_mask_fx4[31:0], `SPC1.fgu.fpc.gsr7_11bits_fx4[10:0]}),
1518 .TICK_CMPR_reg (`PROBES1.tick_cmpr_7),
1519 .STICK_CMPR_reg (`PROBES1.stick_cmpr_7),
1520 .HSTICK_CMPR_reg (`PROBES1.hstick_cmpr_7),
1521 .PSTATE_reg (`SPC1.tlu.tsd1.arch_pstate3),
1522 .TL_reg (`SPC1.tlu.trl1.tl3),
1523 .PIL_reg (`SPC1.tlu.trl1.pil3),
1524 .TBA_reg (`SPC1.tlu.tsd1.tba3[47:15]),
1525 .VER_reg (`SPC1.tlu.asi.hver_value), // static
1526 .CWP_reg (`SPC1.exu1.rml.cwp_thr3),
1527 .CANSAVE_reg (`SPC1.exu1.rml.cansave_thr3),
1528 .CANRESTORE_reg (`SPC1.exu1.rml.canrestore_thr3),
1529 .OTHERWIN_reg (`SPC1.exu1.rml.otherwin_thr3),
1530 .WSTATE_reg (`SPC1.exu1.rml.wstate_thr3),
1531 .CLEANWIN_reg (`SPC1.exu1.rml.cleanwin_thr3),
1532 .rd_SOFTINT_reg (`SPC1.tlu.trl1.rd_softint3),
1533 .SOFTINT_reg (`SPC1.tlu.trl1.softint3),
1534 .INTR_RECEIVE_reg (`SPC1.tlu.cth.int_rec7),
1535 .GL_reg (`SPC1.tlu.tlu_gl7),
1536 .HPSTATE_reg (`SPC1.tlu.tsd1.arch_hpstate3),
1537 .HTBA_reg (`SPC1.tlu.tsd1.htba3[47:14]),
1538 .HINTP_reg (`SPC1.tlu.trl1.hintp3),
1539
1540 .CTXT_PRIM_0_reg ({51'b0,`SPC1.lsu.dcs.p0ctxt_7[12:0]}),
1541 .CTXT_SEC_0_reg ({51'b0,`SPC1.lsu.dcs.s0ctxt_7[12:0]}),
1542 .CTXT_PRIM_1_reg ({51'b0,`SPC1.lsu.dcs.p1ctxt_7[12:0]}),
1543 .CTXT_SEC_1_reg ({51'b0,`SPC1.lsu.dcs.s1ctxt_7[12:0]}),
1544 .LSU_CONTROL_reg ({29'd0,
1545 `SPC1.lsu.dcs.wpt_mode_7[1:0],
1546 `SPC1.lsu.dcs.wpt_mask_7[7:0],
1547 `SPC1.lsu.dcs.wpt_enable_7[1:0],
1548 18'd0,
1549 `SPC1.lsu.dcs.spec_enable[7],
1550 `SPC1.lsu.dcs.dmmu_enable[7],
1551 `SPC1.lsu.dcs.immu_enable[7],
1552 `SPC1.lsu.dcs.dc_enable[7],
1553 `SPC1.lsu.dcs.ic_enable[7]}),
1554 .I_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.immu_tag_access_3[47:0]}),
1555 .D_TAG_ACC_reg ({16'b0,`SPC1.mmu.asd1.dmmu_tag_access_3[47:0]}),
1556 .WATCHPOINT_ADDR_reg ({16'b0,`SPC1.lsu.dcs.watchpoint7[47:3],3'b00}),
1557 .DSFAR_reg (`SPC1.tlu.dfd.dsfar_7[47:0]),
1558
1559 .Trap_Entry_1 (`PROBES1.trap_entry_1_t7),
1560 .Trap_Entry_2 (`PROBES1.trap_entry_2_t7),
1561 .Trap_Entry_3 (`PROBES1.trap_entry_3_t7),
1562 .Trap_Entry_4 (`PROBES1.trap_entry_4_t7),
1563 .Trap_Entry_5 (`PROBES1.trap_entry_5_t7),
1564 .Trap_Entry_6 (`PROBES1.trap_entry_6_t7),
1565
1566 .exu_valid (`PROBES1.ex_valid[7]),
1567
1568 .imul_valid (`PROBES1.imul_valid[7]),
1569
1570 .fp_valid (`PROBES1.fg_valid[7]),
1571 .frf_w1_valid (`SPC1.fgu.frf.w1_valid),
1572 .frf_w1_tid (`SPC1.fgu.frf.w1_tid),
1573 .frf_w1_addr (`SPC1.fgu.frf.w1_addr),
1574
1575 .idiv_valid (`PROBES1.fgu_idiv_valid[7]),
1576
1577 .fdiv_valid (`PROBES1.fgu_fdiv_valid[7]),
1578
1579 .lsu_valid (`PROBES1.lsu_valid[7]),
1580 .frf_w2_valid (`SPC1.fgu.frf.w2_valid),
1581 .frf_w2_tid (`SPC1.fgu.frf.w2_tid),
1582 .frf_w2_addr (`SPC1.fgu.frf.w2_addr),
1583
1584 .asi_valid (`PROBES1.asi_valid_fx5[7]),
1585 .asi_in_progress (`PROBES1.asi_in_progress_fx4[7]),
1586
1587 .tlu_valid (`PROBES1.tlu_valid[7])
1588`endif
1589 );
1590
1591//----------------------------------------------------------
1592
1593
1594//----------------------------------------------------------
1595endmodule
1596
1597`endif
1598
1599`ifdef CORE_2
1600
1601module nas_core2 (
1602
1603 cid
1604);
1605
1606input [2:0] cid;
1607
1608integer i;
1609
1610//----------------------------------------------------------
1611
1612//----------------------------------------------------------
1613
1614//----------------------------------------------------------
1615//
1616// THREAD 0
1617//
1618
1619 nas_pipe2 t0 (
1620 .mycid (cid),
1621 .mytid (3'h0),
1622
1623// If GATESIM, instantiate "dummy" module with floating ports since unused.
1624`ifdef GATESIM
1625 .opcode () // this and all other ports are unconnected
1626`else
1627 .opcode ({`PROBES2.op_0_w}),
1628 .PC_reg ({`PROBES2.pc_0_w}),
1629 .Y_reg (`SPC2.exu0.rml.arch_yreg_tid0_ff),
1630 .CCR_reg (`SPC2.exu0.ect.arch_ccr_tid0_lth),
1631 .FPRS_reg (`SPC2.fgu.fac.fprs_tid0),
1632 .FSR_reg (`SPC2.fgu.fad.fsr0_fx1[27:0]),
1633 .ASI_reg (`SPC2.lsu.dcs.asi_state0),
1634 .GSR_reg ({`SPC2.fgu.fgd.gsr0_mask_fx4[31:0], `SPC2.fgu.fpc.gsr0_11bits_fx4[10:0]}),
1635 .TICK_CMPR_reg (`PROBES2.tick_cmpr_0),
1636 .STICK_CMPR_reg (`PROBES2.stick_cmpr_0),
1637 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_0),
1638 .PSTATE_reg (`SPC2.tlu.tsd0.arch_pstate0),
1639 .TL_reg (`SPC2.tlu.trl0.tl0),
1640 .PIL_reg (`SPC2.tlu.trl0.pil0),
1641 .TBA_reg (`SPC2.tlu.tsd0.tba0[47:15]),
1642 .VER_reg (`SPC2.tlu.asi.hver_value), // static
1643 .CWP_reg (`SPC2.exu0.rml.cwp_thr0),
1644 .CANSAVE_reg (`SPC2.exu0.rml.cansave_thr0),
1645 .CANRESTORE_reg (`SPC2.exu0.rml.canrestore_thr0),
1646 .OTHERWIN_reg (`SPC2.exu0.rml.otherwin_thr0),
1647 .WSTATE_reg (`SPC2.exu0.rml.wstate_thr0),
1648 .CLEANWIN_reg (`SPC2.exu0.rml.cleanwin_thr0),
1649 .rd_SOFTINT_reg (`SPC2.tlu.trl0.rd_softint0),
1650 .SOFTINT_reg (`SPC2.tlu.trl0.softint0),
1651 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec0),
1652 .GL_reg (`SPC2.tlu.tlu_gl0),
1653 .HPSTATE_reg (`SPC2.tlu.tsd0.arch_hpstate0),
1654 .HTBA_reg (`SPC2.tlu.tsd0.htba0[47:14]),
1655 .HINTP_reg (`SPC2.tlu.trl0.hintp0),
1656
1657 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_0[12:0]}),
1658 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_0[12:0]}),
1659 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_0[12:0]}),
1660 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_0[12:0]}),
1661 .LSU_CONTROL_reg ({29'd0,
1662 `SPC2.lsu.dcs.wpt_mode_0[1:0],
1663 `SPC2.lsu.dcs.wpt_mask_0[7:0],
1664 `SPC2.lsu.dcs.wpt_enable_0[1:0],
1665 18'd0,
1666 `SPC2.lsu.dcs.spec_enable[0],
1667 `SPC2.lsu.dcs.dmmu_enable[0],
1668 `SPC2.lsu.dcs.immu_enable[0],
1669 `SPC2.lsu.dcs.dc_enable[0],
1670 `SPC2.lsu.dcs.ic_enable[0]}),
1671 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.immu_tag_access_0[47:0]}),
1672 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.dmmu_tag_access_0[47:0]}),
1673 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint0[47:3],3'b00}),
1674 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_0[47:0]),
1675
1676 .Trap_Entry_1 (`PROBES2.trap_entry_1_t0),
1677 .Trap_Entry_2 (`PROBES2.trap_entry_2_t0),
1678 .Trap_Entry_3 (`PROBES2.trap_entry_3_t0),
1679 .Trap_Entry_4 (`PROBES2.trap_entry_4_t0),
1680 .Trap_Entry_5 (`PROBES2.trap_entry_5_t0),
1681 .Trap_Entry_6 (`PROBES2.trap_entry_6_t0),
1682
1683 .exu_valid (`PROBES2.ex_valid[0]),
1684
1685 .imul_valid (`PROBES2.imul_valid[0]),
1686
1687 .fp_valid (`PROBES2.fg_valid[0]),
1688 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
1689 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
1690 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
1691
1692 .idiv_valid (`PROBES2.fgu_idiv_valid[0]),
1693
1694 .fdiv_valid (`PROBES2.fgu_fdiv_valid[0]),
1695
1696 .lsu_valid (`PROBES2.lsu_valid[0]),
1697 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
1698 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
1699 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
1700
1701 .asi_valid (`PROBES2.asi_valid_fx5[0]),
1702 .asi_in_progress (`PROBES2.asi_in_progress_fx4[0]),
1703
1704 .tlu_valid (`PROBES2.tlu_valid[0])
1705`endif
1706 );
1707
1708
1709//----------------------------------------------------------
1710//
1711// THREAD 1
1712//
1713
1714 nas_pipe2 t1 (
1715 .mycid (cid),
1716 .mytid (3'h1),
1717
1718// If GATESIM, instantiate "dummy" module with floating ports since unused.
1719`ifdef GATESIM
1720 .opcode () // this and all other ports are unconnected
1721`else
1722 .opcode ({`PROBES2.op_1_w}),
1723 .PC_reg ({`PROBES2.pc_1_w}),
1724 .Y_reg (`SPC2.exu0.rml.arch_yreg_tid1_ff),
1725 .CCR_reg (`SPC2.exu0.ect.arch_ccr_tid1_lth),
1726 .FPRS_reg (`SPC2.fgu.fac.fprs_tid1),
1727 .FSR_reg (`SPC2.fgu.fad.fsr1_fx1[27:0]),
1728 .ASI_reg (`SPC2.lsu.dcs.asi_state1),
1729 .GSR_reg ({`SPC2.fgu.fgd.gsr1_mask_fx4[31:0], `SPC2.fgu.fpc.gsr1_11bits_fx4[10:0]}),
1730 .TICK_CMPR_reg (`PROBES2.tick_cmpr_1),
1731 .STICK_CMPR_reg (`PROBES2.stick_cmpr_1),
1732 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_1),
1733 .PSTATE_reg (`SPC2.tlu.tsd0.arch_pstate1),
1734 .TL_reg (`SPC2.tlu.trl0.tl1),
1735 .PIL_reg (`SPC2.tlu.trl0.pil1),
1736 .TBA_reg (`SPC2.tlu.tsd0.tba1[47:15]),
1737 .VER_reg (`SPC2.tlu.asi.hver_value), // static
1738 .CWP_reg (`SPC2.exu0.rml.cwp_thr1),
1739 .CANSAVE_reg (`SPC2.exu0.rml.cansave_thr1),
1740 .CANRESTORE_reg (`SPC2.exu0.rml.canrestore_thr1),
1741 .OTHERWIN_reg (`SPC2.exu0.rml.otherwin_thr1),
1742 .WSTATE_reg (`SPC2.exu0.rml.wstate_thr1),
1743 .CLEANWIN_reg (`SPC2.exu0.rml.cleanwin_thr1),
1744 .rd_SOFTINT_reg (`SPC2.tlu.trl0.rd_softint1),
1745 .SOFTINT_reg (`SPC2.tlu.trl0.softint1),
1746 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec1),
1747 .GL_reg (`SPC2.tlu.tlu_gl1),
1748 .HPSTATE_reg (`SPC2.tlu.tsd0.arch_hpstate1),
1749 .HTBA_reg (`SPC2.tlu.tsd0.htba1[47:14]),
1750 .HINTP_reg (`SPC2.tlu.trl0.hintp1),
1751
1752 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_1[12:0]}),
1753 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_1[12:0]}),
1754 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_1[12:0]}),
1755 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_1[12:0]}),
1756 .LSU_CONTROL_reg ({29'd0,
1757 `SPC2.lsu.dcs.wpt_mode_1[1:0],
1758 `SPC2.lsu.dcs.wpt_mask_1[7:0],
1759 `SPC2.lsu.dcs.wpt_enable_1[1:0],
1760 18'd0,
1761 `SPC2.lsu.dcs.spec_enable[1],
1762 `SPC2.lsu.dcs.dmmu_enable[1],
1763 `SPC2.lsu.dcs.immu_enable[1],
1764 `SPC2.lsu.dcs.dc_enable[1],
1765 `SPC2.lsu.dcs.ic_enable[1]}),
1766 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.immu_tag_access_1[47:0]}),
1767 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.dmmu_tag_access_1[47:0]}),
1768 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint1[47:3],3'b00}),
1769 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_1[47:0]),
1770
1771 .Trap_Entry_1 (`PROBES2.trap_entry_1_t1),
1772 .Trap_Entry_2 (`PROBES2.trap_entry_2_t1),
1773 .Trap_Entry_3 (`PROBES2.trap_entry_3_t1),
1774 .Trap_Entry_4 (`PROBES2.trap_entry_4_t1),
1775 .Trap_Entry_5 (`PROBES2.trap_entry_5_t1),
1776 .Trap_Entry_6 (`PROBES2.trap_entry_6_t1),
1777
1778 .exu_valid (`PROBES2.ex_valid[1]),
1779
1780 .imul_valid (`PROBES2.imul_valid[1]),
1781
1782 .fp_valid (`PROBES2.fg_valid[1]),
1783 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
1784 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
1785 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
1786
1787 .idiv_valid (`PROBES2.fgu_idiv_valid[1]),
1788
1789 .fdiv_valid (`PROBES2.fgu_fdiv_valid[1]),
1790
1791 .lsu_valid (`PROBES2.lsu_valid[1]),
1792 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
1793 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
1794 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
1795
1796 .asi_valid (`PROBES2.asi_valid_fx5[1]),
1797 .asi_in_progress (`PROBES2.asi_in_progress_fx4[1]),
1798
1799 .tlu_valid (`PROBES2.tlu_valid[1])
1800`endif
1801 );
1802
1803
1804//----------------------------------------------------------
1805//
1806// THREAD 2
1807//
1808
1809 nas_pipe2 t2 (
1810 .mycid (cid),
1811 .mytid (3'h2),
1812
1813// If GATESIM, instantiate "dummy" module with floating ports since unused.
1814`ifdef GATESIM
1815 .opcode () // this and all other ports are unconnected
1816`else
1817 .opcode ({`PROBES2.op_2_w}),
1818 .PC_reg ({`PROBES2.pc_2_w}),
1819 .Y_reg (`SPC2.exu0.rml.arch_yreg_tid2_ff),
1820 .CCR_reg (`SPC2.exu0.ect.arch_ccr_tid2_lth),
1821 .FPRS_reg (`SPC2.fgu.fac.fprs_tid2),
1822 .FSR_reg (`SPC2.fgu.fad.fsr2_fx1[27:0]),
1823 .ASI_reg (`SPC2.lsu.dcs.asi_state2),
1824 .GSR_reg ({`SPC2.fgu.fgd.gsr2_mask_fx4[31:0], `SPC2.fgu.fpc.gsr2_11bits_fx4[10:0]}),
1825 .TICK_CMPR_reg (`PROBES2.tick_cmpr_2),
1826 .STICK_CMPR_reg (`PROBES2.stick_cmpr_2),
1827 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_2),
1828 .PSTATE_reg (`SPC2.tlu.tsd0.arch_pstate2),
1829 .TL_reg (`SPC2.tlu.trl0.tl2),
1830 .PIL_reg (`SPC2.tlu.trl0.pil2),
1831 .TBA_reg (`SPC2.tlu.tsd0.tba2[47:15]),
1832 .VER_reg (`SPC2.tlu.asi.hver_value), // static
1833 .CWP_reg (`SPC2.exu0.rml.cwp_thr2),
1834 .CANSAVE_reg (`SPC2.exu0.rml.cansave_thr2),
1835 .CANRESTORE_reg (`SPC2.exu0.rml.canrestore_thr2),
1836 .OTHERWIN_reg (`SPC2.exu0.rml.otherwin_thr2),
1837 .WSTATE_reg (`SPC2.exu0.rml.wstate_thr2),
1838 .CLEANWIN_reg (`SPC2.exu0.rml.cleanwin_thr2),
1839 .rd_SOFTINT_reg (`SPC2.tlu.trl0.rd_softint2),
1840 .SOFTINT_reg (`SPC2.tlu.trl0.softint2),
1841 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec2),
1842 .GL_reg (`SPC2.tlu.tlu_gl2),
1843 .HPSTATE_reg (`SPC2.tlu.tsd0.arch_hpstate2),
1844 .HTBA_reg (`SPC2.tlu.tsd0.htba2[47:14]),
1845 .HINTP_reg (`SPC2.tlu.trl0.hintp2),
1846
1847 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_2[12:0]}),
1848 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_2[12:0]}),
1849 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_2[12:0]}),
1850 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_2[12:0]}),
1851 .LSU_CONTROL_reg ({29'd0,
1852 `SPC2.lsu.dcs.wpt_mode_2[1:0],
1853 `SPC2.lsu.dcs.wpt_mask_2[7:0],
1854 `SPC2.lsu.dcs.wpt_enable_2[1:0],
1855 18'd0,
1856 `SPC2.lsu.dcs.spec_enable[2],
1857 `SPC2.lsu.dcs.dmmu_enable[2],
1858 `SPC2.lsu.dcs.immu_enable[2],
1859 `SPC2.lsu.dcs.dc_enable[2],
1860 `SPC2.lsu.dcs.ic_enable[2]}),
1861 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.immu_tag_access_2[47:0]}),
1862 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.dmmu_tag_access_2[47:0]}),
1863 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint2[47:3],3'b00}),
1864 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_2[47:0]),
1865
1866 .Trap_Entry_1 (`PROBES2.trap_entry_1_t2),
1867 .Trap_Entry_2 (`PROBES2.trap_entry_2_t2),
1868 .Trap_Entry_3 (`PROBES2.trap_entry_3_t2),
1869 .Trap_Entry_4 (`PROBES2.trap_entry_4_t2),
1870 .Trap_Entry_5 (`PROBES2.trap_entry_5_t2),
1871 .Trap_Entry_6 (`PROBES2.trap_entry_6_t2),
1872
1873 .exu_valid (`PROBES2.ex_valid[2]),
1874
1875 .imul_valid (`PROBES2.imul_valid[2]),
1876
1877 .fp_valid (`PROBES2.fg_valid[2]),
1878 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
1879 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
1880 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
1881
1882 .idiv_valid (`PROBES2.fgu_idiv_valid[2]),
1883
1884 .fdiv_valid (`PROBES2.fgu_fdiv_valid[2]),
1885
1886 .lsu_valid (`PROBES2.lsu_valid[2]),
1887 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
1888 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
1889 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
1890
1891 .asi_valid (`PROBES2.asi_valid_fx5[2]),
1892 .asi_in_progress (`PROBES2.asi_in_progress_fx4[2]),
1893
1894 .tlu_valid (`PROBES2.tlu_valid[2])
1895`endif
1896 );
1897
1898
1899//----------------------------------------------------------
1900//
1901// THREAD 3
1902//
1903
1904 nas_pipe2 t3 (
1905 .mycid (cid),
1906 .mytid (3'h3),
1907
1908// If GATESIM, instantiate "dummy" module with floating ports since unused.
1909`ifdef GATESIM
1910 .opcode () // this and all other ports are unconnected
1911`else
1912 .opcode ({`PROBES2.op_3_w}),
1913 .PC_reg ({`PROBES2.pc_3_w}),
1914 .Y_reg (`SPC2.exu0.rml.arch_yreg_tid3_ff),
1915 .CCR_reg (`SPC2.exu0.ect.arch_ccr_tid3_lth),
1916 .FPRS_reg (`SPC2.fgu.fac.fprs_tid3),
1917 .FSR_reg (`SPC2.fgu.fad.fsr3_fx1[27:0]),
1918 .ASI_reg (`SPC2.lsu.dcs.asi_state3),
1919 .GSR_reg ({`SPC2.fgu.fgd.gsr3_mask_fx4[31:0], `SPC2.fgu.fpc.gsr3_11bits_fx4[10:0]}),
1920 .TICK_CMPR_reg (`PROBES2.tick_cmpr_3),
1921 .STICK_CMPR_reg (`PROBES2.stick_cmpr_3),
1922 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_3),
1923 .PSTATE_reg (`SPC2.tlu.tsd0.arch_pstate3),
1924 .TL_reg (`SPC2.tlu.trl0.tl3),
1925 .PIL_reg (`SPC2.tlu.trl0.pil3),
1926 .TBA_reg (`SPC2.tlu.tsd0.tba3[47:15]),
1927 .VER_reg (`SPC2.tlu.asi.hver_value), // static
1928 .CWP_reg (`SPC2.exu0.rml.cwp_thr3),
1929 .CANSAVE_reg (`SPC2.exu0.rml.cansave_thr3),
1930 .CANRESTORE_reg (`SPC2.exu0.rml.canrestore_thr3),
1931 .OTHERWIN_reg (`SPC2.exu0.rml.otherwin_thr3),
1932 .WSTATE_reg (`SPC2.exu0.rml.wstate_thr3),
1933 .CLEANWIN_reg (`SPC2.exu0.rml.cleanwin_thr3),
1934 .rd_SOFTINT_reg (`SPC2.tlu.trl0.rd_softint3),
1935 .SOFTINT_reg (`SPC2.tlu.trl0.softint3),
1936 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec3),
1937 .GL_reg (`SPC2.tlu.tlu_gl3),
1938 .HPSTATE_reg (`SPC2.tlu.tsd0.arch_hpstate3),
1939 .HTBA_reg (`SPC2.tlu.tsd0.htba3[47:14]),
1940 .HINTP_reg (`SPC2.tlu.trl0.hintp3),
1941
1942 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_3[12:0]}),
1943 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_3[12:0]}),
1944 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_3[12:0]}),
1945 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_3[12:0]}),
1946 .LSU_CONTROL_reg ({29'd0,
1947 `SPC2.lsu.dcs.wpt_mode_3[1:0],
1948 `SPC2.lsu.dcs.wpt_mask_3[7:0],
1949 `SPC2.lsu.dcs.wpt_enable_3[1:0],
1950 18'd0,
1951 `SPC2.lsu.dcs.spec_enable[3],
1952 `SPC2.lsu.dcs.dmmu_enable[3],
1953 `SPC2.lsu.dcs.immu_enable[3],
1954 `SPC2.lsu.dcs.dc_enable[3],
1955 `SPC2.lsu.dcs.ic_enable[3]}),
1956 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.immu_tag_access_3[47:0]}),
1957 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd0.dmmu_tag_access_3[47:0]}),
1958 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint3[47:3],3'b00}),
1959 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_3[47:0]),
1960
1961 .Trap_Entry_1 (`PROBES2.trap_entry_1_t3),
1962 .Trap_Entry_2 (`PROBES2.trap_entry_2_t3),
1963 .Trap_Entry_3 (`PROBES2.trap_entry_3_t3),
1964 .Trap_Entry_4 (`PROBES2.trap_entry_4_t3),
1965 .Trap_Entry_5 (`PROBES2.trap_entry_5_t3),
1966 .Trap_Entry_6 (`PROBES2.trap_entry_6_t3),
1967
1968 .exu_valid (`PROBES2.ex_valid[3]),
1969
1970 .imul_valid (`PROBES2.imul_valid[3]),
1971
1972 .fp_valid (`PROBES2.fg_valid[3]),
1973 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
1974 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
1975 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
1976
1977 .idiv_valid (`PROBES2.fgu_idiv_valid[3]),
1978
1979 .fdiv_valid (`PROBES2.fgu_fdiv_valid[3]),
1980
1981 .lsu_valid (`PROBES2.lsu_valid[3]),
1982 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
1983 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
1984 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
1985
1986 .asi_valid (`PROBES2.asi_valid_fx5[3]),
1987 .asi_in_progress (`PROBES2.asi_in_progress_fx4[3]),
1988
1989 .tlu_valid (`PROBES2.tlu_valid[3])
1990`endif
1991 );
1992
1993
1994//----------------------------------------------------------
1995//
1996// THREAD 4
1997//
1998
1999 nas_pipe2 t4 (
2000 .mycid (cid),
2001 .mytid (3'h4),
2002
2003// If GATESIM, instantiate "dummy" module with floating ports since unused.
2004`ifdef GATESIM
2005 .opcode () // this and all other ports are unconnected
2006`else
2007 .opcode ({`PROBES2.op_4_w}),
2008 .PC_reg ({`PROBES2.pc_4_w}),
2009 .Y_reg (`SPC2.exu1.rml.arch_yreg_tid0_ff),
2010 .CCR_reg (`SPC2.exu1.ect.arch_ccr_tid0_lth),
2011 .FPRS_reg (`SPC2.fgu.fac.fprs_tid4),
2012 .FSR_reg (`SPC2.fgu.fad.fsr4_fx1[27:0]),
2013 .ASI_reg (`SPC2.lsu.dcs.asi_state4),
2014 .GSR_reg ({`SPC2.fgu.fgd.gsr4_mask_fx4[31:0], `SPC2.fgu.fpc.gsr4_11bits_fx4[10:0]}),
2015 .TICK_CMPR_reg (`PROBES2.tick_cmpr_4),
2016 .STICK_CMPR_reg (`PROBES2.stick_cmpr_4),
2017 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_4),
2018 .PSTATE_reg (`SPC2.tlu.tsd1.arch_pstate0),
2019 .TL_reg (`SPC2.tlu.trl1.tl0),
2020 .PIL_reg (`SPC2.tlu.trl1.pil0),
2021 .TBA_reg (`SPC2.tlu.tsd1.tba0[47:15]),
2022 .VER_reg (`SPC2.tlu.asi.hver_value), // static
2023 .CWP_reg (`SPC2.exu1.rml.cwp_thr0),
2024 .CANSAVE_reg (`SPC2.exu1.rml.cansave_thr0),
2025 .CANRESTORE_reg (`SPC2.exu1.rml.canrestore_thr0),
2026 .OTHERWIN_reg (`SPC2.exu1.rml.otherwin_thr0),
2027 .WSTATE_reg (`SPC2.exu1.rml.wstate_thr0),
2028 .CLEANWIN_reg (`SPC2.exu1.rml.cleanwin_thr0),
2029 .rd_SOFTINT_reg (`SPC2.tlu.trl1.rd_softint0),
2030 .SOFTINT_reg (`SPC2.tlu.trl1.softint0),
2031 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec4),
2032 .GL_reg (`SPC2.tlu.tlu_gl4),
2033 .HPSTATE_reg (`SPC2.tlu.tsd1.arch_hpstate0),
2034 .HTBA_reg (`SPC2.tlu.tsd1.htba0[47:14]),
2035 .HINTP_reg (`SPC2.tlu.trl1.hintp0),
2036
2037 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_4[12:0]}),
2038 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_4[12:0]}),
2039 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_4[12:0]}),
2040 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_4[12:0]}),
2041 .LSU_CONTROL_reg ({29'd0,
2042 `SPC2.lsu.dcs.wpt_mode_4[1:0],
2043 `SPC2.lsu.dcs.wpt_mask_4[7:0],
2044 `SPC2.lsu.dcs.wpt_enable_4[1:0],
2045 18'd0,
2046 `SPC2.lsu.dcs.spec_enable[4],
2047 `SPC2.lsu.dcs.dmmu_enable[4],
2048 `SPC2.lsu.dcs.immu_enable[4],
2049 `SPC2.lsu.dcs.dc_enable[4],
2050 `SPC2.lsu.dcs.ic_enable[4]}),
2051 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.immu_tag_access_0[47:0]}),
2052 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.dmmu_tag_access_0[47:0]}),
2053 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint4[47:3],3'b00}),
2054 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_4[47:0]),
2055
2056 .Trap_Entry_1 (`PROBES2.trap_entry_1_t4),
2057 .Trap_Entry_2 (`PROBES2.trap_entry_2_t4),
2058 .Trap_Entry_3 (`PROBES2.trap_entry_3_t4),
2059 .Trap_Entry_4 (`PROBES2.trap_entry_4_t4),
2060 .Trap_Entry_5 (`PROBES2.trap_entry_5_t4),
2061 .Trap_Entry_6 (`PROBES2.trap_entry_6_t4),
2062
2063 .exu_valid (`PROBES2.ex_valid[4]),
2064
2065 .imul_valid (`PROBES2.imul_valid[4]),
2066
2067 .fp_valid (`PROBES2.fg_valid[4]),
2068 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
2069 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
2070 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
2071
2072 .idiv_valid (`PROBES2.fgu_idiv_valid[4]),
2073
2074 .fdiv_valid (`PROBES2.fgu_fdiv_valid[4]),
2075
2076 .lsu_valid (`PROBES2.lsu_valid[4]),
2077 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
2078 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
2079 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
2080
2081 .asi_valid (`PROBES2.asi_valid_fx5[4]),
2082 .asi_in_progress (`PROBES2.asi_in_progress_fx4[4]),
2083
2084 .tlu_valid (`PROBES2.tlu_valid[4])
2085`endif
2086 );
2087
2088
2089//----------------------------------------------------------
2090//
2091// THREAD 5
2092//
2093
2094 nas_pipe2 t5 (
2095 .mycid (cid),
2096 .mytid (3'h5),
2097
2098// If GATESIM, instantiate "dummy" module with floating ports since unused.
2099`ifdef GATESIM
2100 .opcode () // this and all other ports are unconnected
2101`else
2102 .opcode ({`PROBES2.op_5_w}),
2103 .PC_reg ({`PROBES2.pc_5_w}),
2104 .Y_reg (`SPC2.exu1.rml.arch_yreg_tid1_ff),
2105 .CCR_reg (`SPC2.exu1.ect.arch_ccr_tid1_lth),
2106 .FPRS_reg (`SPC2.fgu.fac.fprs_tid5),
2107 .FSR_reg (`SPC2.fgu.fad.fsr5_fx1[27:0]),
2108 .ASI_reg (`SPC2.lsu.dcs.asi_state5),
2109 .GSR_reg ({`SPC2.fgu.fgd.gsr5_mask_fx4[31:0], `SPC2.fgu.fpc.gsr5_11bits_fx4[10:0]}),
2110 .TICK_CMPR_reg (`PROBES2.tick_cmpr_5),
2111 .STICK_CMPR_reg (`PROBES2.stick_cmpr_5),
2112 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_5),
2113 .PSTATE_reg (`SPC2.tlu.tsd1.arch_pstate1),
2114 .TL_reg (`SPC2.tlu.trl1.tl1),
2115 .PIL_reg (`SPC2.tlu.trl1.pil1),
2116 .TBA_reg (`SPC2.tlu.tsd1.tba1[47:15]),
2117 .VER_reg (`SPC2.tlu.asi.hver_value), // static
2118 .CWP_reg (`SPC2.exu1.rml.cwp_thr1),
2119 .CANSAVE_reg (`SPC2.exu1.rml.cansave_thr1),
2120 .CANRESTORE_reg (`SPC2.exu1.rml.canrestore_thr1),
2121 .OTHERWIN_reg (`SPC2.exu1.rml.otherwin_thr1),
2122 .WSTATE_reg (`SPC2.exu1.rml.wstate_thr1),
2123 .CLEANWIN_reg (`SPC2.exu1.rml.cleanwin_thr1),
2124 .rd_SOFTINT_reg (`SPC2.tlu.trl1.rd_softint1),
2125 .SOFTINT_reg (`SPC2.tlu.trl1.softint1),
2126 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec5),
2127 .GL_reg (`SPC2.tlu.tlu_gl5),
2128 .HPSTATE_reg (`SPC2.tlu.tsd1.arch_hpstate1),
2129 .HTBA_reg (`SPC2.tlu.tsd1.htba1[47:14]),
2130 .HINTP_reg (`SPC2.tlu.trl1.hintp1),
2131
2132 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_5[12:0]}),
2133 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_5[12:0]}),
2134 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_5[12:0]}),
2135 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_5[12:0]}),
2136 .LSU_CONTROL_reg ({29'd0,
2137 `SPC2.lsu.dcs.wpt_mode_5[1:0],
2138 `SPC2.lsu.dcs.wpt_mask_5[7:0],
2139 `SPC2.lsu.dcs.wpt_enable_5[1:0],
2140 18'd0,
2141 `SPC2.lsu.dcs.spec_enable[5],
2142 `SPC2.lsu.dcs.dmmu_enable[5],
2143 `SPC2.lsu.dcs.immu_enable[5],
2144 `SPC2.lsu.dcs.dc_enable[5],
2145 `SPC2.lsu.dcs.ic_enable[5]}),
2146 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.immu_tag_access_1[47:0]}),
2147 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.dmmu_tag_access_1[47:0]}),
2148 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint5[47:3],3'b00}),
2149 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_5[47:0]),
2150
2151 .Trap_Entry_1 (`PROBES2.trap_entry_1_t5),
2152 .Trap_Entry_2 (`PROBES2.trap_entry_2_t5),
2153 .Trap_Entry_3 (`PROBES2.trap_entry_3_t5),
2154 .Trap_Entry_4 (`PROBES2.trap_entry_4_t5),
2155 .Trap_Entry_5 (`PROBES2.trap_entry_5_t5),
2156 .Trap_Entry_6 (`PROBES2.trap_entry_6_t5),
2157
2158 .exu_valid (`PROBES2.ex_valid[5]),
2159
2160 .imul_valid (`PROBES2.imul_valid[5]),
2161
2162 .fp_valid (`PROBES2.fg_valid[5]),
2163 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
2164 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
2165 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
2166
2167 .idiv_valid (`PROBES2.fgu_idiv_valid[5]),
2168
2169 .fdiv_valid (`PROBES2.fgu_fdiv_valid[5]),
2170
2171 .lsu_valid (`PROBES2.lsu_valid[5]),
2172 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
2173 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
2174 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
2175
2176 .asi_valid (`PROBES2.asi_valid_fx5[5]),
2177 .asi_in_progress (`PROBES2.asi_in_progress_fx4[5]),
2178
2179 .tlu_valid (`PROBES2.tlu_valid[5])
2180`endif
2181 );
2182
2183
2184//----------------------------------------------------------
2185//
2186// THREAD 6
2187//
2188
2189 nas_pipe2 t6 (
2190 .mycid (cid),
2191 .mytid (3'h6),
2192
2193// If GATESIM, instantiate "dummy" module with floating ports since unused.
2194`ifdef GATESIM
2195 .opcode () // this and all other ports are unconnected
2196`else
2197 .opcode ({`PROBES2.op_6_w}),
2198 .PC_reg ({`PROBES2.pc_6_w}),
2199 .Y_reg (`SPC2.exu1.rml.arch_yreg_tid2_ff),
2200 .CCR_reg (`SPC2.exu1.ect.arch_ccr_tid2_lth),
2201 .FPRS_reg (`SPC2.fgu.fac.fprs_tid6),
2202 .FSR_reg (`SPC2.fgu.fad.fsr6_fx1[27:0]),
2203 .ASI_reg (`SPC2.lsu.dcs.asi_state6),
2204 .GSR_reg ({`SPC2.fgu.fgd.gsr6_mask_fx4[31:0], `SPC2.fgu.fpc.gsr6_11bits_fx4[10:0]}),
2205 .TICK_CMPR_reg (`PROBES2.tick_cmpr_6),
2206 .STICK_CMPR_reg (`PROBES2.stick_cmpr_6),
2207 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_6),
2208 .PSTATE_reg (`SPC2.tlu.tsd1.arch_pstate2),
2209 .TL_reg (`SPC2.tlu.trl1.tl2),
2210 .PIL_reg (`SPC2.tlu.trl1.pil2),
2211 .TBA_reg (`SPC2.tlu.tsd1.tba2[47:15]),
2212 .VER_reg (`SPC2.tlu.asi.hver_value), // static
2213 .CWP_reg (`SPC2.exu1.rml.cwp_thr2),
2214 .CANSAVE_reg (`SPC2.exu1.rml.cansave_thr2),
2215 .CANRESTORE_reg (`SPC2.exu1.rml.canrestore_thr2),
2216 .OTHERWIN_reg (`SPC2.exu1.rml.otherwin_thr2),
2217 .WSTATE_reg (`SPC2.exu1.rml.wstate_thr2),
2218 .CLEANWIN_reg (`SPC2.exu1.rml.cleanwin_thr2),
2219 .rd_SOFTINT_reg (`SPC2.tlu.trl1.rd_softint2),
2220 .SOFTINT_reg (`SPC2.tlu.trl1.softint2),
2221 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec6),
2222 .GL_reg (`SPC2.tlu.tlu_gl6),
2223 .HPSTATE_reg (`SPC2.tlu.tsd1.arch_hpstate2),
2224 .HTBA_reg (`SPC2.tlu.tsd1.htba2[47:14]),
2225 .HINTP_reg (`SPC2.tlu.trl1.hintp2),
2226
2227 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_6[12:0]}),
2228 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_6[12:0]}),
2229 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_6[12:0]}),
2230 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_6[12:0]}),
2231 .LSU_CONTROL_reg ({29'd0,
2232 `SPC2.lsu.dcs.wpt_mode_6[1:0],
2233 `SPC2.lsu.dcs.wpt_mask_6[7:0],
2234 `SPC2.lsu.dcs.wpt_enable_6[1:0],
2235 18'd0,
2236 `SPC2.lsu.dcs.spec_enable[6],
2237 `SPC2.lsu.dcs.dmmu_enable[6],
2238 `SPC2.lsu.dcs.immu_enable[6],
2239 `SPC2.lsu.dcs.dc_enable[6],
2240 `SPC2.lsu.dcs.ic_enable[6]}),
2241 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.immu_tag_access_2[47:0]}),
2242 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.dmmu_tag_access_2[47:0]}),
2243 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint6[47:3],3'b00}),
2244 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_6[47:0]),
2245
2246 .Trap_Entry_1 (`PROBES2.trap_entry_1_t6),
2247 .Trap_Entry_2 (`PROBES2.trap_entry_2_t6),
2248 .Trap_Entry_3 (`PROBES2.trap_entry_3_t6),
2249 .Trap_Entry_4 (`PROBES2.trap_entry_4_t6),
2250 .Trap_Entry_5 (`PROBES2.trap_entry_5_t6),
2251 .Trap_Entry_6 (`PROBES2.trap_entry_6_t6),
2252
2253 .exu_valid (`PROBES2.ex_valid[6]),
2254
2255 .imul_valid (`PROBES2.imul_valid[6]),
2256
2257 .fp_valid (`PROBES2.fg_valid[6]),
2258 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
2259 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
2260 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
2261
2262 .idiv_valid (`PROBES2.fgu_idiv_valid[6]),
2263
2264 .fdiv_valid (`PROBES2.fgu_fdiv_valid[6]),
2265
2266 .lsu_valid (`PROBES2.lsu_valid[6]),
2267 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
2268 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
2269 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
2270
2271 .asi_valid (`PROBES2.asi_valid_fx5[6]),
2272 .asi_in_progress (`PROBES2.asi_in_progress_fx4[6]),
2273
2274 .tlu_valid (`PROBES2.tlu_valid[6])
2275`endif
2276 );
2277
2278
2279//----------------------------------------------------------
2280//
2281// THREAD 7
2282//
2283
2284 nas_pipe2 t7 (
2285 .mycid (cid),
2286 .mytid (3'h7),
2287
2288// If GATESIM, instantiate "dummy" module with floating ports since unused.
2289`ifdef GATESIM
2290 .opcode () // this and all other ports are unconnected
2291`else
2292 .opcode ({`PROBES2.op_7_w}),
2293 .PC_reg ({`PROBES2.pc_7_w}),
2294 .Y_reg (`SPC2.exu1.rml.arch_yreg_tid3_ff),
2295 .CCR_reg (`SPC2.exu1.ect.arch_ccr_tid3_lth),
2296 .FPRS_reg (`SPC2.fgu.fac.fprs_tid7),
2297 .FSR_reg (`SPC2.fgu.fad.fsr7_fx1[27:0]),
2298 .ASI_reg (`SPC2.lsu.dcs.asi_state7),
2299 .GSR_reg ({`SPC2.fgu.fgd.gsr7_mask_fx4[31:0], `SPC2.fgu.fpc.gsr7_11bits_fx4[10:0]}),
2300 .TICK_CMPR_reg (`PROBES2.tick_cmpr_7),
2301 .STICK_CMPR_reg (`PROBES2.stick_cmpr_7),
2302 .HSTICK_CMPR_reg (`PROBES2.hstick_cmpr_7),
2303 .PSTATE_reg (`SPC2.tlu.tsd1.arch_pstate3),
2304 .TL_reg (`SPC2.tlu.trl1.tl3),
2305 .PIL_reg (`SPC2.tlu.trl1.pil3),
2306 .TBA_reg (`SPC2.tlu.tsd1.tba3[47:15]),
2307 .VER_reg (`SPC2.tlu.asi.hver_value), // static
2308 .CWP_reg (`SPC2.exu1.rml.cwp_thr3),
2309 .CANSAVE_reg (`SPC2.exu1.rml.cansave_thr3),
2310 .CANRESTORE_reg (`SPC2.exu1.rml.canrestore_thr3),
2311 .OTHERWIN_reg (`SPC2.exu1.rml.otherwin_thr3),
2312 .WSTATE_reg (`SPC2.exu1.rml.wstate_thr3),
2313 .CLEANWIN_reg (`SPC2.exu1.rml.cleanwin_thr3),
2314 .rd_SOFTINT_reg (`SPC2.tlu.trl1.rd_softint3),
2315 .SOFTINT_reg (`SPC2.tlu.trl1.softint3),
2316 .INTR_RECEIVE_reg (`SPC2.tlu.cth.int_rec7),
2317 .GL_reg (`SPC2.tlu.tlu_gl7),
2318 .HPSTATE_reg (`SPC2.tlu.tsd1.arch_hpstate3),
2319 .HTBA_reg (`SPC2.tlu.tsd1.htba3[47:14]),
2320 .HINTP_reg (`SPC2.tlu.trl1.hintp3),
2321
2322 .CTXT_PRIM_0_reg ({51'b0,`SPC2.lsu.dcs.p0ctxt_7[12:0]}),
2323 .CTXT_SEC_0_reg ({51'b0,`SPC2.lsu.dcs.s0ctxt_7[12:0]}),
2324 .CTXT_PRIM_1_reg ({51'b0,`SPC2.lsu.dcs.p1ctxt_7[12:0]}),
2325 .CTXT_SEC_1_reg ({51'b0,`SPC2.lsu.dcs.s1ctxt_7[12:0]}),
2326 .LSU_CONTROL_reg ({29'd0,
2327 `SPC2.lsu.dcs.wpt_mode_7[1:0],
2328 `SPC2.lsu.dcs.wpt_mask_7[7:0],
2329 `SPC2.lsu.dcs.wpt_enable_7[1:0],
2330 18'd0,
2331 `SPC2.lsu.dcs.spec_enable[7],
2332 `SPC2.lsu.dcs.dmmu_enable[7],
2333 `SPC2.lsu.dcs.immu_enable[7],
2334 `SPC2.lsu.dcs.dc_enable[7],
2335 `SPC2.lsu.dcs.ic_enable[7]}),
2336 .I_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.immu_tag_access_3[47:0]}),
2337 .D_TAG_ACC_reg ({16'b0,`SPC2.mmu.asd1.dmmu_tag_access_3[47:0]}),
2338 .WATCHPOINT_ADDR_reg ({16'b0,`SPC2.lsu.dcs.watchpoint7[47:3],3'b00}),
2339 .DSFAR_reg (`SPC2.tlu.dfd.dsfar_7[47:0]),
2340
2341 .Trap_Entry_1 (`PROBES2.trap_entry_1_t7),
2342 .Trap_Entry_2 (`PROBES2.trap_entry_2_t7),
2343 .Trap_Entry_3 (`PROBES2.trap_entry_3_t7),
2344 .Trap_Entry_4 (`PROBES2.trap_entry_4_t7),
2345 .Trap_Entry_5 (`PROBES2.trap_entry_5_t7),
2346 .Trap_Entry_6 (`PROBES2.trap_entry_6_t7),
2347
2348 .exu_valid (`PROBES2.ex_valid[7]),
2349
2350 .imul_valid (`PROBES2.imul_valid[7]),
2351
2352 .fp_valid (`PROBES2.fg_valid[7]),
2353 .frf_w1_valid (`SPC2.fgu.frf.w1_valid),
2354 .frf_w1_tid (`SPC2.fgu.frf.w1_tid),
2355 .frf_w1_addr (`SPC2.fgu.frf.w1_addr),
2356
2357 .idiv_valid (`PROBES2.fgu_idiv_valid[7]),
2358
2359 .fdiv_valid (`PROBES2.fgu_fdiv_valid[7]),
2360
2361 .lsu_valid (`PROBES2.lsu_valid[7]),
2362 .frf_w2_valid (`SPC2.fgu.frf.w2_valid),
2363 .frf_w2_tid (`SPC2.fgu.frf.w2_tid),
2364 .frf_w2_addr (`SPC2.fgu.frf.w2_addr),
2365
2366 .asi_valid (`PROBES2.asi_valid_fx5[7]),
2367 .asi_in_progress (`PROBES2.asi_in_progress_fx4[7]),
2368
2369 .tlu_valid (`PROBES2.tlu_valid[7])
2370`endif
2371 );
2372
2373//----------------------------------------------------------
2374
2375
2376//----------------------------------------------------------
2377endmodule
2378
2379`endif
2380
2381`ifdef CORE_3
2382
2383module nas_core3 (
2384
2385 cid
2386);
2387
2388input [2:0] cid;
2389
2390integer i;
2391
2392//----------------------------------------------------------
2393
2394//----------------------------------------------------------
2395
2396//----------------------------------------------------------
2397//
2398// THREAD 0
2399//
2400
2401 nas_pipe3 t0 (
2402 .mycid (cid),
2403 .mytid (3'h0),
2404
2405// If GATESIM, instantiate "dummy" module with floating ports since unused.
2406`ifdef GATESIM
2407 .opcode () // this and all other ports are unconnected
2408`else
2409 .opcode ({`PROBES3.op_0_w}),
2410 .PC_reg ({`PROBES3.pc_0_w}),
2411 .Y_reg (`SPC3.exu0.rml.arch_yreg_tid0_ff),
2412 .CCR_reg (`SPC3.exu0.ect.arch_ccr_tid0_lth),
2413 .FPRS_reg (`SPC3.fgu.fac.fprs_tid0),
2414 .FSR_reg (`SPC3.fgu.fad.fsr0_fx1[27:0]),
2415 .ASI_reg (`SPC3.lsu.dcs.asi_state0),
2416 .GSR_reg ({`SPC3.fgu.fgd.gsr0_mask_fx4[31:0], `SPC3.fgu.fpc.gsr0_11bits_fx4[10:0]}),
2417 .TICK_CMPR_reg (`PROBES3.tick_cmpr_0),
2418 .STICK_CMPR_reg (`PROBES3.stick_cmpr_0),
2419 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_0),
2420 .PSTATE_reg (`SPC3.tlu.tsd0.arch_pstate0),
2421 .TL_reg (`SPC3.tlu.trl0.tl0),
2422 .PIL_reg (`SPC3.tlu.trl0.pil0),
2423 .TBA_reg (`SPC3.tlu.tsd0.tba0[47:15]),
2424 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2425 .CWP_reg (`SPC3.exu0.rml.cwp_thr0),
2426 .CANSAVE_reg (`SPC3.exu0.rml.cansave_thr0),
2427 .CANRESTORE_reg (`SPC3.exu0.rml.canrestore_thr0),
2428 .OTHERWIN_reg (`SPC3.exu0.rml.otherwin_thr0),
2429 .WSTATE_reg (`SPC3.exu0.rml.wstate_thr0),
2430 .CLEANWIN_reg (`SPC3.exu0.rml.cleanwin_thr0),
2431 .rd_SOFTINT_reg (`SPC3.tlu.trl0.rd_softint0),
2432 .SOFTINT_reg (`SPC3.tlu.trl0.softint0),
2433 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec0),
2434 .GL_reg (`SPC3.tlu.tlu_gl0),
2435 .HPSTATE_reg (`SPC3.tlu.tsd0.arch_hpstate0),
2436 .HTBA_reg (`SPC3.tlu.tsd0.htba0[47:14]),
2437 .HINTP_reg (`SPC3.tlu.trl0.hintp0),
2438
2439 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_0[12:0]}),
2440 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_0[12:0]}),
2441 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_0[12:0]}),
2442 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_0[12:0]}),
2443 .LSU_CONTROL_reg ({29'd0,
2444 `SPC3.lsu.dcs.wpt_mode_0[1:0],
2445 `SPC3.lsu.dcs.wpt_mask_0[7:0],
2446 `SPC3.lsu.dcs.wpt_enable_0[1:0],
2447 18'd0,
2448 `SPC3.lsu.dcs.spec_enable[0],
2449 `SPC3.lsu.dcs.dmmu_enable[0],
2450 `SPC3.lsu.dcs.immu_enable[0],
2451 `SPC3.lsu.dcs.dc_enable[0],
2452 `SPC3.lsu.dcs.ic_enable[0]}),
2453 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.immu_tag_access_0[47:0]}),
2454 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.dmmu_tag_access_0[47:0]}),
2455 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint0[47:3],3'b00}),
2456 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_0[47:0]),
2457
2458 .Trap_Entry_1 (`PROBES3.trap_entry_1_t0),
2459 .Trap_Entry_2 (`PROBES3.trap_entry_2_t0),
2460 .Trap_Entry_3 (`PROBES3.trap_entry_3_t0),
2461 .Trap_Entry_4 (`PROBES3.trap_entry_4_t0),
2462 .Trap_Entry_5 (`PROBES3.trap_entry_5_t0),
2463 .Trap_Entry_6 (`PROBES3.trap_entry_6_t0),
2464
2465 .exu_valid (`PROBES3.ex_valid[0]),
2466
2467 .imul_valid (`PROBES3.imul_valid[0]),
2468
2469 .fp_valid (`PROBES3.fg_valid[0]),
2470 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2471 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2472 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2473
2474 .idiv_valid (`PROBES3.fgu_idiv_valid[0]),
2475
2476 .fdiv_valid (`PROBES3.fgu_fdiv_valid[0]),
2477
2478 .lsu_valid (`PROBES3.lsu_valid[0]),
2479 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2480 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2481 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2482
2483 .asi_valid (`PROBES3.asi_valid_fx5[0]),
2484 .asi_in_progress (`PROBES3.asi_in_progress_fx4[0]),
2485
2486 .tlu_valid (`PROBES3.tlu_valid[0])
2487`endif
2488 );
2489
2490
2491//----------------------------------------------------------
2492//
2493// THREAD 1
2494//
2495
2496 nas_pipe3 t1 (
2497 .mycid (cid),
2498 .mytid (3'h1),
2499
2500// If GATESIM, instantiate "dummy" module with floating ports since unused.
2501`ifdef GATESIM
2502 .opcode () // this and all other ports are unconnected
2503`else
2504 .opcode ({`PROBES3.op_1_w}),
2505 .PC_reg ({`PROBES3.pc_1_w}),
2506 .Y_reg (`SPC3.exu0.rml.arch_yreg_tid1_ff),
2507 .CCR_reg (`SPC3.exu0.ect.arch_ccr_tid1_lth),
2508 .FPRS_reg (`SPC3.fgu.fac.fprs_tid1),
2509 .FSR_reg (`SPC3.fgu.fad.fsr1_fx1[27:0]),
2510 .ASI_reg (`SPC3.lsu.dcs.asi_state1),
2511 .GSR_reg ({`SPC3.fgu.fgd.gsr1_mask_fx4[31:0], `SPC3.fgu.fpc.gsr1_11bits_fx4[10:0]}),
2512 .TICK_CMPR_reg (`PROBES3.tick_cmpr_1),
2513 .STICK_CMPR_reg (`PROBES3.stick_cmpr_1),
2514 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_1),
2515 .PSTATE_reg (`SPC3.tlu.tsd0.arch_pstate1),
2516 .TL_reg (`SPC3.tlu.trl0.tl1),
2517 .PIL_reg (`SPC3.tlu.trl0.pil1),
2518 .TBA_reg (`SPC3.tlu.tsd0.tba1[47:15]),
2519 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2520 .CWP_reg (`SPC3.exu0.rml.cwp_thr1),
2521 .CANSAVE_reg (`SPC3.exu0.rml.cansave_thr1),
2522 .CANRESTORE_reg (`SPC3.exu0.rml.canrestore_thr1),
2523 .OTHERWIN_reg (`SPC3.exu0.rml.otherwin_thr1),
2524 .WSTATE_reg (`SPC3.exu0.rml.wstate_thr1),
2525 .CLEANWIN_reg (`SPC3.exu0.rml.cleanwin_thr1),
2526 .rd_SOFTINT_reg (`SPC3.tlu.trl0.rd_softint1),
2527 .SOFTINT_reg (`SPC3.tlu.trl0.softint1),
2528 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec1),
2529 .GL_reg (`SPC3.tlu.tlu_gl1),
2530 .HPSTATE_reg (`SPC3.tlu.tsd0.arch_hpstate1),
2531 .HTBA_reg (`SPC3.tlu.tsd0.htba1[47:14]),
2532 .HINTP_reg (`SPC3.tlu.trl0.hintp1),
2533
2534 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_1[12:0]}),
2535 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_1[12:0]}),
2536 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_1[12:0]}),
2537 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_1[12:0]}),
2538 .LSU_CONTROL_reg ({29'd0,
2539 `SPC3.lsu.dcs.wpt_mode_1[1:0],
2540 `SPC3.lsu.dcs.wpt_mask_1[7:0],
2541 `SPC3.lsu.dcs.wpt_enable_1[1:0],
2542 18'd0,
2543 `SPC3.lsu.dcs.spec_enable[1],
2544 `SPC3.lsu.dcs.dmmu_enable[1],
2545 `SPC3.lsu.dcs.immu_enable[1],
2546 `SPC3.lsu.dcs.dc_enable[1],
2547 `SPC3.lsu.dcs.ic_enable[1]}),
2548 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.immu_tag_access_1[47:0]}),
2549 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.dmmu_tag_access_1[47:0]}),
2550 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint1[47:3],3'b00}),
2551 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_1[47:0]),
2552
2553 .Trap_Entry_1 (`PROBES3.trap_entry_1_t1),
2554 .Trap_Entry_2 (`PROBES3.trap_entry_2_t1),
2555 .Trap_Entry_3 (`PROBES3.trap_entry_3_t1),
2556 .Trap_Entry_4 (`PROBES3.trap_entry_4_t1),
2557 .Trap_Entry_5 (`PROBES3.trap_entry_5_t1),
2558 .Trap_Entry_6 (`PROBES3.trap_entry_6_t1),
2559
2560 .exu_valid (`PROBES3.ex_valid[1]),
2561
2562 .imul_valid (`PROBES3.imul_valid[1]),
2563
2564 .fp_valid (`PROBES3.fg_valid[1]),
2565 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2566 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2567 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2568
2569 .idiv_valid (`PROBES3.fgu_idiv_valid[1]),
2570
2571 .fdiv_valid (`PROBES3.fgu_fdiv_valid[1]),
2572
2573 .lsu_valid (`PROBES3.lsu_valid[1]),
2574 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2575 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2576 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2577
2578 .asi_valid (`PROBES3.asi_valid_fx5[1]),
2579 .asi_in_progress (`PROBES3.asi_in_progress_fx4[1]),
2580
2581 .tlu_valid (`PROBES3.tlu_valid[1])
2582`endif
2583 );
2584
2585
2586//----------------------------------------------------------
2587//
2588// THREAD 2
2589//
2590
2591 nas_pipe3 t2 (
2592 .mycid (cid),
2593 .mytid (3'h2),
2594
2595// If GATESIM, instantiate "dummy" module with floating ports since unused.
2596`ifdef GATESIM
2597 .opcode () // this and all other ports are unconnected
2598`else
2599 .opcode ({`PROBES3.op_2_w}),
2600 .PC_reg ({`PROBES3.pc_2_w}),
2601 .Y_reg (`SPC3.exu0.rml.arch_yreg_tid2_ff),
2602 .CCR_reg (`SPC3.exu0.ect.arch_ccr_tid2_lth),
2603 .FPRS_reg (`SPC3.fgu.fac.fprs_tid2),
2604 .FSR_reg (`SPC3.fgu.fad.fsr2_fx1[27:0]),
2605 .ASI_reg (`SPC3.lsu.dcs.asi_state2),
2606 .GSR_reg ({`SPC3.fgu.fgd.gsr2_mask_fx4[31:0], `SPC3.fgu.fpc.gsr2_11bits_fx4[10:0]}),
2607 .TICK_CMPR_reg (`PROBES3.tick_cmpr_2),
2608 .STICK_CMPR_reg (`PROBES3.stick_cmpr_2),
2609 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_2),
2610 .PSTATE_reg (`SPC3.tlu.tsd0.arch_pstate2),
2611 .TL_reg (`SPC3.tlu.trl0.tl2),
2612 .PIL_reg (`SPC3.tlu.trl0.pil2),
2613 .TBA_reg (`SPC3.tlu.tsd0.tba2[47:15]),
2614 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2615 .CWP_reg (`SPC3.exu0.rml.cwp_thr2),
2616 .CANSAVE_reg (`SPC3.exu0.rml.cansave_thr2),
2617 .CANRESTORE_reg (`SPC3.exu0.rml.canrestore_thr2),
2618 .OTHERWIN_reg (`SPC3.exu0.rml.otherwin_thr2),
2619 .WSTATE_reg (`SPC3.exu0.rml.wstate_thr2),
2620 .CLEANWIN_reg (`SPC3.exu0.rml.cleanwin_thr2),
2621 .rd_SOFTINT_reg (`SPC3.tlu.trl0.rd_softint2),
2622 .SOFTINT_reg (`SPC3.tlu.trl0.softint2),
2623 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec2),
2624 .GL_reg (`SPC3.tlu.tlu_gl2),
2625 .HPSTATE_reg (`SPC3.tlu.tsd0.arch_hpstate2),
2626 .HTBA_reg (`SPC3.tlu.tsd0.htba2[47:14]),
2627 .HINTP_reg (`SPC3.tlu.trl0.hintp2),
2628
2629 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_2[12:0]}),
2630 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_2[12:0]}),
2631 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_2[12:0]}),
2632 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_2[12:0]}),
2633 .LSU_CONTROL_reg ({29'd0,
2634 `SPC3.lsu.dcs.wpt_mode_2[1:0],
2635 `SPC3.lsu.dcs.wpt_mask_2[7:0],
2636 `SPC3.lsu.dcs.wpt_enable_2[1:0],
2637 18'd0,
2638 `SPC3.lsu.dcs.spec_enable[2],
2639 `SPC3.lsu.dcs.dmmu_enable[2],
2640 `SPC3.lsu.dcs.immu_enable[2],
2641 `SPC3.lsu.dcs.dc_enable[2],
2642 `SPC3.lsu.dcs.ic_enable[2]}),
2643 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.immu_tag_access_2[47:0]}),
2644 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.dmmu_tag_access_2[47:0]}),
2645 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint2[47:3],3'b00}),
2646 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_2[47:0]),
2647
2648 .Trap_Entry_1 (`PROBES3.trap_entry_1_t2),
2649 .Trap_Entry_2 (`PROBES3.trap_entry_2_t2),
2650 .Trap_Entry_3 (`PROBES3.trap_entry_3_t2),
2651 .Trap_Entry_4 (`PROBES3.trap_entry_4_t2),
2652 .Trap_Entry_5 (`PROBES3.trap_entry_5_t2),
2653 .Trap_Entry_6 (`PROBES3.trap_entry_6_t2),
2654
2655 .exu_valid (`PROBES3.ex_valid[2]),
2656
2657 .imul_valid (`PROBES3.imul_valid[2]),
2658
2659 .fp_valid (`PROBES3.fg_valid[2]),
2660 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2661 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2662 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2663
2664 .idiv_valid (`PROBES3.fgu_idiv_valid[2]),
2665
2666 .fdiv_valid (`PROBES3.fgu_fdiv_valid[2]),
2667
2668 .lsu_valid (`PROBES3.lsu_valid[2]),
2669 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2670 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2671 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2672
2673 .asi_valid (`PROBES3.asi_valid_fx5[2]),
2674 .asi_in_progress (`PROBES3.asi_in_progress_fx4[2]),
2675
2676 .tlu_valid (`PROBES3.tlu_valid[2])
2677`endif
2678 );
2679
2680
2681//----------------------------------------------------------
2682//
2683// THREAD 3
2684//
2685
2686 nas_pipe3 t3 (
2687 .mycid (cid),
2688 .mytid (3'h3),
2689
2690// If GATESIM, instantiate "dummy" module with floating ports since unused.
2691`ifdef GATESIM
2692 .opcode () // this and all other ports are unconnected
2693`else
2694 .opcode ({`PROBES3.op_3_w}),
2695 .PC_reg ({`PROBES3.pc_3_w}),
2696 .Y_reg (`SPC3.exu0.rml.arch_yreg_tid3_ff),
2697 .CCR_reg (`SPC3.exu0.ect.arch_ccr_tid3_lth),
2698 .FPRS_reg (`SPC3.fgu.fac.fprs_tid3),
2699 .FSR_reg (`SPC3.fgu.fad.fsr3_fx1[27:0]),
2700 .ASI_reg (`SPC3.lsu.dcs.asi_state3),
2701 .GSR_reg ({`SPC3.fgu.fgd.gsr3_mask_fx4[31:0], `SPC3.fgu.fpc.gsr3_11bits_fx4[10:0]}),
2702 .TICK_CMPR_reg (`PROBES3.tick_cmpr_3),
2703 .STICK_CMPR_reg (`PROBES3.stick_cmpr_3),
2704 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_3),
2705 .PSTATE_reg (`SPC3.tlu.tsd0.arch_pstate3),
2706 .TL_reg (`SPC3.tlu.trl0.tl3),
2707 .PIL_reg (`SPC3.tlu.trl0.pil3),
2708 .TBA_reg (`SPC3.tlu.tsd0.tba3[47:15]),
2709 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2710 .CWP_reg (`SPC3.exu0.rml.cwp_thr3),
2711 .CANSAVE_reg (`SPC3.exu0.rml.cansave_thr3),
2712 .CANRESTORE_reg (`SPC3.exu0.rml.canrestore_thr3),
2713 .OTHERWIN_reg (`SPC3.exu0.rml.otherwin_thr3),
2714 .WSTATE_reg (`SPC3.exu0.rml.wstate_thr3),
2715 .CLEANWIN_reg (`SPC3.exu0.rml.cleanwin_thr3),
2716 .rd_SOFTINT_reg (`SPC3.tlu.trl0.rd_softint3),
2717 .SOFTINT_reg (`SPC3.tlu.trl0.softint3),
2718 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec3),
2719 .GL_reg (`SPC3.tlu.tlu_gl3),
2720 .HPSTATE_reg (`SPC3.tlu.tsd0.arch_hpstate3),
2721 .HTBA_reg (`SPC3.tlu.tsd0.htba3[47:14]),
2722 .HINTP_reg (`SPC3.tlu.trl0.hintp3),
2723
2724 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_3[12:0]}),
2725 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_3[12:0]}),
2726 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_3[12:0]}),
2727 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_3[12:0]}),
2728 .LSU_CONTROL_reg ({29'd0,
2729 `SPC3.lsu.dcs.wpt_mode_3[1:0],
2730 `SPC3.lsu.dcs.wpt_mask_3[7:0],
2731 `SPC3.lsu.dcs.wpt_enable_3[1:0],
2732 18'd0,
2733 `SPC3.lsu.dcs.spec_enable[3],
2734 `SPC3.lsu.dcs.dmmu_enable[3],
2735 `SPC3.lsu.dcs.immu_enable[3],
2736 `SPC3.lsu.dcs.dc_enable[3],
2737 `SPC3.lsu.dcs.ic_enable[3]}),
2738 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.immu_tag_access_3[47:0]}),
2739 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd0.dmmu_tag_access_3[47:0]}),
2740 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint3[47:3],3'b00}),
2741 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_3[47:0]),
2742
2743 .Trap_Entry_1 (`PROBES3.trap_entry_1_t3),
2744 .Trap_Entry_2 (`PROBES3.trap_entry_2_t3),
2745 .Trap_Entry_3 (`PROBES3.trap_entry_3_t3),
2746 .Trap_Entry_4 (`PROBES3.trap_entry_4_t3),
2747 .Trap_Entry_5 (`PROBES3.trap_entry_5_t3),
2748 .Trap_Entry_6 (`PROBES3.trap_entry_6_t3),
2749
2750 .exu_valid (`PROBES3.ex_valid[3]),
2751
2752 .imul_valid (`PROBES3.imul_valid[3]),
2753
2754 .fp_valid (`PROBES3.fg_valid[3]),
2755 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2756 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2757 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2758
2759 .idiv_valid (`PROBES3.fgu_idiv_valid[3]),
2760
2761 .fdiv_valid (`PROBES3.fgu_fdiv_valid[3]),
2762
2763 .lsu_valid (`PROBES3.lsu_valid[3]),
2764 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2765 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2766 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2767
2768 .asi_valid (`PROBES3.asi_valid_fx5[3]),
2769 .asi_in_progress (`PROBES3.asi_in_progress_fx4[3]),
2770
2771 .tlu_valid (`PROBES3.tlu_valid[3])
2772`endif
2773 );
2774
2775
2776//----------------------------------------------------------
2777//
2778// THREAD 4
2779//
2780
2781 nas_pipe3 t4 (
2782 .mycid (cid),
2783 .mytid (3'h4),
2784
2785// If GATESIM, instantiate "dummy" module with floating ports since unused.
2786`ifdef GATESIM
2787 .opcode () // this and all other ports are unconnected
2788`else
2789 .opcode ({`PROBES3.op_4_w}),
2790 .PC_reg ({`PROBES3.pc_4_w}),
2791 .Y_reg (`SPC3.exu1.rml.arch_yreg_tid0_ff),
2792 .CCR_reg (`SPC3.exu1.ect.arch_ccr_tid0_lth),
2793 .FPRS_reg (`SPC3.fgu.fac.fprs_tid4),
2794 .FSR_reg (`SPC3.fgu.fad.fsr4_fx1[27:0]),
2795 .ASI_reg (`SPC3.lsu.dcs.asi_state4),
2796 .GSR_reg ({`SPC3.fgu.fgd.gsr4_mask_fx4[31:0], `SPC3.fgu.fpc.gsr4_11bits_fx4[10:0]}),
2797 .TICK_CMPR_reg (`PROBES3.tick_cmpr_4),
2798 .STICK_CMPR_reg (`PROBES3.stick_cmpr_4),
2799 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_4),
2800 .PSTATE_reg (`SPC3.tlu.tsd1.arch_pstate0),
2801 .TL_reg (`SPC3.tlu.trl1.tl0),
2802 .PIL_reg (`SPC3.tlu.trl1.pil0),
2803 .TBA_reg (`SPC3.tlu.tsd1.tba0[47:15]),
2804 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2805 .CWP_reg (`SPC3.exu1.rml.cwp_thr0),
2806 .CANSAVE_reg (`SPC3.exu1.rml.cansave_thr0),
2807 .CANRESTORE_reg (`SPC3.exu1.rml.canrestore_thr0),
2808 .OTHERWIN_reg (`SPC3.exu1.rml.otherwin_thr0),
2809 .WSTATE_reg (`SPC3.exu1.rml.wstate_thr0),
2810 .CLEANWIN_reg (`SPC3.exu1.rml.cleanwin_thr0),
2811 .rd_SOFTINT_reg (`SPC3.tlu.trl1.rd_softint0),
2812 .SOFTINT_reg (`SPC3.tlu.trl1.softint0),
2813 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec4),
2814 .GL_reg (`SPC3.tlu.tlu_gl4),
2815 .HPSTATE_reg (`SPC3.tlu.tsd1.arch_hpstate0),
2816 .HTBA_reg (`SPC3.tlu.tsd1.htba0[47:14]),
2817 .HINTP_reg (`SPC3.tlu.trl1.hintp0),
2818
2819 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_4[12:0]}),
2820 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_4[12:0]}),
2821 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_4[12:0]}),
2822 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_4[12:0]}),
2823 .LSU_CONTROL_reg ({29'd0,
2824 `SPC3.lsu.dcs.wpt_mode_4[1:0],
2825 `SPC3.lsu.dcs.wpt_mask_4[7:0],
2826 `SPC3.lsu.dcs.wpt_enable_4[1:0],
2827 18'd0,
2828 `SPC3.lsu.dcs.spec_enable[4],
2829 `SPC3.lsu.dcs.dmmu_enable[4],
2830 `SPC3.lsu.dcs.immu_enable[4],
2831 `SPC3.lsu.dcs.dc_enable[4],
2832 `SPC3.lsu.dcs.ic_enable[4]}),
2833 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.immu_tag_access_0[47:0]}),
2834 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.dmmu_tag_access_0[47:0]}),
2835 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint4[47:3],3'b00}),
2836 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_4[47:0]),
2837
2838 .Trap_Entry_1 (`PROBES3.trap_entry_1_t4),
2839 .Trap_Entry_2 (`PROBES3.trap_entry_2_t4),
2840 .Trap_Entry_3 (`PROBES3.trap_entry_3_t4),
2841 .Trap_Entry_4 (`PROBES3.trap_entry_4_t4),
2842 .Trap_Entry_5 (`PROBES3.trap_entry_5_t4),
2843 .Trap_Entry_6 (`PROBES3.trap_entry_6_t4),
2844
2845 .exu_valid (`PROBES3.ex_valid[4]),
2846
2847 .imul_valid (`PROBES3.imul_valid[4]),
2848
2849 .fp_valid (`PROBES3.fg_valid[4]),
2850 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2851 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2852 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2853
2854 .idiv_valid (`PROBES3.fgu_idiv_valid[4]),
2855
2856 .fdiv_valid (`PROBES3.fgu_fdiv_valid[4]),
2857
2858 .lsu_valid (`PROBES3.lsu_valid[4]),
2859 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2860 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2861 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2862
2863 .asi_valid (`PROBES3.asi_valid_fx5[4]),
2864 .asi_in_progress (`PROBES3.asi_in_progress_fx4[4]),
2865
2866 .tlu_valid (`PROBES3.tlu_valid[4])
2867`endif
2868 );
2869
2870
2871//----------------------------------------------------------
2872//
2873// THREAD 5
2874//
2875
2876 nas_pipe3 t5 (
2877 .mycid (cid),
2878 .mytid (3'h5),
2879
2880// If GATESIM, instantiate "dummy" module with floating ports since unused.
2881`ifdef GATESIM
2882 .opcode () // this and all other ports are unconnected
2883`else
2884 .opcode ({`PROBES3.op_5_w}),
2885 .PC_reg ({`PROBES3.pc_5_w}),
2886 .Y_reg (`SPC3.exu1.rml.arch_yreg_tid1_ff),
2887 .CCR_reg (`SPC3.exu1.ect.arch_ccr_tid1_lth),
2888 .FPRS_reg (`SPC3.fgu.fac.fprs_tid5),
2889 .FSR_reg (`SPC3.fgu.fad.fsr5_fx1[27:0]),
2890 .ASI_reg (`SPC3.lsu.dcs.asi_state5),
2891 .GSR_reg ({`SPC3.fgu.fgd.gsr5_mask_fx4[31:0], `SPC3.fgu.fpc.gsr5_11bits_fx4[10:0]}),
2892 .TICK_CMPR_reg (`PROBES3.tick_cmpr_5),
2893 .STICK_CMPR_reg (`PROBES3.stick_cmpr_5),
2894 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_5),
2895 .PSTATE_reg (`SPC3.tlu.tsd1.arch_pstate1),
2896 .TL_reg (`SPC3.tlu.trl1.tl1),
2897 .PIL_reg (`SPC3.tlu.trl1.pil1),
2898 .TBA_reg (`SPC3.tlu.tsd1.tba1[47:15]),
2899 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2900 .CWP_reg (`SPC3.exu1.rml.cwp_thr1),
2901 .CANSAVE_reg (`SPC3.exu1.rml.cansave_thr1),
2902 .CANRESTORE_reg (`SPC3.exu1.rml.canrestore_thr1),
2903 .OTHERWIN_reg (`SPC3.exu1.rml.otherwin_thr1),
2904 .WSTATE_reg (`SPC3.exu1.rml.wstate_thr1),
2905 .CLEANWIN_reg (`SPC3.exu1.rml.cleanwin_thr1),
2906 .rd_SOFTINT_reg (`SPC3.tlu.trl1.rd_softint1),
2907 .SOFTINT_reg (`SPC3.tlu.trl1.softint1),
2908 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec5),
2909 .GL_reg (`SPC3.tlu.tlu_gl5),
2910 .HPSTATE_reg (`SPC3.tlu.tsd1.arch_hpstate1),
2911 .HTBA_reg (`SPC3.tlu.tsd1.htba1[47:14]),
2912 .HINTP_reg (`SPC3.tlu.trl1.hintp1),
2913
2914 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_5[12:0]}),
2915 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_5[12:0]}),
2916 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_5[12:0]}),
2917 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_5[12:0]}),
2918 .LSU_CONTROL_reg ({29'd0,
2919 `SPC3.lsu.dcs.wpt_mode_5[1:0],
2920 `SPC3.lsu.dcs.wpt_mask_5[7:0],
2921 `SPC3.lsu.dcs.wpt_enable_5[1:0],
2922 18'd0,
2923 `SPC3.lsu.dcs.spec_enable[5],
2924 `SPC3.lsu.dcs.dmmu_enable[5],
2925 `SPC3.lsu.dcs.immu_enable[5],
2926 `SPC3.lsu.dcs.dc_enable[5],
2927 `SPC3.lsu.dcs.ic_enable[5]}),
2928 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.immu_tag_access_1[47:0]}),
2929 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.dmmu_tag_access_1[47:0]}),
2930 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint5[47:3],3'b00}),
2931 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_5[47:0]),
2932
2933 .Trap_Entry_1 (`PROBES3.trap_entry_1_t5),
2934 .Trap_Entry_2 (`PROBES3.trap_entry_2_t5),
2935 .Trap_Entry_3 (`PROBES3.trap_entry_3_t5),
2936 .Trap_Entry_4 (`PROBES3.trap_entry_4_t5),
2937 .Trap_Entry_5 (`PROBES3.trap_entry_5_t5),
2938 .Trap_Entry_6 (`PROBES3.trap_entry_6_t5),
2939
2940 .exu_valid (`PROBES3.ex_valid[5]),
2941
2942 .imul_valid (`PROBES3.imul_valid[5]),
2943
2944 .fp_valid (`PROBES3.fg_valid[5]),
2945 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
2946 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
2947 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
2948
2949 .idiv_valid (`PROBES3.fgu_idiv_valid[5]),
2950
2951 .fdiv_valid (`PROBES3.fgu_fdiv_valid[5]),
2952
2953 .lsu_valid (`PROBES3.lsu_valid[5]),
2954 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
2955 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
2956 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
2957
2958 .asi_valid (`PROBES3.asi_valid_fx5[5]),
2959 .asi_in_progress (`PROBES3.asi_in_progress_fx4[5]),
2960
2961 .tlu_valid (`PROBES3.tlu_valid[5])
2962`endif
2963 );
2964
2965
2966//----------------------------------------------------------
2967//
2968// THREAD 6
2969//
2970
2971 nas_pipe3 t6 (
2972 .mycid (cid),
2973 .mytid (3'h6),
2974
2975// If GATESIM, instantiate "dummy" module with floating ports since unused.
2976`ifdef GATESIM
2977 .opcode () // this and all other ports are unconnected
2978`else
2979 .opcode ({`PROBES3.op_6_w}),
2980 .PC_reg ({`PROBES3.pc_6_w}),
2981 .Y_reg (`SPC3.exu1.rml.arch_yreg_tid2_ff),
2982 .CCR_reg (`SPC3.exu1.ect.arch_ccr_tid2_lth),
2983 .FPRS_reg (`SPC3.fgu.fac.fprs_tid6),
2984 .FSR_reg (`SPC3.fgu.fad.fsr6_fx1[27:0]),
2985 .ASI_reg (`SPC3.lsu.dcs.asi_state6),
2986 .GSR_reg ({`SPC3.fgu.fgd.gsr6_mask_fx4[31:0], `SPC3.fgu.fpc.gsr6_11bits_fx4[10:0]}),
2987 .TICK_CMPR_reg (`PROBES3.tick_cmpr_6),
2988 .STICK_CMPR_reg (`PROBES3.stick_cmpr_6),
2989 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_6),
2990 .PSTATE_reg (`SPC3.tlu.tsd1.arch_pstate2),
2991 .TL_reg (`SPC3.tlu.trl1.tl2),
2992 .PIL_reg (`SPC3.tlu.trl1.pil2),
2993 .TBA_reg (`SPC3.tlu.tsd1.tba2[47:15]),
2994 .VER_reg (`SPC3.tlu.asi.hver_value), // static
2995 .CWP_reg (`SPC3.exu1.rml.cwp_thr2),
2996 .CANSAVE_reg (`SPC3.exu1.rml.cansave_thr2),
2997 .CANRESTORE_reg (`SPC3.exu1.rml.canrestore_thr2),
2998 .OTHERWIN_reg (`SPC3.exu1.rml.otherwin_thr2),
2999 .WSTATE_reg (`SPC3.exu1.rml.wstate_thr2),
3000 .CLEANWIN_reg (`SPC3.exu1.rml.cleanwin_thr2),
3001 .rd_SOFTINT_reg (`SPC3.tlu.trl1.rd_softint2),
3002 .SOFTINT_reg (`SPC3.tlu.trl1.softint2),
3003 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec6),
3004 .GL_reg (`SPC3.tlu.tlu_gl6),
3005 .HPSTATE_reg (`SPC3.tlu.tsd1.arch_hpstate2),
3006 .HTBA_reg (`SPC3.tlu.tsd1.htba2[47:14]),
3007 .HINTP_reg (`SPC3.tlu.trl1.hintp2),
3008
3009 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_6[12:0]}),
3010 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_6[12:0]}),
3011 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_6[12:0]}),
3012 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_6[12:0]}),
3013 .LSU_CONTROL_reg ({29'd0,
3014 `SPC3.lsu.dcs.wpt_mode_6[1:0],
3015 `SPC3.lsu.dcs.wpt_mask_6[7:0],
3016 `SPC3.lsu.dcs.wpt_enable_6[1:0],
3017 18'd0,
3018 `SPC3.lsu.dcs.spec_enable[6],
3019 `SPC3.lsu.dcs.dmmu_enable[6],
3020 `SPC3.lsu.dcs.immu_enable[6],
3021 `SPC3.lsu.dcs.dc_enable[6],
3022 `SPC3.lsu.dcs.ic_enable[6]}),
3023 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.immu_tag_access_2[47:0]}),
3024 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.dmmu_tag_access_2[47:0]}),
3025 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint6[47:3],3'b00}),
3026 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_6[47:0]),
3027
3028 .Trap_Entry_1 (`PROBES3.trap_entry_1_t6),
3029 .Trap_Entry_2 (`PROBES3.trap_entry_2_t6),
3030 .Trap_Entry_3 (`PROBES3.trap_entry_3_t6),
3031 .Trap_Entry_4 (`PROBES3.trap_entry_4_t6),
3032 .Trap_Entry_5 (`PROBES3.trap_entry_5_t6),
3033 .Trap_Entry_6 (`PROBES3.trap_entry_6_t6),
3034
3035 .exu_valid (`PROBES3.ex_valid[6]),
3036
3037 .imul_valid (`PROBES3.imul_valid[6]),
3038
3039 .fp_valid (`PROBES3.fg_valid[6]),
3040 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
3041 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
3042 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
3043
3044 .idiv_valid (`PROBES3.fgu_idiv_valid[6]),
3045
3046 .fdiv_valid (`PROBES3.fgu_fdiv_valid[6]),
3047
3048 .lsu_valid (`PROBES3.lsu_valid[6]),
3049 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
3050 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
3051 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
3052
3053 .asi_valid (`PROBES3.asi_valid_fx5[6]),
3054 .asi_in_progress (`PROBES3.asi_in_progress_fx4[6]),
3055
3056 .tlu_valid (`PROBES3.tlu_valid[6])
3057`endif
3058 );
3059
3060
3061//----------------------------------------------------------
3062//
3063// THREAD 7
3064//
3065
3066 nas_pipe3 t7 (
3067 .mycid (cid),
3068 .mytid (3'h7),
3069
3070// If GATESIM, instantiate "dummy" module with floating ports since unused.
3071`ifdef GATESIM
3072 .opcode () // this and all other ports are unconnected
3073`else
3074 .opcode ({`PROBES3.op_7_w}),
3075 .PC_reg ({`PROBES3.pc_7_w}),
3076 .Y_reg (`SPC3.exu1.rml.arch_yreg_tid3_ff),
3077 .CCR_reg (`SPC3.exu1.ect.arch_ccr_tid3_lth),
3078 .FPRS_reg (`SPC3.fgu.fac.fprs_tid7),
3079 .FSR_reg (`SPC3.fgu.fad.fsr7_fx1[27:0]),
3080 .ASI_reg (`SPC3.lsu.dcs.asi_state7),
3081 .GSR_reg ({`SPC3.fgu.fgd.gsr7_mask_fx4[31:0], `SPC3.fgu.fpc.gsr7_11bits_fx4[10:0]}),
3082 .TICK_CMPR_reg (`PROBES3.tick_cmpr_7),
3083 .STICK_CMPR_reg (`PROBES3.stick_cmpr_7),
3084 .HSTICK_CMPR_reg (`PROBES3.hstick_cmpr_7),
3085 .PSTATE_reg (`SPC3.tlu.tsd1.arch_pstate3),
3086 .TL_reg (`SPC3.tlu.trl1.tl3),
3087 .PIL_reg (`SPC3.tlu.trl1.pil3),
3088 .TBA_reg (`SPC3.tlu.tsd1.tba3[47:15]),
3089 .VER_reg (`SPC3.tlu.asi.hver_value), // static
3090 .CWP_reg (`SPC3.exu1.rml.cwp_thr3),
3091 .CANSAVE_reg (`SPC3.exu1.rml.cansave_thr3),
3092 .CANRESTORE_reg (`SPC3.exu1.rml.canrestore_thr3),
3093 .OTHERWIN_reg (`SPC3.exu1.rml.otherwin_thr3),
3094 .WSTATE_reg (`SPC3.exu1.rml.wstate_thr3),
3095 .CLEANWIN_reg (`SPC3.exu1.rml.cleanwin_thr3),
3096 .rd_SOFTINT_reg (`SPC3.tlu.trl1.rd_softint3),
3097 .SOFTINT_reg (`SPC3.tlu.trl1.softint3),
3098 .INTR_RECEIVE_reg (`SPC3.tlu.cth.int_rec7),
3099 .GL_reg (`SPC3.tlu.tlu_gl7),
3100 .HPSTATE_reg (`SPC3.tlu.tsd1.arch_hpstate3),
3101 .HTBA_reg (`SPC3.tlu.tsd1.htba3[47:14]),
3102 .HINTP_reg (`SPC3.tlu.trl1.hintp3),
3103
3104 .CTXT_PRIM_0_reg ({51'b0,`SPC3.lsu.dcs.p0ctxt_7[12:0]}),
3105 .CTXT_SEC_0_reg ({51'b0,`SPC3.lsu.dcs.s0ctxt_7[12:0]}),
3106 .CTXT_PRIM_1_reg ({51'b0,`SPC3.lsu.dcs.p1ctxt_7[12:0]}),
3107 .CTXT_SEC_1_reg ({51'b0,`SPC3.lsu.dcs.s1ctxt_7[12:0]}),
3108 .LSU_CONTROL_reg ({29'd0,
3109 `SPC3.lsu.dcs.wpt_mode_7[1:0],
3110 `SPC3.lsu.dcs.wpt_mask_7[7:0],
3111 `SPC3.lsu.dcs.wpt_enable_7[1:0],
3112 18'd0,
3113 `SPC3.lsu.dcs.spec_enable[7],
3114 `SPC3.lsu.dcs.dmmu_enable[7],
3115 `SPC3.lsu.dcs.immu_enable[7],
3116 `SPC3.lsu.dcs.dc_enable[7],
3117 `SPC3.lsu.dcs.ic_enable[7]}),
3118 .I_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.immu_tag_access_3[47:0]}),
3119 .D_TAG_ACC_reg ({16'b0,`SPC3.mmu.asd1.dmmu_tag_access_3[47:0]}),
3120 .WATCHPOINT_ADDR_reg ({16'b0,`SPC3.lsu.dcs.watchpoint7[47:3],3'b00}),
3121 .DSFAR_reg (`SPC3.tlu.dfd.dsfar_7[47:0]),
3122
3123 .Trap_Entry_1 (`PROBES3.trap_entry_1_t7),
3124 .Trap_Entry_2 (`PROBES3.trap_entry_2_t7),
3125 .Trap_Entry_3 (`PROBES3.trap_entry_3_t7),
3126 .Trap_Entry_4 (`PROBES3.trap_entry_4_t7),
3127 .Trap_Entry_5 (`PROBES3.trap_entry_5_t7),
3128 .Trap_Entry_6 (`PROBES3.trap_entry_6_t7),
3129
3130 .exu_valid (`PROBES3.ex_valid[7]),
3131
3132 .imul_valid (`PROBES3.imul_valid[7]),
3133
3134 .fp_valid (`PROBES3.fg_valid[7]),
3135 .frf_w1_valid (`SPC3.fgu.frf.w1_valid),
3136 .frf_w1_tid (`SPC3.fgu.frf.w1_tid),
3137 .frf_w1_addr (`SPC3.fgu.frf.w1_addr),
3138
3139 .idiv_valid (`PROBES3.fgu_idiv_valid[7]),
3140
3141 .fdiv_valid (`PROBES3.fgu_fdiv_valid[7]),
3142
3143 .lsu_valid (`PROBES3.lsu_valid[7]),
3144 .frf_w2_valid (`SPC3.fgu.frf.w2_valid),
3145 .frf_w2_tid (`SPC3.fgu.frf.w2_tid),
3146 .frf_w2_addr (`SPC3.fgu.frf.w2_addr),
3147
3148 .asi_valid (`PROBES3.asi_valid_fx5[7]),
3149 .asi_in_progress (`PROBES3.asi_in_progress_fx4[7]),
3150
3151 .tlu_valid (`PROBES3.tlu_valid[7])
3152`endif
3153 );
3154
3155//----------------------------------------------------------
3156
3157
3158//----------------------------------------------------------
3159endmodule
3160
3161`endif
3162
3163`ifdef CORE_4
3164
3165module nas_core4 (
3166
3167 cid
3168);
3169
3170input [2:0] cid;
3171
3172integer i;
3173
3174//----------------------------------------------------------
3175
3176//----------------------------------------------------------
3177
3178//----------------------------------------------------------
3179//
3180// THREAD 0
3181//
3182
3183 nas_pipe4 t0 (
3184 .mycid (cid),
3185 .mytid (3'h0),
3186
3187// If GATESIM, instantiate "dummy" module with floating ports since unused.
3188`ifdef GATESIM
3189 .opcode () // this and all other ports are unconnected
3190`else
3191 .opcode ({`PROBES4.op_0_w}),
3192 .PC_reg ({`PROBES4.pc_0_w}),
3193 .Y_reg (`SPC4.exu0.rml.arch_yreg_tid0_ff),
3194 .CCR_reg (`SPC4.exu0.ect.arch_ccr_tid0_lth),
3195 .FPRS_reg (`SPC4.fgu.fac.fprs_tid0),
3196 .FSR_reg (`SPC4.fgu.fad.fsr0_fx1[27:0]),
3197 .ASI_reg (`SPC4.lsu.dcs.asi_state0),
3198 .GSR_reg ({`SPC4.fgu.fgd.gsr0_mask_fx4[31:0], `SPC4.fgu.fpc.gsr0_11bits_fx4[10:0]}),
3199 .TICK_CMPR_reg (`PROBES4.tick_cmpr_0),
3200 .STICK_CMPR_reg (`PROBES4.stick_cmpr_0),
3201 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_0),
3202 .PSTATE_reg (`SPC4.tlu.tsd0.arch_pstate0),
3203 .TL_reg (`SPC4.tlu.trl0.tl0),
3204 .PIL_reg (`SPC4.tlu.trl0.pil0),
3205 .TBA_reg (`SPC4.tlu.tsd0.tba0[47:15]),
3206 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3207 .CWP_reg (`SPC4.exu0.rml.cwp_thr0),
3208 .CANSAVE_reg (`SPC4.exu0.rml.cansave_thr0),
3209 .CANRESTORE_reg (`SPC4.exu0.rml.canrestore_thr0),
3210 .OTHERWIN_reg (`SPC4.exu0.rml.otherwin_thr0),
3211 .WSTATE_reg (`SPC4.exu0.rml.wstate_thr0),
3212 .CLEANWIN_reg (`SPC4.exu0.rml.cleanwin_thr0),
3213 .rd_SOFTINT_reg (`SPC4.tlu.trl0.rd_softint0),
3214 .SOFTINT_reg (`SPC4.tlu.trl0.softint0),
3215 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec0),
3216 .GL_reg (`SPC4.tlu.tlu_gl0),
3217 .HPSTATE_reg (`SPC4.tlu.tsd0.arch_hpstate0),
3218 .HTBA_reg (`SPC4.tlu.tsd0.htba0[47:14]),
3219 .HINTP_reg (`SPC4.tlu.trl0.hintp0),
3220
3221 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_0[12:0]}),
3222 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_0[12:0]}),
3223 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_0[12:0]}),
3224 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_0[12:0]}),
3225 .LSU_CONTROL_reg ({29'd0,
3226 `SPC4.lsu.dcs.wpt_mode_0[1:0],
3227 `SPC4.lsu.dcs.wpt_mask_0[7:0],
3228 `SPC4.lsu.dcs.wpt_enable_0[1:0],
3229 18'd0,
3230 `SPC4.lsu.dcs.spec_enable[0],
3231 `SPC4.lsu.dcs.dmmu_enable[0],
3232 `SPC4.lsu.dcs.immu_enable[0],
3233 `SPC4.lsu.dcs.dc_enable[0],
3234 `SPC4.lsu.dcs.ic_enable[0]}),
3235 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.immu_tag_access_0[47:0]}),
3236 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.dmmu_tag_access_0[47:0]}),
3237 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint0[47:3],3'b00}),
3238 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_0[47:0]),
3239
3240 .Trap_Entry_1 (`PROBES4.trap_entry_1_t0),
3241 .Trap_Entry_2 (`PROBES4.trap_entry_2_t0),
3242 .Trap_Entry_3 (`PROBES4.trap_entry_3_t0),
3243 .Trap_Entry_4 (`PROBES4.trap_entry_4_t0),
3244 .Trap_Entry_5 (`PROBES4.trap_entry_5_t0),
3245 .Trap_Entry_6 (`PROBES4.trap_entry_6_t0),
3246
3247 .exu_valid (`PROBES4.ex_valid[0]),
3248
3249 .imul_valid (`PROBES4.imul_valid[0]),
3250
3251 .fp_valid (`PROBES4.fg_valid[0]),
3252 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3253 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3254 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3255
3256 .idiv_valid (`PROBES4.fgu_idiv_valid[0]),
3257
3258 .fdiv_valid (`PROBES4.fgu_fdiv_valid[0]),
3259
3260 .lsu_valid (`PROBES4.lsu_valid[0]),
3261 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3262 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3263 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3264
3265 .asi_valid (`PROBES4.asi_valid_fx5[0]),
3266 .asi_in_progress (`PROBES4.asi_in_progress_fx4[0]),
3267
3268 .tlu_valid (`PROBES4.tlu_valid[0])
3269`endif
3270 );
3271
3272
3273//----------------------------------------------------------
3274//
3275// THREAD 1
3276//
3277
3278 nas_pipe4 t1 (
3279 .mycid (cid),
3280 .mytid (3'h1),
3281
3282// If GATESIM, instantiate "dummy" module with floating ports since unused.
3283`ifdef GATESIM
3284 .opcode () // this and all other ports are unconnected
3285`else
3286 .opcode ({`PROBES4.op_1_w}),
3287 .PC_reg ({`PROBES4.pc_1_w}),
3288 .Y_reg (`SPC4.exu0.rml.arch_yreg_tid1_ff),
3289 .CCR_reg (`SPC4.exu0.ect.arch_ccr_tid1_lth),
3290 .FPRS_reg (`SPC4.fgu.fac.fprs_tid1),
3291 .FSR_reg (`SPC4.fgu.fad.fsr1_fx1[27:0]),
3292 .ASI_reg (`SPC4.lsu.dcs.asi_state1),
3293 .GSR_reg ({`SPC4.fgu.fgd.gsr1_mask_fx4[31:0], `SPC4.fgu.fpc.gsr1_11bits_fx4[10:0]}),
3294 .TICK_CMPR_reg (`PROBES4.tick_cmpr_1),
3295 .STICK_CMPR_reg (`PROBES4.stick_cmpr_1),
3296 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_1),
3297 .PSTATE_reg (`SPC4.tlu.tsd0.arch_pstate1),
3298 .TL_reg (`SPC4.tlu.trl0.tl1),
3299 .PIL_reg (`SPC4.tlu.trl0.pil1),
3300 .TBA_reg (`SPC4.tlu.tsd0.tba1[47:15]),
3301 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3302 .CWP_reg (`SPC4.exu0.rml.cwp_thr1),
3303 .CANSAVE_reg (`SPC4.exu0.rml.cansave_thr1),
3304 .CANRESTORE_reg (`SPC4.exu0.rml.canrestore_thr1),
3305 .OTHERWIN_reg (`SPC4.exu0.rml.otherwin_thr1),
3306 .WSTATE_reg (`SPC4.exu0.rml.wstate_thr1),
3307 .CLEANWIN_reg (`SPC4.exu0.rml.cleanwin_thr1),
3308 .rd_SOFTINT_reg (`SPC4.tlu.trl0.rd_softint1),
3309 .SOFTINT_reg (`SPC4.tlu.trl0.softint1),
3310 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec1),
3311 .GL_reg (`SPC4.tlu.tlu_gl1),
3312 .HPSTATE_reg (`SPC4.tlu.tsd0.arch_hpstate1),
3313 .HTBA_reg (`SPC4.tlu.tsd0.htba1[47:14]),
3314 .HINTP_reg (`SPC4.tlu.trl0.hintp1),
3315
3316 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_1[12:0]}),
3317 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_1[12:0]}),
3318 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_1[12:0]}),
3319 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_1[12:0]}),
3320 .LSU_CONTROL_reg ({29'd0,
3321 `SPC4.lsu.dcs.wpt_mode_1[1:0],
3322 `SPC4.lsu.dcs.wpt_mask_1[7:0],
3323 `SPC4.lsu.dcs.wpt_enable_1[1:0],
3324 18'd0,
3325 `SPC4.lsu.dcs.spec_enable[1],
3326 `SPC4.lsu.dcs.dmmu_enable[1],
3327 `SPC4.lsu.dcs.immu_enable[1],
3328 `SPC4.lsu.dcs.dc_enable[1],
3329 `SPC4.lsu.dcs.ic_enable[1]}),
3330 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.immu_tag_access_1[47:0]}),
3331 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.dmmu_tag_access_1[47:0]}),
3332 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint1[47:3],3'b00}),
3333 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_1[47:0]),
3334
3335 .Trap_Entry_1 (`PROBES4.trap_entry_1_t1),
3336 .Trap_Entry_2 (`PROBES4.trap_entry_2_t1),
3337 .Trap_Entry_3 (`PROBES4.trap_entry_3_t1),
3338 .Trap_Entry_4 (`PROBES4.trap_entry_4_t1),
3339 .Trap_Entry_5 (`PROBES4.trap_entry_5_t1),
3340 .Trap_Entry_6 (`PROBES4.trap_entry_6_t1),
3341
3342 .exu_valid (`PROBES4.ex_valid[1]),
3343
3344 .imul_valid (`PROBES4.imul_valid[1]),
3345
3346 .fp_valid (`PROBES4.fg_valid[1]),
3347 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3348 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3349 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3350
3351 .idiv_valid (`PROBES4.fgu_idiv_valid[1]),
3352
3353 .fdiv_valid (`PROBES4.fgu_fdiv_valid[1]),
3354
3355 .lsu_valid (`PROBES4.lsu_valid[1]),
3356 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3357 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3358 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3359
3360 .asi_valid (`PROBES4.asi_valid_fx5[1]),
3361 .asi_in_progress (`PROBES4.asi_in_progress_fx4[1]),
3362
3363 .tlu_valid (`PROBES4.tlu_valid[1])
3364`endif
3365 );
3366
3367
3368//----------------------------------------------------------
3369//
3370// THREAD 2
3371//
3372
3373 nas_pipe4 t2 (
3374 .mycid (cid),
3375 .mytid (3'h2),
3376
3377// If GATESIM, instantiate "dummy" module with floating ports since unused.
3378`ifdef GATESIM
3379 .opcode () // this and all other ports are unconnected
3380`else
3381 .opcode ({`PROBES4.op_2_w}),
3382 .PC_reg ({`PROBES4.pc_2_w}),
3383 .Y_reg (`SPC4.exu0.rml.arch_yreg_tid2_ff),
3384 .CCR_reg (`SPC4.exu0.ect.arch_ccr_tid2_lth),
3385 .FPRS_reg (`SPC4.fgu.fac.fprs_tid2),
3386 .FSR_reg (`SPC4.fgu.fad.fsr2_fx1[27:0]),
3387 .ASI_reg (`SPC4.lsu.dcs.asi_state2),
3388 .GSR_reg ({`SPC4.fgu.fgd.gsr2_mask_fx4[31:0], `SPC4.fgu.fpc.gsr2_11bits_fx4[10:0]}),
3389 .TICK_CMPR_reg (`PROBES4.tick_cmpr_2),
3390 .STICK_CMPR_reg (`PROBES4.stick_cmpr_2),
3391 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_2),
3392 .PSTATE_reg (`SPC4.tlu.tsd0.arch_pstate2),
3393 .TL_reg (`SPC4.tlu.trl0.tl2),
3394 .PIL_reg (`SPC4.tlu.trl0.pil2),
3395 .TBA_reg (`SPC4.tlu.tsd0.tba2[47:15]),
3396 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3397 .CWP_reg (`SPC4.exu0.rml.cwp_thr2),
3398 .CANSAVE_reg (`SPC4.exu0.rml.cansave_thr2),
3399 .CANRESTORE_reg (`SPC4.exu0.rml.canrestore_thr2),
3400 .OTHERWIN_reg (`SPC4.exu0.rml.otherwin_thr2),
3401 .WSTATE_reg (`SPC4.exu0.rml.wstate_thr2),
3402 .CLEANWIN_reg (`SPC4.exu0.rml.cleanwin_thr2),
3403 .rd_SOFTINT_reg (`SPC4.tlu.trl0.rd_softint2),
3404 .SOFTINT_reg (`SPC4.tlu.trl0.softint2),
3405 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec2),
3406 .GL_reg (`SPC4.tlu.tlu_gl2),
3407 .HPSTATE_reg (`SPC4.tlu.tsd0.arch_hpstate2),
3408 .HTBA_reg (`SPC4.tlu.tsd0.htba2[47:14]),
3409 .HINTP_reg (`SPC4.tlu.trl0.hintp2),
3410
3411 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_2[12:0]}),
3412 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_2[12:0]}),
3413 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_2[12:0]}),
3414 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_2[12:0]}),
3415 .LSU_CONTROL_reg ({29'd0,
3416 `SPC4.lsu.dcs.wpt_mode_2[1:0],
3417 `SPC4.lsu.dcs.wpt_mask_2[7:0],
3418 `SPC4.lsu.dcs.wpt_enable_2[1:0],
3419 18'd0,
3420 `SPC4.lsu.dcs.spec_enable[2],
3421 `SPC4.lsu.dcs.dmmu_enable[2],
3422 `SPC4.lsu.dcs.immu_enable[2],
3423 `SPC4.lsu.dcs.dc_enable[2],
3424 `SPC4.lsu.dcs.ic_enable[2]}),
3425 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.immu_tag_access_2[47:0]}),
3426 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.dmmu_tag_access_2[47:0]}),
3427 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint2[47:3],3'b00}),
3428 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_2[47:0]),
3429
3430 .Trap_Entry_1 (`PROBES4.trap_entry_1_t2),
3431 .Trap_Entry_2 (`PROBES4.trap_entry_2_t2),
3432 .Trap_Entry_3 (`PROBES4.trap_entry_3_t2),
3433 .Trap_Entry_4 (`PROBES4.trap_entry_4_t2),
3434 .Trap_Entry_5 (`PROBES4.trap_entry_5_t2),
3435 .Trap_Entry_6 (`PROBES4.trap_entry_6_t2),
3436
3437 .exu_valid (`PROBES4.ex_valid[2]),
3438
3439 .imul_valid (`PROBES4.imul_valid[2]),
3440
3441 .fp_valid (`PROBES4.fg_valid[2]),
3442 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3443 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3444 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3445
3446 .idiv_valid (`PROBES4.fgu_idiv_valid[2]),
3447
3448 .fdiv_valid (`PROBES4.fgu_fdiv_valid[2]),
3449
3450 .lsu_valid (`PROBES4.lsu_valid[2]),
3451 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3452 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3453 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3454
3455 .asi_valid (`PROBES4.asi_valid_fx5[2]),
3456 .asi_in_progress (`PROBES4.asi_in_progress_fx4[2]),
3457
3458 .tlu_valid (`PROBES4.tlu_valid[2])
3459`endif
3460 );
3461
3462
3463//----------------------------------------------------------
3464//
3465// THREAD 3
3466//
3467
3468 nas_pipe4 t3 (
3469 .mycid (cid),
3470 .mytid (3'h3),
3471
3472// If GATESIM, instantiate "dummy" module with floating ports since unused.
3473`ifdef GATESIM
3474 .opcode () // this and all other ports are unconnected
3475`else
3476 .opcode ({`PROBES4.op_3_w}),
3477 .PC_reg ({`PROBES4.pc_3_w}),
3478 .Y_reg (`SPC4.exu0.rml.arch_yreg_tid3_ff),
3479 .CCR_reg (`SPC4.exu0.ect.arch_ccr_tid3_lth),
3480 .FPRS_reg (`SPC4.fgu.fac.fprs_tid3),
3481 .FSR_reg (`SPC4.fgu.fad.fsr3_fx1[27:0]),
3482 .ASI_reg (`SPC4.lsu.dcs.asi_state3),
3483 .GSR_reg ({`SPC4.fgu.fgd.gsr3_mask_fx4[31:0], `SPC4.fgu.fpc.gsr3_11bits_fx4[10:0]}),
3484 .TICK_CMPR_reg (`PROBES4.tick_cmpr_3),
3485 .STICK_CMPR_reg (`PROBES4.stick_cmpr_3),
3486 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_3),
3487 .PSTATE_reg (`SPC4.tlu.tsd0.arch_pstate3),
3488 .TL_reg (`SPC4.tlu.trl0.tl3),
3489 .PIL_reg (`SPC4.tlu.trl0.pil3),
3490 .TBA_reg (`SPC4.tlu.tsd0.tba3[47:15]),
3491 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3492 .CWP_reg (`SPC4.exu0.rml.cwp_thr3),
3493 .CANSAVE_reg (`SPC4.exu0.rml.cansave_thr3),
3494 .CANRESTORE_reg (`SPC4.exu0.rml.canrestore_thr3),
3495 .OTHERWIN_reg (`SPC4.exu0.rml.otherwin_thr3),
3496 .WSTATE_reg (`SPC4.exu0.rml.wstate_thr3),
3497 .CLEANWIN_reg (`SPC4.exu0.rml.cleanwin_thr3),
3498 .rd_SOFTINT_reg (`SPC4.tlu.trl0.rd_softint3),
3499 .SOFTINT_reg (`SPC4.tlu.trl0.softint3),
3500 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec3),
3501 .GL_reg (`SPC4.tlu.tlu_gl3),
3502 .HPSTATE_reg (`SPC4.tlu.tsd0.arch_hpstate3),
3503 .HTBA_reg (`SPC4.tlu.tsd0.htba3[47:14]),
3504 .HINTP_reg (`SPC4.tlu.trl0.hintp3),
3505
3506 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_3[12:0]}),
3507 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_3[12:0]}),
3508 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_3[12:0]}),
3509 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_3[12:0]}),
3510 .LSU_CONTROL_reg ({29'd0,
3511 `SPC4.lsu.dcs.wpt_mode_3[1:0],
3512 `SPC4.lsu.dcs.wpt_mask_3[7:0],
3513 `SPC4.lsu.dcs.wpt_enable_3[1:0],
3514 18'd0,
3515 `SPC4.lsu.dcs.spec_enable[3],
3516 `SPC4.lsu.dcs.dmmu_enable[3],
3517 `SPC4.lsu.dcs.immu_enable[3],
3518 `SPC4.lsu.dcs.dc_enable[3],
3519 `SPC4.lsu.dcs.ic_enable[3]}),
3520 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.immu_tag_access_3[47:0]}),
3521 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd0.dmmu_tag_access_3[47:0]}),
3522 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint3[47:3],3'b00}),
3523 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_3[47:0]),
3524
3525 .Trap_Entry_1 (`PROBES4.trap_entry_1_t3),
3526 .Trap_Entry_2 (`PROBES4.trap_entry_2_t3),
3527 .Trap_Entry_3 (`PROBES4.trap_entry_3_t3),
3528 .Trap_Entry_4 (`PROBES4.trap_entry_4_t3),
3529 .Trap_Entry_5 (`PROBES4.trap_entry_5_t3),
3530 .Trap_Entry_6 (`PROBES4.trap_entry_6_t3),
3531
3532 .exu_valid (`PROBES4.ex_valid[3]),
3533
3534 .imul_valid (`PROBES4.imul_valid[3]),
3535
3536 .fp_valid (`PROBES4.fg_valid[3]),
3537 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3538 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3539 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3540
3541 .idiv_valid (`PROBES4.fgu_idiv_valid[3]),
3542
3543 .fdiv_valid (`PROBES4.fgu_fdiv_valid[3]),
3544
3545 .lsu_valid (`PROBES4.lsu_valid[3]),
3546 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3547 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3548 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3549
3550 .asi_valid (`PROBES4.asi_valid_fx5[3]),
3551 .asi_in_progress (`PROBES4.asi_in_progress_fx4[3]),
3552
3553 .tlu_valid (`PROBES4.tlu_valid[3])
3554`endif
3555 );
3556
3557
3558//----------------------------------------------------------
3559//
3560// THREAD 4
3561//
3562
3563 nas_pipe4 t4 (
3564 .mycid (cid),
3565 .mytid (3'h4),
3566
3567// If GATESIM, instantiate "dummy" module with floating ports since unused.
3568`ifdef GATESIM
3569 .opcode () // this and all other ports are unconnected
3570`else
3571 .opcode ({`PROBES4.op_4_w}),
3572 .PC_reg ({`PROBES4.pc_4_w}),
3573 .Y_reg (`SPC4.exu1.rml.arch_yreg_tid0_ff),
3574 .CCR_reg (`SPC4.exu1.ect.arch_ccr_tid0_lth),
3575 .FPRS_reg (`SPC4.fgu.fac.fprs_tid4),
3576 .FSR_reg (`SPC4.fgu.fad.fsr4_fx1[27:0]),
3577 .ASI_reg (`SPC4.lsu.dcs.asi_state4),
3578 .GSR_reg ({`SPC4.fgu.fgd.gsr4_mask_fx4[31:0], `SPC4.fgu.fpc.gsr4_11bits_fx4[10:0]}),
3579 .TICK_CMPR_reg (`PROBES4.tick_cmpr_4),
3580 .STICK_CMPR_reg (`PROBES4.stick_cmpr_4),
3581 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_4),
3582 .PSTATE_reg (`SPC4.tlu.tsd1.arch_pstate0),
3583 .TL_reg (`SPC4.tlu.trl1.tl0),
3584 .PIL_reg (`SPC4.tlu.trl1.pil0),
3585 .TBA_reg (`SPC4.tlu.tsd1.tba0[47:15]),
3586 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3587 .CWP_reg (`SPC4.exu1.rml.cwp_thr0),
3588 .CANSAVE_reg (`SPC4.exu1.rml.cansave_thr0),
3589 .CANRESTORE_reg (`SPC4.exu1.rml.canrestore_thr0),
3590 .OTHERWIN_reg (`SPC4.exu1.rml.otherwin_thr0),
3591 .WSTATE_reg (`SPC4.exu1.rml.wstate_thr0),
3592 .CLEANWIN_reg (`SPC4.exu1.rml.cleanwin_thr0),
3593 .rd_SOFTINT_reg (`SPC4.tlu.trl1.rd_softint0),
3594 .SOFTINT_reg (`SPC4.tlu.trl1.softint0),
3595 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec4),
3596 .GL_reg (`SPC4.tlu.tlu_gl4),
3597 .HPSTATE_reg (`SPC4.tlu.tsd1.arch_hpstate0),
3598 .HTBA_reg (`SPC4.tlu.tsd1.htba0[47:14]),
3599 .HINTP_reg (`SPC4.tlu.trl1.hintp0),
3600
3601 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_4[12:0]}),
3602 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_4[12:0]}),
3603 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_4[12:0]}),
3604 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_4[12:0]}),
3605 .LSU_CONTROL_reg ({29'd0,
3606 `SPC4.lsu.dcs.wpt_mode_4[1:0],
3607 `SPC4.lsu.dcs.wpt_mask_4[7:0],
3608 `SPC4.lsu.dcs.wpt_enable_4[1:0],
3609 18'd0,
3610 `SPC4.lsu.dcs.spec_enable[4],
3611 `SPC4.lsu.dcs.dmmu_enable[4],
3612 `SPC4.lsu.dcs.immu_enable[4],
3613 `SPC4.lsu.dcs.dc_enable[4],
3614 `SPC4.lsu.dcs.ic_enable[4]}),
3615 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.immu_tag_access_0[47:0]}),
3616 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.dmmu_tag_access_0[47:0]}),
3617 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint4[47:3],3'b00}),
3618 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_4[47:0]),
3619
3620 .Trap_Entry_1 (`PROBES4.trap_entry_1_t4),
3621 .Trap_Entry_2 (`PROBES4.trap_entry_2_t4),
3622 .Trap_Entry_3 (`PROBES4.trap_entry_3_t4),
3623 .Trap_Entry_4 (`PROBES4.trap_entry_4_t4),
3624 .Trap_Entry_5 (`PROBES4.trap_entry_5_t4),
3625 .Trap_Entry_6 (`PROBES4.trap_entry_6_t4),
3626
3627 .exu_valid (`PROBES4.ex_valid[4]),
3628
3629 .imul_valid (`PROBES4.imul_valid[4]),
3630
3631 .fp_valid (`PROBES4.fg_valid[4]),
3632 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3633 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3634 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3635
3636 .idiv_valid (`PROBES4.fgu_idiv_valid[4]),
3637
3638 .fdiv_valid (`PROBES4.fgu_fdiv_valid[4]),
3639
3640 .lsu_valid (`PROBES4.lsu_valid[4]),
3641 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3642 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3643 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3644
3645 .asi_valid (`PROBES4.asi_valid_fx5[4]),
3646 .asi_in_progress (`PROBES4.asi_in_progress_fx4[4]),
3647
3648 .tlu_valid (`PROBES4.tlu_valid[4])
3649`endif
3650 );
3651
3652
3653//----------------------------------------------------------
3654//
3655// THREAD 5
3656//
3657
3658 nas_pipe4 t5 (
3659 .mycid (cid),
3660 .mytid (3'h5),
3661
3662// If GATESIM, instantiate "dummy" module with floating ports since unused.
3663`ifdef GATESIM
3664 .opcode () // this and all other ports are unconnected
3665`else
3666 .opcode ({`PROBES4.op_5_w}),
3667 .PC_reg ({`PROBES4.pc_5_w}),
3668 .Y_reg (`SPC4.exu1.rml.arch_yreg_tid1_ff),
3669 .CCR_reg (`SPC4.exu1.ect.arch_ccr_tid1_lth),
3670 .FPRS_reg (`SPC4.fgu.fac.fprs_tid5),
3671 .FSR_reg (`SPC4.fgu.fad.fsr5_fx1[27:0]),
3672 .ASI_reg (`SPC4.lsu.dcs.asi_state5),
3673 .GSR_reg ({`SPC4.fgu.fgd.gsr5_mask_fx4[31:0], `SPC4.fgu.fpc.gsr5_11bits_fx4[10:0]}),
3674 .TICK_CMPR_reg (`PROBES4.tick_cmpr_5),
3675 .STICK_CMPR_reg (`PROBES4.stick_cmpr_5),
3676 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_5),
3677 .PSTATE_reg (`SPC4.tlu.tsd1.arch_pstate1),
3678 .TL_reg (`SPC4.tlu.trl1.tl1),
3679 .PIL_reg (`SPC4.tlu.trl1.pil1),
3680 .TBA_reg (`SPC4.tlu.tsd1.tba1[47:15]),
3681 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3682 .CWP_reg (`SPC4.exu1.rml.cwp_thr1),
3683 .CANSAVE_reg (`SPC4.exu1.rml.cansave_thr1),
3684 .CANRESTORE_reg (`SPC4.exu1.rml.canrestore_thr1),
3685 .OTHERWIN_reg (`SPC4.exu1.rml.otherwin_thr1),
3686 .WSTATE_reg (`SPC4.exu1.rml.wstate_thr1),
3687 .CLEANWIN_reg (`SPC4.exu1.rml.cleanwin_thr1),
3688 .rd_SOFTINT_reg (`SPC4.tlu.trl1.rd_softint1),
3689 .SOFTINT_reg (`SPC4.tlu.trl1.softint1),
3690 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec5),
3691 .GL_reg (`SPC4.tlu.tlu_gl5),
3692 .HPSTATE_reg (`SPC4.tlu.tsd1.arch_hpstate1),
3693 .HTBA_reg (`SPC4.tlu.tsd1.htba1[47:14]),
3694 .HINTP_reg (`SPC4.tlu.trl1.hintp1),
3695
3696 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_5[12:0]}),
3697 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_5[12:0]}),
3698 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_5[12:0]}),
3699 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_5[12:0]}),
3700 .LSU_CONTROL_reg ({29'd0,
3701 `SPC4.lsu.dcs.wpt_mode_5[1:0],
3702 `SPC4.lsu.dcs.wpt_mask_5[7:0],
3703 `SPC4.lsu.dcs.wpt_enable_5[1:0],
3704 18'd0,
3705 `SPC4.lsu.dcs.spec_enable[5],
3706 `SPC4.lsu.dcs.dmmu_enable[5],
3707 `SPC4.lsu.dcs.immu_enable[5],
3708 `SPC4.lsu.dcs.dc_enable[5],
3709 `SPC4.lsu.dcs.ic_enable[5]}),
3710 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.immu_tag_access_1[47:0]}),
3711 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.dmmu_tag_access_1[47:0]}),
3712 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint5[47:3],3'b00}),
3713 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_5[47:0]),
3714
3715 .Trap_Entry_1 (`PROBES4.trap_entry_1_t5),
3716 .Trap_Entry_2 (`PROBES4.trap_entry_2_t5),
3717 .Trap_Entry_3 (`PROBES4.trap_entry_3_t5),
3718 .Trap_Entry_4 (`PROBES4.trap_entry_4_t5),
3719 .Trap_Entry_5 (`PROBES4.trap_entry_5_t5),
3720 .Trap_Entry_6 (`PROBES4.trap_entry_6_t5),
3721
3722 .exu_valid (`PROBES4.ex_valid[5]),
3723
3724 .imul_valid (`PROBES4.imul_valid[5]),
3725
3726 .fp_valid (`PROBES4.fg_valid[5]),
3727 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3728 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3729 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3730
3731 .idiv_valid (`PROBES4.fgu_idiv_valid[5]),
3732
3733 .fdiv_valid (`PROBES4.fgu_fdiv_valid[5]),
3734
3735 .lsu_valid (`PROBES4.lsu_valid[5]),
3736 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3737 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3738 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3739
3740 .asi_valid (`PROBES4.asi_valid_fx5[5]),
3741 .asi_in_progress (`PROBES4.asi_in_progress_fx4[5]),
3742
3743 .tlu_valid (`PROBES4.tlu_valid[5])
3744`endif
3745 );
3746
3747
3748//----------------------------------------------------------
3749//
3750// THREAD 6
3751//
3752
3753 nas_pipe4 t6 (
3754 .mycid (cid),
3755 .mytid (3'h6),
3756
3757// If GATESIM, instantiate "dummy" module with floating ports since unused.
3758`ifdef GATESIM
3759 .opcode () // this and all other ports are unconnected
3760`else
3761 .opcode ({`PROBES4.op_6_w}),
3762 .PC_reg ({`PROBES4.pc_6_w}),
3763 .Y_reg (`SPC4.exu1.rml.arch_yreg_tid2_ff),
3764 .CCR_reg (`SPC4.exu1.ect.arch_ccr_tid2_lth),
3765 .FPRS_reg (`SPC4.fgu.fac.fprs_tid6),
3766 .FSR_reg (`SPC4.fgu.fad.fsr6_fx1[27:0]),
3767 .ASI_reg (`SPC4.lsu.dcs.asi_state6),
3768 .GSR_reg ({`SPC4.fgu.fgd.gsr6_mask_fx4[31:0], `SPC4.fgu.fpc.gsr6_11bits_fx4[10:0]}),
3769 .TICK_CMPR_reg (`PROBES4.tick_cmpr_6),
3770 .STICK_CMPR_reg (`PROBES4.stick_cmpr_6),
3771 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_6),
3772 .PSTATE_reg (`SPC4.tlu.tsd1.arch_pstate2),
3773 .TL_reg (`SPC4.tlu.trl1.tl2),
3774 .PIL_reg (`SPC4.tlu.trl1.pil2),
3775 .TBA_reg (`SPC4.tlu.tsd1.tba2[47:15]),
3776 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3777 .CWP_reg (`SPC4.exu1.rml.cwp_thr2),
3778 .CANSAVE_reg (`SPC4.exu1.rml.cansave_thr2),
3779 .CANRESTORE_reg (`SPC4.exu1.rml.canrestore_thr2),
3780 .OTHERWIN_reg (`SPC4.exu1.rml.otherwin_thr2),
3781 .WSTATE_reg (`SPC4.exu1.rml.wstate_thr2),
3782 .CLEANWIN_reg (`SPC4.exu1.rml.cleanwin_thr2),
3783 .rd_SOFTINT_reg (`SPC4.tlu.trl1.rd_softint2),
3784 .SOFTINT_reg (`SPC4.tlu.trl1.softint2),
3785 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec6),
3786 .GL_reg (`SPC4.tlu.tlu_gl6),
3787 .HPSTATE_reg (`SPC4.tlu.tsd1.arch_hpstate2),
3788 .HTBA_reg (`SPC4.tlu.tsd1.htba2[47:14]),
3789 .HINTP_reg (`SPC4.tlu.trl1.hintp2),
3790
3791 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_6[12:0]}),
3792 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_6[12:0]}),
3793 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_6[12:0]}),
3794 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_6[12:0]}),
3795 .LSU_CONTROL_reg ({29'd0,
3796 `SPC4.lsu.dcs.wpt_mode_6[1:0],
3797 `SPC4.lsu.dcs.wpt_mask_6[7:0],
3798 `SPC4.lsu.dcs.wpt_enable_6[1:0],
3799 18'd0,
3800 `SPC4.lsu.dcs.spec_enable[6],
3801 `SPC4.lsu.dcs.dmmu_enable[6],
3802 `SPC4.lsu.dcs.immu_enable[6],
3803 `SPC4.lsu.dcs.dc_enable[6],
3804 `SPC4.lsu.dcs.ic_enable[6]}),
3805 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.immu_tag_access_2[47:0]}),
3806 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.dmmu_tag_access_2[47:0]}),
3807 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint6[47:3],3'b00}),
3808 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_6[47:0]),
3809
3810 .Trap_Entry_1 (`PROBES4.trap_entry_1_t6),
3811 .Trap_Entry_2 (`PROBES4.trap_entry_2_t6),
3812 .Trap_Entry_3 (`PROBES4.trap_entry_3_t6),
3813 .Trap_Entry_4 (`PROBES4.trap_entry_4_t6),
3814 .Trap_Entry_5 (`PROBES4.trap_entry_5_t6),
3815 .Trap_Entry_6 (`PROBES4.trap_entry_6_t6),
3816
3817 .exu_valid (`PROBES4.ex_valid[6]),
3818
3819 .imul_valid (`PROBES4.imul_valid[6]),
3820
3821 .fp_valid (`PROBES4.fg_valid[6]),
3822 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3823 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3824 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3825
3826 .idiv_valid (`PROBES4.fgu_idiv_valid[6]),
3827
3828 .fdiv_valid (`PROBES4.fgu_fdiv_valid[6]),
3829
3830 .lsu_valid (`PROBES4.lsu_valid[6]),
3831 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3832 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3833 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3834
3835 .asi_valid (`PROBES4.asi_valid_fx5[6]),
3836 .asi_in_progress (`PROBES4.asi_in_progress_fx4[6]),
3837
3838 .tlu_valid (`PROBES4.tlu_valid[6])
3839`endif
3840 );
3841
3842
3843//----------------------------------------------------------
3844//
3845// THREAD 7
3846//
3847
3848 nas_pipe4 t7 (
3849 .mycid (cid),
3850 .mytid (3'h7),
3851
3852// If GATESIM, instantiate "dummy" module with floating ports since unused.
3853`ifdef GATESIM
3854 .opcode () // this and all other ports are unconnected
3855`else
3856 .opcode ({`PROBES4.op_7_w}),
3857 .PC_reg ({`PROBES4.pc_7_w}),
3858 .Y_reg (`SPC4.exu1.rml.arch_yreg_tid3_ff),
3859 .CCR_reg (`SPC4.exu1.ect.arch_ccr_tid3_lth),
3860 .FPRS_reg (`SPC4.fgu.fac.fprs_tid7),
3861 .FSR_reg (`SPC4.fgu.fad.fsr7_fx1[27:0]),
3862 .ASI_reg (`SPC4.lsu.dcs.asi_state7),
3863 .GSR_reg ({`SPC4.fgu.fgd.gsr7_mask_fx4[31:0], `SPC4.fgu.fpc.gsr7_11bits_fx4[10:0]}),
3864 .TICK_CMPR_reg (`PROBES4.tick_cmpr_7),
3865 .STICK_CMPR_reg (`PROBES4.stick_cmpr_7),
3866 .HSTICK_CMPR_reg (`PROBES4.hstick_cmpr_7),
3867 .PSTATE_reg (`SPC4.tlu.tsd1.arch_pstate3),
3868 .TL_reg (`SPC4.tlu.trl1.tl3),
3869 .PIL_reg (`SPC4.tlu.trl1.pil3),
3870 .TBA_reg (`SPC4.tlu.tsd1.tba3[47:15]),
3871 .VER_reg (`SPC4.tlu.asi.hver_value), // static
3872 .CWP_reg (`SPC4.exu1.rml.cwp_thr3),
3873 .CANSAVE_reg (`SPC4.exu1.rml.cansave_thr3),
3874 .CANRESTORE_reg (`SPC4.exu1.rml.canrestore_thr3),
3875 .OTHERWIN_reg (`SPC4.exu1.rml.otherwin_thr3),
3876 .WSTATE_reg (`SPC4.exu1.rml.wstate_thr3),
3877 .CLEANWIN_reg (`SPC4.exu1.rml.cleanwin_thr3),
3878 .rd_SOFTINT_reg (`SPC4.tlu.trl1.rd_softint3),
3879 .SOFTINT_reg (`SPC4.tlu.trl1.softint3),
3880 .INTR_RECEIVE_reg (`SPC4.tlu.cth.int_rec7),
3881 .GL_reg (`SPC4.tlu.tlu_gl7),
3882 .HPSTATE_reg (`SPC4.tlu.tsd1.arch_hpstate3),
3883 .HTBA_reg (`SPC4.tlu.tsd1.htba3[47:14]),
3884 .HINTP_reg (`SPC4.tlu.trl1.hintp3),
3885
3886 .CTXT_PRIM_0_reg ({51'b0,`SPC4.lsu.dcs.p0ctxt_7[12:0]}),
3887 .CTXT_SEC_0_reg ({51'b0,`SPC4.lsu.dcs.s0ctxt_7[12:0]}),
3888 .CTXT_PRIM_1_reg ({51'b0,`SPC4.lsu.dcs.p1ctxt_7[12:0]}),
3889 .CTXT_SEC_1_reg ({51'b0,`SPC4.lsu.dcs.s1ctxt_7[12:0]}),
3890 .LSU_CONTROL_reg ({29'd0,
3891 `SPC4.lsu.dcs.wpt_mode_7[1:0],
3892 `SPC4.lsu.dcs.wpt_mask_7[7:0],
3893 `SPC4.lsu.dcs.wpt_enable_7[1:0],
3894 18'd0,
3895 `SPC4.lsu.dcs.spec_enable[7],
3896 `SPC4.lsu.dcs.dmmu_enable[7],
3897 `SPC4.lsu.dcs.immu_enable[7],
3898 `SPC4.lsu.dcs.dc_enable[7],
3899 `SPC4.lsu.dcs.ic_enable[7]}),
3900 .I_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.immu_tag_access_3[47:0]}),
3901 .D_TAG_ACC_reg ({16'b0,`SPC4.mmu.asd1.dmmu_tag_access_3[47:0]}),
3902 .WATCHPOINT_ADDR_reg ({16'b0,`SPC4.lsu.dcs.watchpoint7[47:3],3'b00}),
3903 .DSFAR_reg (`SPC4.tlu.dfd.dsfar_7[47:0]),
3904
3905 .Trap_Entry_1 (`PROBES4.trap_entry_1_t7),
3906 .Trap_Entry_2 (`PROBES4.trap_entry_2_t7),
3907 .Trap_Entry_3 (`PROBES4.trap_entry_3_t7),
3908 .Trap_Entry_4 (`PROBES4.trap_entry_4_t7),
3909 .Trap_Entry_5 (`PROBES4.trap_entry_5_t7),
3910 .Trap_Entry_6 (`PROBES4.trap_entry_6_t7),
3911
3912 .exu_valid (`PROBES4.ex_valid[7]),
3913
3914 .imul_valid (`PROBES4.imul_valid[7]),
3915
3916 .fp_valid (`PROBES4.fg_valid[7]),
3917 .frf_w1_valid (`SPC4.fgu.frf.w1_valid),
3918 .frf_w1_tid (`SPC4.fgu.frf.w1_tid),
3919 .frf_w1_addr (`SPC4.fgu.frf.w1_addr),
3920
3921 .idiv_valid (`PROBES4.fgu_idiv_valid[7]),
3922
3923 .fdiv_valid (`PROBES4.fgu_fdiv_valid[7]),
3924
3925 .lsu_valid (`PROBES4.lsu_valid[7]),
3926 .frf_w2_valid (`SPC4.fgu.frf.w2_valid),
3927 .frf_w2_tid (`SPC4.fgu.frf.w2_tid),
3928 .frf_w2_addr (`SPC4.fgu.frf.w2_addr),
3929
3930 .asi_valid (`PROBES4.asi_valid_fx5[7]),
3931 .asi_in_progress (`PROBES4.asi_in_progress_fx4[7]),
3932
3933 .tlu_valid (`PROBES4.tlu_valid[7])
3934`endif
3935 );
3936
3937//----------------------------------------------------------
3938
3939
3940//----------------------------------------------------------
3941endmodule
3942
3943`endif
3944
3945`ifdef CORE_5
3946
3947module nas_core5 (
3948
3949 cid
3950);
3951
3952input [2:0] cid;
3953
3954integer i;
3955
3956//----------------------------------------------------------
3957
3958//----------------------------------------------------------
3959
3960//----------------------------------------------------------
3961//
3962// THREAD 0
3963//
3964
3965 nas_pipe5 t0 (
3966 .mycid (cid),
3967 .mytid (3'h0),
3968
3969// If GATESIM, instantiate "dummy" module with floating ports since unused.
3970`ifdef GATESIM
3971 .opcode () // this and all other ports are unconnected
3972`else
3973 .opcode ({`PROBES5.op_0_w}),
3974 .PC_reg ({`PROBES5.pc_0_w}),
3975 .Y_reg (`SPC5.exu0.rml.arch_yreg_tid0_ff),
3976 .CCR_reg (`SPC5.exu0.ect.arch_ccr_tid0_lth),
3977 .FPRS_reg (`SPC5.fgu.fac.fprs_tid0),
3978 .FSR_reg (`SPC5.fgu.fad.fsr0_fx1[27:0]),
3979 .ASI_reg (`SPC5.lsu.dcs.asi_state0),
3980 .GSR_reg ({`SPC5.fgu.fgd.gsr0_mask_fx4[31:0], `SPC5.fgu.fpc.gsr0_11bits_fx4[10:0]}),
3981 .TICK_CMPR_reg (`PROBES5.tick_cmpr_0),
3982 .STICK_CMPR_reg (`PROBES5.stick_cmpr_0),
3983 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_0),
3984 .PSTATE_reg (`SPC5.tlu.tsd0.arch_pstate0),
3985 .TL_reg (`SPC5.tlu.trl0.tl0),
3986 .PIL_reg (`SPC5.tlu.trl0.pil0),
3987 .TBA_reg (`SPC5.tlu.tsd0.tba0[47:15]),
3988 .VER_reg (`SPC5.tlu.asi.hver_value), // static
3989 .CWP_reg (`SPC5.exu0.rml.cwp_thr0),
3990 .CANSAVE_reg (`SPC5.exu0.rml.cansave_thr0),
3991 .CANRESTORE_reg (`SPC5.exu0.rml.canrestore_thr0),
3992 .OTHERWIN_reg (`SPC5.exu0.rml.otherwin_thr0),
3993 .WSTATE_reg (`SPC5.exu0.rml.wstate_thr0),
3994 .CLEANWIN_reg (`SPC5.exu0.rml.cleanwin_thr0),
3995 .rd_SOFTINT_reg (`SPC5.tlu.trl0.rd_softint0),
3996 .SOFTINT_reg (`SPC5.tlu.trl0.softint0),
3997 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec0),
3998 .GL_reg (`SPC5.tlu.tlu_gl0),
3999 .HPSTATE_reg (`SPC5.tlu.tsd0.arch_hpstate0),
4000 .HTBA_reg (`SPC5.tlu.tsd0.htba0[47:14]),
4001 .HINTP_reg (`SPC5.tlu.trl0.hintp0),
4002
4003 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_0[12:0]}),
4004 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_0[12:0]}),
4005 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_0[12:0]}),
4006 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_0[12:0]}),
4007 .LSU_CONTROL_reg ({29'd0,
4008 `SPC5.lsu.dcs.wpt_mode_0[1:0],
4009 `SPC5.lsu.dcs.wpt_mask_0[7:0],
4010 `SPC5.lsu.dcs.wpt_enable_0[1:0],
4011 18'd0,
4012 `SPC5.lsu.dcs.spec_enable[0],
4013 `SPC5.lsu.dcs.dmmu_enable[0],
4014 `SPC5.lsu.dcs.immu_enable[0],
4015 `SPC5.lsu.dcs.dc_enable[0],
4016 `SPC5.lsu.dcs.ic_enable[0]}),
4017 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.immu_tag_access_0[47:0]}),
4018 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.dmmu_tag_access_0[47:0]}),
4019 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint0[47:3],3'b00}),
4020 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_0[47:0]),
4021
4022 .Trap_Entry_1 (`PROBES5.trap_entry_1_t0),
4023 .Trap_Entry_2 (`PROBES5.trap_entry_2_t0),
4024 .Trap_Entry_3 (`PROBES5.trap_entry_3_t0),
4025 .Trap_Entry_4 (`PROBES5.trap_entry_4_t0),
4026 .Trap_Entry_5 (`PROBES5.trap_entry_5_t0),
4027 .Trap_Entry_6 (`PROBES5.trap_entry_6_t0),
4028
4029 .exu_valid (`PROBES5.ex_valid[0]),
4030
4031 .imul_valid (`PROBES5.imul_valid[0]),
4032
4033 .fp_valid (`PROBES5.fg_valid[0]),
4034 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4035 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4036 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4037
4038 .idiv_valid (`PROBES5.fgu_idiv_valid[0]),
4039
4040 .fdiv_valid (`PROBES5.fgu_fdiv_valid[0]),
4041
4042 .lsu_valid (`PROBES5.lsu_valid[0]),
4043 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4044 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4045 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4046
4047 .asi_valid (`PROBES5.asi_valid_fx5[0]),
4048 .asi_in_progress (`PROBES5.asi_in_progress_fx4[0]),
4049
4050 .tlu_valid (`PROBES5.tlu_valid[0])
4051`endif
4052 );
4053
4054
4055//----------------------------------------------------------
4056//
4057// THREAD 1
4058//
4059
4060 nas_pipe5 t1 (
4061 .mycid (cid),
4062 .mytid (3'h1),
4063
4064// If GATESIM, instantiate "dummy" module with floating ports since unused.
4065`ifdef GATESIM
4066 .opcode () // this and all other ports are unconnected
4067`else
4068 .opcode ({`PROBES5.op_1_w}),
4069 .PC_reg ({`PROBES5.pc_1_w}),
4070 .Y_reg (`SPC5.exu0.rml.arch_yreg_tid1_ff),
4071 .CCR_reg (`SPC5.exu0.ect.arch_ccr_tid1_lth),
4072 .FPRS_reg (`SPC5.fgu.fac.fprs_tid1),
4073 .FSR_reg (`SPC5.fgu.fad.fsr1_fx1[27:0]),
4074 .ASI_reg (`SPC5.lsu.dcs.asi_state1),
4075 .GSR_reg ({`SPC5.fgu.fgd.gsr1_mask_fx4[31:0], `SPC5.fgu.fpc.gsr1_11bits_fx4[10:0]}),
4076 .TICK_CMPR_reg (`PROBES5.tick_cmpr_1),
4077 .STICK_CMPR_reg (`PROBES5.stick_cmpr_1),
4078 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_1),
4079 .PSTATE_reg (`SPC5.tlu.tsd0.arch_pstate1),
4080 .TL_reg (`SPC5.tlu.trl0.tl1),
4081 .PIL_reg (`SPC5.tlu.trl0.pil1),
4082 .TBA_reg (`SPC5.tlu.tsd0.tba1[47:15]),
4083 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4084 .CWP_reg (`SPC5.exu0.rml.cwp_thr1),
4085 .CANSAVE_reg (`SPC5.exu0.rml.cansave_thr1),
4086 .CANRESTORE_reg (`SPC5.exu0.rml.canrestore_thr1),
4087 .OTHERWIN_reg (`SPC5.exu0.rml.otherwin_thr1),
4088 .WSTATE_reg (`SPC5.exu0.rml.wstate_thr1),
4089 .CLEANWIN_reg (`SPC5.exu0.rml.cleanwin_thr1),
4090 .rd_SOFTINT_reg (`SPC5.tlu.trl0.rd_softint1),
4091 .SOFTINT_reg (`SPC5.tlu.trl0.softint1),
4092 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec1),
4093 .GL_reg (`SPC5.tlu.tlu_gl1),
4094 .HPSTATE_reg (`SPC5.tlu.tsd0.arch_hpstate1),
4095 .HTBA_reg (`SPC5.tlu.tsd0.htba1[47:14]),
4096 .HINTP_reg (`SPC5.tlu.trl0.hintp1),
4097
4098 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_1[12:0]}),
4099 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_1[12:0]}),
4100 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_1[12:0]}),
4101 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_1[12:0]}),
4102 .LSU_CONTROL_reg ({29'd0,
4103 `SPC5.lsu.dcs.wpt_mode_1[1:0],
4104 `SPC5.lsu.dcs.wpt_mask_1[7:0],
4105 `SPC5.lsu.dcs.wpt_enable_1[1:0],
4106 18'd0,
4107 `SPC5.lsu.dcs.spec_enable[1],
4108 `SPC5.lsu.dcs.dmmu_enable[1],
4109 `SPC5.lsu.dcs.immu_enable[1],
4110 `SPC5.lsu.dcs.dc_enable[1],
4111 `SPC5.lsu.dcs.ic_enable[1]}),
4112 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.immu_tag_access_1[47:0]}),
4113 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.dmmu_tag_access_1[47:0]}),
4114 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint1[47:3],3'b00}),
4115 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_1[47:0]),
4116
4117 .Trap_Entry_1 (`PROBES5.trap_entry_1_t1),
4118 .Trap_Entry_2 (`PROBES5.trap_entry_2_t1),
4119 .Trap_Entry_3 (`PROBES5.trap_entry_3_t1),
4120 .Trap_Entry_4 (`PROBES5.trap_entry_4_t1),
4121 .Trap_Entry_5 (`PROBES5.trap_entry_5_t1),
4122 .Trap_Entry_6 (`PROBES5.trap_entry_6_t1),
4123
4124 .exu_valid (`PROBES5.ex_valid[1]),
4125
4126 .imul_valid (`PROBES5.imul_valid[1]),
4127
4128 .fp_valid (`PROBES5.fg_valid[1]),
4129 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4130 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4131 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4132
4133 .idiv_valid (`PROBES5.fgu_idiv_valid[1]),
4134
4135 .fdiv_valid (`PROBES5.fgu_fdiv_valid[1]),
4136
4137 .lsu_valid (`PROBES5.lsu_valid[1]),
4138 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4139 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4140 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4141
4142 .asi_valid (`PROBES5.asi_valid_fx5[1]),
4143 .asi_in_progress (`PROBES5.asi_in_progress_fx4[1]),
4144
4145 .tlu_valid (`PROBES5.tlu_valid[1])
4146`endif
4147 );
4148
4149
4150//----------------------------------------------------------
4151//
4152// THREAD 2
4153//
4154
4155 nas_pipe5 t2 (
4156 .mycid (cid),
4157 .mytid (3'h2),
4158
4159// If GATESIM, instantiate "dummy" module with floating ports since unused.
4160`ifdef GATESIM
4161 .opcode () // this and all other ports are unconnected
4162`else
4163 .opcode ({`PROBES5.op_2_w}),
4164 .PC_reg ({`PROBES5.pc_2_w}),
4165 .Y_reg (`SPC5.exu0.rml.arch_yreg_tid2_ff),
4166 .CCR_reg (`SPC5.exu0.ect.arch_ccr_tid2_lth),
4167 .FPRS_reg (`SPC5.fgu.fac.fprs_tid2),
4168 .FSR_reg (`SPC5.fgu.fad.fsr2_fx1[27:0]),
4169 .ASI_reg (`SPC5.lsu.dcs.asi_state2),
4170 .GSR_reg ({`SPC5.fgu.fgd.gsr2_mask_fx4[31:0], `SPC5.fgu.fpc.gsr2_11bits_fx4[10:0]}),
4171 .TICK_CMPR_reg (`PROBES5.tick_cmpr_2),
4172 .STICK_CMPR_reg (`PROBES5.stick_cmpr_2),
4173 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_2),
4174 .PSTATE_reg (`SPC5.tlu.tsd0.arch_pstate2),
4175 .TL_reg (`SPC5.tlu.trl0.tl2),
4176 .PIL_reg (`SPC5.tlu.trl0.pil2),
4177 .TBA_reg (`SPC5.tlu.tsd0.tba2[47:15]),
4178 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4179 .CWP_reg (`SPC5.exu0.rml.cwp_thr2),
4180 .CANSAVE_reg (`SPC5.exu0.rml.cansave_thr2),
4181 .CANRESTORE_reg (`SPC5.exu0.rml.canrestore_thr2),
4182 .OTHERWIN_reg (`SPC5.exu0.rml.otherwin_thr2),
4183 .WSTATE_reg (`SPC5.exu0.rml.wstate_thr2),
4184 .CLEANWIN_reg (`SPC5.exu0.rml.cleanwin_thr2),
4185 .rd_SOFTINT_reg (`SPC5.tlu.trl0.rd_softint2),
4186 .SOFTINT_reg (`SPC5.tlu.trl0.softint2),
4187 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec2),
4188 .GL_reg (`SPC5.tlu.tlu_gl2),
4189 .HPSTATE_reg (`SPC5.tlu.tsd0.arch_hpstate2),
4190 .HTBA_reg (`SPC5.tlu.tsd0.htba2[47:14]),
4191 .HINTP_reg (`SPC5.tlu.trl0.hintp2),
4192
4193 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_2[12:0]}),
4194 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_2[12:0]}),
4195 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_2[12:0]}),
4196 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_2[12:0]}),
4197 .LSU_CONTROL_reg ({29'd0,
4198 `SPC5.lsu.dcs.wpt_mode_2[1:0],
4199 `SPC5.lsu.dcs.wpt_mask_2[7:0],
4200 `SPC5.lsu.dcs.wpt_enable_2[1:0],
4201 18'd0,
4202 `SPC5.lsu.dcs.spec_enable[2],
4203 `SPC5.lsu.dcs.dmmu_enable[2],
4204 `SPC5.lsu.dcs.immu_enable[2],
4205 `SPC5.lsu.dcs.dc_enable[2],
4206 `SPC5.lsu.dcs.ic_enable[2]}),
4207 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.immu_tag_access_2[47:0]}),
4208 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.dmmu_tag_access_2[47:0]}),
4209 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint2[47:3],3'b00}),
4210 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_2[47:0]),
4211
4212 .Trap_Entry_1 (`PROBES5.trap_entry_1_t2),
4213 .Trap_Entry_2 (`PROBES5.trap_entry_2_t2),
4214 .Trap_Entry_3 (`PROBES5.trap_entry_3_t2),
4215 .Trap_Entry_4 (`PROBES5.trap_entry_4_t2),
4216 .Trap_Entry_5 (`PROBES5.trap_entry_5_t2),
4217 .Trap_Entry_6 (`PROBES5.trap_entry_6_t2),
4218
4219 .exu_valid (`PROBES5.ex_valid[2]),
4220
4221 .imul_valid (`PROBES5.imul_valid[2]),
4222
4223 .fp_valid (`PROBES5.fg_valid[2]),
4224 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4225 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4226 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4227
4228 .idiv_valid (`PROBES5.fgu_idiv_valid[2]),
4229
4230 .fdiv_valid (`PROBES5.fgu_fdiv_valid[2]),
4231
4232 .lsu_valid (`PROBES5.lsu_valid[2]),
4233 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4234 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4235 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4236
4237 .asi_valid (`PROBES5.asi_valid_fx5[2]),
4238 .asi_in_progress (`PROBES5.asi_in_progress_fx4[2]),
4239
4240 .tlu_valid (`PROBES5.tlu_valid[2])
4241`endif
4242 );
4243
4244
4245//----------------------------------------------------------
4246//
4247// THREAD 3
4248//
4249
4250 nas_pipe5 t3 (
4251 .mycid (cid),
4252 .mytid (3'h3),
4253
4254// If GATESIM, instantiate "dummy" module with floating ports since unused.
4255`ifdef GATESIM
4256 .opcode () // this and all other ports are unconnected
4257`else
4258 .opcode ({`PROBES5.op_3_w}),
4259 .PC_reg ({`PROBES5.pc_3_w}),
4260 .Y_reg (`SPC5.exu0.rml.arch_yreg_tid3_ff),
4261 .CCR_reg (`SPC5.exu0.ect.arch_ccr_tid3_lth),
4262 .FPRS_reg (`SPC5.fgu.fac.fprs_tid3),
4263 .FSR_reg (`SPC5.fgu.fad.fsr3_fx1[27:0]),
4264 .ASI_reg (`SPC5.lsu.dcs.asi_state3),
4265 .GSR_reg ({`SPC5.fgu.fgd.gsr3_mask_fx4[31:0], `SPC5.fgu.fpc.gsr3_11bits_fx4[10:0]}),
4266 .TICK_CMPR_reg (`PROBES5.tick_cmpr_3),
4267 .STICK_CMPR_reg (`PROBES5.stick_cmpr_3),
4268 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_3),
4269 .PSTATE_reg (`SPC5.tlu.tsd0.arch_pstate3),
4270 .TL_reg (`SPC5.tlu.trl0.tl3),
4271 .PIL_reg (`SPC5.tlu.trl0.pil3),
4272 .TBA_reg (`SPC5.tlu.tsd0.tba3[47:15]),
4273 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4274 .CWP_reg (`SPC5.exu0.rml.cwp_thr3),
4275 .CANSAVE_reg (`SPC5.exu0.rml.cansave_thr3),
4276 .CANRESTORE_reg (`SPC5.exu0.rml.canrestore_thr3),
4277 .OTHERWIN_reg (`SPC5.exu0.rml.otherwin_thr3),
4278 .WSTATE_reg (`SPC5.exu0.rml.wstate_thr3),
4279 .CLEANWIN_reg (`SPC5.exu0.rml.cleanwin_thr3),
4280 .rd_SOFTINT_reg (`SPC5.tlu.trl0.rd_softint3),
4281 .SOFTINT_reg (`SPC5.tlu.trl0.softint3),
4282 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec3),
4283 .GL_reg (`SPC5.tlu.tlu_gl3),
4284 .HPSTATE_reg (`SPC5.tlu.tsd0.arch_hpstate3),
4285 .HTBA_reg (`SPC5.tlu.tsd0.htba3[47:14]),
4286 .HINTP_reg (`SPC5.tlu.trl0.hintp3),
4287
4288 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_3[12:0]}),
4289 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_3[12:0]}),
4290 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_3[12:0]}),
4291 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_3[12:0]}),
4292 .LSU_CONTROL_reg ({29'd0,
4293 `SPC5.lsu.dcs.wpt_mode_3[1:0],
4294 `SPC5.lsu.dcs.wpt_mask_3[7:0],
4295 `SPC5.lsu.dcs.wpt_enable_3[1:0],
4296 18'd0,
4297 `SPC5.lsu.dcs.spec_enable[3],
4298 `SPC5.lsu.dcs.dmmu_enable[3],
4299 `SPC5.lsu.dcs.immu_enable[3],
4300 `SPC5.lsu.dcs.dc_enable[3],
4301 `SPC5.lsu.dcs.ic_enable[3]}),
4302 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.immu_tag_access_3[47:0]}),
4303 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd0.dmmu_tag_access_3[47:0]}),
4304 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint3[47:3],3'b00}),
4305 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_3[47:0]),
4306
4307 .Trap_Entry_1 (`PROBES5.trap_entry_1_t3),
4308 .Trap_Entry_2 (`PROBES5.trap_entry_2_t3),
4309 .Trap_Entry_3 (`PROBES5.trap_entry_3_t3),
4310 .Trap_Entry_4 (`PROBES5.trap_entry_4_t3),
4311 .Trap_Entry_5 (`PROBES5.trap_entry_5_t3),
4312 .Trap_Entry_6 (`PROBES5.trap_entry_6_t3),
4313
4314 .exu_valid (`PROBES5.ex_valid[3]),
4315
4316 .imul_valid (`PROBES5.imul_valid[3]),
4317
4318 .fp_valid (`PROBES5.fg_valid[3]),
4319 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4320 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4321 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4322
4323 .idiv_valid (`PROBES5.fgu_idiv_valid[3]),
4324
4325 .fdiv_valid (`PROBES5.fgu_fdiv_valid[3]),
4326
4327 .lsu_valid (`PROBES5.lsu_valid[3]),
4328 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4329 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4330 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4331
4332 .asi_valid (`PROBES5.asi_valid_fx5[3]),
4333 .asi_in_progress (`PROBES5.asi_in_progress_fx4[3]),
4334
4335 .tlu_valid (`PROBES5.tlu_valid[3])
4336`endif
4337 );
4338
4339
4340//----------------------------------------------------------
4341//
4342// THREAD 4
4343//
4344
4345 nas_pipe5 t4 (
4346 .mycid (cid),
4347 .mytid (3'h4),
4348
4349// If GATESIM, instantiate "dummy" module with floating ports since unused.
4350`ifdef GATESIM
4351 .opcode () // this and all other ports are unconnected
4352`else
4353 .opcode ({`PROBES5.op_4_w}),
4354 .PC_reg ({`PROBES5.pc_4_w}),
4355 .Y_reg (`SPC5.exu1.rml.arch_yreg_tid0_ff),
4356 .CCR_reg (`SPC5.exu1.ect.arch_ccr_tid0_lth),
4357 .FPRS_reg (`SPC5.fgu.fac.fprs_tid4),
4358 .FSR_reg (`SPC5.fgu.fad.fsr4_fx1[27:0]),
4359 .ASI_reg (`SPC5.lsu.dcs.asi_state4),
4360 .GSR_reg ({`SPC5.fgu.fgd.gsr4_mask_fx4[31:0], `SPC5.fgu.fpc.gsr4_11bits_fx4[10:0]}),
4361 .TICK_CMPR_reg (`PROBES5.tick_cmpr_4),
4362 .STICK_CMPR_reg (`PROBES5.stick_cmpr_4),
4363 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_4),
4364 .PSTATE_reg (`SPC5.tlu.tsd1.arch_pstate0),
4365 .TL_reg (`SPC5.tlu.trl1.tl0),
4366 .PIL_reg (`SPC5.tlu.trl1.pil0),
4367 .TBA_reg (`SPC5.tlu.tsd1.tba0[47:15]),
4368 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4369 .CWP_reg (`SPC5.exu1.rml.cwp_thr0),
4370 .CANSAVE_reg (`SPC5.exu1.rml.cansave_thr0),
4371 .CANRESTORE_reg (`SPC5.exu1.rml.canrestore_thr0),
4372 .OTHERWIN_reg (`SPC5.exu1.rml.otherwin_thr0),
4373 .WSTATE_reg (`SPC5.exu1.rml.wstate_thr0),
4374 .CLEANWIN_reg (`SPC5.exu1.rml.cleanwin_thr0),
4375 .rd_SOFTINT_reg (`SPC5.tlu.trl1.rd_softint0),
4376 .SOFTINT_reg (`SPC5.tlu.trl1.softint0),
4377 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec4),
4378 .GL_reg (`SPC5.tlu.tlu_gl4),
4379 .HPSTATE_reg (`SPC5.tlu.tsd1.arch_hpstate0),
4380 .HTBA_reg (`SPC5.tlu.tsd1.htba0[47:14]),
4381 .HINTP_reg (`SPC5.tlu.trl1.hintp0),
4382
4383 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_4[12:0]}),
4384 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_4[12:0]}),
4385 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_4[12:0]}),
4386 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_4[12:0]}),
4387 .LSU_CONTROL_reg ({29'd0,
4388 `SPC5.lsu.dcs.wpt_mode_4[1:0],
4389 `SPC5.lsu.dcs.wpt_mask_4[7:0],
4390 `SPC5.lsu.dcs.wpt_enable_4[1:0],
4391 18'd0,
4392 `SPC5.lsu.dcs.spec_enable[4],
4393 `SPC5.lsu.dcs.dmmu_enable[4],
4394 `SPC5.lsu.dcs.immu_enable[4],
4395 `SPC5.lsu.dcs.dc_enable[4],
4396 `SPC5.lsu.dcs.ic_enable[4]}),
4397 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.immu_tag_access_0[47:0]}),
4398 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.dmmu_tag_access_0[47:0]}),
4399 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint4[47:3],3'b00}),
4400 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_4[47:0]),
4401
4402 .Trap_Entry_1 (`PROBES5.trap_entry_1_t4),
4403 .Trap_Entry_2 (`PROBES5.trap_entry_2_t4),
4404 .Trap_Entry_3 (`PROBES5.trap_entry_3_t4),
4405 .Trap_Entry_4 (`PROBES5.trap_entry_4_t4),
4406 .Trap_Entry_5 (`PROBES5.trap_entry_5_t4),
4407 .Trap_Entry_6 (`PROBES5.trap_entry_6_t4),
4408
4409 .exu_valid (`PROBES5.ex_valid[4]),
4410
4411 .imul_valid (`PROBES5.imul_valid[4]),
4412
4413 .fp_valid (`PROBES5.fg_valid[4]),
4414 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4415 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4416 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4417
4418 .idiv_valid (`PROBES5.fgu_idiv_valid[4]),
4419
4420 .fdiv_valid (`PROBES5.fgu_fdiv_valid[4]),
4421
4422 .lsu_valid (`PROBES5.lsu_valid[4]),
4423 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4424 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4425 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4426
4427 .asi_valid (`PROBES5.asi_valid_fx5[4]),
4428 .asi_in_progress (`PROBES5.asi_in_progress_fx4[4]),
4429
4430 .tlu_valid (`PROBES5.tlu_valid[4])
4431`endif
4432 );
4433
4434
4435//----------------------------------------------------------
4436//
4437// THREAD 5
4438//
4439
4440 nas_pipe5 t5 (
4441 .mycid (cid),
4442 .mytid (3'h5),
4443
4444// If GATESIM, instantiate "dummy" module with floating ports since unused.
4445`ifdef GATESIM
4446 .opcode () // this and all other ports are unconnected
4447`else
4448 .opcode ({`PROBES5.op_5_w}),
4449 .PC_reg ({`PROBES5.pc_5_w}),
4450 .Y_reg (`SPC5.exu1.rml.arch_yreg_tid1_ff),
4451 .CCR_reg (`SPC5.exu1.ect.arch_ccr_tid1_lth),
4452 .FPRS_reg (`SPC5.fgu.fac.fprs_tid5),
4453 .FSR_reg (`SPC5.fgu.fad.fsr5_fx1[27:0]),
4454 .ASI_reg (`SPC5.lsu.dcs.asi_state5),
4455 .GSR_reg ({`SPC5.fgu.fgd.gsr5_mask_fx4[31:0], `SPC5.fgu.fpc.gsr5_11bits_fx4[10:0]}),
4456 .TICK_CMPR_reg (`PROBES5.tick_cmpr_5),
4457 .STICK_CMPR_reg (`PROBES5.stick_cmpr_5),
4458 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_5),
4459 .PSTATE_reg (`SPC5.tlu.tsd1.arch_pstate1),
4460 .TL_reg (`SPC5.tlu.trl1.tl1),
4461 .PIL_reg (`SPC5.tlu.trl1.pil1),
4462 .TBA_reg (`SPC5.tlu.tsd1.tba1[47:15]),
4463 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4464 .CWP_reg (`SPC5.exu1.rml.cwp_thr1),
4465 .CANSAVE_reg (`SPC5.exu1.rml.cansave_thr1),
4466 .CANRESTORE_reg (`SPC5.exu1.rml.canrestore_thr1),
4467 .OTHERWIN_reg (`SPC5.exu1.rml.otherwin_thr1),
4468 .WSTATE_reg (`SPC5.exu1.rml.wstate_thr1),
4469 .CLEANWIN_reg (`SPC5.exu1.rml.cleanwin_thr1),
4470 .rd_SOFTINT_reg (`SPC5.tlu.trl1.rd_softint1),
4471 .SOFTINT_reg (`SPC5.tlu.trl1.softint1),
4472 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec5),
4473 .GL_reg (`SPC5.tlu.tlu_gl5),
4474 .HPSTATE_reg (`SPC5.tlu.tsd1.arch_hpstate1),
4475 .HTBA_reg (`SPC5.tlu.tsd1.htba1[47:14]),
4476 .HINTP_reg (`SPC5.tlu.trl1.hintp1),
4477
4478 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_5[12:0]}),
4479 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_5[12:0]}),
4480 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_5[12:0]}),
4481 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_5[12:0]}),
4482 .LSU_CONTROL_reg ({29'd0,
4483 `SPC5.lsu.dcs.wpt_mode_5[1:0],
4484 `SPC5.lsu.dcs.wpt_mask_5[7:0],
4485 `SPC5.lsu.dcs.wpt_enable_5[1:0],
4486 18'd0,
4487 `SPC5.lsu.dcs.spec_enable[5],
4488 `SPC5.lsu.dcs.dmmu_enable[5],
4489 `SPC5.lsu.dcs.immu_enable[5],
4490 `SPC5.lsu.dcs.dc_enable[5],
4491 `SPC5.lsu.dcs.ic_enable[5]}),
4492 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.immu_tag_access_1[47:0]}),
4493 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.dmmu_tag_access_1[47:0]}),
4494 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint5[47:3],3'b00}),
4495 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_5[47:0]),
4496
4497 .Trap_Entry_1 (`PROBES5.trap_entry_1_t5),
4498 .Trap_Entry_2 (`PROBES5.trap_entry_2_t5),
4499 .Trap_Entry_3 (`PROBES5.trap_entry_3_t5),
4500 .Trap_Entry_4 (`PROBES5.trap_entry_4_t5),
4501 .Trap_Entry_5 (`PROBES5.trap_entry_5_t5),
4502 .Trap_Entry_6 (`PROBES5.trap_entry_6_t5),
4503
4504 .exu_valid (`PROBES5.ex_valid[5]),
4505
4506 .imul_valid (`PROBES5.imul_valid[5]),
4507
4508 .fp_valid (`PROBES5.fg_valid[5]),
4509 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4510 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4511 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4512
4513 .idiv_valid (`PROBES5.fgu_idiv_valid[5]),
4514
4515 .fdiv_valid (`PROBES5.fgu_fdiv_valid[5]),
4516
4517 .lsu_valid (`PROBES5.lsu_valid[5]),
4518 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4519 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4520 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4521
4522 .asi_valid (`PROBES5.asi_valid_fx5[5]),
4523 .asi_in_progress (`PROBES5.asi_in_progress_fx4[5]),
4524
4525 .tlu_valid (`PROBES5.tlu_valid[5])
4526`endif
4527 );
4528
4529
4530//----------------------------------------------------------
4531//
4532// THREAD 6
4533//
4534
4535 nas_pipe5 t6 (
4536 .mycid (cid),
4537 .mytid (3'h6),
4538
4539// If GATESIM, instantiate "dummy" module with floating ports since unused.
4540`ifdef GATESIM
4541 .opcode () // this and all other ports are unconnected
4542`else
4543 .opcode ({`PROBES5.op_6_w}),
4544 .PC_reg ({`PROBES5.pc_6_w}),
4545 .Y_reg (`SPC5.exu1.rml.arch_yreg_tid2_ff),
4546 .CCR_reg (`SPC5.exu1.ect.arch_ccr_tid2_lth),
4547 .FPRS_reg (`SPC5.fgu.fac.fprs_tid6),
4548 .FSR_reg (`SPC5.fgu.fad.fsr6_fx1[27:0]),
4549 .ASI_reg (`SPC5.lsu.dcs.asi_state6),
4550 .GSR_reg ({`SPC5.fgu.fgd.gsr6_mask_fx4[31:0], `SPC5.fgu.fpc.gsr6_11bits_fx4[10:0]}),
4551 .TICK_CMPR_reg (`PROBES5.tick_cmpr_6),
4552 .STICK_CMPR_reg (`PROBES5.stick_cmpr_6),
4553 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_6),
4554 .PSTATE_reg (`SPC5.tlu.tsd1.arch_pstate2),
4555 .TL_reg (`SPC5.tlu.trl1.tl2),
4556 .PIL_reg (`SPC5.tlu.trl1.pil2),
4557 .TBA_reg (`SPC5.tlu.tsd1.tba2[47:15]),
4558 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4559 .CWP_reg (`SPC5.exu1.rml.cwp_thr2),
4560 .CANSAVE_reg (`SPC5.exu1.rml.cansave_thr2),
4561 .CANRESTORE_reg (`SPC5.exu1.rml.canrestore_thr2),
4562 .OTHERWIN_reg (`SPC5.exu1.rml.otherwin_thr2),
4563 .WSTATE_reg (`SPC5.exu1.rml.wstate_thr2),
4564 .CLEANWIN_reg (`SPC5.exu1.rml.cleanwin_thr2),
4565 .rd_SOFTINT_reg (`SPC5.tlu.trl1.rd_softint2),
4566 .SOFTINT_reg (`SPC5.tlu.trl1.softint2),
4567 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec6),
4568 .GL_reg (`SPC5.tlu.tlu_gl6),
4569 .HPSTATE_reg (`SPC5.tlu.tsd1.arch_hpstate2),
4570 .HTBA_reg (`SPC5.tlu.tsd1.htba2[47:14]),
4571 .HINTP_reg (`SPC5.tlu.trl1.hintp2),
4572
4573 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_6[12:0]}),
4574 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_6[12:0]}),
4575 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_6[12:0]}),
4576 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_6[12:0]}),
4577 .LSU_CONTROL_reg ({29'd0,
4578 `SPC5.lsu.dcs.wpt_mode_6[1:0],
4579 `SPC5.lsu.dcs.wpt_mask_6[7:0],
4580 `SPC5.lsu.dcs.wpt_enable_6[1:0],
4581 18'd0,
4582 `SPC5.lsu.dcs.spec_enable[6],
4583 `SPC5.lsu.dcs.dmmu_enable[6],
4584 `SPC5.lsu.dcs.immu_enable[6],
4585 `SPC5.lsu.dcs.dc_enable[6],
4586 `SPC5.lsu.dcs.ic_enable[6]}),
4587 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.immu_tag_access_2[47:0]}),
4588 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.dmmu_tag_access_2[47:0]}),
4589 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint6[47:3],3'b00}),
4590 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_6[47:0]),
4591
4592 .Trap_Entry_1 (`PROBES5.trap_entry_1_t6),
4593 .Trap_Entry_2 (`PROBES5.trap_entry_2_t6),
4594 .Trap_Entry_3 (`PROBES5.trap_entry_3_t6),
4595 .Trap_Entry_4 (`PROBES5.trap_entry_4_t6),
4596 .Trap_Entry_5 (`PROBES5.trap_entry_5_t6),
4597 .Trap_Entry_6 (`PROBES5.trap_entry_6_t6),
4598
4599 .exu_valid (`PROBES5.ex_valid[6]),
4600
4601 .imul_valid (`PROBES5.imul_valid[6]),
4602
4603 .fp_valid (`PROBES5.fg_valid[6]),
4604 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4605 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4606 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4607
4608 .idiv_valid (`PROBES5.fgu_idiv_valid[6]),
4609
4610 .fdiv_valid (`PROBES5.fgu_fdiv_valid[6]),
4611
4612 .lsu_valid (`PROBES5.lsu_valid[6]),
4613 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4614 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4615 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4616
4617 .asi_valid (`PROBES5.asi_valid_fx5[6]),
4618 .asi_in_progress (`PROBES5.asi_in_progress_fx4[6]),
4619
4620 .tlu_valid (`PROBES5.tlu_valid[6])
4621`endif
4622 );
4623
4624
4625//----------------------------------------------------------
4626//
4627// THREAD 7
4628//
4629
4630 nas_pipe5 t7 (
4631 .mycid (cid),
4632 .mytid (3'h7),
4633
4634// If GATESIM, instantiate "dummy" module with floating ports since unused.
4635`ifdef GATESIM
4636 .opcode () // this and all other ports are unconnected
4637`else
4638 .opcode ({`PROBES5.op_7_w}),
4639 .PC_reg ({`PROBES5.pc_7_w}),
4640 .Y_reg (`SPC5.exu1.rml.arch_yreg_tid3_ff),
4641 .CCR_reg (`SPC5.exu1.ect.arch_ccr_tid3_lth),
4642 .FPRS_reg (`SPC5.fgu.fac.fprs_tid7),
4643 .FSR_reg (`SPC5.fgu.fad.fsr7_fx1[27:0]),
4644 .ASI_reg (`SPC5.lsu.dcs.asi_state7),
4645 .GSR_reg ({`SPC5.fgu.fgd.gsr7_mask_fx4[31:0], `SPC5.fgu.fpc.gsr7_11bits_fx4[10:0]}),
4646 .TICK_CMPR_reg (`PROBES5.tick_cmpr_7),
4647 .STICK_CMPR_reg (`PROBES5.stick_cmpr_7),
4648 .HSTICK_CMPR_reg (`PROBES5.hstick_cmpr_7),
4649 .PSTATE_reg (`SPC5.tlu.tsd1.arch_pstate3),
4650 .TL_reg (`SPC5.tlu.trl1.tl3),
4651 .PIL_reg (`SPC5.tlu.trl1.pil3),
4652 .TBA_reg (`SPC5.tlu.tsd1.tba3[47:15]),
4653 .VER_reg (`SPC5.tlu.asi.hver_value), // static
4654 .CWP_reg (`SPC5.exu1.rml.cwp_thr3),
4655 .CANSAVE_reg (`SPC5.exu1.rml.cansave_thr3),
4656 .CANRESTORE_reg (`SPC5.exu1.rml.canrestore_thr3),
4657 .OTHERWIN_reg (`SPC5.exu1.rml.otherwin_thr3),
4658 .WSTATE_reg (`SPC5.exu1.rml.wstate_thr3),
4659 .CLEANWIN_reg (`SPC5.exu1.rml.cleanwin_thr3),
4660 .rd_SOFTINT_reg (`SPC5.tlu.trl1.rd_softint3),
4661 .SOFTINT_reg (`SPC5.tlu.trl1.softint3),
4662 .INTR_RECEIVE_reg (`SPC5.tlu.cth.int_rec7),
4663 .GL_reg (`SPC5.tlu.tlu_gl7),
4664 .HPSTATE_reg (`SPC5.tlu.tsd1.arch_hpstate3),
4665 .HTBA_reg (`SPC5.tlu.tsd1.htba3[47:14]),
4666 .HINTP_reg (`SPC5.tlu.trl1.hintp3),
4667
4668 .CTXT_PRIM_0_reg ({51'b0,`SPC5.lsu.dcs.p0ctxt_7[12:0]}),
4669 .CTXT_SEC_0_reg ({51'b0,`SPC5.lsu.dcs.s0ctxt_7[12:0]}),
4670 .CTXT_PRIM_1_reg ({51'b0,`SPC5.lsu.dcs.p1ctxt_7[12:0]}),
4671 .CTXT_SEC_1_reg ({51'b0,`SPC5.lsu.dcs.s1ctxt_7[12:0]}),
4672 .LSU_CONTROL_reg ({29'd0,
4673 `SPC5.lsu.dcs.wpt_mode_7[1:0],
4674 `SPC5.lsu.dcs.wpt_mask_7[7:0],
4675 `SPC5.lsu.dcs.wpt_enable_7[1:0],
4676 18'd0,
4677 `SPC5.lsu.dcs.spec_enable[7],
4678 `SPC5.lsu.dcs.dmmu_enable[7],
4679 `SPC5.lsu.dcs.immu_enable[7],
4680 `SPC5.lsu.dcs.dc_enable[7],
4681 `SPC5.lsu.dcs.ic_enable[7]}),
4682 .I_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.immu_tag_access_3[47:0]}),
4683 .D_TAG_ACC_reg ({16'b0,`SPC5.mmu.asd1.dmmu_tag_access_3[47:0]}),
4684 .WATCHPOINT_ADDR_reg ({16'b0,`SPC5.lsu.dcs.watchpoint7[47:3],3'b00}),
4685 .DSFAR_reg (`SPC5.tlu.dfd.dsfar_7[47:0]),
4686
4687 .Trap_Entry_1 (`PROBES5.trap_entry_1_t7),
4688 .Trap_Entry_2 (`PROBES5.trap_entry_2_t7),
4689 .Trap_Entry_3 (`PROBES5.trap_entry_3_t7),
4690 .Trap_Entry_4 (`PROBES5.trap_entry_4_t7),
4691 .Trap_Entry_5 (`PROBES5.trap_entry_5_t7),
4692 .Trap_Entry_6 (`PROBES5.trap_entry_6_t7),
4693
4694 .exu_valid (`PROBES5.ex_valid[7]),
4695
4696 .imul_valid (`PROBES5.imul_valid[7]),
4697
4698 .fp_valid (`PROBES5.fg_valid[7]),
4699 .frf_w1_valid (`SPC5.fgu.frf.w1_valid),
4700 .frf_w1_tid (`SPC5.fgu.frf.w1_tid),
4701 .frf_w1_addr (`SPC5.fgu.frf.w1_addr),
4702
4703 .idiv_valid (`PROBES5.fgu_idiv_valid[7]),
4704
4705 .fdiv_valid (`PROBES5.fgu_fdiv_valid[7]),
4706
4707 .lsu_valid (`PROBES5.lsu_valid[7]),
4708 .frf_w2_valid (`SPC5.fgu.frf.w2_valid),
4709 .frf_w2_tid (`SPC5.fgu.frf.w2_tid),
4710 .frf_w2_addr (`SPC5.fgu.frf.w2_addr),
4711
4712 .asi_valid (`PROBES5.asi_valid_fx5[7]),
4713 .asi_in_progress (`PROBES5.asi_in_progress_fx4[7]),
4714
4715 .tlu_valid (`PROBES5.tlu_valid[7])
4716`endif
4717 );
4718
4719//----------------------------------------------------------
4720
4721
4722//----------------------------------------------------------
4723endmodule
4724
4725`endif
4726
4727`ifdef CORE_6
4728
4729module nas_core6 (
4730
4731 cid
4732);
4733
4734input [2:0] cid;
4735
4736integer i;
4737
4738//----------------------------------------------------------
4739
4740//----------------------------------------------------------
4741
4742//----------------------------------------------------------
4743//
4744// THREAD 0
4745//
4746
4747 nas_pipe6 t0 (
4748 .mycid (cid),
4749 .mytid (3'h0),
4750
4751// If GATESIM, instantiate "dummy" module with floating ports since unused.
4752`ifdef GATESIM
4753 .opcode () // this and all other ports are unconnected
4754`else
4755 .opcode ({`PROBES6.op_0_w}),
4756 .PC_reg ({`PROBES6.pc_0_w}),
4757 .Y_reg (`SPC6.exu0.rml.arch_yreg_tid0_ff),
4758 .CCR_reg (`SPC6.exu0.ect.arch_ccr_tid0_lth),
4759 .FPRS_reg (`SPC6.fgu.fac.fprs_tid0),
4760 .FSR_reg (`SPC6.fgu.fad.fsr0_fx1[27:0]),
4761 .ASI_reg (`SPC6.lsu.dcs.asi_state0),
4762 .GSR_reg ({`SPC6.fgu.fgd.gsr0_mask_fx4[31:0], `SPC6.fgu.fpc.gsr0_11bits_fx4[10:0]}),
4763 .TICK_CMPR_reg (`PROBES6.tick_cmpr_0),
4764 .STICK_CMPR_reg (`PROBES6.stick_cmpr_0),
4765 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_0),
4766 .PSTATE_reg (`SPC6.tlu.tsd0.arch_pstate0),
4767 .TL_reg (`SPC6.tlu.trl0.tl0),
4768 .PIL_reg (`SPC6.tlu.trl0.pil0),
4769 .TBA_reg (`SPC6.tlu.tsd0.tba0[47:15]),
4770 .VER_reg (`SPC6.tlu.asi.hver_value), // static
4771 .CWP_reg (`SPC6.exu0.rml.cwp_thr0),
4772 .CANSAVE_reg (`SPC6.exu0.rml.cansave_thr0),
4773 .CANRESTORE_reg (`SPC6.exu0.rml.canrestore_thr0),
4774 .OTHERWIN_reg (`SPC6.exu0.rml.otherwin_thr0),
4775 .WSTATE_reg (`SPC6.exu0.rml.wstate_thr0),
4776 .CLEANWIN_reg (`SPC6.exu0.rml.cleanwin_thr0),
4777 .rd_SOFTINT_reg (`SPC6.tlu.trl0.rd_softint0),
4778 .SOFTINT_reg (`SPC6.tlu.trl0.softint0),
4779 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec0),
4780 .GL_reg (`SPC6.tlu.tlu_gl0),
4781 .HPSTATE_reg (`SPC6.tlu.tsd0.arch_hpstate0),
4782 .HTBA_reg (`SPC6.tlu.tsd0.htba0[47:14]),
4783 .HINTP_reg (`SPC6.tlu.trl0.hintp0),
4784
4785 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_0[12:0]}),
4786 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_0[12:0]}),
4787 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_0[12:0]}),
4788 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_0[12:0]}),
4789 .LSU_CONTROL_reg ({29'd0,
4790 `SPC6.lsu.dcs.wpt_mode_0[1:0],
4791 `SPC6.lsu.dcs.wpt_mask_0[7:0],
4792 `SPC6.lsu.dcs.wpt_enable_0[1:0],
4793 18'd0,
4794 `SPC6.lsu.dcs.spec_enable[0],
4795 `SPC6.lsu.dcs.dmmu_enable[0],
4796 `SPC6.lsu.dcs.immu_enable[0],
4797 `SPC6.lsu.dcs.dc_enable[0],
4798 `SPC6.lsu.dcs.ic_enable[0]}),
4799 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.immu_tag_access_0[47:0]}),
4800 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.dmmu_tag_access_0[47:0]}),
4801 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint0[47:3],3'b00}),
4802 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_0[47:0]),
4803
4804 .Trap_Entry_1 (`PROBES6.trap_entry_1_t0),
4805 .Trap_Entry_2 (`PROBES6.trap_entry_2_t0),
4806 .Trap_Entry_3 (`PROBES6.trap_entry_3_t0),
4807 .Trap_Entry_4 (`PROBES6.trap_entry_4_t0),
4808 .Trap_Entry_5 (`PROBES6.trap_entry_5_t0),
4809 .Trap_Entry_6 (`PROBES6.trap_entry_6_t0),
4810
4811 .exu_valid (`PROBES6.ex_valid[0]),
4812
4813 .imul_valid (`PROBES6.imul_valid[0]),
4814
4815 .fp_valid (`PROBES6.fg_valid[0]),
4816 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
4817 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
4818 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
4819
4820 .idiv_valid (`PROBES6.fgu_idiv_valid[0]),
4821
4822 .fdiv_valid (`PROBES6.fgu_fdiv_valid[0]),
4823
4824 .lsu_valid (`PROBES6.lsu_valid[0]),
4825 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
4826 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
4827 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
4828
4829 .asi_valid (`PROBES6.asi_valid_fx5[0]),
4830 .asi_in_progress (`PROBES6.asi_in_progress_fx4[0]),
4831
4832 .tlu_valid (`PROBES6.tlu_valid[0])
4833`endif
4834 );
4835
4836
4837//----------------------------------------------------------
4838//
4839// THREAD 1
4840//
4841
4842 nas_pipe6 t1 (
4843 .mycid (cid),
4844 .mytid (3'h1),
4845
4846// If GATESIM, instantiate "dummy" module with floating ports since unused.
4847`ifdef GATESIM
4848 .opcode () // this and all other ports are unconnected
4849`else
4850 .opcode ({`PROBES6.op_1_w}),
4851 .PC_reg ({`PROBES6.pc_1_w}),
4852 .Y_reg (`SPC6.exu0.rml.arch_yreg_tid1_ff),
4853 .CCR_reg (`SPC6.exu0.ect.arch_ccr_tid1_lth),
4854 .FPRS_reg (`SPC6.fgu.fac.fprs_tid1),
4855 .FSR_reg (`SPC6.fgu.fad.fsr1_fx1[27:0]),
4856 .ASI_reg (`SPC6.lsu.dcs.asi_state1),
4857 .GSR_reg ({`SPC6.fgu.fgd.gsr1_mask_fx4[31:0], `SPC6.fgu.fpc.gsr1_11bits_fx4[10:0]}),
4858 .TICK_CMPR_reg (`PROBES6.tick_cmpr_1),
4859 .STICK_CMPR_reg (`PROBES6.stick_cmpr_1),
4860 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_1),
4861 .PSTATE_reg (`SPC6.tlu.tsd0.arch_pstate1),
4862 .TL_reg (`SPC6.tlu.trl0.tl1),
4863 .PIL_reg (`SPC6.tlu.trl0.pil1),
4864 .TBA_reg (`SPC6.tlu.tsd0.tba1[47:15]),
4865 .VER_reg (`SPC6.tlu.asi.hver_value), // static
4866 .CWP_reg (`SPC6.exu0.rml.cwp_thr1),
4867 .CANSAVE_reg (`SPC6.exu0.rml.cansave_thr1),
4868 .CANRESTORE_reg (`SPC6.exu0.rml.canrestore_thr1),
4869 .OTHERWIN_reg (`SPC6.exu0.rml.otherwin_thr1),
4870 .WSTATE_reg (`SPC6.exu0.rml.wstate_thr1),
4871 .CLEANWIN_reg (`SPC6.exu0.rml.cleanwin_thr1),
4872 .rd_SOFTINT_reg (`SPC6.tlu.trl0.rd_softint1),
4873 .SOFTINT_reg (`SPC6.tlu.trl0.softint1),
4874 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec1),
4875 .GL_reg (`SPC6.tlu.tlu_gl1),
4876 .HPSTATE_reg (`SPC6.tlu.tsd0.arch_hpstate1),
4877 .HTBA_reg (`SPC6.tlu.tsd0.htba1[47:14]),
4878 .HINTP_reg (`SPC6.tlu.trl0.hintp1),
4879
4880 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_1[12:0]}),
4881 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_1[12:0]}),
4882 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_1[12:0]}),
4883 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_1[12:0]}),
4884 .LSU_CONTROL_reg ({29'd0,
4885 `SPC6.lsu.dcs.wpt_mode_1[1:0],
4886 `SPC6.lsu.dcs.wpt_mask_1[7:0],
4887 `SPC6.lsu.dcs.wpt_enable_1[1:0],
4888 18'd0,
4889 `SPC6.lsu.dcs.spec_enable[1],
4890 `SPC6.lsu.dcs.dmmu_enable[1],
4891 `SPC6.lsu.dcs.immu_enable[1],
4892 `SPC6.lsu.dcs.dc_enable[1],
4893 `SPC6.lsu.dcs.ic_enable[1]}),
4894 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.immu_tag_access_1[47:0]}),
4895 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.dmmu_tag_access_1[47:0]}),
4896 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint1[47:3],3'b00}),
4897 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_1[47:0]),
4898
4899 .Trap_Entry_1 (`PROBES6.trap_entry_1_t1),
4900 .Trap_Entry_2 (`PROBES6.trap_entry_2_t1),
4901 .Trap_Entry_3 (`PROBES6.trap_entry_3_t1),
4902 .Trap_Entry_4 (`PROBES6.trap_entry_4_t1),
4903 .Trap_Entry_5 (`PROBES6.trap_entry_5_t1),
4904 .Trap_Entry_6 (`PROBES6.trap_entry_6_t1),
4905
4906 .exu_valid (`PROBES6.ex_valid[1]),
4907
4908 .imul_valid (`PROBES6.imul_valid[1]),
4909
4910 .fp_valid (`PROBES6.fg_valid[1]),
4911 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
4912 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
4913 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
4914
4915 .idiv_valid (`PROBES6.fgu_idiv_valid[1]),
4916
4917 .fdiv_valid (`PROBES6.fgu_fdiv_valid[1]),
4918
4919 .lsu_valid (`PROBES6.lsu_valid[1]),
4920 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
4921 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
4922 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
4923
4924 .asi_valid (`PROBES6.asi_valid_fx5[1]),
4925 .asi_in_progress (`PROBES6.asi_in_progress_fx4[1]),
4926
4927 .tlu_valid (`PROBES6.tlu_valid[1])
4928`endif
4929 );
4930
4931
4932//----------------------------------------------------------
4933//
4934// THREAD 2
4935//
4936
4937 nas_pipe6 t2 (
4938 .mycid (cid),
4939 .mytid (3'h2),
4940
4941// If GATESIM, instantiate "dummy" module with floating ports since unused.
4942`ifdef GATESIM
4943 .opcode () // this and all other ports are unconnected
4944`else
4945 .opcode ({`PROBES6.op_2_w}),
4946 .PC_reg ({`PROBES6.pc_2_w}),
4947 .Y_reg (`SPC6.exu0.rml.arch_yreg_tid2_ff),
4948 .CCR_reg (`SPC6.exu0.ect.arch_ccr_tid2_lth),
4949 .FPRS_reg (`SPC6.fgu.fac.fprs_tid2),
4950 .FSR_reg (`SPC6.fgu.fad.fsr2_fx1[27:0]),
4951 .ASI_reg (`SPC6.lsu.dcs.asi_state2),
4952 .GSR_reg ({`SPC6.fgu.fgd.gsr2_mask_fx4[31:0], `SPC6.fgu.fpc.gsr2_11bits_fx4[10:0]}),
4953 .TICK_CMPR_reg (`PROBES6.tick_cmpr_2),
4954 .STICK_CMPR_reg (`PROBES6.stick_cmpr_2),
4955 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_2),
4956 .PSTATE_reg (`SPC6.tlu.tsd0.arch_pstate2),
4957 .TL_reg (`SPC6.tlu.trl0.tl2),
4958 .PIL_reg (`SPC6.tlu.trl0.pil2),
4959 .TBA_reg (`SPC6.tlu.tsd0.tba2[47:15]),
4960 .VER_reg (`SPC6.tlu.asi.hver_value), // static
4961 .CWP_reg (`SPC6.exu0.rml.cwp_thr2),
4962 .CANSAVE_reg (`SPC6.exu0.rml.cansave_thr2),
4963 .CANRESTORE_reg (`SPC6.exu0.rml.canrestore_thr2),
4964 .OTHERWIN_reg (`SPC6.exu0.rml.otherwin_thr2),
4965 .WSTATE_reg (`SPC6.exu0.rml.wstate_thr2),
4966 .CLEANWIN_reg (`SPC6.exu0.rml.cleanwin_thr2),
4967 .rd_SOFTINT_reg (`SPC6.tlu.trl0.rd_softint2),
4968 .SOFTINT_reg (`SPC6.tlu.trl0.softint2),
4969 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec2),
4970 .GL_reg (`SPC6.tlu.tlu_gl2),
4971 .HPSTATE_reg (`SPC6.tlu.tsd0.arch_hpstate2),
4972 .HTBA_reg (`SPC6.tlu.tsd0.htba2[47:14]),
4973 .HINTP_reg (`SPC6.tlu.trl0.hintp2),
4974
4975 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_2[12:0]}),
4976 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_2[12:0]}),
4977 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_2[12:0]}),
4978 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_2[12:0]}),
4979 .LSU_CONTROL_reg ({29'd0,
4980 `SPC6.lsu.dcs.wpt_mode_2[1:0],
4981 `SPC6.lsu.dcs.wpt_mask_2[7:0],
4982 `SPC6.lsu.dcs.wpt_enable_2[1:0],
4983 18'd0,
4984 `SPC6.lsu.dcs.spec_enable[2],
4985 `SPC6.lsu.dcs.dmmu_enable[2],
4986 `SPC6.lsu.dcs.immu_enable[2],
4987 `SPC6.lsu.dcs.dc_enable[2],
4988 `SPC6.lsu.dcs.ic_enable[2]}),
4989 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.immu_tag_access_2[47:0]}),
4990 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.dmmu_tag_access_2[47:0]}),
4991 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint2[47:3],3'b00}),
4992 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_2[47:0]),
4993
4994 .Trap_Entry_1 (`PROBES6.trap_entry_1_t2),
4995 .Trap_Entry_2 (`PROBES6.trap_entry_2_t2),
4996 .Trap_Entry_3 (`PROBES6.trap_entry_3_t2),
4997 .Trap_Entry_4 (`PROBES6.trap_entry_4_t2),
4998 .Trap_Entry_5 (`PROBES6.trap_entry_5_t2),
4999 .Trap_Entry_6 (`PROBES6.trap_entry_6_t2),
5000
5001 .exu_valid (`PROBES6.ex_valid[2]),
5002
5003 .imul_valid (`PROBES6.imul_valid[2]),
5004
5005 .fp_valid (`PROBES6.fg_valid[2]),
5006 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5007 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5008 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5009
5010 .idiv_valid (`PROBES6.fgu_idiv_valid[2]),
5011
5012 .fdiv_valid (`PROBES6.fgu_fdiv_valid[2]),
5013
5014 .lsu_valid (`PROBES6.lsu_valid[2]),
5015 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5016 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5017 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5018
5019 .asi_valid (`PROBES6.asi_valid_fx5[2]),
5020 .asi_in_progress (`PROBES6.asi_in_progress_fx4[2]),
5021
5022 .tlu_valid (`PROBES6.tlu_valid[2])
5023`endif
5024 );
5025
5026
5027//----------------------------------------------------------
5028//
5029// THREAD 3
5030//
5031
5032 nas_pipe6 t3 (
5033 .mycid (cid),
5034 .mytid (3'h3),
5035
5036// If GATESIM, instantiate "dummy" module with floating ports since unused.
5037`ifdef GATESIM
5038 .opcode () // this and all other ports are unconnected
5039`else
5040 .opcode ({`PROBES6.op_3_w}),
5041 .PC_reg ({`PROBES6.pc_3_w}),
5042 .Y_reg (`SPC6.exu0.rml.arch_yreg_tid3_ff),
5043 .CCR_reg (`SPC6.exu0.ect.arch_ccr_tid3_lth),
5044 .FPRS_reg (`SPC6.fgu.fac.fprs_tid3),
5045 .FSR_reg (`SPC6.fgu.fad.fsr3_fx1[27:0]),
5046 .ASI_reg (`SPC6.lsu.dcs.asi_state3),
5047 .GSR_reg ({`SPC6.fgu.fgd.gsr3_mask_fx4[31:0], `SPC6.fgu.fpc.gsr3_11bits_fx4[10:0]}),
5048 .TICK_CMPR_reg (`PROBES6.tick_cmpr_3),
5049 .STICK_CMPR_reg (`PROBES6.stick_cmpr_3),
5050 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_3),
5051 .PSTATE_reg (`SPC6.tlu.tsd0.arch_pstate3),
5052 .TL_reg (`SPC6.tlu.trl0.tl3),
5053 .PIL_reg (`SPC6.tlu.trl0.pil3),
5054 .TBA_reg (`SPC6.tlu.tsd0.tba3[47:15]),
5055 .VER_reg (`SPC6.tlu.asi.hver_value), // static
5056 .CWP_reg (`SPC6.exu0.rml.cwp_thr3),
5057 .CANSAVE_reg (`SPC6.exu0.rml.cansave_thr3),
5058 .CANRESTORE_reg (`SPC6.exu0.rml.canrestore_thr3),
5059 .OTHERWIN_reg (`SPC6.exu0.rml.otherwin_thr3),
5060 .WSTATE_reg (`SPC6.exu0.rml.wstate_thr3),
5061 .CLEANWIN_reg (`SPC6.exu0.rml.cleanwin_thr3),
5062 .rd_SOFTINT_reg (`SPC6.tlu.trl0.rd_softint3),
5063 .SOFTINT_reg (`SPC6.tlu.trl0.softint3),
5064 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec3),
5065 .GL_reg (`SPC6.tlu.tlu_gl3),
5066 .HPSTATE_reg (`SPC6.tlu.tsd0.arch_hpstate3),
5067 .HTBA_reg (`SPC6.tlu.tsd0.htba3[47:14]),
5068 .HINTP_reg (`SPC6.tlu.trl0.hintp3),
5069
5070 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_3[12:0]}),
5071 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_3[12:0]}),
5072 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_3[12:0]}),
5073 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_3[12:0]}),
5074 .LSU_CONTROL_reg ({29'd0,
5075 `SPC6.lsu.dcs.wpt_mode_3[1:0],
5076 `SPC6.lsu.dcs.wpt_mask_3[7:0],
5077 `SPC6.lsu.dcs.wpt_enable_3[1:0],
5078 18'd0,
5079 `SPC6.lsu.dcs.spec_enable[3],
5080 `SPC6.lsu.dcs.dmmu_enable[3],
5081 `SPC6.lsu.dcs.immu_enable[3],
5082 `SPC6.lsu.dcs.dc_enable[3],
5083 `SPC6.lsu.dcs.ic_enable[3]}),
5084 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.immu_tag_access_3[47:0]}),
5085 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd0.dmmu_tag_access_3[47:0]}),
5086 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint3[47:3],3'b00}),
5087 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_3[47:0]),
5088
5089 .Trap_Entry_1 (`PROBES6.trap_entry_1_t3),
5090 .Trap_Entry_2 (`PROBES6.trap_entry_2_t3),
5091 .Trap_Entry_3 (`PROBES6.trap_entry_3_t3),
5092 .Trap_Entry_4 (`PROBES6.trap_entry_4_t3),
5093 .Trap_Entry_5 (`PROBES6.trap_entry_5_t3),
5094 .Trap_Entry_6 (`PROBES6.trap_entry_6_t3),
5095
5096 .exu_valid (`PROBES6.ex_valid[3]),
5097
5098 .imul_valid (`PROBES6.imul_valid[3]),
5099
5100 .fp_valid (`PROBES6.fg_valid[3]),
5101 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5102 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5103 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5104
5105 .idiv_valid (`PROBES6.fgu_idiv_valid[3]),
5106
5107 .fdiv_valid (`PROBES6.fgu_fdiv_valid[3]),
5108
5109 .lsu_valid (`PROBES6.lsu_valid[3]),
5110 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5111 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5112 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5113
5114 .asi_valid (`PROBES6.asi_valid_fx5[3]),
5115 .asi_in_progress (`PROBES6.asi_in_progress_fx4[3]),
5116
5117 .tlu_valid (`PROBES6.tlu_valid[3])
5118`endif
5119 );
5120
5121
5122//----------------------------------------------------------
5123//
5124// THREAD 4
5125//
5126
5127 nas_pipe6 t4 (
5128 .mycid (cid),
5129 .mytid (3'h4),
5130
5131// If GATESIM, instantiate "dummy" module with floating ports since unused.
5132`ifdef GATESIM
5133 .opcode () // this and all other ports are unconnected
5134`else
5135 .opcode ({`PROBES6.op_4_w}),
5136 .PC_reg ({`PROBES6.pc_4_w}),
5137 .Y_reg (`SPC6.exu1.rml.arch_yreg_tid0_ff),
5138 .CCR_reg (`SPC6.exu1.ect.arch_ccr_tid0_lth),
5139 .FPRS_reg (`SPC6.fgu.fac.fprs_tid4),
5140 .FSR_reg (`SPC6.fgu.fad.fsr4_fx1[27:0]),
5141 .ASI_reg (`SPC6.lsu.dcs.asi_state4),
5142 .GSR_reg ({`SPC6.fgu.fgd.gsr4_mask_fx4[31:0], `SPC6.fgu.fpc.gsr4_11bits_fx4[10:0]}),
5143 .TICK_CMPR_reg (`PROBES6.tick_cmpr_4),
5144 .STICK_CMPR_reg (`PROBES6.stick_cmpr_4),
5145 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_4),
5146 .PSTATE_reg (`SPC6.tlu.tsd1.arch_pstate0),
5147 .TL_reg (`SPC6.tlu.trl1.tl0),
5148 .PIL_reg (`SPC6.tlu.trl1.pil0),
5149 .TBA_reg (`SPC6.tlu.tsd1.tba0[47:15]),
5150 .VER_reg (`SPC6.tlu.asi.hver_value), // static
5151 .CWP_reg (`SPC6.exu1.rml.cwp_thr0),
5152 .CANSAVE_reg (`SPC6.exu1.rml.cansave_thr0),
5153 .CANRESTORE_reg (`SPC6.exu1.rml.canrestore_thr0),
5154 .OTHERWIN_reg (`SPC6.exu1.rml.otherwin_thr0),
5155 .WSTATE_reg (`SPC6.exu1.rml.wstate_thr0),
5156 .CLEANWIN_reg (`SPC6.exu1.rml.cleanwin_thr0),
5157 .rd_SOFTINT_reg (`SPC6.tlu.trl1.rd_softint0),
5158 .SOFTINT_reg (`SPC6.tlu.trl1.softint0),
5159 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec4),
5160 .GL_reg (`SPC6.tlu.tlu_gl4),
5161 .HPSTATE_reg (`SPC6.tlu.tsd1.arch_hpstate0),
5162 .HTBA_reg (`SPC6.tlu.tsd1.htba0[47:14]),
5163 .HINTP_reg (`SPC6.tlu.trl1.hintp0),
5164
5165 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_4[12:0]}),
5166 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_4[12:0]}),
5167 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_4[12:0]}),
5168 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_4[12:0]}),
5169 .LSU_CONTROL_reg ({29'd0,
5170 `SPC6.lsu.dcs.wpt_mode_4[1:0],
5171 `SPC6.lsu.dcs.wpt_mask_4[7:0],
5172 `SPC6.lsu.dcs.wpt_enable_4[1:0],
5173 18'd0,
5174 `SPC6.lsu.dcs.spec_enable[4],
5175 `SPC6.lsu.dcs.dmmu_enable[4],
5176 `SPC6.lsu.dcs.immu_enable[4],
5177 `SPC6.lsu.dcs.dc_enable[4],
5178 `SPC6.lsu.dcs.ic_enable[4]}),
5179 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.immu_tag_access_0[47:0]}),
5180 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.dmmu_tag_access_0[47:0]}),
5181 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint4[47:3],3'b00}),
5182 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_4[47:0]),
5183
5184 .Trap_Entry_1 (`PROBES6.trap_entry_1_t4),
5185 .Trap_Entry_2 (`PROBES6.trap_entry_2_t4),
5186 .Trap_Entry_3 (`PROBES6.trap_entry_3_t4),
5187 .Trap_Entry_4 (`PROBES6.trap_entry_4_t4),
5188 .Trap_Entry_5 (`PROBES6.trap_entry_5_t4),
5189 .Trap_Entry_6 (`PROBES6.trap_entry_6_t4),
5190
5191 .exu_valid (`PROBES6.ex_valid[4]),
5192
5193 .imul_valid (`PROBES6.imul_valid[4]),
5194
5195 .fp_valid (`PROBES6.fg_valid[4]),
5196 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5197 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5198 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5199
5200 .idiv_valid (`PROBES6.fgu_idiv_valid[4]),
5201
5202 .fdiv_valid (`PROBES6.fgu_fdiv_valid[4]),
5203
5204 .lsu_valid (`PROBES6.lsu_valid[4]),
5205 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5206 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5207 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5208
5209 .asi_valid (`PROBES6.asi_valid_fx5[4]),
5210 .asi_in_progress (`PROBES6.asi_in_progress_fx4[4]),
5211
5212 .tlu_valid (`PROBES6.tlu_valid[4])
5213`endif
5214 );
5215
5216
5217//----------------------------------------------------------
5218//
5219// THREAD 5
5220//
5221
5222 nas_pipe6 t5 (
5223 .mycid (cid),
5224 .mytid (3'h5),
5225
5226// If GATESIM, instantiate "dummy" module with floating ports since unused.
5227`ifdef GATESIM
5228 .opcode () // this and all other ports are unconnected
5229`else
5230 .opcode ({`PROBES6.op_5_w}),
5231 .PC_reg ({`PROBES6.pc_5_w}),
5232 .Y_reg (`SPC6.exu1.rml.arch_yreg_tid1_ff),
5233 .CCR_reg (`SPC6.exu1.ect.arch_ccr_tid1_lth),
5234 .FPRS_reg (`SPC6.fgu.fac.fprs_tid5),
5235 .FSR_reg (`SPC6.fgu.fad.fsr5_fx1[27:0]),
5236 .ASI_reg (`SPC6.lsu.dcs.asi_state5),
5237 .GSR_reg ({`SPC6.fgu.fgd.gsr5_mask_fx4[31:0], `SPC6.fgu.fpc.gsr5_11bits_fx4[10:0]}),
5238 .TICK_CMPR_reg (`PROBES6.tick_cmpr_5),
5239 .STICK_CMPR_reg (`PROBES6.stick_cmpr_5),
5240 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_5),
5241 .PSTATE_reg (`SPC6.tlu.tsd1.arch_pstate1),
5242 .TL_reg (`SPC6.tlu.trl1.tl1),
5243 .PIL_reg (`SPC6.tlu.trl1.pil1),
5244 .TBA_reg (`SPC6.tlu.tsd1.tba1[47:15]),
5245 .VER_reg (`SPC6.tlu.asi.hver_value), // static
5246 .CWP_reg (`SPC6.exu1.rml.cwp_thr1),
5247 .CANSAVE_reg (`SPC6.exu1.rml.cansave_thr1),
5248 .CANRESTORE_reg (`SPC6.exu1.rml.canrestore_thr1),
5249 .OTHERWIN_reg (`SPC6.exu1.rml.otherwin_thr1),
5250 .WSTATE_reg (`SPC6.exu1.rml.wstate_thr1),
5251 .CLEANWIN_reg (`SPC6.exu1.rml.cleanwin_thr1),
5252 .rd_SOFTINT_reg (`SPC6.tlu.trl1.rd_softint1),
5253 .SOFTINT_reg (`SPC6.tlu.trl1.softint1),
5254 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec5),
5255 .GL_reg (`SPC6.tlu.tlu_gl5),
5256 .HPSTATE_reg (`SPC6.tlu.tsd1.arch_hpstate1),
5257 .HTBA_reg (`SPC6.tlu.tsd1.htba1[47:14]),
5258 .HINTP_reg (`SPC6.tlu.trl1.hintp1),
5259
5260 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_5[12:0]}),
5261 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_5[12:0]}),
5262 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_5[12:0]}),
5263 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_5[12:0]}),
5264 .LSU_CONTROL_reg ({29'd0,
5265 `SPC6.lsu.dcs.wpt_mode_5[1:0],
5266 `SPC6.lsu.dcs.wpt_mask_5[7:0],
5267 `SPC6.lsu.dcs.wpt_enable_5[1:0],
5268 18'd0,
5269 `SPC6.lsu.dcs.spec_enable[5],
5270 `SPC6.lsu.dcs.dmmu_enable[5],
5271 `SPC6.lsu.dcs.immu_enable[5],
5272 `SPC6.lsu.dcs.dc_enable[5],
5273 `SPC6.lsu.dcs.ic_enable[5]}),
5274 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.immu_tag_access_1[47:0]}),
5275 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.dmmu_tag_access_1[47:0]}),
5276 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint5[47:3],3'b00}),
5277 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_5[47:0]),
5278
5279 .Trap_Entry_1 (`PROBES6.trap_entry_1_t5),
5280 .Trap_Entry_2 (`PROBES6.trap_entry_2_t5),
5281 .Trap_Entry_3 (`PROBES6.trap_entry_3_t5),
5282 .Trap_Entry_4 (`PROBES6.trap_entry_4_t5),
5283 .Trap_Entry_5 (`PROBES6.trap_entry_5_t5),
5284 .Trap_Entry_6 (`PROBES6.trap_entry_6_t5),
5285
5286 .exu_valid (`PROBES6.ex_valid[5]),
5287
5288 .imul_valid (`PROBES6.imul_valid[5]),
5289
5290 .fp_valid (`PROBES6.fg_valid[5]),
5291 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5292 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5293 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5294
5295 .idiv_valid (`PROBES6.fgu_idiv_valid[5]),
5296
5297 .fdiv_valid (`PROBES6.fgu_fdiv_valid[5]),
5298
5299 .lsu_valid (`PROBES6.lsu_valid[5]),
5300 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5301 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5302 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5303
5304 .asi_valid (`PROBES6.asi_valid_fx5[5]),
5305 .asi_in_progress (`PROBES6.asi_in_progress_fx4[5]),
5306
5307 .tlu_valid (`PROBES6.tlu_valid[5])
5308`endif
5309 );
5310
5311
5312//----------------------------------------------------------
5313//
5314// THREAD 6
5315//
5316
5317 nas_pipe6 t6 (
5318 .mycid (cid),
5319 .mytid (3'h6),
5320
5321// If GATESIM, instantiate "dummy" module with floating ports since unused.
5322`ifdef GATESIM
5323 .opcode () // this and all other ports are unconnected
5324`else
5325 .opcode ({`PROBES6.op_6_w}),
5326 .PC_reg ({`PROBES6.pc_6_w}),
5327 .Y_reg (`SPC6.exu1.rml.arch_yreg_tid2_ff),
5328 .CCR_reg (`SPC6.exu1.ect.arch_ccr_tid2_lth),
5329 .FPRS_reg (`SPC6.fgu.fac.fprs_tid6),
5330 .FSR_reg (`SPC6.fgu.fad.fsr6_fx1[27:0]),
5331 .ASI_reg (`SPC6.lsu.dcs.asi_state6),
5332 .GSR_reg ({`SPC6.fgu.fgd.gsr6_mask_fx4[31:0], `SPC6.fgu.fpc.gsr6_11bits_fx4[10:0]}),
5333 .TICK_CMPR_reg (`PROBES6.tick_cmpr_6),
5334 .STICK_CMPR_reg (`PROBES6.stick_cmpr_6),
5335 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_6),
5336 .PSTATE_reg (`SPC6.tlu.tsd1.arch_pstate2),
5337 .TL_reg (`SPC6.tlu.trl1.tl2),
5338 .PIL_reg (`SPC6.tlu.trl1.pil2),
5339 .TBA_reg (`SPC6.tlu.tsd1.tba2[47:15]),
5340 .VER_reg (`SPC6.tlu.asi.hver_value), // static
5341 .CWP_reg (`SPC6.exu1.rml.cwp_thr2),
5342 .CANSAVE_reg (`SPC6.exu1.rml.cansave_thr2),
5343 .CANRESTORE_reg (`SPC6.exu1.rml.canrestore_thr2),
5344 .OTHERWIN_reg (`SPC6.exu1.rml.otherwin_thr2),
5345 .WSTATE_reg (`SPC6.exu1.rml.wstate_thr2),
5346 .CLEANWIN_reg (`SPC6.exu1.rml.cleanwin_thr2),
5347 .rd_SOFTINT_reg (`SPC6.tlu.trl1.rd_softint2),
5348 .SOFTINT_reg (`SPC6.tlu.trl1.softint2),
5349 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec6),
5350 .GL_reg (`SPC6.tlu.tlu_gl6),
5351 .HPSTATE_reg (`SPC6.tlu.tsd1.arch_hpstate2),
5352 .HTBA_reg (`SPC6.tlu.tsd1.htba2[47:14]),
5353 .HINTP_reg (`SPC6.tlu.trl1.hintp2),
5354
5355 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_6[12:0]}),
5356 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_6[12:0]}),
5357 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_6[12:0]}),
5358 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_6[12:0]}),
5359 .LSU_CONTROL_reg ({29'd0,
5360 `SPC6.lsu.dcs.wpt_mode_6[1:0],
5361 `SPC6.lsu.dcs.wpt_mask_6[7:0],
5362 `SPC6.lsu.dcs.wpt_enable_6[1:0],
5363 18'd0,
5364 `SPC6.lsu.dcs.spec_enable[6],
5365 `SPC6.lsu.dcs.dmmu_enable[6],
5366 `SPC6.lsu.dcs.immu_enable[6],
5367 `SPC6.lsu.dcs.dc_enable[6],
5368 `SPC6.lsu.dcs.ic_enable[6]}),
5369 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.immu_tag_access_2[47:0]}),
5370 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.dmmu_tag_access_2[47:0]}),
5371 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint6[47:3],3'b00}),
5372 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_6[47:0]),
5373
5374 .Trap_Entry_1 (`PROBES6.trap_entry_1_t6),
5375 .Trap_Entry_2 (`PROBES6.trap_entry_2_t6),
5376 .Trap_Entry_3 (`PROBES6.trap_entry_3_t6),
5377 .Trap_Entry_4 (`PROBES6.trap_entry_4_t6),
5378 .Trap_Entry_5 (`PROBES6.trap_entry_5_t6),
5379 .Trap_Entry_6 (`PROBES6.trap_entry_6_t6),
5380
5381 .exu_valid (`PROBES6.ex_valid[6]),
5382
5383 .imul_valid (`PROBES6.imul_valid[6]),
5384
5385 .fp_valid (`PROBES6.fg_valid[6]),
5386 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5387 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5388 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5389
5390 .idiv_valid (`PROBES6.fgu_idiv_valid[6]),
5391
5392 .fdiv_valid (`PROBES6.fgu_fdiv_valid[6]),
5393
5394 .lsu_valid (`PROBES6.lsu_valid[6]),
5395 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5396 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5397 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5398
5399 .asi_valid (`PROBES6.asi_valid_fx5[6]),
5400 .asi_in_progress (`PROBES6.asi_in_progress_fx4[6]),
5401
5402 .tlu_valid (`PROBES6.tlu_valid[6])
5403`endif
5404 );
5405
5406
5407//----------------------------------------------------------
5408//
5409// THREAD 7
5410//
5411
5412 nas_pipe6 t7 (
5413 .mycid (cid),
5414 .mytid (3'h7),
5415
5416// If GATESIM, instantiate "dummy" module with floating ports since unused.
5417`ifdef GATESIM
5418 .opcode () // this and all other ports are unconnected
5419`else
5420 .opcode ({`PROBES6.op_7_w}),
5421 .PC_reg ({`PROBES6.pc_7_w}),
5422 .Y_reg (`SPC6.exu1.rml.arch_yreg_tid3_ff),
5423 .CCR_reg (`SPC6.exu1.ect.arch_ccr_tid3_lth),
5424 .FPRS_reg (`SPC6.fgu.fac.fprs_tid7),
5425 .FSR_reg (`SPC6.fgu.fad.fsr7_fx1[27:0]),
5426 .ASI_reg (`SPC6.lsu.dcs.asi_state7),
5427 .GSR_reg ({`SPC6.fgu.fgd.gsr7_mask_fx4[31:0], `SPC6.fgu.fpc.gsr7_11bits_fx4[10:0]}),
5428 .TICK_CMPR_reg (`PROBES6.tick_cmpr_7),
5429 .STICK_CMPR_reg (`PROBES6.stick_cmpr_7),
5430 .HSTICK_CMPR_reg (`PROBES6.hstick_cmpr_7),
5431 .PSTATE_reg (`SPC6.tlu.tsd1.arch_pstate3),
5432 .TL_reg (`SPC6.tlu.trl1.tl3),
5433 .PIL_reg (`SPC6.tlu.trl1.pil3),
5434 .TBA_reg (`SPC6.tlu.tsd1.tba3[47:15]),
5435 .VER_reg (`SPC6.tlu.asi.hver_value), // static
5436 .CWP_reg (`SPC6.exu1.rml.cwp_thr3),
5437 .CANSAVE_reg (`SPC6.exu1.rml.cansave_thr3),
5438 .CANRESTORE_reg (`SPC6.exu1.rml.canrestore_thr3),
5439 .OTHERWIN_reg (`SPC6.exu1.rml.otherwin_thr3),
5440 .WSTATE_reg (`SPC6.exu1.rml.wstate_thr3),
5441 .CLEANWIN_reg (`SPC6.exu1.rml.cleanwin_thr3),
5442 .rd_SOFTINT_reg (`SPC6.tlu.trl1.rd_softint3),
5443 .SOFTINT_reg (`SPC6.tlu.trl1.softint3),
5444 .INTR_RECEIVE_reg (`SPC6.tlu.cth.int_rec7),
5445 .GL_reg (`SPC6.tlu.tlu_gl7),
5446 .HPSTATE_reg (`SPC6.tlu.tsd1.arch_hpstate3),
5447 .HTBA_reg (`SPC6.tlu.tsd1.htba3[47:14]),
5448 .HINTP_reg (`SPC6.tlu.trl1.hintp3),
5449
5450 .CTXT_PRIM_0_reg ({51'b0,`SPC6.lsu.dcs.p0ctxt_7[12:0]}),
5451 .CTXT_SEC_0_reg ({51'b0,`SPC6.lsu.dcs.s0ctxt_7[12:0]}),
5452 .CTXT_PRIM_1_reg ({51'b0,`SPC6.lsu.dcs.p1ctxt_7[12:0]}),
5453 .CTXT_SEC_1_reg ({51'b0,`SPC6.lsu.dcs.s1ctxt_7[12:0]}),
5454 .LSU_CONTROL_reg ({29'd0,
5455 `SPC6.lsu.dcs.wpt_mode_7[1:0],
5456 `SPC6.lsu.dcs.wpt_mask_7[7:0],
5457 `SPC6.lsu.dcs.wpt_enable_7[1:0],
5458 18'd0,
5459 `SPC6.lsu.dcs.spec_enable[7],
5460 `SPC6.lsu.dcs.dmmu_enable[7],
5461 `SPC6.lsu.dcs.immu_enable[7],
5462 `SPC6.lsu.dcs.dc_enable[7],
5463 `SPC6.lsu.dcs.ic_enable[7]}),
5464 .I_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.immu_tag_access_3[47:0]}),
5465 .D_TAG_ACC_reg ({16'b0,`SPC6.mmu.asd1.dmmu_tag_access_3[47:0]}),
5466 .WATCHPOINT_ADDR_reg ({16'b0,`SPC6.lsu.dcs.watchpoint7[47:3],3'b00}),
5467 .DSFAR_reg (`SPC6.tlu.dfd.dsfar_7[47:0]),
5468
5469 .Trap_Entry_1 (`PROBES6.trap_entry_1_t7),
5470 .Trap_Entry_2 (`PROBES6.trap_entry_2_t7),
5471 .Trap_Entry_3 (`PROBES6.trap_entry_3_t7),
5472 .Trap_Entry_4 (`PROBES6.trap_entry_4_t7),
5473 .Trap_Entry_5 (`PROBES6.trap_entry_5_t7),
5474 .Trap_Entry_6 (`PROBES6.trap_entry_6_t7),
5475
5476 .exu_valid (`PROBES6.ex_valid[7]),
5477
5478 .imul_valid (`PROBES6.imul_valid[7]),
5479
5480 .fp_valid (`PROBES6.fg_valid[7]),
5481 .frf_w1_valid (`SPC6.fgu.frf.w1_valid),
5482 .frf_w1_tid (`SPC6.fgu.frf.w1_tid),
5483 .frf_w1_addr (`SPC6.fgu.frf.w1_addr),
5484
5485 .idiv_valid (`PROBES6.fgu_idiv_valid[7]),
5486
5487 .fdiv_valid (`PROBES6.fgu_fdiv_valid[7]),
5488
5489 .lsu_valid (`PROBES6.lsu_valid[7]),
5490 .frf_w2_valid (`SPC6.fgu.frf.w2_valid),
5491 .frf_w2_tid (`SPC6.fgu.frf.w2_tid),
5492 .frf_w2_addr (`SPC6.fgu.frf.w2_addr),
5493
5494 .asi_valid (`PROBES6.asi_valid_fx5[7]),
5495 .asi_in_progress (`PROBES6.asi_in_progress_fx4[7]),
5496
5497 .tlu_valid (`PROBES6.tlu_valid[7])
5498`endif
5499 );
5500
5501//----------------------------------------------------------
5502
5503
5504//----------------------------------------------------------
5505endmodule
5506
5507`endif
5508
5509`ifdef CORE_7
5510
5511module nas_core7 (
5512
5513 cid
5514);
5515
5516input [2:0] cid;
5517
5518integer i;
5519
5520//----------------------------------------------------------
5521
5522//----------------------------------------------------------
5523
5524//----------------------------------------------------------
5525//
5526// THREAD 0
5527//
5528
5529 nas_pipe7 t0 (
5530 .mycid (cid),
5531 .mytid (3'h0),
5532
5533// If GATESIM, instantiate "dummy" module with floating ports since unused.
5534`ifdef GATESIM
5535 .opcode () // this and all other ports are unconnected
5536`else
5537 .opcode ({`PROBES7.op_0_w}),
5538 .PC_reg ({`PROBES7.pc_0_w}),
5539 .Y_reg (`SPC7.exu0.rml.arch_yreg_tid0_ff),
5540 .CCR_reg (`SPC7.exu0.ect.arch_ccr_tid0_lth),
5541 .FPRS_reg (`SPC7.fgu.fac.fprs_tid0),
5542 .FSR_reg (`SPC7.fgu.fad.fsr0_fx1[27:0]),
5543 .ASI_reg (`SPC7.lsu.dcs.asi_state0),
5544 .GSR_reg ({`SPC7.fgu.fgd.gsr0_mask_fx4[31:0], `SPC7.fgu.fpc.gsr0_11bits_fx4[10:0]}),
5545 .TICK_CMPR_reg (`PROBES7.tick_cmpr_0),
5546 .STICK_CMPR_reg (`PROBES7.stick_cmpr_0),
5547 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_0),
5548 .PSTATE_reg (`SPC7.tlu.tsd0.arch_pstate0),
5549 .TL_reg (`SPC7.tlu.trl0.tl0),
5550 .PIL_reg (`SPC7.tlu.trl0.pil0),
5551 .TBA_reg (`SPC7.tlu.tsd0.tba0[47:15]),
5552 .VER_reg (`SPC7.tlu.asi.hver_value), // static
5553 .CWP_reg (`SPC7.exu0.rml.cwp_thr0),
5554 .CANSAVE_reg (`SPC7.exu0.rml.cansave_thr0),
5555 .CANRESTORE_reg (`SPC7.exu0.rml.canrestore_thr0),
5556 .OTHERWIN_reg (`SPC7.exu0.rml.otherwin_thr0),
5557 .WSTATE_reg (`SPC7.exu0.rml.wstate_thr0),
5558 .CLEANWIN_reg (`SPC7.exu0.rml.cleanwin_thr0),
5559 .rd_SOFTINT_reg (`SPC7.tlu.trl0.rd_softint0),
5560 .SOFTINT_reg (`SPC7.tlu.trl0.softint0),
5561 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec0),
5562 .GL_reg (`SPC7.tlu.tlu_gl0),
5563 .HPSTATE_reg (`SPC7.tlu.tsd0.arch_hpstate0),
5564 .HTBA_reg (`SPC7.tlu.tsd0.htba0[47:14]),
5565 .HINTP_reg (`SPC7.tlu.trl0.hintp0),
5566
5567 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_0[12:0]}),
5568 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_0[12:0]}),
5569 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_0[12:0]}),
5570 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_0[12:0]}),
5571 .LSU_CONTROL_reg ({29'd0,
5572 `SPC7.lsu.dcs.wpt_mode_0[1:0],
5573 `SPC7.lsu.dcs.wpt_mask_0[7:0],
5574 `SPC7.lsu.dcs.wpt_enable_0[1:0],
5575 18'd0,
5576 `SPC7.lsu.dcs.spec_enable[0],
5577 `SPC7.lsu.dcs.dmmu_enable[0],
5578 `SPC7.lsu.dcs.immu_enable[0],
5579 `SPC7.lsu.dcs.dc_enable[0],
5580 `SPC7.lsu.dcs.ic_enable[0]}),
5581 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.immu_tag_access_0[47:0]}),
5582 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.dmmu_tag_access_0[47:0]}),
5583 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint0[47:3],3'b00}),
5584 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_0[47:0]),
5585
5586 .Trap_Entry_1 (`PROBES7.trap_entry_1_t0),
5587 .Trap_Entry_2 (`PROBES7.trap_entry_2_t0),
5588 .Trap_Entry_3 (`PROBES7.trap_entry_3_t0),
5589 .Trap_Entry_4 (`PROBES7.trap_entry_4_t0),
5590 .Trap_Entry_5 (`PROBES7.trap_entry_5_t0),
5591 .Trap_Entry_6 (`PROBES7.trap_entry_6_t0),
5592
5593 .exu_valid (`PROBES7.ex_valid[0]),
5594
5595 .imul_valid (`PROBES7.imul_valid[0]),
5596
5597 .fp_valid (`PROBES7.fg_valid[0]),
5598 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
5599 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
5600 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
5601
5602 .idiv_valid (`PROBES7.fgu_idiv_valid[0]),
5603
5604 .fdiv_valid (`PROBES7.fgu_fdiv_valid[0]),
5605
5606 .lsu_valid (`PROBES7.lsu_valid[0]),
5607 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
5608 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
5609 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
5610
5611 .asi_valid (`PROBES7.asi_valid_fx5[0]),
5612 .asi_in_progress (`PROBES7.asi_in_progress_fx4[0]),
5613
5614 .tlu_valid (`PROBES7.tlu_valid[0])
5615`endif
5616 );
5617
5618
5619//----------------------------------------------------------
5620//
5621// THREAD 1
5622//
5623
5624 nas_pipe7 t1 (
5625 .mycid (cid),
5626 .mytid (3'h1),
5627
5628// If GATESIM, instantiate "dummy" module with floating ports since unused.
5629`ifdef GATESIM
5630 .opcode () // this and all other ports are unconnected
5631`else
5632 .opcode ({`PROBES7.op_1_w}),
5633 .PC_reg ({`PROBES7.pc_1_w}),
5634 .Y_reg (`SPC7.exu0.rml.arch_yreg_tid1_ff),
5635 .CCR_reg (`SPC7.exu0.ect.arch_ccr_tid1_lth),
5636 .FPRS_reg (`SPC7.fgu.fac.fprs_tid1),
5637 .FSR_reg (`SPC7.fgu.fad.fsr1_fx1[27:0]),
5638 .ASI_reg (`SPC7.lsu.dcs.asi_state1),
5639 .GSR_reg ({`SPC7.fgu.fgd.gsr1_mask_fx4[31:0], `SPC7.fgu.fpc.gsr1_11bits_fx4[10:0]}),
5640 .TICK_CMPR_reg (`PROBES7.tick_cmpr_1),
5641 .STICK_CMPR_reg (`PROBES7.stick_cmpr_1),
5642 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_1),
5643 .PSTATE_reg (`SPC7.tlu.tsd0.arch_pstate1),
5644 .TL_reg (`SPC7.tlu.trl0.tl1),
5645 .PIL_reg (`SPC7.tlu.trl0.pil1),
5646 .TBA_reg (`SPC7.tlu.tsd0.tba1[47:15]),
5647 .VER_reg (`SPC7.tlu.asi.hver_value), // static
5648 .CWP_reg (`SPC7.exu0.rml.cwp_thr1),
5649 .CANSAVE_reg (`SPC7.exu0.rml.cansave_thr1),
5650 .CANRESTORE_reg (`SPC7.exu0.rml.canrestore_thr1),
5651 .OTHERWIN_reg (`SPC7.exu0.rml.otherwin_thr1),
5652 .WSTATE_reg (`SPC7.exu0.rml.wstate_thr1),
5653 .CLEANWIN_reg (`SPC7.exu0.rml.cleanwin_thr1),
5654 .rd_SOFTINT_reg (`SPC7.tlu.trl0.rd_softint1),
5655 .SOFTINT_reg (`SPC7.tlu.trl0.softint1),
5656 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec1),
5657 .GL_reg (`SPC7.tlu.tlu_gl1),
5658 .HPSTATE_reg (`SPC7.tlu.tsd0.arch_hpstate1),
5659 .HTBA_reg (`SPC7.tlu.tsd0.htba1[47:14]),
5660 .HINTP_reg (`SPC7.tlu.trl0.hintp1),
5661
5662 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_1[12:0]}),
5663 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_1[12:0]}),
5664 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_1[12:0]}),
5665 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_1[12:0]}),
5666 .LSU_CONTROL_reg ({29'd0,
5667 `SPC7.lsu.dcs.wpt_mode_1[1:0],
5668 `SPC7.lsu.dcs.wpt_mask_1[7:0],
5669 `SPC7.lsu.dcs.wpt_enable_1[1:0],
5670 18'd0,
5671 `SPC7.lsu.dcs.spec_enable[1],
5672 `SPC7.lsu.dcs.dmmu_enable[1],
5673 `SPC7.lsu.dcs.immu_enable[1],
5674 `SPC7.lsu.dcs.dc_enable[1],
5675 `SPC7.lsu.dcs.ic_enable[1]}),
5676 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.immu_tag_access_1[47:0]}),
5677 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.dmmu_tag_access_1[47:0]}),
5678 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint1[47:3],3'b00}),
5679 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_1[47:0]),
5680
5681 .Trap_Entry_1 (`PROBES7.trap_entry_1_t1),
5682 .Trap_Entry_2 (`PROBES7.trap_entry_2_t1),
5683 .Trap_Entry_3 (`PROBES7.trap_entry_3_t1),
5684 .Trap_Entry_4 (`PROBES7.trap_entry_4_t1),
5685 .Trap_Entry_5 (`PROBES7.trap_entry_5_t1),
5686 .Trap_Entry_6 (`PROBES7.trap_entry_6_t1),
5687
5688 .exu_valid (`PROBES7.ex_valid[1]),
5689
5690 .imul_valid (`PROBES7.imul_valid[1]),
5691
5692 .fp_valid (`PROBES7.fg_valid[1]),
5693 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
5694 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
5695 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
5696
5697 .idiv_valid (`PROBES7.fgu_idiv_valid[1]),
5698
5699 .fdiv_valid (`PROBES7.fgu_fdiv_valid[1]),
5700
5701 .lsu_valid (`PROBES7.lsu_valid[1]),
5702 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
5703 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
5704 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
5705
5706 .asi_valid (`PROBES7.asi_valid_fx5[1]),
5707 .asi_in_progress (`PROBES7.asi_in_progress_fx4[1]),
5708
5709 .tlu_valid (`PROBES7.tlu_valid[1])
5710`endif
5711 );
5712
5713
5714//----------------------------------------------------------
5715//
5716// THREAD 2
5717//
5718
5719 nas_pipe7 t2 (
5720 .mycid (cid),
5721 .mytid (3'h2),
5722
5723// If GATESIM, instantiate "dummy" module with floating ports since unused.
5724`ifdef GATESIM
5725 .opcode () // this and all other ports are unconnected
5726`else
5727 .opcode ({`PROBES7.op_2_w}),
5728 .PC_reg ({`PROBES7.pc_2_w}),
5729 .Y_reg (`SPC7.exu0.rml.arch_yreg_tid2_ff),
5730 .CCR_reg (`SPC7.exu0.ect.arch_ccr_tid2_lth),
5731 .FPRS_reg (`SPC7.fgu.fac.fprs_tid2),
5732 .FSR_reg (`SPC7.fgu.fad.fsr2_fx1[27:0]),
5733 .ASI_reg (`SPC7.lsu.dcs.asi_state2),
5734 .GSR_reg ({`SPC7.fgu.fgd.gsr2_mask_fx4[31:0], `SPC7.fgu.fpc.gsr2_11bits_fx4[10:0]}),
5735 .TICK_CMPR_reg (`PROBES7.tick_cmpr_2),
5736 .STICK_CMPR_reg (`PROBES7.stick_cmpr_2),
5737 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_2),
5738 .PSTATE_reg (`SPC7.tlu.tsd0.arch_pstate2),
5739 .TL_reg (`SPC7.tlu.trl0.tl2),
5740 .PIL_reg (`SPC7.tlu.trl0.pil2),
5741 .TBA_reg (`SPC7.tlu.tsd0.tba2[47:15]),
5742 .VER_reg (`SPC7.tlu.asi.hver_value), // static
5743 .CWP_reg (`SPC7.exu0.rml.cwp_thr2),
5744 .CANSAVE_reg (`SPC7.exu0.rml.cansave_thr2),
5745 .CANRESTORE_reg (`SPC7.exu0.rml.canrestore_thr2),
5746 .OTHERWIN_reg (`SPC7.exu0.rml.otherwin_thr2),
5747 .WSTATE_reg (`SPC7.exu0.rml.wstate_thr2),
5748 .CLEANWIN_reg (`SPC7.exu0.rml.cleanwin_thr2),
5749 .rd_SOFTINT_reg (`SPC7.tlu.trl0.rd_softint2),
5750 .SOFTINT_reg (`SPC7.tlu.trl0.softint2),
5751 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec2),
5752 .GL_reg (`SPC7.tlu.tlu_gl2),
5753 .HPSTATE_reg (`SPC7.tlu.tsd0.arch_hpstate2),
5754 .HTBA_reg (`SPC7.tlu.tsd0.htba2[47:14]),
5755 .HINTP_reg (`SPC7.tlu.trl0.hintp2),
5756
5757 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_2[12:0]}),
5758 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_2[12:0]}),
5759 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_2[12:0]}),
5760 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_2[12:0]}),
5761 .LSU_CONTROL_reg ({29'd0,
5762 `SPC7.lsu.dcs.wpt_mode_2[1:0],
5763 `SPC7.lsu.dcs.wpt_mask_2[7:0],
5764 `SPC7.lsu.dcs.wpt_enable_2[1:0],
5765 18'd0,
5766 `SPC7.lsu.dcs.spec_enable[2],
5767 `SPC7.lsu.dcs.dmmu_enable[2],
5768 `SPC7.lsu.dcs.immu_enable[2],
5769 `SPC7.lsu.dcs.dc_enable[2],
5770 `SPC7.lsu.dcs.ic_enable[2]}),
5771 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.immu_tag_access_2[47:0]}),
5772 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.dmmu_tag_access_2[47:0]}),
5773 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint2[47:3],3'b00}),
5774 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_2[47:0]),
5775
5776 .Trap_Entry_1 (`PROBES7.trap_entry_1_t2),
5777 .Trap_Entry_2 (`PROBES7.trap_entry_2_t2),
5778 .Trap_Entry_3 (`PROBES7.trap_entry_3_t2),
5779 .Trap_Entry_4 (`PROBES7.trap_entry_4_t2),
5780 .Trap_Entry_5 (`PROBES7.trap_entry_5_t2),
5781 .Trap_Entry_6 (`PROBES7.trap_entry_6_t2),
5782
5783 .exu_valid (`PROBES7.ex_valid[2]),
5784
5785 .imul_valid (`PROBES7.imul_valid[2]),
5786
5787 .fp_valid (`PROBES7.fg_valid[2]),
5788 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
5789 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
5790 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
5791
5792 .idiv_valid (`PROBES7.fgu_idiv_valid[2]),
5793
5794 .fdiv_valid (`PROBES7.fgu_fdiv_valid[2]),
5795
5796 .lsu_valid (`PROBES7.lsu_valid[2]),
5797 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
5798 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
5799 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
5800
5801 .asi_valid (`PROBES7.asi_valid_fx5[2]),
5802 .asi_in_progress (`PROBES7.asi_in_progress_fx4[2]),
5803
5804 .tlu_valid (`PROBES7.tlu_valid[2])
5805`endif
5806 );
5807
5808
5809//----------------------------------------------------------
5810//
5811// THREAD 3
5812//
5813
5814 nas_pipe7 t3 (
5815 .mycid (cid),
5816 .mytid (3'h3),
5817
5818// If GATESIM, instantiate "dummy" module with floating ports since unused.
5819`ifdef GATESIM
5820 .opcode () // this and all other ports are unconnected
5821`else
5822 .opcode ({`PROBES7.op_3_w}),
5823 .PC_reg ({`PROBES7.pc_3_w}),
5824 .Y_reg (`SPC7.exu0.rml.arch_yreg_tid3_ff),
5825 .CCR_reg (`SPC7.exu0.ect.arch_ccr_tid3_lth),
5826 .FPRS_reg (`SPC7.fgu.fac.fprs_tid3),
5827 .FSR_reg (`SPC7.fgu.fad.fsr3_fx1[27:0]),
5828 .ASI_reg (`SPC7.lsu.dcs.asi_state3),
5829 .GSR_reg ({`SPC7.fgu.fgd.gsr3_mask_fx4[31:0], `SPC7.fgu.fpc.gsr3_11bits_fx4[10:0]}),
5830 .TICK_CMPR_reg (`PROBES7.tick_cmpr_3),
5831 .STICK_CMPR_reg (`PROBES7.stick_cmpr_3),
5832 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_3),
5833 .PSTATE_reg (`SPC7.tlu.tsd0.arch_pstate3),
5834 .TL_reg (`SPC7.tlu.trl0.tl3),
5835 .PIL_reg (`SPC7.tlu.trl0.pil3),
5836 .TBA_reg (`SPC7.tlu.tsd0.tba3[47:15]),
5837 .VER_reg (`SPC7.tlu.asi.hver_value), // static
5838 .CWP_reg (`SPC7.exu0.rml.cwp_thr3),
5839 .CANSAVE_reg (`SPC7.exu0.rml.cansave_thr3),
5840 .CANRESTORE_reg (`SPC7.exu0.rml.canrestore_thr3),
5841 .OTHERWIN_reg (`SPC7.exu0.rml.otherwin_thr3),
5842 .WSTATE_reg (`SPC7.exu0.rml.wstate_thr3),
5843 .CLEANWIN_reg (`SPC7.exu0.rml.cleanwin_thr3),
5844 .rd_SOFTINT_reg (`SPC7.tlu.trl0.rd_softint3),
5845 .SOFTINT_reg (`SPC7.tlu.trl0.softint3),
5846 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec3),
5847 .GL_reg (`SPC7.tlu.tlu_gl3),
5848 .HPSTATE_reg (`SPC7.tlu.tsd0.arch_hpstate3),
5849 .HTBA_reg (`SPC7.tlu.tsd0.htba3[47:14]),
5850 .HINTP_reg (`SPC7.tlu.trl0.hintp3),
5851
5852 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_3[12:0]}),
5853 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_3[12:0]}),
5854 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_3[12:0]}),
5855 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_3[12:0]}),
5856 .LSU_CONTROL_reg ({29'd0,
5857 `SPC7.lsu.dcs.wpt_mode_3[1:0],
5858 `SPC7.lsu.dcs.wpt_mask_3[7:0],
5859 `SPC7.lsu.dcs.wpt_enable_3[1:0],
5860 18'd0,
5861 `SPC7.lsu.dcs.spec_enable[3],
5862 `SPC7.lsu.dcs.dmmu_enable[3],
5863 `SPC7.lsu.dcs.immu_enable[3],
5864 `SPC7.lsu.dcs.dc_enable[3],
5865 `SPC7.lsu.dcs.ic_enable[3]}),
5866 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.immu_tag_access_3[47:0]}),
5867 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd0.dmmu_tag_access_3[47:0]}),
5868 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint3[47:3],3'b00}),
5869 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_3[47:0]),
5870
5871 .Trap_Entry_1 (`PROBES7.trap_entry_1_t3),
5872 .Trap_Entry_2 (`PROBES7.trap_entry_2_t3),
5873 .Trap_Entry_3 (`PROBES7.trap_entry_3_t3),
5874 .Trap_Entry_4 (`PROBES7.trap_entry_4_t3),
5875 .Trap_Entry_5 (`PROBES7.trap_entry_5_t3),
5876 .Trap_Entry_6 (`PROBES7.trap_entry_6_t3),
5877
5878 .exu_valid (`PROBES7.ex_valid[3]),
5879
5880 .imul_valid (`PROBES7.imul_valid[3]),
5881
5882 .fp_valid (`PROBES7.fg_valid[3]),
5883 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
5884 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
5885 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
5886
5887 .idiv_valid (`PROBES7.fgu_idiv_valid[3]),
5888
5889 .fdiv_valid (`PROBES7.fgu_fdiv_valid[3]),
5890
5891 .lsu_valid (`PROBES7.lsu_valid[3]),
5892 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
5893 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
5894 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
5895
5896 .asi_valid (`PROBES7.asi_valid_fx5[3]),
5897 .asi_in_progress (`PROBES7.asi_in_progress_fx4[3]),
5898
5899 .tlu_valid (`PROBES7.tlu_valid[3])
5900`endif
5901 );
5902
5903
5904//----------------------------------------------------------
5905//
5906// THREAD 4
5907//
5908
5909 nas_pipe7 t4 (
5910 .mycid (cid),
5911 .mytid (3'h4),
5912
5913// If GATESIM, instantiate "dummy" module with floating ports since unused.
5914`ifdef GATESIM
5915 .opcode () // this and all other ports are unconnected
5916`else
5917 .opcode ({`PROBES7.op_4_w}),
5918 .PC_reg ({`PROBES7.pc_4_w}),
5919 .Y_reg (`SPC7.exu1.rml.arch_yreg_tid0_ff),
5920 .CCR_reg (`SPC7.exu1.ect.arch_ccr_tid0_lth),
5921 .FPRS_reg (`SPC7.fgu.fac.fprs_tid4),
5922 .FSR_reg (`SPC7.fgu.fad.fsr4_fx1[27:0]),
5923 .ASI_reg (`SPC7.lsu.dcs.asi_state4),
5924 .GSR_reg ({`SPC7.fgu.fgd.gsr4_mask_fx4[31:0], `SPC7.fgu.fpc.gsr4_11bits_fx4[10:0]}),
5925 .TICK_CMPR_reg (`PROBES7.tick_cmpr_4),
5926 .STICK_CMPR_reg (`PROBES7.stick_cmpr_4),
5927 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_4),
5928 .PSTATE_reg (`SPC7.tlu.tsd1.arch_pstate0),
5929 .TL_reg (`SPC7.tlu.trl1.tl0),
5930 .PIL_reg (`SPC7.tlu.trl1.pil0),
5931 .TBA_reg (`SPC7.tlu.tsd1.tba0[47:15]),
5932 .VER_reg (`SPC7.tlu.asi.hver_value), // static
5933 .CWP_reg (`SPC7.exu1.rml.cwp_thr0),
5934 .CANSAVE_reg (`SPC7.exu1.rml.cansave_thr0),
5935 .CANRESTORE_reg (`SPC7.exu1.rml.canrestore_thr0),
5936 .OTHERWIN_reg (`SPC7.exu1.rml.otherwin_thr0),
5937 .WSTATE_reg (`SPC7.exu1.rml.wstate_thr0),
5938 .CLEANWIN_reg (`SPC7.exu1.rml.cleanwin_thr0),
5939 .rd_SOFTINT_reg (`SPC7.tlu.trl1.rd_softint0),
5940 .SOFTINT_reg (`SPC7.tlu.trl1.softint0),
5941 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec4),
5942 .GL_reg (`SPC7.tlu.tlu_gl4),
5943 .HPSTATE_reg (`SPC7.tlu.tsd1.arch_hpstate0),
5944 .HTBA_reg (`SPC7.tlu.tsd1.htba0[47:14]),
5945 .HINTP_reg (`SPC7.tlu.trl1.hintp0),
5946
5947 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_4[12:0]}),
5948 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_4[12:0]}),
5949 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_4[12:0]}),
5950 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_4[12:0]}),
5951 .LSU_CONTROL_reg ({29'd0,
5952 `SPC7.lsu.dcs.wpt_mode_4[1:0],
5953 `SPC7.lsu.dcs.wpt_mask_4[7:0],
5954 `SPC7.lsu.dcs.wpt_enable_4[1:0],
5955 18'd0,
5956 `SPC7.lsu.dcs.spec_enable[4],
5957 `SPC7.lsu.dcs.dmmu_enable[4],
5958 `SPC7.lsu.dcs.immu_enable[4],
5959 `SPC7.lsu.dcs.dc_enable[4],
5960 `SPC7.lsu.dcs.ic_enable[4]}),
5961 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.immu_tag_access_0[47:0]}),
5962 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.dmmu_tag_access_0[47:0]}),
5963 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint4[47:3],3'b00}),
5964 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_4[47:0]),
5965
5966 .Trap_Entry_1 (`PROBES7.trap_entry_1_t4),
5967 .Trap_Entry_2 (`PROBES7.trap_entry_2_t4),
5968 .Trap_Entry_3 (`PROBES7.trap_entry_3_t4),
5969 .Trap_Entry_4 (`PROBES7.trap_entry_4_t4),
5970 .Trap_Entry_5 (`PROBES7.trap_entry_5_t4),
5971 .Trap_Entry_6 (`PROBES7.trap_entry_6_t4),
5972
5973 .exu_valid (`PROBES7.ex_valid[4]),
5974
5975 .imul_valid (`PROBES7.imul_valid[4]),
5976
5977 .fp_valid (`PROBES7.fg_valid[4]),
5978 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
5979 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
5980 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
5981
5982 .idiv_valid (`PROBES7.fgu_idiv_valid[4]),
5983
5984 .fdiv_valid (`PROBES7.fgu_fdiv_valid[4]),
5985
5986 .lsu_valid (`PROBES7.lsu_valid[4]),
5987 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
5988 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
5989 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
5990
5991 .asi_valid (`PROBES7.asi_valid_fx5[4]),
5992 .asi_in_progress (`PROBES7.asi_in_progress_fx4[4]),
5993
5994 .tlu_valid (`PROBES7.tlu_valid[4])
5995`endif
5996 );
5997
5998
5999//----------------------------------------------------------
6000//
6001// THREAD 5
6002//
6003
6004 nas_pipe7 t5 (
6005 .mycid (cid),
6006 .mytid (3'h5),
6007
6008// If GATESIM, instantiate "dummy" module with floating ports since unused.
6009`ifdef GATESIM
6010 .opcode () // this and all other ports are unconnected
6011`else
6012 .opcode ({`PROBES7.op_5_w}),
6013 .PC_reg ({`PROBES7.pc_5_w}),
6014 .Y_reg (`SPC7.exu1.rml.arch_yreg_tid1_ff),
6015 .CCR_reg (`SPC7.exu1.ect.arch_ccr_tid1_lth),
6016 .FPRS_reg (`SPC7.fgu.fac.fprs_tid5),
6017 .FSR_reg (`SPC7.fgu.fad.fsr5_fx1[27:0]),
6018 .ASI_reg (`SPC7.lsu.dcs.asi_state5),
6019 .GSR_reg ({`SPC7.fgu.fgd.gsr5_mask_fx4[31:0], `SPC7.fgu.fpc.gsr5_11bits_fx4[10:0]}),
6020 .TICK_CMPR_reg (`PROBES7.tick_cmpr_5),
6021 .STICK_CMPR_reg (`PROBES7.stick_cmpr_5),
6022 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_5),
6023 .PSTATE_reg (`SPC7.tlu.tsd1.arch_pstate1),
6024 .TL_reg (`SPC7.tlu.trl1.tl1),
6025 .PIL_reg (`SPC7.tlu.trl1.pil1),
6026 .TBA_reg (`SPC7.tlu.tsd1.tba1[47:15]),
6027 .VER_reg (`SPC7.tlu.asi.hver_value), // static
6028 .CWP_reg (`SPC7.exu1.rml.cwp_thr1),
6029 .CANSAVE_reg (`SPC7.exu1.rml.cansave_thr1),
6030 .CANRESTORE_reg (`SPC7.exu1.rml.canrestore_thr1),
6031 .OTHERWIN_reg (`SPC7.exu1.rml.otherwin_thr1),
6032 .WSTATE_reg (`SPC7.exu1.rml.wstate_thr1),
6033 .CLEANWIN_reg (`SPC7.exu1.rml.cleanwin_thr1),
6034 .rd_SOFTINT_reg (`SPC7.tlu.trl1.rd_softint1),
6035 .SOFTINT_reg (`SPC7.tlu.trl1.softint1),
6036 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec5),
6037 .GL_reg (`SPC7.tlu.tlu_gl5),
6038 .HPSTATE_reg (`SPC7.tlu.tsd1.arch_hpstate1),
6039 .HTBA_reg (`SPC7.tlu.tsd1.htba1[47:14]),
6040 .HINTP_reg (`SPC7.tlu.trl1.hintp1),
6041
6042 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_5[12:0]}),
6043 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_5[12:0]}),
6044 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_5[12:0]}),
6045 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_5[12:0]}),
6046 .LSU_CONTROL_reg ({29'd0,
6047 `SPC7.lsu.dcs.wpt_mode_5[1:0],
6048 `SPC7.lsu.dcs.wpt_mask_5[7:0],
6049 `SPC7.lsu.dcs.wpt_enable_5[1:0],
6050 18'd0,
6051 `SPC7.lsu.dcs.spec_enable[5],
6052 `SPC7.lsu.dcs.dmmu_enable[5],
6053 `SPC7.lsu.dcs.immu_enable[5],
6054 `SPC7.lsu.dcs.dc_enable[5],
6055 `SPC7.lsu.dcs.ic_enable[5]}),
6056 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.immu_tag_access_1[47:0]}),
6057 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.dmmu_tag_access_1[47:0]}),
6058 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint5[47:3],3'b00}),
6059 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_5[47:0]),
6060
6061 .Trap_Entry_1 (`PROBES7.trap_entry_1_t5),
6062 .Trap_Entry_2 (`PROBES7.trap_entry_2_t5),
6063 .Trap_Entry_3 (`PROBES7.trap_entry_3_t5),
6064 .Trap_Entry_4 (`PROBES7.trap_entry_4_t5),
6065 .Trap_Entry_5 (`PROBES7.trap_entry_5_t5),
6066 .Trap_Entry_6 (`PROBES7.trap_entry_6_t5),
6067
6068 .exu_valid (`PROBES7.ex_valid[5]),
6069
6070 .imul_valid (`PROBES7.imul_valid[5]),
6071
6072 .fp_valid (`PROBES7.fg_valid[5]),
6073 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
6074 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
6075 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
6076
6077 .idiv_valid (`PROBES7.fgu_idiv_valid[5]),
6078
6079 .fdiv_valid (`PROBES7.fgu_fdiv_valid[5]),
6080
6081 .lsu_valid (`PROBES7.lsu_valid[5]),
6082 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
6083 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
6084 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
6085
6086 .asi_valid (`PROBES7.asi_valid_fx5[5]),
6087 .asi_in_progress (`PROBES7.asi_in_progress_fx4[5]),
6088
6089 .tlu_valid (`PROBES7.tlu_valid[5])
6090`endif
6091 );
6092
6093
6094//----------------------------------------------------------
6095//
6096// THREAD 6
6097//
6098
6099 nas_pipe7 t6 (
6100 .mycid (cid),
6101 .mytid (3'h6),
6102
6103// If GATESIM, instantiate "dummy" module with floating ports since unused.
6104`ifdef GATESIM
6105 .opcode () // this and all other ports are unconnected
6106`else
6107 .opcode ({`PROBES7.op_6_w}),
6108 .PC_reg ({`PROBES7.pc_6_w}),
6109 .Y_reg (`SPC7.exu1.rml.arch_yreg_tid2_ff),
6110 .CCR_reg (`SPC7.exu1.ect.arch_ccr_tid2_lth),
6111 .FPRS_reg (`SPC7.fgu.fac.fprs_tid6),
6112 .FSR_reg (`SPC7.fgu.fad.fsr6_fx1[27:0]),
6113 .ASI_reg (`SPC7.lsu.dcs.asi_state6),
6114 .GSR_reg ({`SPC7.fgu.fgd.gsr6_mask_fx4[31:0], `SPC7.fgu.fpc.gsr6_11bits_fx4[10:0]}),
6115 .TICK_CMPR_reg (`PROBES7.tick_cmpr_6),
6116 .STICK_CMPR_reg (`PROBES7.stick_cmpr_6),
6117 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_6),
6118 .PSTATE_reg (`SPC7.tlu.tsd1.arch_pstate2),
6119 .TL_reg (`SPC7.tlu.trl1.tl2),
6120 .PIL_reg (`SPC7.tlu.trl1.pil2),
6121 .TBA_reg (`SPC7.tlu.tsd1.tba2[47:15]),
6122 .VER_reg (`SPC7.tlu.asi.hver_value), // static
6123 .CWP_reg (`SPC7.exu1.rml.cwp_thr2),
6124 .CANSAVE_reg (`SPC7.exu1.rml.cansave_thr2),
6125 .CANRESTORE_reg (`SPC7.exu1.rml.canrestore_thr2),
6126 .OTHERWIN_reg (`SPC7.exu1.rml.otherwin_thr2),
6127 .WSTATE_reg (`SPC7.exu1.rml.wstate_thr2),
6128 .CLEANWIN_reg (`SPC7.exu1.rml.cleanwin_thr2),
6129 .rd_SOFTINT_reg (`SPC7.tlu.trl1.rd_softint2),
6130 .SOFTINT_reg (`SPC7.tlu.trl1.softint2),
6131 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec6),
6132 .GL_reg (`SPC7.tlu.tlu_gl6),
6133 .HPSTATE_reg (`SPC7.tlu.tsd1.arch_hpstate2),
6134 .HTBA_reg (`SPC7.tlu.tsd1.htba2[47:14]),
6135 .HINTP_reg (`SPC7.tlu.trl1.hintp2),
6136
6137 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_6[12:0]}),
6138 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_6[12:0]}),
6139 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_6[12:0]}),
6140 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_6[12:0]}),
6141 .LSU_CONTROL_reg ({29'd0,
6142 `SPC7.lsu.dcs.wpt_mode_6[1:0],
6143 `SPC7.lsu.dcs.wpt_mask_6[7:0],
6144 `SPC7.lsu.dcs.wpt_enable_6[1:0],
6145 18'd0,
6146 `SPC7.lsu.dcs.spec_enable[6],
6147 `SPC7.lsu.dcs.dmmu_enable[6],
6148 `SPC7.lsu.dcs.immu_enable[6],
6149 `SPC7.lsu.dcs.dc_enable[6],
6150 `SPC7.lsu.dcs.ic_enable[6]}),
6151 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.immu_tag_access_2[47:0]}),
6152 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.dmmu_tag_access_2[47:0]}),
6153 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint6[47:3],3'b00}),
6154 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_6[47:0]),
6155
6156 .Trap_Entry_1 (`PROBES7.trap_entry_1_t6),
6157 .Trap_Entry_2 (`PROBES7.trap_entry_2_t6),
6158 .Trap_Entry_3 (`PROBES7.trap_entry_3_t6),
6159 .Trap_Entry_4 (`PROBES7.trap_entry_4_t6),
6160 .Trap_Entry_5 (`PROBES7.trap_entry_5_t6),
6161 .Trap_Entry_6 (`PROBES7.trap_entry_6_t6),
6162
6163 .exu_valid (`PROBES7.ex_valid[6]),
6164
6165 .imul_valid (`PROBES7.imul_valid[6]),
6166
6167 .fp_valid (`PROBES7.fg_valid[6]),
6168 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
6169 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
6170 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
6171
6172 .idiv_valid (`PROBES7.fgu_idiv_valid[6]),
6173
6174 .fdiv_valid (`PROBES7.fgu_fdiv_valid[6]),
6175
6176 .lsu_valid (`PROBES7.lsu_valid[6]),
6177 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
6178 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
6179 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
6180
6181 .asi_valid (`PROBES7.asi_valid_fx5[6]),
6182 .asi_in_progress (`PROBES7.asi_in_progress_fx4[6]),
6183
6184 .tlu_valid (`PROBES7.tlu_valid[6])
6185`endif
6186 );
6187
6188
6189//----------------------------------------------------------
6190//
6191// THREAD 7
6192//
6193
6194 nas_pipe7 t7 (
6195 .mycid (cid),
6196 .mytid (3'h7),
6197
6198// If GATESIM, instantiate "dummy" module with floating ports since unused.
6199`ifdef GATESIM
6200 .opcode () // this and all other ports are unconnected
6201`else
6202 .opcode ({`PROBES7.op_7_w}),
6203 .PC_reg ({`PROBES7.pc_7_w}),
6204 .Y_reg (`SPC7.exu1.rml.arch_yreg_tid3_ff),
6205 .CCR_reg (`SPC7.exu1.ect.arch_ccr_tid3_lth),
6206 .FPRS_reg (`SPC7.fgu.fac.fprs_tid7),
6207 .FSR_reg (`SPC7.fgu.fad.fsr7_fx1[27:0]),
6208 .ASI_reg (`SPC7.lsu.dcs.asi_state7),
6209 .GSR_reg ({`SPC7.fgu.fgd.gsr7_mask_fx4[31:0], `SPC7.fgu.fpc.gsr7_11bits_fx4[10:0]}),
6210 .TICK_CMPR_reg (`PROBES7.tick_cmpr_7),
6211 .STICK_CMPR_reg (`PROBES7.stick_cmpr_7),
6212 .HSTICK_CMPR_reg (`PROBES7.hstick_cmpr_7),
6213 .PSTATE_reg (`SPC7.tlu.tsd1.arch_pstate3),
6214 .TL_reg (`SPC7.tlu.trl1.tl3),
6215 .PIL_reg (`SPC7.tlu.trl1.pil3),
6216 .TBA_reg (`SPC7.tlu.tsd1.tba3[47:15]),
6217 .VER_reg (`SPC7.tlu.asi.hver_value), // static
6218 .CWP_reg (`SPC7.exu1.rml.cwp_thr3),
6219 .CANSAVE_reg (`SPC7.exu1.rml.cansave_thr3),
6220 .CANRESTORE_reg (`SPC7.exu1.rml.canrestore_thr3),
6221 .OTHERWIN_reg (`SPC7.exu1.rml.otherwin_thr3),
6222 .WSTATE_reg (`SPC7.exu1.rml.wstate_thr3),
6223 .CLEANWIN_reg (`SPC7.exu1.rml.cleanwin_thr3),
6224 .rd_SOFTINT_reg (`SPC7.tlu.trl1.rd_softint3),
6225 .SOFTINT_reg (`SPC7.tlu.trl1.softint3),
6226 .INTR_RECEIVE_reg (`SPC7.tlu.cth.int_rec7),
6227 .GL_reg (`SPC7.tlu.tlu_gl7),
6228 .HPSTATE_reg (`SPC7.tlu.tsd1.arch_hpstate3),
6229 .HTBA_reg (`SPC7.tlu.tsd1.htba3[47:14]),
6230 .HINTP_reg (`SPC7.tlu.trl1.hintp3),
6231
6232 .CTXT_PRIM_0_reg ({51'b0,`SPC7.lsu.dcs.p0ctxt_7[12:0]}),
6233 .CTXT_SEC_0_reg ({51'b0,`SPC7.lsu.dcs.s0ctxt_7[12:0]}),
6234 .CTXT_PRIM_1_reg ({51'b0,`SPC7.lsu.dcs.p1ctxt_7[12:0]}),
6235 .CTXT_SEC_1_reg ({51'b0,`SPC7.lsu.dcs.s1ctxt_7[12:0]}),
6236 .LSU_CONTROL_reg ({29'd0,
6237 `SPC7.lsu.dcs.wpt_mode_7[1:0],
6238 `SPC7.lsu.dcs.wpt_mask_7[7:0],
6239 `SPC7.lsu.dcs.wpt_enable_7[1:0],
6240 18'd0,
6241 `SPC7.lsu.dcs.spec_enable[7],
6242 `SPC7.lsu.dcs.dmmu_enable[7],
6243 `SPC7.lsu.dcs.immu_enable[7],
6244 `SPC7.lsu.dcs.dc_enable[7],
6245 `SPC7.lsu.dcs.ic_enable[7]}),
6246 .I_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.immu_tag_access_3[47:0]}),
6247 .D_TAG_ACC_reg ({16'b0,`SPC7.mmu.asd1.dmmu_tag_access_3[47:0]}),
6248 .WATCHPOINT_ADDR_reg ({16'b0,`SPC7.lsu.dcs.watchpoint7[47:3],3'b00}),
6249 .DSFAR_reg (`SPC7.tlu.dfd.dsfar_7[47:0]),
6250
6251 .Trap_Entry_1 (`PROBES7.trap_entry_1_t7),
6252 .Trap_Entry_2 (`PROBES7.trap_entry_2_t7),
6253 .Trap_Entry_3 (`PROBES7.trap_entry_3_t7),
6254 .Trap_Entry_4 (`PROBES7.trap_entry_4_t7),
6255 .Trap_Entry_5 (`PROBES7.trap_entry_5_t7),
6256 .Trap_Entry_6 (`PROBES7.trap_entry_6_t7),
6257
6258 .exu_valid (`PROBES7.ex_valid[7]),
6259
6260 .imul_valid (`PROBES7.imul_valid[7]),
6261
6262 .fp_valid (`PROBES7.fg_valid[7]),
6263 .frf_w1_valid (`SPC7.fgu.frf.w1_valid),
6264 .frf_w1_tid (`SPC7.fgu.frf.w1_tid),
6265 .frf_w1_addr (`SPC7.fgu.frf.w1_addr),
6266
6267 .idiv_valid (`PROBES7.fgu_idiv_valid[7]),
6268
6269 .fdiv_valid (`PROBES7.fgu_fdiv_valid[7]),
6270
6271 .lsu_valid (`PROBES7.lsu_valid[7]),
6272 .frf_w2_valid (`SPC7.fgu.frf.w2_valid),
6273 .frf_w2_tid (`SPC7.fgu.frf.w2_tid),
6274 .frf_w2_addr (`SPC7.fgu.frf.w2_addr),
6275
6276 .asi_valid (`PROBES7.asi_valid_fx5[7]),
6277 .asi_in_progress (`PROBES7.asi_in_progress_fx4[7]),
6278
6279 .tlu_valid (`PROBES7.tlu_valid[7])
6280`endif
6281 );
6282
6283//----------------------------------------------------------
6284
6285
6286//----------------------------------------------------------
6287endmodule
6288
6289`endif
6290
Full OpenSPARC design & verification tarball including full HDL.