[OpenSPARC-T2-DV] / verif / env / common / verilog / nas_car / nas_regs.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: nas_regs.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
`ifndef GATESIM

wire [63:0] GSR_wire =  { GSR_reg[42:11]           , // Mask
                          4'b0                     , // Unused
                          GSR_reg[10]              , // IM
                          GSR_reg[9:8]             , // IRND
                          17'b0                    , // Unused
                          GSR_reg[7:3]             , // Scale
                          GSR_reg[2:0]               // Align
                          };


wire [63:0] FSR_wire = {26'b0                 , // unused
                             FSR_reg[7:6]     , // fcc3
                             FSR_reg[5:4]     , // fcc2
                             FSR_reg[3:2]     , // fcc1
                             FSR_reg[27:26]   , // RD
                             2'b0             , // unused
                             FSR_reg[25:21]   , // TEM
                             FSR_reg[20]      , // NS
                             2'b0             , // unused
                             3'b0             , // ver
                             1'b0             , // ftt[2]
                             FSR_reg[19:18]   , // ftt[1:0]
                             1'b0             , // qne
                             1'b0             , // unused
                             FSR_reg[1:0]     , // fcc0
                             FSR_reg[17:13]   , // aexc
                             FSR_reg[12:8] }  ; // cexc

// Exploding Trap Stack 


wire [47:0] TPC1_wire     = {Trap_Entry_1[91:46],2'b0};
wire [47:0] TNPC1_wire    = {Trap_Entry_1[45:0],2'b0};
wire [8 :0] TT1_wire      = Trap_Entry_1[100:92];
wire [41:0] TSTATE1_wire  = {Trap_Entry_1[132:131],    // GL[1:0]
                             Trap_Entry_1[130:123],    // CCR[7:0]
                             Trap_Entry_1[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_1[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_1[113],        // pstate.cle
                             Trap_Entry_1[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_1[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_1[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE1_wire = {Trap_Entry_1[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_1[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_1[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_1[104]         // hpstate.tlz
                             };


wire [47:0] TPC2_wire     = {Trap_Entry_2[91:46],2'b0};
wire [47:0] TNPC2_wire    = {Trap_Entry_2[45:0],2'b0};
wire [8 :0] TT2_wire      = Trap_Entry_2[100:92];
wire [41:0] TSTATE2_wire  = {Trap_Entry_2[132:131],    // GL[1:0]
                             Trap_Entry_2[130:123],    // CCR[7:0]
                             Trap_Entry_2[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_2[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_2[113],        // pstate.cle
                             Trap_Entry_2[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_2[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_2[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE2_wire = {Trap_Entry_2[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_2[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_2[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_2[104]         // hpstate.tlz
                             };


wire [47:0] TPC3_wire     = {Trap_Entry_3[91:46],2'b0};
wire [47:0] TNPC3_wire    = {Trap_Entry_3[45:0],2'b0};
wire [8 :0] TT3_wire      = Trap_Entry_3[100:92];
wire [41:0] TSTATE3_wire  = {Trap_Entry_3[132:131],    // GL[1:0]
                             Trap_Entry_3[130:123],    // CCR[7:0]
                             Trap_Entry_3[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_3[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_3[113],        // pstate.cle
                             Trap_Entry_3[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_3[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_3[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE3_wire = {Trap_Entry_3[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_3[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_3[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_3[104]         // hpstate.tlz
                             };


wire [47:0] TPC4_wire     = {Trap_Entry_4[91:46],2'b0};
wire [47:0] TNPC4_wire    = {Trap_Entry_4[45:0],2'b0};
wire [8 :0] TT4_wire      = Trap_Entry_4[100:92];
wire [41:0] TSTATE4_wire  = {Trap_Entry_4[132:131],    // GL[1:0]
                             Trap_Entry_4[130:123],    // CCR[7:0]
                             Trap_Entry_4[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_4[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_4[113],        // pstate.cle
                             Trap_Entry_4[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_4[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_4[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE4_wire = {Trap_Entry_4[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_4[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_4[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_4[104]         // hpstate.tlz
                             };


wire [47:0] TPC5_wire     = {Trap_Entry_5[91:46],2'b0};
wire [47:0] TNPC5_wire    = {Trap_Entry_5[45:0],2'b0};
wire [8 :0] TT5_wire      = Trap_Entry_5[100:92];
wire [41:0] TSTATE5_wire  = {Trap_Entry_5[132:131],    // GL[1:0]
                             Trap_Entry_5[130:123],    // CCR[7:0]
                             Trap_Entry_5[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_5[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_5[113],        // pstate.cle
                             Trap_Entry_5[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_5[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_5[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE5_wire = {Trap_Entry_5[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_5[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_5[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_5[104]         // hpstate.tlz
                             };


wire [47:0] TPC6_wire     = {Trap_Entry_6[91:46],2'b0};
wire [47:0] TNPC6_wire    = {Trap_Entry_6[45:0],2'b0};
wire [8 :0] TT6_wire      = Trap_Entry_6[100:92];
wire [41:0] TSTATE6_wire  = {Trap_Entry_6[132:131],    // GL[1:0]
                             Trap_Entry_6[130:123],    // CCR[7:0]
                             Trap_Entry_6[122:115],    // ASI[7:0]
                             2'b0,
                             1'b0,                     // pstate[13]
                             Trap_Entry_6[111],        // pstate.tct
                             2'b0,
                             Trap_Entry_6[113],        // pstate.cle
                             Trap_Entry_6[112],        // pstate.tle
                             3'b0,
                             Trap_Entry_6[108:105],    // pstate.{pef.am.prv.ie}
                             1'b0,
                             5'b0,
                             Trap_Entry_6[103:101]     // CWP[2:0]
                             };
wire [10:0] HTSTATE6_wire = {Trap_Entry_6[114],        // hpstate.ibe
                             4'b0,
                             Trap_Entry_6[109],        // hpstate.red
                             2'b0,
                             Trap_Entry_6[110],        // hpstate.hpriv
                             1'b0,
                             Trap_Entry_6[104]         // hpstate.tlz
                             };


wire [63:0] TICK_CMPR_wire = {~TICK_CMPR_reg[63],TICK_CMPR_reg[62:0]};
wire [63:0] STICK_CMPR_wire = {~STICK_CMPR_reg[63],STICK_CMPR_reg[62:0]};
wire [63:0] HSTICK_CMPR_wire = {~HSTICK_CMPR_reg[63],HSTICK_CMPR_reg[62:0]};

`endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: nas_regs.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	`ifndef GATESIM
	36
	37	wire [63:0] GSR_wire = { GSR_reg[42:11] , // Mask
	38	4'b0 , // Unused
	39	GSR_reg[10] , // IM
	40	GSR_reg[9:8] , // IRND
	41	17'b0 , // Unused
	42	GSR_reg[7:3] , // Scale
	43	GSR_reg[2:0] // Align
	44	};
	45
	46
	47	wire [63:0] FSR_wire = {26'b0 , // unused
	48	FSR_reg[7:6] , // fcc3
	49	FSR_reg[5:4] , // fcc2
	50	FSR_reg[3:2] , // fcc1
	51	FSR_reg[27:26] , // RD
	52	2'b0 , // unused
	53	FSR_reg[25:21] , // TEM
	54	FSR_reg[20] , // NS
	55	2'b0 , // unused
	56	3'b0 , // ver
	57	1'b0 , // ftt[2]
	58	FSR_reg[19:18] , // ftt[1:0]
	59	1'b0 , // qne
	60	1'b0 , // unused
	61	FSR_reg[1:0] , // fcc0
	62	FSR_reg[17:13] , // aexc
	63	FSR_reg[12:8] } ; // cexc
	64
65	// Exploding Trap Stack
66
67
68	wire [47:0] TPC1_wire = {Trap_Entry_1[91:46],2'b0};
69	wire [47:0] TNPC1_wire = {Trap_Entry_1[45:0],2'b0};
70	wire [8 :0] TT1_wire = Trap_Entry_1[100:92];
71	wire [41:0] TSTATE1_wire = {Trap_Entry_1[132:131], // GL[1:0]
72	Trap_Entry_1[130:123], // CCR[7:0]
73	Trap_Entry_1[122:115], // ASI[7:0]
74	2'b0,
75	1'b0, // pstate[13]
76	Trap_Entry_1[111], // pstate.tct
77	2'b0,
78	Trap_Entry_1[113], // pstate.cle
79	Trap_Entry_1[112], // pstate.tle
80	3'b0,
81	Trap_Entry_1[108:105], // pstate.{pef.am.prv.ie}
82	1'b0,
83	5'b0,
84	Trap_Entry_1[103:101] // CWP[2:0]
85	};
86	wire [10:0] HTSTATE1_wire = {Trap_Entry_1[114], // hpstate.ibe
87	4'b0,
88	Trap_Entry_1[109], // hpstate.red
89	2'b0,
90	Trap_Entry_1[110], // hpstate.hpriv
91	1'b0,
92	Trap_Entry_1[104] // hpstate.tlz
93	};
94
95
96	wire [47:0] TPC2_wire = {Trap_Entry_2[91:46],2'b0};
97	wire [47:0] TNPC2_wire = {Trap_Entry_2[45:0],2'b0};
98	wire [8 :0] TT2_wire = Trap_Entry_2[100:92];
99	wire [41:0] TSTATE2_wire = {Trap_Entry_2[132:131], // GL[1:0]
100	Trap_Entry_2[130:123], // CCR[7:0]
101	Trap_Entry_2[122:115], // ASI[7:0]
102	2'b0,
103	1'b0, // pstate[13]
104	Trap_Entry_2[111], // pstate.tct
105	2'b0,
106	Trap_Entry_2[113], // pstate.cle
107	Trap_Entry_2[112], // pstate.tle
108	3'b0,
109	Trap_Entry_2[108:105], // pstate.{pef.am.prv.ie}
110	1'b0,
111	5'b0,
112	Trap_Entry_2[103:101] // CWP[2:0]
113	};
114	wire [10:0] HTSTATE2_wire = {Trap_Entry_2[114], // hpstate.ibe
115	4'b0,
116	Trap_Entry_2[109], // hpstate.red
117	2'b0,
118	Trap_Entry_2[110], // hpstate.hpriv
119	1'b0,
120	Trap_Entry_2[104] // hpstate.tlz
121	};
122
123
124	wire [47:0] TPC3_wire = {Trap_Entry_3[91:46],2'b0};
125	wire [47:0] TNPC3_wire = {Trap_Entry_3[45:0],2'b0};
126	wire [8 :0] TT3_wire = Trap_Entry_3[100:92];
127	wire [41:0] TSTATE3_wire = {Trap_Entry_3[132:131], // GL[1:0]
128	Trap_Entry_3[130:123], // CCR[7:0]
129	Trap_Entry_3[122:115], // ASI[7:0]
130	2'b0,
131	1'b0, // pstate[13]
132	Trap_Entry_3[111], // pstate.tct
133	2'b0,
134	Trap_Entry_3[113], // pstate.cle
135	Trap_Entry_3[112], // pstate.tle
136	3'b0,
137	Trap_Entry_3[108:105], // pstate.{pef.am.prv.ie}
138	1'b0,
139	5'b0,
140	Trap_Entry_3[103:101] // CWP[2:0]
141	};
142	wire [10:0] HTSTATE3_wire = {Trap_Entry_3[114], // hpstate.ibe
143	4'b0,
144	Trap_Entry_3[109], // hpstate.red
145	2'b0,
146	Trap_Entry_3[110], // hpstate.hpriv
147	1'b0,
148	Trap_Entry_3[104] // hpstate.tlz
149	};
150
151
152	wire [47:0] TPC4_wire = {Trap_Entry_4[91:46],2'b0};
153	wire [47:0] TNPC4_wire = {Trap_Entry_4[45:0],2'b0};
154	wire [8 :0] TT4_wire = Trap_Entry_4[100:92];
155	wire [41:0] TSTATE4_wire = {Trap_Entry_4[132:131], // GL[1:0]
156	Trap_Entry_4[130:123], // CCR[7:0]
157	Trap_Entry_4[122:115], // ASI[7:0]
158	2'b0,
159	1'b0, // pstate[13]
160	Trap_Entry_4[111], // pstate.tct
161	2'b0,
162	Trap_Entry_4[113], // pstate.cle
163	Trap_Entry_4[112], // pstate.tle
164	3'b0,
165	Trap_Entry_4[108:105], // pstate.{pef.am.prv.ie}
166	1'b0,
167	5'b0,
168	Trap_Entry_4[103:101] // CWP[2:0]
169	};
170	wire [10:0] HTSTATE4_wire = {Trap_Entry_4[114], // hpstate.ibe
171	4'b0,
172	Trap_Entry_4[109], // hpstate.red
173	2'b0,
174	Trap_Entry_4[110], // hpstate.hpriv
175	1'b0,
176	Trap_Entry_4[104] // hpstate.tlz
177	};
178
179
180	wire [47:0] TPC5_wire = {Trap_Entry_5[91:46],2'b0};
181	wire [47:0] TNPC5_wire = {Trap_Entry_5[45:0],2'b0};
182	wire [8 :0] TT5_wire = Trap_Entry_5[100:92];
183	wire [41:0] TSTATE5_wire = {Trap_Entry_5[132:131], // GL[1:0]
184	Trap_Entry_5[130:123], // CCR[7:0]
185	Trap_Entry_5[122:115], // ASI[7:0]
186	2'b0,
187	1'b0, // pstate[13]
188	Trap_Entry_5[111], // pstate.tct
189	2'b0,
190	Trap_Entry_5[113], // pstate.cle
191	Trap_Entry_5[112], // pstate.tle
192	3'b0,
193	Trap_Entry_5[108:105], // pstate.{pef.am.prv.ie}
194	1'b0,
195	5'b0,
196	Trap_Entry_5[103:101] // CWP[2:0]
197	};
198	wire [10:0] HTSTATE5_wire = {Trap_Entry_5[114], // hpstate.ibe
199	4'b0,
200	Trap_Entry_5[109], // hpstate.red
201	2'b0,
202	Trap_Entry_5[110], // hpstate.hpriv
203	1'b0,
204	Trap_Entry_5[104] // hpstate.tlz
205	};
206
207
208	wire [47:0] TPC6_wire = {Trap_Entry_6[91:46],2'b0};
209	wire [47:0] TNPC6_wire = {Trap_Entry_6[45:0],2'b0};
210	wire [8 :0] TT6_wire = Trap_Entry_6[100:92];
211	wire [41:0] TSTATE6_wire = {Trap_Entry_6[132:131], // GL[1:0]
212	Trap_Entry_6[130:123], // CCR[7:0]
213	Trap_Entry_6[122:115], // ASI[7:0]
214	2'b0,
215	1'b0, // pstate[13]
216	Trap_Entry_6[111], // pstate.tct
217	2'b0,
218	Trap_Entry_6[113], // pstate.cle
219	Trap_Entry_6[112], // pstate.tle
220	3'b0,
221	Trap_Entry_6[108:105], // pstate.{pef.am.prv.ie}
222	1'b0,
223	5'b0,
224	Trap_Entry_6[103:101] // CWP[2:0]
225	};
226	wire [10:0] HTSTATE6_wire = {Trap_Entry_6[114], // hpstate.ibe
227	4'b0,
228	Trap_Entry_6[109], // hpstate.red
229	2'b0,
230	Trap_Entry_6[110], // hpstate.hpriv
231	1'b0,
232	Trap_Entry_6[104] // hpstate.tlz
233	};
234
235
236
237	wire [63:0] TICK_CMPR_wire = {~TICK_CMPR_reg[63],TICK_CMPR_reg[62:0]};
238	wire [63:0] STICK_CMPR_wire = {~STICK_CMPR_reg[63],STICK_CMPR_reg[62:0]};
239	wire [63:0] HSTICK_CMPR_wire = {~HSTICK_CMPR_reg[63],HSTICK_CMPR_reg[62:0]};
240
241	`endif