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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: nas_top_inc.vh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | reg [63:0] lsu_stb_empty_1; | |
36 | reg [63:0] lsu_stb_empty_2; | |
37 | reg [63:0] lsu_stb_empty_3; | |
38 | wire [63:0] lsu_stb_empty = lsu_stb_empty_3; // Used by nas_top & nas_pipe | |
39 | wire [63:0] lsu_stb_empty_0 = | |
40 | { | |
41 | `ifdef CORE_7 | |
42 | `CPU.spc7.lsu_stb_empty, | |
43 | `else | |
44 | 8'hff, | |
45 | `endif | |
46 | `ifdef CORE_6 | |
47 | `CPU.spc6.lsu_stb_empty, | |
48 | `else | |
49 | 8'hff, | |
50 | `endif | |
51 | `ifdef CORE_5 | |
52 | `CPU.spc5.lsu_stb_empty, | |
53 | `else | |
54 | 8'hff, | |
55 | `endif | |
56 | `ifdef CORE_4 | |
57 | `CPU.spc4.lsu_stb_empty, | |
58 | `else | |
59 | 8'hff, | |
60 | `endif | |
61 | `ifdef CORE_3 | |
62 | `CPU.spc3.lsu_stb_empty, | |
63 | `else | |
64 | 8'hff, | |
65 | `endif | |
66 | `ifdef CORE_2 | |
67 | `CPU.spc2.lsu_stb_empty, | |
68 | `else | |
69 | 8'hff, | |
70 | `endif | |
71 | `ifdef CORE_1 | |
72 | `CPU.spc1.lsu_stb_empty, | |
73 | `else | |
74 | 8'hff, | |
75 | `endif | |
76 | `ifdef CORE_0 | |
77 | `CPU.spc0.lsu_stb_empty | |
78 | `else | |
79 | 8'hff | |
80 | `endif | |
81 | }; | |
82 | ||
83 | //---------------------------------------------------------------------- | |
84 | // Finish the simulation when all outstanding I$ reqs are over. | |
85 | // Required for global_chkr (L1/L2 cache checker) to work properly. | |
86 | ||
87 | reg [63:0] ireq_pending_1; | |
88 | reg [63:0] ireq_pending_2; | |
89 | reg [63:0] ireq_pending_3; | |
90 | wire [7:0] ireq_pending_c0 = | |
91 | { | |
92 | `ifdef CORE_0 | |
93 | `ifdef GATESIM | |
94 | 8'hff | |
95 | `else | |
96 | `SPC0.ifu_cmu.cmt.csm7.null_state, `SPC0.ifu_cmu.cmt.csm6.null_state, | |
97 | `SPC0.ifu_cmu.cmt.csm5.null_state, `SPC0.ifu_cmu.cmt.csm4.null_state, | |
98 | `SPC0.ifu_cmu.cmt.csm3.null_state, `SPC0.ifu_cmu.cmt.csm2.null_state, | |
99 | `SPC0.ifu_cmu.cmt.csm1.null_state, `SPC0.ifu_cmu.cmt.csm0.null_state | |
100 | `endif | |
101 | `else | |
102 | 8'hff | |
103 | `endif | |
104 | }; | |
105 | wire [7:0] ireq_pending_c1 = | |
106 | { | |
107 | `ifdef CORE_1 | |
108 | `ifdef GATESIM | |
109 | 8'hff | |
110 | `else | |
111 | `SPC1.ifu_cmu.cmt.csm7.null_state, `SPC1.ifu_cmu.cmt.csm6.null_state, | |
112 | `SPC1.ifu_cmu.cmt.csm5.null_state, `SPC1.ifu_cmu.cmt.csm4.null_state, | |
113 | `SPC1.ifu_cmu.cmt.csm3.null_state, `SPC1.ifu_cmu.cmt.csm2.null_state, | |
114 | `SPC1.ifu_cmu.cmt.csm1.null_state, `SPC1.ifu_cmu.cmt.csm0.null_state | |
115 | `endif | |
116 | `else | |
117 | 8'hff | |
118 | `endif | |
119 | }; | |
120 | wire [7:0] ireq_pending_c2 = | |
121 | { | |
122 | `ifdef CORE_2 | |
123 | `ifdef GATESIM | |
124 | 8'hff | |
125 | `else | |
126 | `SPC2.ifu_cmu.cmt.csm7.null_state, `SPC2.ifu_cmu.cmt.csm6.null_state, | |
127 | `SPC2.ifu_cmu.cmt.csm5.null_state, `SPC2.ifu_cmu.cmt.csm4.null_state, | |
128 | `SPC2.ifu_cmu.cmt.csm3.null_state, `SPC2.ifu_cmu.cmt.csm2.null_state, | |
129 | `SPC2.ifu_cmu.cmt.csm1.null_state, `SPC2.ifu_cmu.cmt.csm0.null_state | |
130 | `endif | |
131 | `else | |
132 | 8'hff | |
133 | `endif | |
134 | }; | |
135 | wire [7:0] ireq_pending_c3 = | |
136 | { | |
137 | `ifdef CORE_3 | |
138 | `ifdef GATESIM | |
139 | 8'hff | |
140 | `else | |
141 | `SPC3.ifu_cmu.cmt.csm7.null_state, `SPC3.ifu_cmu.cmt.csm6.null_state, | |
142 | `SPC3.ifu_cmu.cmt.csm5.null_state, `SPC3.ifu_cmu.cmt.csm4.null_state, | |
143 | `SPC3.ifu_cmu.cmt.csm3.null_state, `SPC3.ifu_cmu.cmt.csm2.null_state, | |
144 | `SPC3.ifu_cmu.cmt.csm1.null_state, `SPC3.ifu_cmu.cmt.csm0.null_state | |
145 | `endif | |
146 | `else | |
147 | 8'hff | |
148 | `endif | |
149 | }; | |
150 | wire [7:0] ireq_pending_c4 = | |
151 | { | |
152 | `ifdef CORE_4 | |
153 | `ifdef GATESIM | |
154 | 8'hff | |
155 | `else | |
156 | `SPC4.ifu_cmu.cmt.csm7.null_state, `SPC4.ifu_cmu.cmt.csm6.null_state, | |
157 | `SPC4.ifu_cmu.cmt.csm5.null_state, `SPC4.ifu_cmu.cmt.csm4.null_state, | |
158 | `SPC4.ifu_cmu.cmt.csm3.null_state, `SPC4.ifu_cmu.cmt.csm2.null_state, | |
159 | `SPC4.ifu_cmu.cmt.csm1.null_state, `SPC4.ifu_cmu.cmt.csm0.null_state | |
160 | `endif | |
161 | `else | |
162 | 8'hff | |
163 | `endif | |
164 | }; | |
165 | wire [7:0] ireq_pending_c5 = | |
166 | { | |
167 | `ifdef CORE_5 | |
168 | `ifdef GATESIM | |
169 | 8'hff | |
170 | `else | |
171 | `SPC5.ifu_cmu.cmt.csm7.null_state, `SPC5.ifu_cmu.cmt.csm6.null_state, | |
172 | `SPC5.ifu_cmu.cmt.csm5.null_state, `SPC5.ifu_cmu.cmt.csm4.null_state, | |
173 | `SPC5.ifu_cmu.cmt.csm3.null_state, `SPC5.ifu_cmu.cmt.csm2.null_state, | |
174 | `SPC5.ifu_cmu.cmt.csm1.null_state, `SPC5.ifu_cmu.cmt.csm0.null_state | |
175 | `endif | |
176 | `else | |
177 | 8'hff | |
178 | `endif | |
179 | }; | |
180 | wire [7:0] ireq_pending_c6 = | |
181 | { | |
182 | `ifdef CORE_6 | |
183 | `ifdef GATESIM | |
184 | 8'hff | |
185 | `else | |
186 | `SPC6.ifu_cmu.cmt.csm7.null_state, `SPC6.ifu_cmu.cmt.csm6.null_state, | |
187 | `SPC6.ifu_cmu.cmt.csm5.null_state, `SPC6.ifu_cmu.cmt.csm4.null_state, | |
188 | `SPC6.ifu_cmu.cmt.csm3.null_state, `SPC6.ifu_cmu.cmt.csm2.null_state, | |
189 | `SPC6.ifu_cmu.cmt.csm1.null_state, `SPC6.ifu_cmu.cmt.csm0.null_state | |
190 | `endif | |
191 | `else | |
192 | 8'hff | |
193 | `endif | |
194 | }; | |
195 | wire [7:0] ireq_pending_c7 = | |
196 | { | |
197 | `ifdef CORE_7 | |
198 | `ifdef GATESIM | |
199 | 8'hff | |
200 | `else | |
201 | `SPC7.ifu_cmu.cmt.csm7.null_state, `SPC7.ifu_cmu.cmt.csm6.null_state, | |
202 | `SPC7.ifu_cmu.cmt.csm5.null_state, `SPC7.ifu_cmu.cmt.csm4.null_state, | |
203 | `SPC7.ifu_cmu.cmt.csm3.null_state, `SPC7.ifu_cmu.cmt.csm2.null_state, | |
204 | `SPC7.ifu_cmu.cmt.csm1.null_state, `SPC7.ifu_cmu.cmt.csm0.null_state | |
205 | `endif | |
206 | `else | |
207 | 8'hff | |
208 | `endif | |
209 | }; | |
210 | ||
211 | wire [63:0] ireq_pending = `PARGS.gchkr_on ? ireq_pending_3 : 64'hffffffffffffffff; | |
212 | ||
213 | //---------------------------------------------------------------------- | |
214 | always @ (posedge `BENCH_SPC0_GCLK) begin // { | |
215 | ||
216 | // Pipeline STB_empty so that STACK can occur | |
217 | // before th_check_enable is turned off. (G,M,B,W = 3 cycles) | |
218 | lsu_stb_empty_1 <= lsu_stb_empty_0; | |
219 | lsu_stb_empty_2 <= lsu_stb_empty_1; | |
220 | lsu_stb_empty_3 <= lsu_stb_empty_2; | |
221 | ||
222 | //stage ireq to give time for linefill to be written into the I$ | |
223 | ireq_pending_1 <= {ireq_pending_c7,ireq_pending_c6,ireq_pending_c5,ireq_pending_c4, | |
224 | ireq_pending_c3,ireq_pending_c2,ireq_pending_c1,ireq_pending_c0}; | |
225 | ||
226 | ireq_pending_2 <= ireq_pending_1; | |
227 | ireq_pending_3 <= ireq_pending_2; | |
228 | end // } | |
229 | ||
230 | //---------------------------------------------------------------------- | |
231 | //---------------------------------------------------------------------- |