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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / common / verilog / reg_slam / reg_slam.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: reg_slam.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module reg_slam;
36
37 task slam_TsbSearchMode_core0_thread0;
38 input [63:0] value;
39 reg [5:0] tid;
40 integer junk;
41
42 begin
43`ifdef AXIS_EMUL_COSIM
44//Do Nothing
45`else
46`ifdef GATESIM
47//Do Nothing
48`else
49`ifdef CORE_0
50 @(posedge `SPC0.l2clk);
51 force `SPC0.mmu.asi.hwtw_config_0 = value;
52 @(posedge `SPC0.l2clk);
53 release `SPC0.mmu.asi.hwtw_config_0;
54 if (`PARGS.nas_check_on) begin
55 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 0, 58, value);
56 tid = 0;
57 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
58 end
59`endif
60
61`endif
62
63`endif
64
65 end
66 endtask
67
68
69 task slam_TsbSearchMode_core0_thread1;
70 input [63:0] value;
71 reg [5:0] tid;
72 integer junk;
73
74 begin
75`ifdef AXIS_EMUL_COSIM
76//Do Nothing
77`else
78`ifdef GATESIM
79//Do Nothing
80`else
81`ifdef CORE_0
82 @(posedge `SPC0.l2clk);
83 force `SPC0.mmu.asi.hwtw_config_1 = value;
84 @(posedge `SPC0.l2clk);
85 release `SPC0.mmu.asi.hwtw_config_1;
86 if (`PARGS.nas_check_on) begin
87 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 1, 58, value);
88 tid = 1;
89 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
90 end
91`endif
92
93`endif
94
95`endif
96
97 end
98 endtask
99
100
101 task slam_TsbSearchMode_core0_thread2;
102 input [63:0] value;
103 reg [5:0] tid;
104 integer junk;
105
106 begin
107`ifdef AXIS_EMUL_COSIM
108//Do Nothing
109`else
110`ifdef GATESIM
111//Do Nothing
112`else
113`ifdef CORE_0
114 @(posedge `SPC0.l2clk);
115 force `SPC0.mmu.asi.hwtw_config_2 = value;
116 @(posedge `SPC0.l2clk);
117 release `SPC0.mmu.asi.hwtw_config_2;
118 if (`PARGS.nas_check_on) begin
119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 2, 58, value);
120 tid = 2;
121 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
122 end
123`endif
124
125`endif
126
127`endif
128
129 end
130 endtask
131
132
133 task slam_TsbSearchMode_core0_thread3;
134 input [63:0] value;
135 reg [5:0] tid;
136 integer junk;
137
138 begin
139`ifdef AXIS_EMUL_COSIM
140//Do Nothing
141`else
142`ifdef GATESIM
143//Do Nothing
144`else
145`ifdef CORE_0
146 @(posedge `SPC0.l2clk);
147 force `SPC0.mmu.asi.hwtw_config_3 = value;
148 @(posedge `SPC0.l2clk);
149 release `SPC0.mmu.asi.hwtw_config_3;
150 if (`PARGS.nas_check_on) begin
151 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 3, 58, value);
152 tid = 3;
153 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
154 end
155`endif
156
157`endif
158
159`endif
160
161 end
162 endtask
163
164
165 task slam_TsbSearchMode_core0_thread4;
166 input [63:0] value;
167 reg [5:0] tid;
168 integer junk;
169
170 begin
171`ifdef AXIS_EMUL_COSIM
172//Do Nothing
173`else
174`ifdef GATESIM
175//Do Nothing
176`else
177`ifdef CORE_0
178 @(posedge `SPC0.l2clk);
179 force `SPC0.mmu.asi.hwtw_config_4 = value;
180 @(posedge `SPC0.l2clk);
181 release `SPC0.mmu.asi.hwtw_config_4;
182 if (`PARGS.nas_check_on) begin
183 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 4, 58, value);
184 tid = 4;
185 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
186 end
187`endif
188
189`endif
190
191`endif
192
193 end
194 endtask
195
196
197 task slam_TsbSearchMode_core0_thread5;
198 input [63:0] value;
199 reg [5:0] tid;
200 integer junk;
201
202 begin
203`ifdef AXIS_EMUL_COSIM
204//Do Nothing
205`else
206`ifdef GATESIM
207//Do Nothing
208`else
209`ifdef CORE_0
210 @(posedge `SPC0.l2clk);
211 force `SPC0.mmu.asi.hwtw_config_5 = value;
212 @(posedge `SPC0.l2clk);
213 release `SPC0.mmu.asi.hwtw_config_5;
214 if (`PARGS.nas_check_on) begin
215 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 5, 58, value);
216 tid = 5;
217 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
218 end
219`endif
220
221`endif
222
223`endif
224
225 end
226 endtask
227
228
229 task slam_TsbSearchMode_core0_thread6;
230 input [63:0] value;
231 reg [5:0] tid;
232 integer junk;
233
234 begin
235`ifdef AXIS_EMUL_COSIM
236//Do Nothing
237`else
238`ifdef GATESIM
239//Do Nothing
240`else
241`ifdef CORE_0
242 @(posedge `SPC0.l2clk);
243 force `SPC0.mmu.asi.hwtw_config_6 = value;
244 @(posedge `SPC0.l2clk);
245 release `SPC0.mmu.asi.hwtw_config_6;
246 if (`PARGS.nas_check_on) begin
247 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 6, 58, value);
248 tid = 6;
249 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
250 end
251`endif
252
253`endif
254
255`endif
256
257 end
258 endtask
259
260
261 task slam_TsbSearchMode_core0_thread7;
262 input [63:0] value;
263 reg [5:0] tid;
264 integer junk;
265
266 begin
267`ifdef AXIS_EMUL_COSIM
268//Do Nothing
269`else
270`ifdef GATESIM
271//Do Nothing
272`else
273`ifdef CORE_0
274 @(posedge `SPC0.l2clk);
275 force `SPC0.mmu.asi.hwtw_config_7 = value;
276 @(posedge `SPC0.l2clk);
277 release `SPC0.mmu.asi.hwtw_config_7;
278 if (`PARGS.nas_check_on) begin
279 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 0, 7, 58, value);
280 tid = 7;
281 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
282 end
283`endif
284
285`endif
286
287`endif
288
289 end
290 endtask
291
292
293 task slam_TsbSearchMode_core1_thread0;
294 input [63:0] value;
295 reg [5:0] tid;
296 integer junk;
297
298 begin
299`ifdef AXIS_EMUL_COSIM
300//Do Nothing
301`else
302`ifdef GATESIM
303//Do Nothing
304`else
305`ifdef CORE_1
306 @(posedge `SPC1.l2clk);
307 force `SPC1.mmu.asi.hwtw_config_0 = value;
308 @(posedge `SPC1.l2clk);
309 release `SPC1.mmu.asi.hwtw_config_0;
310 if (`PARGS.nas_check_on) begin
311 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 0, 58, value);
312 tid = 0;
313 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
314 end
315`endif
316
317`endif
318
319`endif
320
321 end
322 endtask
323
324
325 task slam_TsbSearchMode_core1_thread1;
326 input [63:0] value;
327 reg [5:0] tid;
328 integer junk;
329
330 begin
331`ifdef AXIS_EMUL_COSIM
332//Do Nothing
333`else
334`ifdef GATESIM
335//Do Nothing
336`else
337`ifdef CORE_1
338 @(posedge `SPC1.l2clk);
339 force `SPC1.mmu.asi.hwtw_config_1 = value;
340 @(posedge `SPC1.l2clk);
341 release `SPC1.mmu.asi.hwtw_config_1;
342 if (`PARGS.nas_check_on) begin
343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 1, 58, value);
344 tid = 1;
345 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
346 end
347`endif
348
349`endif
350
351`endif
352
353 end
354 endtask
355
356
357 task slam_TsbSearchMode_core1_thread2;
358 input [63:0] value;
359 reg [5:0] tid;
360 integer junk;
361
362 begin
363`ifdef AXIS_EMUL_COSIM
364//Do Nothing
365`else
366`ifdef GATESIM
367//Do Nothing
368`else
369`ifdef CORE_1
370 @(posedge `SPC1.l2clk);
371 force `SPC1.mmu.asi.hwtw_config_2 = value;
372 @(posedge `SPC1.l2clk);
373 release `SPC1.mmu.asi.hwtw_config_2;
374 if (`PARGS.nas_check_on) begin
375 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 2, 58, value);
376 tid = 2;
377 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
378 end
379`endif
380
381`endif
382
383`endif
384
385 end
386 endtask
387
388
389 task slam_TsbSearchMode_core1_thread3;
390 input [63:0] value;
391 reg [5:0] tid;
392 integer junk;
393
394 begin
395`ifdef AXIS_EMUL_COSIM
396//Do Nothing
397`else
398`ifdef GATESIM
399//Do Nothing
400`else
401`ifdef CORE_1
402 @(posedge `SPC1.l2clk);
403 force `SPC1.mmu.asi.hwtw_config_3 = value;
404 @(posedge `SPC1.l2clk);
405 release `SPC1.mmu.asi.hwtw_config_3;
406 if (`PARGS.nas_check_on) begin
407 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 3, 58, value);
408 tid = 3;
409 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
410 end
411`endif
412
413`endif
414
415`endif
416
417 end
418 endtask
419
420
421 task slam_TsbSearchMode_core1_thread4;
422 input [63:0] value;
423 reg [5:0] tid;
424 integer junk;
425
426 begin
427`ifdef AXIS_EMUL_COSIM
428//Do Nothing
429`else
430`ifdef GATESIM
431//Do Nothing
432`else
433`ifdef CORE_1
434 @(posedge `SPC1.l2clk);
435 force `SPC1.mmu.asi.hwtw_config_4 = value;
436 @(posedge `SPC1.l2clk);
437 release `SPC1.mmu.asi.hwtw_config_4;
438 if (`PARGS.nas_check_on) begin
439 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 4, 58, value);
440 tid = 4;
441 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
442 end
443`endif
444
445`endif
446
447`endif
448
449 end
450 endtask
451
452
453 task slam_TsbSearchMode_core1_thread5;
454 input [63:0] value;
455 reg [5:0] tid;
456 integer junk;
457
458 begin
459`ifdef AXIS_EMUL_COSIM
460//Do Nothing
461`else
462`ifdef GATESIM
463//Do Nothing
464`else
465`ifdef CORE_1
466 @(posedge `SPC1.l2clk);
467 force `SPC1.mmu.asi.hwtw_config_5 = value;
468 @(posedge `SPC1.l2clk);
469 release `SPC1.mmu.asi.hwtw_config_5;
470 if (`PARGS.nas_check_on) begin
471 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 5, 58, value);
472 tid = 5;
473 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
474 end
475`endif
476
477`endif
478
479`endif
480
481 end
482 endtask
483
484
485 task slam_TsbSearchMode_core1_thread6;
486 input [63:0] value;
487 reg [5:0] tid;
488 integer junk;
489
490 begin
491`ifdef AXIS_EMUL_COSIM
492//Do Nothing
493`else
494`ifdef GATESIM
495//Do Nothing
496`else
497`ifdef CORE_1
498 @(posedge `SPC1.l2clk);
499 force `SPC1.mmu.asi.hwtw_config_6 = value;
500 @(posedge `SPC1.l2clk);
501 release `SPC1.mmu.asi.hwtw_config_6;
502 if (`PARGS.nas_check_on) begin
503 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 6, 58, value);
504 tid = 6;
505 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
506 end
507`endif
508
509`endif
510
511`endif
512
513 end
514 endtask
515
516
517 task slam_TsbSearchMode_core1_thread7;
518 input [63:0] value;
519 reg [5:0] tid;
520 integer junk;
521
522 begin
523`ifdef AXIS_EMUL_COSIM
524//Do Nothing
525`else
526`ifdef GATESIM
527//Do Nothing
528`else
529`ifdef CORE_1
530 @(posedge `SPC1.l2clk);
531 force `SPC1.mmu.asi.hwtw_config_7 = value;
532 @(posedge `SPC1.l2clk);
533 release `SPC1.mmu.asi.hwtw_config_7;
534 if (`PARGS.nas_check_on) begin
535 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 1, 7, 58, value);
536 tid = 7;
537 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
538 end
539`endif
540
541`endif
542
543`endif
544
545 end
546 endtask
547
548
549 task slam_TsbSearchMode_core2_thread0;
550 input [63:0] value;
551 reg [5:0] tid;
552 integer junk;
553
554 begin
555`ifdef AXIS_EMUL_COSIM
556//Do Nothing
557`else
558`ifdef GATESIM
559//Do Nothing
560`else
561`ifdef CORE_2
562 @(posedge `SPC2.l2clk);
563 force `SPC2.mmu.asi.hwtw_config_0 = value;
564 @(posedge `SPC2.l2clk);
565 release `SPC2.mmu.asi.hwtw_config_0;
566 if (`PARGS.nas_check_on) begin
567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 0, 58, value);
568 tid = 0;
569 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
570 end
571`endif
572
573`endif
574
575`endif
576
577 end
578 endtask
579
580
581 task slam_TsbSearchMode_core2_thread1;
582 input [63:0] value;
583 reg [5:0] tid;
584 integer junk;
585
586 begin
587`ifdef AXIS_EMUL_COSIM
588//Do Nothing
589`else
590`ifdef GATESIM
591//Do Nothing
592`else
593`ifdef CORE_2
594 @(posedge `SPC2.l2clk);
595 force `SPC2.mmu.asi.hwtw_config_1 = value;
596 @(posedge `SPC2.l2clk);
597 release `SPC2.mmu.asi.hwtw_config_1;
598 if (`PARGS.nas_check_on) begin
599 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 1, 58, value);
600 tid = 1;
601 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
602 end
603`endif
604
605`endif
606
607`endif
608
609 end
610 endtask
611
612
613 task slam_TsbSearchMode_core2_thread2;
614 input [63:0] value;
615 reg [5:0] tid;
616 integer junk;
617
618 begin
619`ifdef AXIS_EMUL_COSIM
620//Do Nothing
621`else
622`ifdef GATESIM
623//Do Nothing
624`else
625`ifdef CORE_2
626 @(posedge `SPC2.l2clk);
627 force `SPC2.mmu.asi.hwtw_config_2 = value;
628 @(posedge `SPC2.l2clk);
629 release `SPC2.mmu.asi.hwtw_config_2;
630 if (`PARGS.nas_check_on) begin
631 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 2, 58, value);
632 tid = 2;
633 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
634 end
635`endif
636
637`endif
638
639`endif
640
641 end
642 endtask
643
644
645 task slam_TsbSearchMode_core2_thread3;
646 input [63:0] value;
647 reg [5:0] tid;
648 integer junk;
649
650 begin
651`ifdef AXIS_EMUL_COSIM
652//Do Nothing
653`else
654`ifdef GATESIM
655//Do Nothing
656`else
657`ifdef CORE_2
658 @(posedge `SPC2.l2clk);
659 force `SPC2.mmu.asi.hwtw_config_3 = value;
660 @(posedge `SPC2.l2clk);
661 release `SPC2.mmu.asi.hwtw_config_3;
662 if (`PARGS.nas_check_on) begin
663 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 3, 58, value);
664 tid = 3;
665 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
666 end
667`endif
668
669`endif
670
671`endif
672
673 end
674 endtask
675
676
677 task slam_TsbSearchMode_core2_thread4;
678 input [63:0] value;
679 reg [5:0] tid;
680 integer junk;
681
682 begin
683`ifdef AXIS_EMUL_COSIM
684//Do Nothing
685`else
686`ifdef GATESIM
687//Do Nothing
688`else
689`ifdef CORE_2
690 @(posedge `SPC2.l2clk);
691 force `SPC2.mmu.asi.hwtw_config_4 = value;
692 @(posedge `SPC2.l2clk);
693 release `SPC2.mmu.asi.hwtw_config_4;
694 if (`PARGS.nas_check_on) begin
695 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 4, 58, value);
696 tid = 4;
697 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
698 end
699`endif
700
701`endif
702
703`endif
704
705 end
706 endtask
707
708
709 task slam_TsbSearchMode_core2_thread5;
710 input [63:0] value;
711 reg [5:0] tid;
712 integer junk;
713
714 begin
715`ifdef AXIS_EMUL_COSIM
716//Do Nothing
717`else
718`ifdef GATESIM
719//Do Nothing
720`else
721`ifdef CORE_2
722 @(posedge `SPC2.l2clk);
723 force `SPC2.mmu.asi.hwtw_config_5 = value;
724 @(posedge `SPC2.l2clk);
725 release `SPC2.mmu.asi.hwtw_config_5;
726 if (`PARGS.nas_check_on) begin
727 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 5, 58, value);
728 tid = 5;
729 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
730 end
731`endif
732
733`endif
734
735`endif
736
737 end
738 endtask
739
740
741 task slam_TsbSearchMode_core2_thread6;
742 input [63:0] value;
743 reg [5:0] tid;
744 integer junk;
745
746 begin
747`ifdef AXIS_EMUL_COSIM
748//Do Nothing
749`else
750`ifdef GATESIM
751//Do Nothing
752`else
753`ifdef CORE_2
754 @(posedge `SPC2.l2clk);
755 force `SPC2.mmu.asi.hwtw_config_6 = value;
756 @(posedge `SPC2.l2clk);
757 release `SPC2.mmu.asi.hwtw_config_6;
758 if (`PARGS.nas_check_on) begin
759 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 6, 58, value);
760 tid = 6;
761 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
762 end
763`endif
764
765`endif
766
767`endif
768
769 end
770 endtask
771
772
773 task slam_TsbSearchMode_core2_thread7;
774 input [63:0] value;
775 reg [5:0] tid;
776 integer junk;
777
778 begin
779`ifdef AXIS_EMUL_COSIM
780//Do Nothing
781`else
782`ifdef GATESIM
783//Do Nothing
784`else
785`ifdef CORE_2
786 @(posedge `SPC2.l2clk);
787 force `SPC2.mmu.asi.hwtw_config_7 = value;
788 @(posedge `SPC2.l2clk);
789 release `SPC2.mmu.asi.hwtw_config_7;
790 if (`PARGS.nas_check_on) begin
791 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 2, 7, 58, value);
792 tid = 7;
793 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
794 end
795`endif
796
797`endif
798
799`endif
800
801 end
802 endtask
803
804
805 task slam_TsbSearchMode_core3_thread0;
806 input [63:0] value;
807 reg [5:0] tid;
808 integer junk;
809
810 begin
811`ifdef AXIS_EMUL_COSIM
812//Do Nothing
813`else
814`ifdef GATESIM
815//Do Nothing
816`else
817`ifdef CORE_3
818 @(posedge `SPC3.l2clk);
819 force `SPC3.mmu.asi.hwtw_config_0 = value;
820 @(posedge `SPC3.l2clk);
821 release `SPC3.mmu.asi.hwtw_config_0;
822 if (`PARGS.nas_check_on) begin
823 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 0, 58, value);
824 tid = 0;
825 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
826 end
827`endif
828
829`endif
830
831`endif
832
833 end
834 endtask
835
836
837 task slam_TsbSearchMode_core3_thread1;
838 input [63:0] value;
839 reg [5:0] tid;
840 integer junk;
841
842 begin
843`ifdef AXIS_EMUL_COSIM
844//Do Nothing
845`else
846`ifdef GATESIM
847//Do Nothing
848`else
849`ifdef CORE_3
850 @(posedge `SPC3.l2clk);
851 force `SPC3.mmu.asi.hwtw_config_1 = value;
852 @(posedge `SPC3.l2clk);
853 release `SPC3.mmu.asi.hwtw_config_1;
854 if (`PARGS.nas_check_on) begin
855 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 1, 58, value);
856 tid = 1;
857 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
858 end
859`endif
860
861`endif
862
863`endif
864
865 end
866 endtask
867
868
869 task slam_TsbSearchMode_core3_thread2;
870 input [63:0] value;
871 reg [5:0] tid;
872 integer junk;
873
874 begin
875`ifdef AXIS_EMUL_COSIM
876//Do Nothing
877`else
878`ifdef GATESIM
879//Do Nothing
880`else
881`ifdef CORE_3
882 @(posedge `SPC3.l2clk);
883 force `SPC3.mmu.asi.hwtw_config_2 = value;
884 @(posedge `SPC3.l2clk);
885 release `SPC3.mmu.asi.hwtw_config_2;
886 if (`PARGS.nas_check_on) begin
887 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 2, 58, value);
888 tid = 2;
889 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
890 end
891`endif
892
893`endif
894
895`endif
896
897 end
898 endtask
899
900
901 task slam_TsbSearchMode_core3_thread3;
902 input [63:0] value;
903 reg [5:0] tid;
904 integer junk;
905
906 begin
907`ifdef AXIS_EMUL_COSIM
908//Do Nothing
909`else
910`ifdef GATESIM
911//Do Nothing
912`else
913`ifdef CORE_3
914 @(posedge `SPC3.l2clk);
915 force `SPC3.mmu.asi.hwtw_config_3 = value;
916 @(posedge `SPC3.l2clk);
917 release `SPC3.mmu.asi.hwtw_config_3;
918 if (`PARGS.nas_check_on) begin
919 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 3, 58, value);
920 tid = 3;
921 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
922 end
923`endif
924
925`endif
926
927`endif
928
929 end
930 endtask
931
932
933 task slam_TsbSearchMode_core3_thread4;
934 input [63:0] value;
935 reg [5:0] tid;
936 integer junk;
937
938 begin
939`ifdef AXIS_EMUL_COSIM
940//Do Nothing
941`else
942`ifdef GATESIM
943//Do Nothing
944`else
945`ifdef CORE_3
946 @(posedge `SPC3.l2clk);
947 force `SPC3.mmu.asi.hwtw_config_4 = value;
948 @(posedge `SPC3.l2clk);
949 release `SPC3.mmu.asi.hwtw_config_4;
950 if (`PARGS.nas_check_on) begin
951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 4, 58, value);
952 tid = 4;
953 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
954 end
955`endif
956
957`endif
958
959`endif
960
961 end
962 endtask
963
964
965 task slam_TsbSearchMode_core3_thread5;
966 input [63:0] value;
967 reg [5:0] tid;
968 integer junk;
969
970 begin
971`ifdef AXIS_EMUL_COSIM
972//Do Nothing
973`else
974`ifdef GATESIM
975//Do Nothing
976`else
977`ifdef CORE_3
978 @(posedge `SPC3.l2clk);
979 force `SPC3.mmu.asi.hwtw_config_5 = value;
980 @(posedge `SPC3.l2clk);
981 release `SPC3.mmu.asi.hwtw_config_5;
982 if (`PARGS.nas_check_on) begin
983 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 5, 58, value);
984 tid = 5;
985 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
986 end
987`endif
988
989`endif
990
991`endif
992
993 end
994 endtask
995
996
997 task slam_TsbSearchMode_core3_thread6;
998 input [63:0] value;
999 reg [5:0] tid;
1000 integer junk;
1001
1002 begin
1003`ifdef AXIS_EMUL_COSIM
1004//Do Nothing
1005`else
1006`ifdef GATESIM
1007//Do Nothing
1008`else
1009`ifdef CORE_3
1010 @(posedge `SPC3.l2clk);
1011 force `SPC3.mmu.asi.hwtw_config_6 = value;
1012 @(posedge `SPC3.l2clk);
1013 release `SPC3.mmu.asi.hwtw_config_6;
1014 if (`PARGS.nas_check_on) begin
1015 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 6, 58, value);
1016 tid = 6;
1017 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1018 end
1019`endif
1020
1021`endif
1022
1023`endif
1024
1025 end
1026 endtask
1027
1028
1029 task slam_TsbSearchMode_core3_thread7;
1030 input [63:0] value;
1031 reg [5:0] tid;
1032 integer junk;
1033
1034 begin
1035`ifdef AXIS_EMUL_COSIM
1036//Do Nothing
1037`else
1038`ifdef GATESIM
1039//Do Nothing
1040`else
1041`ifdef CORE_3
1042 @(posedge `SPC3.l2clk);
1043 force `SPC3.mmu.asi.hwtw_config_7 = value;
1044 @(posedge `SPC3.l2clk);
1045 release `SPC3.mmu.asi.hwtw_config_7;
1046 if (`PARGS.nas_check_on) begin
1047 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 3, 7, 58, value);
1048 tid = 7;
1049 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1050 end
1051`endif
1052
1053`endif
1054
1055`endif
1056
1057 end
1058 endtask
1059
1060
1061 task slam_TsbSearchMode_core4_thread0;
1062 input [63:0] value;
1063 reg [5:0] tid;
1064 integer junk;
1065
1066 begin
1067`ifdef AXIS_EMUL_COSIM
1068//Do Nothing
1069`else
1070`ifdef GATESIM
1071//Do Nothing
1072`else
1073`ifdef CORE_4
1074 @(posedge `SPC4.l2clk);
1075 force `SPC4.mmu.asi.hwtw_config_0 = value;
1076 @(posedge `SPC4.l2clk);
1077 release `SPC4.mmu.asi.hwtw_config_0;
1078 if (`PARGS.nas_check_on) begin
1079 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 0, 58, value);
1080 tid = 0;
1081 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1082 end
1083`endif
1084
1085`endif
1086
1087`endif
1088
1089 end
1090 endtask
1091
1092
1093 task slam_TsbSearchMode_core4_thread1;
1094 input [63:0] value;
1095 reg [5:0] tid;
1096 integer junk;
1097
1098 begin
1099`ifdef AXIS_EMUL_COSIM
1100//Do Nothing
1101`else
1102`ifdef GATESIM
1103//Do Nothing
1104`else
1105`ifdef CORE_4
1106 @(posedge `SPC4.l2clk);
1107 force `SPC4.mmu.asi.hwtw_config_1 = value;
1108 @(posedge `SPC4.l2clk);
1109 release `SPC4.mmu.asi.hwtw_config_1;
1110 if (`PARGS.nas_check_on) begin
1111 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 1, 58, value);
1112 tid = 1;
1113 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1114 end
1115`endif
1116
1117`endif
1118
1119`endif
1120
1121 end
1122 endtask
1123
1124
1125 task slam_TsbSearchMode_core4_thread2;
1126 input [63:0] value;
1127 reg [5:0] tid;
1128 integer junk;
1129
1130 begin
1131`ifdef AXIS_EMUL_COSIM
1132//Do Nothing
1133`else
1134`ifdef GATESIM
1135//Do Nothing
1136`else
1137`ifdef CORE_4
1138 @(posedge `SPC4.l2clk);
1139 force `SPC4.mmu.asi.hwtw_config_2 = value;
1140 @(posedge `SPC4.l2clk);
1141 release `SPC4.mmu.asi.hwtw_config_2;
1142 if (`PARGS.nas_check_on) begin
1143 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 2, 58, value);
1144 tid = 2;
1145 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1146 end
1147`endif
1148
1149`endif
1150
1151`endif
1152
1153 end
1154 endtask
1155
1156
1157 task slam_TsbSearchMode_core4_thread3;
1158 input [63:0] value;
1159 reg [5:0] tid;
1160 integer junk;
1161
1162 begin
1163`ifdef AXIS_EMUL_COSIM
1164//Do Nothing
1165`else
1166`ifdef GATESIM
1167//Do Nothing
1168`else
1169`ifdef CORE_4
1170 @(posedge `SPC4.l2clk);
1171 force `SPC4.mmu.asi.hwtw_config_3 = value;
1172 @(posedge `SPC4.l2clk);
1173 release `SPC4.mmu.asi.hwtw_config_3;
1174 if (`PARGS.nas_check_on) begin
1175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 3, 58, value);
1176 tid = 3;
1177 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1178 end
1179`endif
1180
1181`endif
1182
1183`endif
1184
1185 end
1186 endtask
1187
1188
1189 task slam_TsbSearchMode_core4_thread4;
1190 input [63:0] value;
1191 reg [5:0] tid;
1192 integer junk;
1193
1194 begin
1195`ifdef AXIS_EMUL_COSIM
1196//Do Nothing
1197`else
1198`ifdef GATESIM
1199//Do Nothing
1200`else
1201`ifdef CORE_4
1202 @(posedge `SPC4.l2clk);
1203 force `SPC4.mmu.asi.hwtw_config_4 = value;
1204 @(posedge `SPC4.l2clk);
1205 release `SPC4.mmu.asi.hwtw_config_4;
1206 if (`PARGS.nas_check_on) begin
1207 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 4, 58, value);
1208 tid = 4;
1209 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1210 end
1211`endif
1212
1213`endif
1214
1215`endif
1216
1217 end
1218 endtask
1219
1220
1221 task slam_TsbSearchMode_core4_thread5;
1222 input [63:0] value;
1223 reg [5:0] tid;
1224 integer junk;
1225
1226 begin
1227`ifdef AXIS_EMUL_COSIM
1228//Do Nothing
1229`else
1230`ifdef GATESIM
1231//Do Nothing
1232`else
1233`ifdef CORE_4
1234 @(posedge `SPC4.l2clk);
1235 force `SPC4.mmu.asi.hwtw_config_5 = value;
1236 @(posedge `SPC4.l2clk);
1237 release `SPC4.mmu.asi.hwtw_config_5;
1238 if (`PARGS.nas_check_on) begin
1239 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 5, 58, value);
1240 tid = 5;
1241 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1242 end
1243`endif
1244
1245`endif
1246
1247`endif
1248
1249 end
1250 endtask
1251
1252
1253 task slam_TsbSearchMode_core4_thread6;
1254 input [63:0] value;
1255 reg [5:0] tid;
1256 integer junk;
1257
1258 begin
1259`ifdef AXIS_EMUL_COSIM
1260//Do Nothing
1261`else
1262`ifdef GATESIM
1263//Do Nothing
1264`else
1265`ifdef CORE_4
1266 @(posedge `SPC4.l2clk);
1267 force `SPC4.mmu.asi.hwtw_config_6 = value;
1268 @(posedge `SPC4.l2clk);
1269 release `SPC4.mmu.asi.hwtw_config_6;
1270 if (`PARGS.nas_check_on) begin
1271 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 6, 58, value);
1272 tid = 6;
1273 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1274 end
1275`endif
1276
1277`endif
1278
1279`endif
1280
1281 end
1282 endtask
1283
1284
1285 task slam_TsbSearchMode_core4_thread7;
1286 input [63:0] value;
1287 reg [5:0] tid;
1288 integer junk;
1289
1290 begin
1291`ifdef AXIS_EMUL_COSIM
1292//Do Nothing
1293`else
1294`ifdef GATESIM
1295//Do Nothing
1296`else
1297`ifdef CORE_4
1298 @(posedge `SPC4.l2clk);
1299 force `SPC4.mmu.asi.hwtw_config_7 = value;
1300 @(posedge `SPC4.l2clk);
1301 release `SPC4.mmu.asi.hwtw_config_7;
1302 if (`PARGS.nas_check_on) begin
1303 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 4, 7, 58, value);
1304 tid = 7;
1305 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1306 end
1307`endif
1308
1309`endif
1310
1311`endif
1312
1313 end
1314 endtask
1315
1316
1317 task slam_TsbSearchMode_core5_thread0;
1318 input [63:0] value;
1319 reg [5:0] tid;
1320 integer junk;
1321
1322 begin
1323`ifdef AXIS_EMUL_COSIM
1324//Do Nothing
1325`else
1326`ifdef GATESIM
1327//Do Nothing
1328`else
1329`ifdef CORE_5
1330 @(posedge `SPC5.l2clk);
1331 force `SPC5.mmu.asi.hwtw_config_0 = value;
1332 @(posedge `SPC5.l2clk);
1333 release `SPC5.mmu.asi.hwtw_config_0;
1334 if (`PARGS.nas_check_on) begin
1335 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 0, 58, value);
1336 tid = 0;
1337 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1338 end
1339`endif
1340
1341`endif
1342
1343`endif
1344
1345 end
1346 endtask
1347
1348
1349 task slam_TsbSearchMode_core5_thread1;
1350 input [63:0] value;
1351 reg [5:0] tid;
1352 integer junk;
1353
1354 begin
1355`ifdef AXIS_EMUL_COSIM
1356//Do Nothing
1357`else
1358`ifdef GATESIM
1359//Do Nothing
1360`else
1361`ifdef CORE_5
1362 @(posedge `SPC5.l2clk);
1363 force `SPC5.mmu.asi.hwtw_config_1 = value;
1364 @(posedge `SPC5.l2clk);
1365 release `SPC5.mmu.asi.hwtw_config_1;
1366 if (`PARGS.nas_check_on) begin
1367 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 1, 58, value);
1368 tid = 1;
1369 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1370 end
1371`endif
1372
1373`endif
1374
1375`endif
1376
1377 end
1378 endtask
1379
1380
1381 task slam_TsbSearchMode_core5_thread2;
1382 input [63:0] value;
1383 reg [5:0] tid;
1384 integer junk;
1385
1386 begin
1387`ifdef AXIS_EMUL_COSIM
1388//Do Nothing
1389`else
1390`ifdef GATESIM
1391//Do Nothing
1392`else
1393`ifdef CORE_5
1394 @(posedge `SPC5.l2clk);
1395 force `SPC5.mmu.asi.hwtw_config_2 = value;
1396 @(posedge `SPC5.l2clk);
1397 release `SPC5.mmu.asi.hwtw_config_2;
1398 if (`PARGS.nas_check_on) begin
1399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 2, 58, value);
1400 tid = 2;
1401 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1402 end
1403`endif
1404
1405`endif
1406
1407`endif
1408
1409 end
1410 endtask
1411
1412
1413 task slam_TsbSearchMode_core5_thread3;
1414 input [63:0] value;
1415 reg [5:0] tid;
1416 integer junk;
1417
1418 begin
1419`ifdef AXIS_EMUL_COSIM
1420//Do Nothing
1421`else
1422`ifdef GATESIM
1423//Do Nothing
1424`else
1425`ifdef CORE_5
1426 @(posedge `SPC5.l2clk);
1427 force `SPC5.mmu.asi.hwtw_config_3 = value;
1428 @(posedge `SPC5.l2clk);
1429 release `SPC5.mmu.asi.hwtw_config_3;
1430 if (`PARGS.nas_check_on) begin
1431 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 3, 58, value);
1432 tid = 3;
1433 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1434 end
1435`endif
1436
1437`endif
1438
1439`endif
1440
1441 end
1442 endtask
1443
1444
1445 task slam_TsbSearchMode_core5_thread4;
1446 input [63:0] value;
1447 reg [5:0] tid;
1448 integer junk;
1449
1450 begin
1451`ifdef AXIS_EMUL_COSIM
1452//Do Nothing
1453`else
1454`ifdef GATESIM
1455//Do Nothing
1456`else
1457`ifdef CORE_5
1458 @(posedge `SPC5.l2clk);
1459 force `SPC5.mmu.asi.hwtw_config_4 = value;
1460 @(posedge `SPC5.l2clk);
1461 release `SPC5.mmu.asi.hwtw_config_4;
1462 if (`PARGS.nas_check_on) begin
1463 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 4, 58, value);
1464 tid = 4;
1465 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1466 end
1467`endif
1468
1469`endif
1470
1471`endif
1472
1473 end
1474 endtask
1475
1476
1477 task slam_TsbSearchMode_core5_thread5;
1478 input [63:0] value;
1479 reg [5:0] tid;
1480 integer junk;
1481
1482 begin
1483`ifdef AXIS_EMUL_COSIM
1484//Do Nothing
1485`else
1486`ifdef GATESIM
1487//Do Nothing
1488`else
1489`ifdef CORE_5
1490 @(posedge `SPC5.l2clk);
1491 force `SPC5.mmu.asi.hwtw_config_5 = value;
1492 @(posedge `SPC5.l2clk);
1493 release `SPC5.mmu.asi.hwtw_config_5;
1494 if (`PARGS.nas_check_on) begin
1495 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 5, 58, value);
1496 tid = 5;
1497 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1498 end
1499`endif
1500
1501`endif
1502
1503`endif
1504
1505 end
1506 endtask
1507
1508
1509 task slam_TsbSearchMode_core5_thread6;
1510 input [63:0] value;
1511 reg [5:0] tid;
1512 integer junk;
1513
1514 begin
1515`ifdef AXIS_EMUL_COSIM
1516//Do Nothing
1517`else
1518`ifdef GATESIM
1519//Do Nothing
1520`else
1521`ifdef CORE_5
1522 @(posedge `SPC5.l2clk);
1523 force `SPC5.mmu.asi.hwtw_config_6 = value;
1524 @(posedge `SPC5.l2clk);
1525 release `SPC5.mmu.asi.hwtw_config_6;
1526 if (`PARGS.nas_check_on) begin
1527 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 6, 58, value);
1528 tid = 6;
1529 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1530 end
1531`endif
1532
1533`endif
1534
1535`endif
1536
1537 end
1538 endtask
1539
1540
1541 task slam_TsbSearchMode_core5_thread7;
1542 input [63:0] value;
1543 reg [5:0] tid;
1544 integer junk;
1545
1546 begin
1547`ifdef AXIS_EMUL_COSIM
1548//Do Nothing
1549`else
1550`ifdef GATESIM
1551//Do Nothing
1552`else
1553`ifdef CORE_5
1554 @(posedge `SPC5.l2clk);
1555 force `SPC5.mmu.asi.hwtw_config_7 = value;
1556 @(posedge `SPC5.l2clk);
1557 release `SPC5.mmu.asi.hwtw_config_7;
1558 if (`PARGS.nas_check_on) begin
1559 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 5, 7, 58, value);
1560 tid = 7;
1561 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1562 end
1563`endif
1564
1565`endif
1566
1567`endif
1568
1569 end
1570 endtask
1571
1572
1573 task slam_TsbSearchMode_core6_thread0;
1574 input [63:0] value;
1575 reg [5:0] tid;
1576 integer junk;
1577
1578 begin
1579`ifdef AXIS_EMUL_COSIM
1580//Do Nothing
1581`else
1582`ifdef GATESIM
1583//Do Nothing
1584`else
1585`ifdef CORE_6
1586 @(posedge `SPC6.l2clk);
1587 force `SPC6.mmu.asi.hwtw_config_0 = value;
1588 @(posedge `SPC6.l2clk);
1589 release `SPC6.mmu.asi.hwtw_config_0;
1590 if (`PARGS.nas_check_on) begin
1591 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 0, 58, value);
1592 tid = 0;
1593 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1594 end
1595`endif
1596
1597`endif
1598
1599`endif
1600
1601 end
1602 endtask
1603
1604
1605 task slam_TsbSearchMode_core6_thread1;
1606 input [63:0] value;
1607 reg [5:0] tid;
1608 integer junk;
1609
1610 begin
1611`ifdef AXIS_EMUL_COSIM
1612//Do Nothing
1613`else
1614`ifdef GATESIM
1615//Do Nothing
1616`else
1617`ifdef CORE_6
1618 @(posedge `SPC6.l2clk);
1619 force `SPC6.mmu.asi.hwtw_config_1 = value;
1620 @(posedge `SPC6.l2clk);
1621 release `SPC6.mmu.asi.hwtw_config_1;
1622 if (`PARGS.nas_check_on) begin
1623 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 1, 58, value);
1624 tid = 1;
1625 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1626 end
1627`endif
1628
1629`endif
1630
1631`endif
1632
1633 end
1634 endtask
1635
1636
1637 task slam_TsbSearchMode_core6_thread2;
1638 input [63:0] value;
1639 reg [5:0] tid;
1640 integer junk;
1641
1642 begin
1643`ifdef AXIS_EMUL_COSIM
1644//Do Nothing
1645`else
1646`ifdef GATESIM
1647//Do Nothing
1648`else
1649`ifdef CORE_6
1650 @(posedge `SPC6.l2clk);
1651 force `SPC6.mmu.asi.hwtw_config_2 = value;
1652 @(posedge `SPC6.l2clk);
1653 release `SPC6.mmu.asi.hwtw_config_2;
1654 if (`PARGS.nas_check_on) begin
1655 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 2, 58, value);
1656 tid = 2;
1657 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1658 end
1659`endif
1660
1661`endif
1662
1663`endif
1664
1665 end
1666 endtask
1667
1668
1669 task slam_TsbSearchMode_core6_thread3;
1670 input [63:0] value;
1671 reg [5:0] tid;
1672 integer junk;
1673
1674 begin
1675`ifdef AXIS_EMUL_COSIM
1676//Do Nothing
1677`else
1678`ifdef GATESIM
1679//Do Nothing
1680`else
1681`ifdef CORE_6
1682 @(posedge `SPC6.l2clk);
1683 force `SPC6.mmu.asi.hwtw_config_3 = value;
1684 @(posedge `SPC6.l2clk);
1685 release `SPC6.mmu.asi.hwtw_config_3;
1686 if (`PARGS.nas_check_on) begin
1687 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 3, 58, value);
1688 tid = 3;
1689 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1690 end
1691`endif
1692
1693`endif
1694
1695`endif
1696
1697 end
1698 endtask
1699
1700
1701 task slam_TsbSearchMode_core6_thread4;
1702 input [63:0] value;
1703 reg [5:0] tid;
1704 integer junk;
1705
1706 begin
1707`ifdef AXIS_EMUL_COSIM
1708//Do Nothing
1709`else
1710`ifdef GATESIM
1711//Do Nothing
1712`else
1713`ifdef CORE_6
1714 @(posedge `SPC6.l2clk);
1715 force `SPC6.mmu.asi.hwtw_config_4 = value;
1716 @(posedge `SPC6.l2clk);
1717 release `SPC6.mmu.asi.hwtw_config_4;
1718 if (`PARGS.nas_check_on) begin
1719 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 4, 58, value);
1720 tid = 4;
1721 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1722 end
1723`endif
1724
1725`endif
1726
1727`endif
1728
1729 end
1730 endtask
1731
1732
1733 task slam_TsbSearchMode_core6_thread5;
1734 input [63:0] value;
1735 reg [5:0] tid;
1736 integer junk;
1737
1738 begin
1739`ifdef AXIS_EMUL_COSIM
1740//Do Nothing
1741`else
1742`ifdef GATESIM
1743//Do Nothing
1744`else
1745`ifdef CORE_6
1746 @(posedge `SPC6.l2clk);
1747 force `SPC6.mmu.asi.hwtw_config_5 = value;
1748 @(posedge `SPC6.l2clk);
1749 release `SPC6.mmu.asi.hwtw_config_5;
1750 if (`PARGS.nas_check_on) begin
1751 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 5, 58, value);
1752 tid = 5;
1753 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1754 end
1755`endif
1756
1757`endif
1758
1759`endif
1760
1761 end
1762 endtask
1763
1764
1765 task slam_TsbSearchMode_core6_thread6;
1766 input [63:0] value;
1767 reg [5:0] tid;
1768 integer junk;
1769
1770 begin
1771`ifdef AXIS_EMUL_COSIM
1772//Do Nothing
1773`else
1774`ifdef GATESIM
1775//Do Nothing
1776`else
1777`ifdef CORE_6
1778 @(posedge `SPC6.l2clk);
1779 force `SPC6.mmu.asi.hwtw_config_6 = value;
1780 @(posedge `SPC6.l2clk);
1781 release `SPC6.mmu.asi.hwtw_config_6;
1782 if (`PARGS.nas_check_on) begin
1783 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 6, 58, value);
1784 tid = 6;
1785 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1786 end
1787`endif
1788
1789`endif
1790
1791`endif
1792
1793 end
1794 endtask
1795
1796
1797 task slam_TsbSearchMode_core6_thread7;
1798 input [63:0] value;
1799 reg [5:0] tid;
1800 integer junk;
1801
1802 begin
1803`ifdef AXIS_EMUL_COSIM
1804//Do Nothing
1805`else
1806`ifdef GATESIM
1807//Do Nothing
1808`else
1809`ifdef CORE_6
1810 @(posedge `SPC6.l2clk);
1811 force `SPC6.mmu.asi.hwtw_config_7 = value;
1812 @(posedge `SPC6.l2clk);
1813 release `SPC6.mmu.asi.hwtw_config_7;
1814 if (`PARGS.nas_check_on) begin
1815 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 6, 7, 58, value);
1816 tid = 7;
1817 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1818 end
1819`endif
1820
1821`endif
1822
1823`endif
1824
1825 end
1826 endtask
1827
1828
1829 task slam_TsbSearchMode_core7_thread0;
1830 input [63:0] value;
1831 reg [5:0] tid;
1832 integer junk;
1833
1834 begin
1835`ifdef AXIS_EMUL_COSIM
1836//Do Nothing
1837`else
1838`ifdef GATESIM
1839//Do Nothing
1840`else
1841`ifdef CORE_7
1842 @(posedge `SPC7.l2clk);
1843 force `SPC7.mmu.asi.hwtw_config_0 = value;
1844 @(posedge `SPC7.l2clk);
1845 release `SPC7.mmu.asi.hwtw_config_0;
1846 if (`PARGS.nas_check_on) begin
1847 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 0, 58, value);
1848 tid = 0;
1849 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1850 end
1851`endif
1852
1853`endif
1854
1855`endif
1856
1857 end
1858 endtask
1859
1860
1861 task slam_TsbSearchMode_core7_thread1;
1862 input [63:0] value;
1863 reg [5:0] tid;
1864 integer junk;
1865
1866 begin
1867`ifdef AXIS_EMUL_COSIM
1868//Do Nothing
1869`else
1870`ifdef GATESIM
1871//Do Nothing
1872`else
1873`ifdef CORE_7
1874 @(posedge `SPC7.l2clk);
1875 force `SPC7.mmu.asi.hwtw_config_1 = value;
1876 @(posedge `SPC7.l2clk);
1877 release `SPC7.mmu.asi.hwtw_config_1;
1878 if (`PARGS.nas_check_on) begin
1879 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 1, 58, value);
1880 tid = 1;
1881 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1882 end
1883`endif
1884
1885`endif
1886
1887`endif
1888
1889 end
1890 endtask
1891
1892
1893 task slam_TsbSearchMode_core7_thread2;
1894 input [63:0] value;
1895 reg [5:0] tid;
1896 integer junk;
1897
1898 begin
1899`ifdef AXIS_EMUL_COSIM
1900//Do Nothing
1901`else
1902`ifdef GATESIM
1903//Do Nothing
1904`else
1905`ifdef CORE_7
1906 @(posedge `SPC7.l2clk);
1907 force `SPC7.mmu.asi.hwtw_config_2 = value;
1908 @(posedge `SPC7.l2clk);
1909 release `SPC7.mmu.asi.hwtw_config_2;
1910 if (`PARGS.nas_check_on) begin
1911 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 2, 58, value);
1912 tid = 2;
1913 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1914 end
1915`endif
1916
1917`endif
1918
1919`endif
1920
1921 end
1922 endtask
1923
1924
1925 task slam_TsbSearchMode_core7_thread3;
1926 input [63:0] value;
1927 reg [5:0] tid;
1928 integer junk;
1929
1930 begin
1931`ifdef AXIS_EMUL_COSIM
1932//Do Nothing
1933`else
1934`ifdef GATESIM
1935//Do Nothing
1936`else
1937`ifdef CORE_7
1938 @(posedge `SPC7.l2clk);
1939 force `SPC7.mmu.asi.hwtw_config_3 = value;
1940 @(posedge `SPC7.l2clk);
1941 release `SPC7.mmu.asi.hwtw_config_3;
1942 if (`PARGS.nas_check_on) begin
1943 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 3, 58, value);
1944 tid = 3;
1945 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1946 end
1947`endif
1948
1949`endif
1950
1951`endif
1952
1953 end
1954 endtask
1955
1956
1957 task slam_TsbSearchMode_core7_thread4;
1958 input [63:0] value;
1959 reg [5:0] tid;
1960 integer junk;
1961
1962 begin
1963`ifdef AXIS_EMUL_COSIM
1964//Do Nothing
1965`else
1966`ifdef GATESIM
1967//Do Nothing
1968`else
1969`ifdef CORE_7
1970 @(posedge `SPC7.l2clk);
1971 force `SPC7.mmu.asi.hwtw_config_4 = value;
1972 @(posedge `SPC7.l2clk);
1973 release `SPC7.mmu.asi.hwtw_config_4;
1974 if (`PARGS.nas_check_on) begin
1975 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 4, 58, value);
1976 tid = 4;
1977 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
1978 end
1979`endif
1980
1981`endif
1982
1983`endif
1984
1985 end
1986 endtask
1987
1988
1989 task slam_TsbSearchMode_core7_thread5;
1990 input [63:0] value;
1991 reg [5:0] tid;
1992 integer junk;
1993
1994 begin
1995`ifdef AXIS_EMUL_COSIM
1996//Do Nothing
1997`else
1998`ifdef GATESIM
1999//Do Nothing
2000`else
2001`ifdef CORE_7
2002 @(posedge `SPC7.l2clk);
2003 force `SPC7.mmu.asi.hwtw_config_5 = value;
2004 @(posedge `SPC7.l2clk);
2005 release `SPC7.mmu.asi.hwtw_config_5;
2006 if (`PARGS.nas_check_on) begin
2007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 5, 58, value);
2008 tid = 5;
2009 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
2010 end
2011`endif
2012
2013`endif
2014
2015`endif
2016
2017 end
2018 endtask
2019
2020
2021 task slam_TsbSearchMode_core7_thread6;
2022 input [63:0] value;
2023 reg [5:0] tid;
2024 integer junk;
2025
2026 begin
2027`ifdef AXIS_EMUL_COSIM
2028//Do Nothing
2029`else
2030`ifdef GATESIM
2031//Do Nothing
2032`else
2033`ifdef CORE_7
2034 @(posedge `SPC7.l2clk);
2035 force `SPC7.mmu.asi.hwtw_config_6 = value;
2036 @(posedge `SPC7.l2clk);
2037 release `SPC7.mmu.asi.hwtw_config_6;
2038 if (`PARGS.nas_check_on) begin
2039 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 6, 58, value);
2040 tid = 6;
2041 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
2042 end
2043`endif
2044
2045`endif
2046
2047`endif
2048
2049 end
2050 endtask
2051
2052
2053 task slam_TsbSearchMode_core7_thread7;
2054 input [63:0] value;
2055 reg [5:0] tid;
2056 integer junk;
2057
2058 begin
2059`ifdef AXIS_EMUL_COSIM
2060//Do Nothing
2061`else
2062`ifdef GATESIM
2063//Do Nothing
2064`else
2065`ifdef CORE_7
2066 @(posedge `SPC7.l2clk);
2067 force `SPC7.mmu.asi.hwtw_config_7 = value;
2068 @(posedge `SPC7.l2clk);
2069 release `SPC7.mmu.asi.hwtw_config_7;
2070 if (`PARGS.nas_check_on) begin
2071 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x0 val=0x%h", 7, 7, 58, value);
2072 tid = 7;
2073 junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h58, 64'h40, value);
2074 end
2075`endif
2076
2077`endif
2078
2079`endif
2080
2081 end
2082 endtask
2083
2084
2085 task slam_MraRow0_core0_thread0;
2086 input [127:0] value;
2087 reg [5:0] tid;
2088 integer junk;
2089
2090 begin
2091`ifdef AXIS_EMUL_COSIM
2092//Do Nothing
2093`else
2094`ifdef GATESIM
2095//Do Nothing
2096`else
2097`ifdef CORE_0
2098 value[82] = ^value[40:0];
2099 value[83] = ^value[81:41];
2100 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
2101 `SPC0.mmu.mra0.array.mem[0] <= value;
2102`endif
2103
2104`endif
2105
2106`endif
2107
2108 end
2109 endtask
2110
2111
2112 task slam_MraRow0_core0_thread1;
2113 input [127:0] value;
2114 reg [5:0] tid;
2115 integer junk;
2116
2117 begin
2118`ifdef AXIS_EMUL_COSIM
2119//Do Nothing
2120`else
2121`ifdef GATESIM
2122//Do Nothing
2123`else
2124`ifdef CORE_0
2125 value[82] = ^value[40:0];
2126 value[83] = ^value[81:41];
2127 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
2128 `SPC0.mmu.mra0.array.mem[8] <= value;
2129`endif
2130
2131`endif
2132
2133`endif
2134
2135 end
2136 endtask
2137
2138
2139 task slam_MraRow0_core0_thread2;
2140 input [127:0] value;
2141 reg [5:0] tid;
2142 integer junk;
2143
2144 begin
2145`ifdef AXIS_EMUL_COSIM
2146//Do Nothing
2147`else
2148`ifdef GATESIM
2149//Do Nothing
2150`else
2151`ifdef CORE_0
2152 value[82] = ^value[40:0];
2153 value[83] = ^value[81:41];
2154 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
2155 `SPC0.mmu.mra0.array.mem[16] <= value;
2156`endif
2157
2158`endif
2159
2160`endif
2161
2162 end
2163 endtask
2164
2165
2166 task slam_MraRow0_core0_thread3;
2167 input [127:0] value;
2168 reg [5:0] tid;
2169 integer junk;
2170
2171 begin
2172`ifdef AXIS_EMUL_COSIM
2173//Do Nothing
2174`else
2175`ifdef GATESIM
2176//Do Nothing
2177`else
2178`ifdef CORE_0
2179 value[82] = ^value[40:0];
2180 value[83] = ^value[81:41];
2181 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
2182 `SPC0.mmu.mra0.array.mem[24] <= value;
2183`endif
2184
2185`endif
2186
2187`endif
2188
2189 end
2190 endtask
2191
2192
2193 task slam_MraRow0_core0_thread4;
2194 input [127:0] value;
2195 reg [5:0] tid;
2196 integer junk;
2197
2198 begin
2199`ifdef AXIS_EMUL_COSIM
2200//Do Nothing
2201`else
2202`ifdef GATESIM
2203//Do Nothing
2204`else
2205`ifdef CORE_0
2206 value[82] = ^value[40:0];
2207 value[83] = ^value[81:41];
2208 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
2209 `SPC0.mmu.mra1.array.mem[0] <= value;
2210`endif
2211
2212`endif
2213
2214`endif
2215
2216 end
2217 endtask
2218
2219
2220 task slam_MraRow0_core0_thread5;
2221 input [127:0] value;
2222 reg [5:0] tid;
2223 integer junk;
2224
2225 begin
2226`ifdef AXIS_EMUL_COSIM
2227//Do Nothing
2228`else
2229`ifdef GATESIM
2230//Do Nothing
2231`else
2232`ifdef CORE_0
2233 value[82] = ^value[40:0];
2234 value[83] = ^value[81:41];
2235 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
2236 `SPC0.mmu.mra1.array.mem[8] <= value;
2237`endif
2238
2239`endif
2240
2241`endif
2242
2243 end
2244 endtask
2245
2246
2247 task slam_MraRow0_core0_thread6;
2248 input [127:0] value;
2249 reg [5:0] tid;
2250 integer junk;
2251
2252 begin
2253`ifdef AXIS_EMUL_COSIM
2254//Do Nothing
2255`else
2256`ifdef GATESIM
2257//Do Nothing
2258`else
2259`ifdef CORE_0
2260 value[82] = ^value[40:0];
2261 value[83] = ^value[81:41];
2262 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
2263 `SPC0.mmu.mra1.array.mem[16] <= value;
2264`endif
2265
2266`endif
2267
2268`endif
2269
2270 end
2271 endtask
2272
2273
2274 task slam_MraRow0_core0_thread7;
2275 input [127:0] value;
2276 reg [5:0] tid;
2277 integer junk;
2278
2279 begin
2280`ifdef AXIS_EMUL_COSIM
2281//Do Nothing
2282`else
2283`ifdef GATESIM
2284//Do Nothing
2285`else
2286`ifdef CORE_0
2287 value[82] = ^value[40:0];
2288 value[83] = ^value[81:41];
2289 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
2290 `SPC0.mmu.mra1.array.mem[24] <= value;
2291`endif
2292
2293`endif
2294
2295`endif
2296
2297 end
2298 endtask
2299
2300
2301 task slam_MraRow0_core1_thread0;
2302 input [127:0] value;
2303 reg [5:0] tid;
2304 integer junk;
2305
2306 begin
2307`ifdef AXIS_EMUL_COSIM
2308//Do Nothing
2309`else
2310`ifdef GATESIM
2311//Do Nothing
2312`else
2313`ifdef CORE_1
2314 value[82] = ^value[40:0];
2315 value[83] = ^value[81:41];
2316 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
2317 `SPC1.mmu.mra0.array.mem[0] <= value;
2318`endif
2319
2320`endif
2321
2322`endif
2323
2324 end
2325 endtask
2326
2327
2328 task slam_MraRow0_core1_thread1;
2329 input [127:0] value;
2330 reg [5:0] tid;
2331 integer junk;
2332
2333 begin
2334`ifdef AXIS_EMUL_COSIM
2335//Do Nothing
2336`else
2337`ifdef GATESIM
2338//Do Nothing
2339`else
2340`ifdef CORE_1
2341 value[82] = ^value[40:0];
2342 value[83] = ^value[81:41];
2343 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
2344 `SPC1.mmu.mra0.array.mem[8] <= value;
2345`endif
2346
2347`endif
2348
2349`endif
2350
2351 end
2352 endtask
2353
2354
2355 task slam_MraRow0_core1_thread2;
2356 input [127:0] value;
2357 reg [5:0] tid;
2358 integer junk;
2359
2360 begin
2361`ifdef AXIS_EMUL_COSIM
2362//Do Nothing
2363`else
2364`ifdef GATESIM
2365//Do Nothing
2366`else
2367`ifdef CORE_1
2368 value[82] = ^value[40:0];
2369 value[83] = ^value[81:41];
2370 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
2371 `SPC1.mmu.mra0.array.mem[16] <= value;
2372`endif
2373
2374`endif
2375
2376`endif
2377
2378 end
2379 endtask
2380
2381
2382 task slam_MraRow0_core1_thread3;
2383 input [127:0] value;
2384 reg [5:0] tid;
2385 integer junk;
2386
2387 begin
2388`ifdef AXIS_EMUL_COSIM
2389//Do Nothing
2390`else
2391`ifdef GATESIM
2392//Do Nothing
2393`else
2394`ifdef CORE_1
2395 value[82] = ^value[40:0];
2396 value[83] = ^value[81:41];
2397 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
2398 `SPC1.mmu.mra0.array.mem[24] <= value;
2399`endif
2400
2401`endif
2402
2403`endif
2404
2405 end
2406 endtask
2407
2408
2409 task slam_MraRow0_core1_thread4;
2410 input [127:0] value;
2411 reg [5:0] tid;
2412 integer junk;
2413
2414 begin
2415`ifdef AXIS_EMUL_COSIM
2416//Do Nothing
2417`else
2418`ifdef GATESIM
2419//Do Nothing
2420`else
2421`ifdef CORE_1
2422 value[82] = ^value[40:0];
2423 value[83] = ^value[81:41];
2424 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
2425 `SPC1.mmu.mra1.array.mem[0] <= value;
2426`endif
2427
2428`endif
2429
2430`endif
2431
2432 end
2433 endtask
2434
2435
2436 task slam_MraRow0_core1_thread5;
2437 input [127:0] value;
2438 reg [5:0] tid;
2439 integer junk;
2440
2441 begin
2442`ifdef AXIS_EMUL_COSIM
2443//Do Nothing
2444`else
2445`ifdef GATESIM
2446//Do Nothing
2447`else
2448`ifdef CORE_1
2449 value[82] = ^value[40:0];
2450 value[83] = ^value[81:41];
2451 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
2452 `SPC1.mmu.mra1.array.mem[8] <= value;
2453`endif
2454
2455`endif
2456
2457`endif
2458
2459 end
2460 endtask
2461
2462
2463 task slam_MraRow0_core1_thread6;
2464 input [127:0] value;
2465 reg [5:0] tid;
2466 integer junk;
2467
2468 begin
2469`ifdef AXIS_EMUL_COSIM
2470//Do Nothing
2471`else
2472`ifdef GATESIM
2473//Do Nothing
2474`else
2475`ifdef CORE_1
2476 value[82] = ^value[40:0];
2477 value[83] = ^value[81:41];
2478 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
2479 `SPC1.mmu.mra1.array.mem[16] <= value;
2480`endif
2481
2482`endif
2483
2484`endif
2485
2486 end
2487 endtask
2488
2489
2490 task slam_MraRow0_core1_thread7;
2491 input [127:0] value;
2492 reg [5:0] tid;
2493 integer junk;
2494
2495 begin
2496`ifdef AXIS_EMUL_COSIM
2497//Do Nothing
2498`else
2499`ifdef GATESIM
2500//Do Nothing
2501`else
2502`ifdef CORE_1
2503 value[82] = ^value[40:0];
2504 value[83] = ^value[81:41];
2505 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
2506 `SPC1.mmu.mra1.array.mem[24] <= value;
2507`endif
2508
2509`endif
2510
2511`endif
2512
2513 end
2514 endtask
2515
2516
2517 task slam_MraRow0_core2_thread0;
2518 input [127:0] value;
2519 reg [5:0] tid;
2520 integer junk;
2521
2522 begin
2523`ifdef AXIS_EMUL_COSIM
2524//Do Nothing
2525`else
2526`ifdef GATESIM
2527//Do Nothing
2528`else
2529`ifdef CORE_2
2530 value[82] = ^value[40:0];
2531 value[83] = ^value[81:41];
2532 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
2533 `SPC2.mmu.mra0.array.mem[0] <= value;
2534`endif
2535
2536`endif
2537
2538`endif
2539
2540 end
2541 endtask
2542
2543
2544 task slam_MraRow0_core2_thread1;
2545 input [127:0] value;
2546 reg [5:0] tid;
2547 integer junk;
2548
2549 begin
2550`ifdef AXIS_EMUL_COSIM
2551//Do Nothing
2552`else
2553`ifdef GATESIM
2554//Do Nothing
2555`else
2556`ifdef CORE_2
2557 value[82] = ^value[40:0];
2558 value[83] = ^value[81:41];
2559 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
2560 `SPC2.mmu.mra0.array.mem[8] <= value;
2561`endif
2562
2563`endif
2564
2565`endif
2566
2567 end
2568 endtask
2569
2570
2571 task slam_MraRow0_core2_thread2;
2572 input [127:0] value;
2573 reg [5:0] tid;
2574 integer junk;
2575
2576 begin
2577`ifdef AXIS_EMUL_COSIM
2578//Do Nothing
2579`else
2580`ifdef GATESIM
2581//Do Nothing
2582`else
2583`ifdef CORE_2
2584 value[82] = ^value[40:0];
2585 value[83] = ^value[81:41];
2586 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
2587 `SPC2.mmu.mra0.array.mem[16] <= value;
2588`endif
2589
2590`endif
2591
2592`endif
2593
2594 end
2595 endtask
2596
2597
2598 task slam_MraRow0_core2_thread3;
2599 input [127:0] value;
2600 reg [5:0] tid;
2601 integer junk;
2602
2603 begin
2604`ifdef AXIS_EMUL_COSIM
2605//Do Nothing
2606`else
2607`ifdef GATESIM
2608//Do Nothing
2609`else
2610`ifdef CORE_2
2611 value[82] = ^value[40:0];
2612 value[83] = ^value[81:41];
2613 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
2614 `SPC2.mmu.mra0.array.mem[24] <= value;
2615`endif
2616
2617`endif
2618
2619`endif
2620
2621 end
2622 endtask
2623
2624
2625 task slam_MraRow0_core2_thread4;
2626 input [127:0] value;
2627 reg [5:0] tid;
2628 integer junk;
2629
2630 begin
2631`ifdef AXIS_EMUL_COSIM
2632//Do Nothing
2633`else
2634`ifdef GATESIM
2635//Do Nothing
2636`else
2637`ifdef CORE_2
2638 value[82] = ^value[40:0];
2639 value[83] = ^value[81:41];
2640 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
2641 `SPC2.mmu.mra1.array.mem[0] <= value;
2642`endif
2643
2644`endif
2645
2646`endif
2647
2648 end
2649 endtask
2650
2651
2652 task slam_MraRow0_core2_thread5;
2653 input [127:0] value;
2654 reg [5:0] tid;
2655 integer junk;
2656
2657 begin
2658`ifdef AXIS_EMUL_COSIM
2659//Do Nothing
2660`else
2661`ifdef GATESIM
2662//Do Nothing
2663`else
2664`ifdef CORE_2
2665 value[82] = ^value[40:0];
2666 value[83] = ^value[81:41];
2667 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
2668 `SPC2.mmu.mra1.array.mem[8] <= value;
2669`endif
2670
2671`endif
2672
2673`endif
2674
2675 end
2676 endtask
2677
2678
2679 task slam_MraRow0_core2_thread6;
2680 input [127:0] value;
2681 reg [5:0] tid;
2682 integer junk;
2683
2684 begin
2685`ifdef AXIS_EMUL_COSIM
2686//Do Nothing
2687`else
2688`ifdef GATESIM
2689//Do Nothing
2690`else
2691`ifdef CORE_2
2692 value[82] = ^value[40:0];
2693 value[83] = ^value[81:41];
2694 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
2695 `SPC2.mmu.mra1.array.mem[16] <= value;
2696`endif
2697
2698`endif
2699
2700`endif
2701
2702 end
2703 endtask
2704
2705
2706 task slam_MraRow0_core2_thread7;
2707 input [127:0] value;
2708 reg [5:0] tid;
2709 integer junk;
2710
2711 begin
2712`ifdef AXIS_EMUL_COSIM
2713//Do Nothing
2714`else
2715`ifdef GATESIM
2716//Do Nothing
2717`else
2718`ifdef CORE_2
2719 value[82] = ^value[40:0];
2720 value[83] = ^value[81:41];
2721 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
2722 `SPC2.mmu.mra1.array.mem[24] <= value;
2723`endif
2724
2725`endif
2726
2727`endif
2728
2729 end
2730 endtask
2731
2732
2733 task slam_MraRow0_core3_thread0;
2734 input [127:0] value;
2735 reg [5:0] tid;
2736 integer junk;
2737
2738 begin
2739`ifdef AXIS_EMUL_COSIM
2740//Do Nothing
2741`else
2742`ifdef GATESIM
2743//Do Nothing
2744`else
2745`ifdef CORE_3
2746 value[82] = ^value[40:0];
2747 value[83] = ^value[81:41];
2748 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
2749 `SPC3.mmu.mra0.array.mem[0] <= value;
2750`endif
2751
2752`endif
2753
2754`endif
2755
2756 end
2757 endtask
2758
2759
2760 task slam_MraRow0_core3_thread1;
2761 input [127:0] value;
2762 reg [5:0] tid;
2763 integer junk;
2764
2765 begin
2766`ifdef AXIS_EMUL_COSIM
2767//Do Nothing
2768`else
2769`ifdef GATESIM
2770//Do Nothing
2771`else
2772`ifdef CORE_3
2773 value[82] = ^value[40:0];
2774 value[83] = ^value[81:41];
2775 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
2776 `SPC3.mmu.mra0.array.mem[8] <= value;
2777`endif
2778
2779`endif
2780
2781`endif
2782
2783 end
2784 endtask
2785
2786
2787 task slam_MraRow0_core3_thread2;
2788 input [127:0] value;
2789 reg [5:0] tid;
2790 integer junk;
2791
2792 begin
2793`ifdef AXIS_EMUL_COSIM
2794//Do Nothing
2795`else
2796`ifdef GATESIM
2797//Do Nothing
2798`else
2799`ifdef CORE_3
2800 value[82] = ^value[40:0];
2801 value[83] = ^value[81:41];
2802 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
2803 `SPC3.mmu.mra0.array.mem[16] <= value;
2804`endif
2805
2806`endif
2807
2808`endif
2809
2810 end
2811 endtask
2812
2813
2814 task slam_MraRow0_core3_thread3;
2815 input [127:0] value;
2816 reg [5:0] tid;
2817 integer junk;
2818
2819 begin
2820`ifdef AXIS_EMUL_COSIM
2821//Do Nothing
2822`else
2823`ifdef GATESIM
2824//Do Nothing
2825`else
2826`ifdef CORE_3
2827 value[82] = ^value[40:0];
2828 value[83] = ^value[81:41];
2829 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
2830 `SPC3.mmu.mra0.array.mem[24] <= value;
2831`endif
2832
2833`endif
2834
2835`endif
2836
2837 end
2838 endtask
2839
2840
2841 task slam_MraRow0_core3_thread4;
2842 input [127:0] value;
2843 reg [5:0] tid;
2844 integer junk;
2845
2846 begin
2847`ifdef AXIS_EMUL_COSIM
2848//Do Nothing
2849`else
2850`ifdef GATESIM
2851//Do Nothing
2852`else
2853`ifdef CORE_3
2854 value[82] = ^value[40:0];
2855 value[83] = ^value[81:41];
2856 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
2857 `SPC3.mmu.mra1.array.mem[0] <= value;
2858`endif
2859
2860`endif
2861
2862`endif
2863
2864 end
2865 endtask
2866
2867
2868 task slam_MraRow0_core3_thread5;
2869 input [127:0] value;
2870 reg [5:0] tid;
2871 integer junk;
2872
2873 begin
2874`ifdef AXIS_EMUL_COSIM
2875//Do Nothing
2876`else
2877`ifdef GATESIM
2878//Do Nothing
2879`else
2880`ifdef CORE_3
2881 value[82] = ^value[40:0];
2882 value[83] = ^value[81:41];
2883 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
2884 `SPC3.mmu.mra1.array.mem[8] <= value;
2885`endif
2886
2887`endif
2888
2889`endif
2890
2891 end
2892 endtask
2893
2894
2895 task slam_MraRow0_core3_thread6;
2896 input [127:0] value;
2897 reg [5:0] tid;
2898 integer junk;
2899
2900 begin
2901`ifdef AXIS_EMUL_COSIM
2902//Do Nothing
2903`else
2904`ifdef GATESIM
2905//Do Nothing
2906`else
2907`ifdef CORE_3
2908 value[82] = ^value[40:0];
2909 value[83] = ^value[81:41];
2910 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
2911 `SPC3.mmu.mra1.array.mem[16] <= value;
2912`endif
2913
2914`endif
2915
2916`endif
2917
2918 end
2919 endtask
2920
2921
2922 task slam_MraRow0_core3_thread7;
2923 input [127:0] value;
2924 reg [5:0] tid;
2925 integer junk;
2926
2927 begin
2928`ifdef AXIS_EMUL_COSIM
2929//Do Nothing
2930`else
2931`ifdef GATESIM
2932//Do Nothing
2933`else
2934`ifdef CORE_3
2935 value[82] = ^value[40:0];
2936 value[83] = ^value[81:41];
2937 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
2938 `SPC3.mmu.mra1.array.mem[24] <= value;
2939`endif
2940
2941`endif
2942
2943`endif
2944
2945 end
2946 endtask
2947
2948
2949 task slam_MraRow0_core4_thread0;
2950 input [127:0] value;
2951 reg [5:0] tid;
2952 integer junk;
2953
2954 begin
2955`ifdef AXIS_EMUL_COSIM
2956//Do Nothing
2957`else
2958`ifdef GATESIM
2959//Do Nothing
2960`else
2961`ifdef CORE_4
2962 value[82] = ^value[40:0];
2963 value[83] = ^value[81:41];
2964 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
2965 `SPC4.mmu.mra0.array.mem[0] <= value;
2966`endif
2967
2968`endif
2969
2970`endif
2971
2972 end
2973 endtask
2974
2975
2976 task slam_MraRow0_core4_thread1;
2977 input [127:0] value;
2978 reg [5:0] tid;
2979 integer junk;
2980
2981 begin
2982`ifdef AXIS_EMUL_COSIM
2983//Do Nothing
2984`else
2985`ifdef GATESIM
2986//Do Nothing
2987`else
2988`ifdef CORE_4
2989 value[82] = ^value[40:0];
2990 value[83] = ^value[81:41];
2991 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
2992 `SPC4.mmu.mra0.array.mem[8] <= value;
2993`endif
2994
2995`endif
2996
2997`endif
2998
2999 end
3000 endtask
3001
3002
3003 task slam_MraRow0_core4_thread2;
3004 input [127:0] value;
3005 reg [5:0] tid;
3006 integer junk;
3007
3008 begin
3009`ifdef AXIS_EMUL_COSIM
3010//Do Nothing
3011`else
3012`ifdef GATESIM
3013//Do Nothing
3014`else
3015`ifdef CORE_4
3016 value[82] = ^value[40:0];
3017 value[83] = ^value[81:41];
3018 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
3019 `SPC4.mmu.mra0.array.mem[16] <= value;
3020`endif
3021
3022`endif
3023
3024`endif
3025
3026 end
3027 endtask
3028
3029
3030 task slam_MraRow0_core4_thread3;
3031 input [127:0] value;
3032 reg [5:0] tid;
3033 integer junk;
3034
3035 begin
3036`ifdef AXIS_EMUL_COSIM
3037//Do Nothing
3038`else
3039`ifdef GATESIM
3040//Do Nothing
3041`else
3042`ifdef CORE_4
3043 value[82] = ^value[40:0];
3044 value[83] = ^value[81:41];
3045 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
3046 `SPC4.mmu.mra0.array.mem[24] <= value;
3047`endif
3048
3049`endif
3050
3051`endif
3052
3053 end
3054 endtask
3055
3056
3057 task slam_MraRow0_core4_thread4;
3058 input [127:0] value;
3059 reg [5:0] tid;
3060 integer junk;
3061
3062 begin
3063`ifdef AXIS_EMUL_COSIM
3064//Do Nothing
3065`else
3066`ifdef GATESIM
3067//Do Nothing
3068`else
3069`ifdef CORE_4
3070 value[82] = ^value[40:0];
3071 value[83] = ^value[81:41];
3072 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
3073 `SPC4.mmu.mra1.array.mem[0] <= value;
3074`endif
3075
3076`endif
3077
3078`endif
3079
3080 end
3081 endtask
3082
3083
3084 task slam_MraRow0_core4_thread5;
3085 input [127:0] value;
3086 reg [5:0] tid;
3087 integer junk;
3088
3089 begin
3090`ifdef AXIS_EMUL_COSIM
3091//Do Nothing
3092`else
3093`ifdef GATESIM
3094//Do Nothing
3095`else
3096`ifdef CORE_4
3097 value[82] = ^value[40:0];
3098 value[83] = ^value[81:41];
3099 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
3100 `SPC4.mmu.mra1.array.mem[8] <= value;
3101`endif
3102
3103`endif
3104
3105`endif
3106
3107 end
3108 endtask
3109
3110
3111 task slam_MraRow0_core4_thread6;
3112 input [127:0] value;
3113 reg [5:0] tid;
3114 integer junk;
3115
3116 begin
3117`ifdef AXIS_EMUL_COSIM
3118//Do Nothing
3119`else
3120`ifdef GATESIM
3121//Do Nothing
3122`else
3123`ifdef CORE_4
3124 value[82] = ^value[40:0];
3125 value[83] = ^value[81:41];
3126 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
3127 `SPC4.mmu.mra1.array.mem[16] <= value;
3128`endif
3129
3130`endif
3131
3132`endif
3133
3134 end
3135 endtask
3136
3137
3138 task slam_MraRow0_core4_thread7;
3139 input [127:0] value;
3140 reg [5:0] tid;
3141 integer junk;
3142
3143 begin
3144`ifdef AXIS_EMUL_COSIM
3145//Do Nothing
3146`else
3147`ifdef GATESIM
3148//Do Nothing
3149`else
3150`ifdef CORE_4
3151 value[82] = ^value[40:0];
3152 value[83] = ^value[81:41];
3153 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
3154 `SPC4.mmu.mra1.array.mem[24] <= value;
3155`endif
3156
3157`endif
3158
3159`endif
3160
3161 end
3162 endtask
3163
3164
3165 task slam_MraRow0_core5_thread0;
3166 input [127:0] value;
3167 reg [5:0] tid;
3168 integer junk;
3169
3170 begin
3171`ifdef AXIS_EMUL_COSIM
3172//Do Nothing
3173`else
3174`ifdef GATESIM
3175//Do Nothing
3176`else
3177`ifdef CORE_5
3178 value[82] = ^value[40:0];
3179 value[83] = ^value[81:41];
3180 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
3181 `SPC5.mmu.mra0.array.mem[0] <= value;
3182`endif
3183
3184`endif
3185
3186`endif
3187
3188 end
3189 endtask
3190
3191
3192 task slam_MraRow0_core5_thread1;
3193 input [127:0] value;
3194 reg [5:0] tid;
3195 integer junk;
3196
3197 begin
3198`ifdef AXIS_EMUL_COSIM
3199//Do Nothing
3200`else
3201`ifdef GATESIM
3202//Do Nothing
3203`else
3204`ifdef CORE_5
3205 value[82] = ^value[40:0];
3206 value[83] = ^value[81:41];
3207 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
3208 `SPC5.mmu.mra0.array.mem[8] <= value;
3209`endif
3210
3211`endif
3212
3213`endif
3214
3215 end
3216 endtask
3217
3218
3219 task slam_MraRow0_core5_thread2;
3220 input [127:0] value;
3221 reg [5:0] tid;
3222 integer junk;
3223
3224 begin
3225`ifdef AXIS_EMUL_COSIM
3226//Do Nothing
3227`else
3228`ifdef GATESIM
3229//Do Nothing
3230`else
3231`ifdef CORE_5
3232 value[82] = ^value[40:0];
3233 value[83] = ^value[81:41];
3234 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
3235 `SPC5.mmu.mra0.array.mem[16] <= value;
3236`endif
3237
3238`endif
3239
3240`endif
3241
3242 end
3243 endtask
3244
3245
3246 task slam_MraRow0_core5_thread3;
3247 input [127:0] value;
3248 reg [5:0] tid;
3249 integer junk;
3250
3251 begin
3252`ifdef AXIS_EMUL_COSIM
3253//Do Nothing
3254`else
3255`ifdef GATESIM
3256//Do Nothing
3257`else
3258`ifdef CORE_5
3259 value[82] = ^value[40:0];
3260 value[83] = ^value[81:41];
3261 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
3262 `SPC5.mmu.mra0.array.mem[24] <= value;
3263`endif
3264
3265`endif
3266
3267`endif
3268
3269 end
3270 endtask
3271
3272
3273 task slam_MraRow0_core5_thread4;
3274 input [127:0] value;
3275 reg [5:0] tid;
3276 integer junk;
3277
3278 begin
3279`ifdef AXIS_EMUL_COSIM
3280//Do Nothing
3281`else
3282`ifdef GATESIM
3283//Do Nothing
3284`else
3285`ifdef CORE_5
3286 value[82] = ^value[40:0];
3287 value[83] = ^value[81:41];
3288 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
3289 `SPC5.mmu.mra1.array.mem[0] <= value;
3290`endif
3291
3292`endif
3293
3294`endif
3295
3296 end
3297 endtask
3298
3299
3300 task slam_MraRow0_core5_thread5;
3301 input [127:0] value;
3302 reg [5:0] tid;
3303 integer junk;
3304
3305 begin
3306`ifdef AXIS_EMUL_COSIM
3307//Do Nothing
3308`else
3309`ifdef GATESIM
3310//Do Nothing
3311`else
3312`ifdef CORE_5
3313 value[82] = ^value[40:0];
3314 value[83] = ^value[81:41];
3315 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
3316 `SPC5.mmu.mra1.array.mem[8] <= value;
3317`endif
3318
3319`endif
3320
3321`endif
3322
3323 end
3324 endtask
3325
3326
3327 task slam_MraRow0_core5_thread6;
3328 input [127:0] value;
3329 reg [5:0] tid;
3330 integer junk;
3331
3332 begin
3333`ifdef AXIS_EMUL_COSIM
3334//Do Nothing
3335`else
3336`ifdef GATESIM
3337//Do Nothing
3338`else
3339`ifdef CORE_5
3340 value[82] = ^value[40:0];
3341 value[83] = ^value[81:41];
3342 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
3343 `SPC5.mmu.mra1.array.mem[16] <= value;
3344`endif
3345
3346`endif
3347
3348`endif
3349
3350 end
3351 endtask
3352
3353
3354 task slam_MraRow0_core5_thread7;
3355 input [127:0] value;
3356 reg [5:0] tid;
3357 integer junk;
3358
3359 begin
3360`ifdef AXIS_EMUL_COSIM
3361//Do Nothing
3362`else
3363`ifdef GATESIM
3364//Do Nothing
3365`else
3366`ifdef CORE_5
3367 value[82] = ^value[40:0];
3368 value[83] = ^value[81:41];
3369 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
3370 `SPC5.mmu.mra1.array.mem[24] <= value;
3371`endif
3372
3373`endif
3374
3375`endif
3376
3377 end
3378 endtask
3379
3380
3381 task slam_MraRow0_core6_thread0;
3382 input [127:0] value;
3383 reg [5:0] tid;
3384 integer junk;
3385
3386 begin
3387`ifdef AXIS_EMUL_COSIM
3388//Do Nothing
3389`else
3390`ifdef GATESIM
3391//Do Nothing
3392`else
3393`ifdef CORE_6
3394 value[82] = ^value[40:0];
3395 value[83] = ^value[81:41];
3396 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
3397 `SPC6.mmu.mra0.array.mem[0] <= value;
3398`endif
3399
3400`endif
3401
3402`endif
3403
3404 end
3405 endtask
3406
3407
3408 task slam_MraRow0_core6_thread1;
3409 input [127:0] value;
3410 reg [5:0] tid;
3411 integer junk;
3412
3413 begin
3414`ifdef AXIS_EMUL_COSIM
3415//Do Nothing
3416`else
3417`ifdef GATESIM
3418//Do Nothing
3419`else
3420`ifdef CORE_6
3421 value[82] = ^value[40:0];
3422 value[83] = ^value[81:41];
3423 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
3424 `SPC6.mmu.mra0.array.mem[8] <= value;
3425`endif
3426
3427`endif
3428
3429`endif
3430
3431 end
3432 endtask
3433
3434
3435 task slam_MraRow0_core6_thread2;
3436 input [127:0] value;
3437 reg [5:0] tid;
3438 integer junk;
3439
3440 begin
3441`ifdef AXIS_EMUL_COSIM
3442//Do Nothing
3443`else
3444`ifdef GATESIM
3445//Do Nothing
3446`else
3447`ifdef CORE_6
3448 value[82] = ^value[40:0];
3449 value[83] = ^value[81:41];
3450 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
3451 `SPC6.mmu.mra0.array.mem[16] <= value;
3452`endif
3453
3454`endif
3455
3456`endif
3457
3458 end
3459 endtask
3460
3461
3462 task slam_MraRow0_core6_thread3;
3463 input [127:0] value;
3464 reg [5:0] tid;
3465 integer junk;
3466
3467 begin
3468`ifdef AXIS_EMUL_COSIM
3469//Do Nothing
3470`else
3471`ifdef GATESIM
3472//Do Nothing
3473`else
3474`ifdef CORE_6
3475 value[82] = ^value[40:0];
3476 value[83] = ^value[81:41];
3477 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
3478 `SPC6.mmu.mra0.array.mem[24] <= value;
3479`endif
3480
3481`endif
3482
3483`endif
3484
3485 end
3486 endtask
3487
3488
3489 task slam_MraRow0_core6_thread4;
3490 input [127:0] value;
3491 reg [5:0] tid;
3492 integer junk;
3493
3494 begin
3495`ifdef AXIS_EMUL_COSIM
3496//Do Nothing
3497`else
3498`ifdef GATESIM
3499//Do Nothing
3500`else
3501`ifdef CORE_6
3502 value[82] = ^value[40:0];
3503 value[83] = ^value[81:41];
3504 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
3505 `SPC6.mmu.mra1.array.mem[0] <= value;
3506`endif
3507
3508`endif
3509
3510`endif
3511
3512 end
3513 endtask
3514
3515
3516 task slam_MraRow0_core6_thread5;
3517 input [127:0] value;
3518 reg [5:0] tid;
3519 integer junk;
3520
3521 begin
3522`ifdef AXIS_EMUL_COSIM
3523//Do Nothing
3524`else
3525`ifdef GATESIM
3526//Do Nothing
3527`else
3528`ifdef CORE_6
3529 value[82] = ^value[40:0];
3530 value[83] = ^value[81:41];
3531 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
3532 `SPC6.mmu.mra1.array.mem[8] <= value;
3533`endif
3534
3535`endif
3536
3537`endif
3538
3539 end
3540 endtask
3541
3542
3543 task slam_MraRow0_core6_thread6;
3544 input [127:0] value;
3545 reg [5:0] tid;
3546 integer junk;
3547
3548 begin
3549`ifdef AXIS_EMUL_COSIM
3550//Do Nothing
3551`else
3552`ifdef GATESIM
3553//Do Nothing
3554`else
3555`ifdef CORE_6
3556 value[82] = ^value[40:0];
3557 value[83] = ^value[81:41];
3558 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
3559 `SPC6.mmu.mra1.array.mem[16] <= value;
3560`endif
3561
3562`endif
3563
3564`endif
3565
3566 end
3567 endtask
3568
3569
3570 task slam_MraRow0_core6_thread7;
3571 input [127:0] value;
3572 reg [5:0] tid;
3573 integer junk;
3574
3575 begin
3576`ifdef AXIS_EMUL_COSIM
3577//Do Nothing
3578`else
3579`ifdef GATESIM
3580//Do Nothing
3581`else
3582`ifdef CORE_6
3583 value[82] = ^value[40:0];
3584 value[83] = ^value[81:41];
3585 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
3586 `SPC6.mmu.mra1.array.mem[24] <= value;
3587`endif
3588
3589`endif
3590
3591`endif
3592
3593 end
3594 endtask
3595
3596
3597 task slam_MraRow0_core7_thread0;
3598 input [127:0] value;
3599 reg [5:0] tid;
3600 integer junk;
3601
3602 begin
3603`ifdef AXIS_EMUL_COSIM
3604//Do Nothing
3605`else
3606`ifdef GATESIM
3607//Do Nothing
3608`else
3609`ifdef CORE_7
3610 value[82] = ^value[40:0];
3611 value[83] = ^value[81:41];
3612 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[0]" );
3613 `SPC7.mmu.mra0.array.mem[0] <= value;
3614`endif
3615
3616`endif
3617
3618`endif
3619
3620 end
3621 endtask
3622
3623
3624 task slam_MraRow0_core7_thread1;
3625 input [127:0] value;
3626 reg [5:0] tid;
3627 integer junk;
3628
3629 begin
3630`ifdef AXIS_EMUL_COSIM
3631//Do Nothing
3632`else
3633`ifdef GATESIM
3634//Do Nothing
3635`else
3636`ifdef CORE_7
3637 value[82] = ^value[40:0];
3638 value[83] = ^value[81:41];
3639 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[8]" );
3640 `SPC7.mmu.mra0.array.mem[8] <= value;
3641`endif
3642
3643`endif
3644
3645`endif
3646
3647 end
3648 endtask
3649
3650
3651 task slam_MraRow0_core7_thread2;
3652 input [127:0] value;
3653 reg [5:0] tid;
3654 integer junk;
3655
3656 begin
3657`ifdef AXIS_EMUL_COSIM
3658//Do Nothing
3659`else
3660`ifdef GATESIM
3661//Do Nothing
3662`else
3663`ifdef CORE_7
3664 value[82] = ^value[40:0];
3665 value[83] = ^value[81:41];
3666 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[16]" );
3667 `SPC7.mmu.mra0.array.mem[16] <= value;
3668`endif
3669
3670`endif
3671
3672`endif
3673
3674 end
3675 endtask
3676
3677
3678 task slam_MraRow0_core7_thread3;
3679 input [127:0] value;
3680 reg [5:0] tid;
3681 integer junk;
3682
3683 begin
3684`ifdef AXIS_EMUL_COSIM
3685//Do Nothing
3686`else
3687`ifdef GATESIM
3688//Do Nothing
3689`else
3690`ifdef CORE_7
3691 value[82] = ^value[40:0];
3692 value[83] = ^value[81:41];
3693 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[24]" );
3694 `SPC7.mmu.mra0.array.mem[24] <= value;
3695`endif
3696
3697`endif
3698
3699`endif
3700
3701 end
3702 endtask
3703
3704
3705 task slam_MraRow0_core7_thread4;
3706 input [127:0] value;
3707 reg [5:0] tid;
3708 integer junk;
3709
3710 begin
3711`ifdef AXIS_EMUL_COSIM
3712//Do Nothing
3713`else
3714`ifdef GATESIM
3715//Do Nothing
3716`else
3717`ifdef CORE_7
3718 value[82] = ^value[40:0];
3719 value[83] = ^value[81:41];
3720 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[0]" );
3721 `SPC7.mmu.mra1.array.mem[0] <= value;
3722`endif
3723
3724`endif
3725
3726`endif
3727
3728 end
3729 endtask
3730
3731
3732 task slam_MraRow0_core7_thread5;
3733 input [127:0] value;
3734 reg [5:0] tid;
3735 integer junk;
3736
3737 begin
3738`ifdef AXIS_EMUL_COSIM
3739//Do Nothing
3740`else
3741`ifdef GATESIM
3742//Do Nothing
3743`else
3744`ifdef CORE_7
3745 value[82] = ^value[40:0];
3746 value[83] = ^value[81:41];
3747 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[8]" );
3748 `SPC7.mmu.mra1.array.mem[8] <= value;
3749`endif
3750
3751`endif
3752
3753`endif
3754
3755 end
3756 endtask
3757
3758
3759 task slam_MraRow0_core7_thread6;
3760 input [127:0] value;
3761 reg [5:0] tid;
3762 integer junk;
3763
3764 begin
3765`ifdef AXIS_EMUL_COSIM
3766//Do Nothing
3767`else
3768`ifdef GATESIM
3769//Do Nothing
3770`else
3771`ifdef CORE_7
3772 value[82] = ^value[40:0];
3773 value[83] = ^value[81:41];
3774 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[16]" );
3775 `SPC7.mmu.mra1.array.mem[16] <= value;
3776`endif
3777
3778`endif
3779
3780`endif
3781
3782 end
3783 endtask
3784
3785
3786 task slam_MraRow0_core7_thread7;
3787 input [127:0] value;
3788 reg [5:0] tid;
3789 integer junk;
3790
3791 begin
3792`ifdef AXIS_EMUL_COSIM
3793//Do Nothing
3794`else
3795`ifdef GATESIM
3796//Do Nothing
3797`else
3798`ifdef CORE_7
3799 value[82] = ^value[40:0];
3800 value[83] = ^value[81:41];
3801 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[24]" );
3802 `SPC7.mmu.mra1.array.mem[24] <= value;
3803`endif
3804
3805`endif
3806
3807`endif
3808
3809 end
3810 endtask
3811
3812
3813 task slam_MraRow1_core0_thread0;
3814 input [127:0] value;
3815 reg [5:0] tid;
3816 integer junk;
3817
3818 begin
3819`ifdef AXIS_EMUL_COSIM
3820//Do Nothing
3821`else
3822`ifdef GATESIM
3823//Do Nothing
3824`else
3825`ifdef CORE_0
3826 value[82] = ^value[40:0];
3827 value[83] = ^value[81:41];
3828 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
3829 `SPC0.mmu.mra0.array.mem[1] <= value;
3830`endif
3831
3832`endif
3833
3834`endif
3835
3836 end
3837 endtask
3838
3839
3840 task slam_MraRow1_core0_thread1;
3841 input [127:0] value;
3842 reg [5:0] tid;
3843 integer junk;
3844
3845 begin
3846`ifdef AXIS_EMUL_COSIM
3847//Do Nothing
3848`else
3849`ifdef GATESIM
3850//Do Nothing
3851`else
3852`ifdef CORE_0
3853 value[82] = ^value[40:0];
3854 value[83] = ^value[81:41];
3855 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
3856 `SPC0.mmu.mra0.array.mem[9] <= value;
3857`endif
3858
3859`endif
3860
3861`endif
3862
3863 end
3864 endtask
3865
3866
3867 task slam_MraRow1_core0_thread2;
3868 input [127:0] value;
3869 reg [5:0] tid;
3870 integer junk;
3871
3872 begin
3873`ifdef AXIS_EMUL_COSIM
3874//Do Nothing
3875`else
3876`ifdef GATESIM
3877//Do Nothing
3878`else
3879`ifdef CORE_0
3880 value[82] = ^value[40:0];
3881 value[83] = ^value[81:41];
3882 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
3883 `SPC0.mmu.mra0.array.mem[17] <= value;
3884`endif
3885
3886`endif
3887
3888`endif
3889
3890 end
3891 endtask
3892
3893
3894 task slam_MraRow1_core0_thread3;
3895 input [127:0] value;
3896 reg [5:0] tid;
3897 integer junk;
3898
3899 begin
3900`ifdef AXIS_EMUL_COSIM
3901//Do Nothing
3902`else
3903`ifdef GATESIM
3904//Do Nothing
3905`else
3906`ifdef CORE_0
3907 value[82] = ^value[40:0];
3908 value[83] = ^value[81:41];
3909 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
3910 `SPC0.mmu.mra0.array.mem[25] <= value;
3911`endif
3912
3913`endif
3914
3915`endif
3916
3917 end
3918 endtask
3919
3920
3921 task slam_MraRow1_core0_thread4;
3922 input [127:0] value;
3923 reg [5:0] tid;
3924 integer junk;
3925
3926 begin
3927`ifdef AXIS_EMUL_COSIM
3928//Do Nothing
3929`else
3930`ifdef GATESIM
3931//Do Nothing
3932`else
3933`ifdef CORE_0
3934 value[82] = ^value[40:0];
3935 value[83] = ^value[81:41];
3936 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
3937 `SPC0.mmu.mra1.array.mem[1] <= value;
3938`endif
3939
3940`endif
3941
3942`endif
3943
3944 end
3945 endtask
3946
3947
3948 task slam_MraRow1_core0_thread5;
3949 input [127:0] value;
3950 reg [5:0] tid;
3951 integer junk;
3952
3953 begin
3954`ifdef AXIS_EMUL_COSIM
3955//Do Nothing
3956`else
3957`ifdef GATESIM
3958//Do Nothing
3959`else
3960`ifdef CORE_0
3961 value[82] = ^value[40:0];
3962 value[83] = ^value[81:41];
3963 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
3964 `SPC0.mmu.mra1.array.mem[9] <= value;
3965`endif
3966
3967`endif
3968
3969`endif
3970
3971 end
3972 endtask
3973
3974
3975 task slam_MraRow1_core0_thread6;
3976 input [127:0] value;
3977 reg [5:0] tid;
3978 integer junk;
3979
3980 begin
3981`ifdef AXIS_EMUL_COSIM
3982//Do Nothing
3983`else
3984`ifdef GATESIM
3985//Do Nothing
3986`else
3987`ifdef CORE_0
3988 value[82] = ^value[40:0];
3989 value[83] = ^value[81:41];
3990 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
3991 `SPC0.mmu.mra1.array.mem[17] <= value;
3992`endif
3993
3994`endif
3995
3996`endif
3997
3998 end
3999 endtask
4000
4001
4002 task slam_MraRow1_core0_thread7;
4003 input [127:0] value;
4004 reg [5:0] tid;
4005 integer junk;
4006
4007 begin
4008`ifdef AXIS_EMUL_COSIM
4009//Do Nothing
4010`else
4011`ifdef GATESIM
4012//Do Nothing
4013`else
4014`ifdef CORE_0
4015 value[82] = ^value[40:0];
4016 value[83] = ^value[81:41];
4017 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
4018 `SPC0.mmu.mra1.array.mem[25] <= value;
4019`endif
4020
4021`endif
4022
4023`endif
4024
4025 end
4026 endtask
4027
4028
4029 task slam_MraRow1_core1_thread0;
4030 input [127:0] value;
4031 reg [5:0] tid;
4032 integer junk;
4033
4034 begin
4035`ifdef AXIS_EMUL_COSIM
4036//Do Nothing
4037`else
4038`ifdef GATESIM
4039//Do Nothing
4040`else
4041`ifdef CORE_1
4042 value[82] = ^value[40:0];
4043 value[83] = ^value[81:41];
4044 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
4045 `SPC1.mmu.mra0.array.mem[1] <= value;
4046`endif
4047
4048`endif
4049
4050`endif
4051
4052 end
4053 endtask
4054
4055
4056 task slam_MraRow1_core1_thread1;
4057 input [127:0] value;
4058 reg [5:0] tid;
4059 integer junk;
4060
4061 begin
4062`ifdef AXIS_EMUL_COSIM
4063//Do Nothing
4064`else
4065`ifdef GATESIM
4066//Do Nothing
4067`else
4068`ifdef CORE_1
4069 value[82] = ^value[40:0];
4070 value[83] = ^value[81:41];
4071 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
4072 `SPC1.mmu.mra0.array.mem[9] <= value;
4073`endif
4074
4075`endif
4076
4077`endif
4078
4079 end
4080 endtask
4081
4082
4083 task slam_MraRow1_core1_thread2;
4084 input [127:0] value;
4085 reg [5:0] tid;
4086 integer junk;
4087
4088 begin
4089`ifdef AXIS_EMUL_COSIM
4090//Do Nothing
4091`else
4092`ifdef GATESIM
4093//Do Nothing
4094`else
4095`ifdef CORE_1
4096 value[82] = ^value[40:0];
4097 value[83] = ^value[81:41];
4098 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
4099 `SPC1.mmu.mra0.array.mem[17] <= value;
4100`endif
4101
4102`endif
4103
4104`endif
4105
4106 end
4107 endtask
4108
4109
4110 task slam_MraRow1_core1_thread3;
4111 input [127:0] value;
4112 reg [5:0] tid;
4113 integer junk;
4114
4115 begin
4116`ifdef AXIS_EMUL_COSIM
4117//Do Nothing
4118`else
4119`ifdef GATESIM
4120//Do Nothing
4121`else
4122`ifdef CORE_1
4123 value[82] = ^value[40:0];
4124 value[83] = ^value[81:41];
4125 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
4126 `SPC1.mmu.mra0.array.mem[25] <= value;
4127`endif
4128
4129`endif
4130
4131`endif
4132
4133 end
4134 endtask
4135
4136
4137 task slam_MraRow1_core1_thread4;
4138 input [127:0] value;
4139 reg [5:0] tid;
4140 integer junk;
4141
4142 begin
4143`ifdef AXIS_EMUL_COSIM
4144//Do Nothing
4145`else
4146`ifdef GATESIM
4147//Do Nothing
4148`else
4149`ifdef CORE_1
4150 value[82] = ^value[40:0];
4151 value[83] = ^value[81:41];
4152 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
4153 `SPC1.mmu.mra1.array.mem[1] <= value;
4154`endif
4155
4156`endif
4157
4158`endif
4159
4160 end
4161 endtask
4162
4163
4164 task slam_MraRow1_core1_thread5;
4165 input [127:0] value;
4166 reg [5:0] tid;
4167 integer junk;
4168
4169 begin
4170`ifdef AXIS_EMUL_COSIM
4171//Do Nothing
4172`else
4173`ifdef GATESIM
4174//Do Nothing
4175`else
4176`ifdef CORE_1
4177 value[82] = ^value[40:0];
4178 value[83] = ^value[81:41];
4179 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
4180 `SPC1.mmu.mra1.array.mem[9] <= value;
4181`endif
4182
4183`endif
4184
4185`endif
4186
4187 end
4188 endtask
4189
4190
4191 task slam_MraRow1_core1_thread6;
4192 input [127:0] value;
4193 reg [5:0] tid;
4194 integer junk;
4195
4196 begin
4197`ifdef AXIS_EMUL_COSIM
4198//Do Nothing
4199`else
4200`ifdef GATESIM
4201//Do Nothing
4202`else
4203`ifdef CORE_1
4204 value[82] = ^value[40:0];
4205 value[83] = ^value[81:41];
4206 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
4207 `SPC1.mmu.mra1.array.mem[17] <= value;
4208`endif
4209
4210`endif
4211
4212`endif
4213
4214 end
4215 endtask
4216
4217
4218 task slam_MraRow1_core1_thread7;
4219 input [127:0] value;
4220 reg [5:0] tid;
4221 integer junk;
4222
4223 begin
4224`ifdef AXIS_EMUL_COSIM
4225//Do Nothing
4226`else
4227`ifdef GATESIM
4228//Do Nothing
4229`else
4230`ifdef CORE_1
4231 value[82] = ^value[40:0];
4232 value[83] = ^value[81:41];
4233 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
4234 `SPC1.mmu.mra1.array.mem[25] <= value;
4235`endif
4236
4237`endif
4238
4239`endif
4240
4241 end
4242 endtask
4243
4244
4245 task slam_MraRow1_core2_thread0;
4246 input [127:0] value;
4247 reg [5:0] tid;
4248 integer junk;
4249
4250 begin
4251`ifdef AXIS_EMUL_COSIM
4252//Do Nothing
4253`else
4254`ifdef GATESIM
4255//Do Nothing
4256`else
4257`ifdef CORE_2
4258 value[82] = ^value[40:0];
4259 value[83] = ^value[81:41];
4260 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
4261 `SPC2.mmu.mra0.array.mem[1] <= value;
4262`endif
4263
4264`endif
4265
4266`endif
4267
4268 end
4269 endtask
4270
4271
4272 task slam_MraRow1_core2_thread1;
4273 input [127:0] value;
4274 reg [5:0] tid;
4275 integer junk;
4276
4277 begin
4278`ifdef AXIS_EMUL_COSIM
4279//Do Nothing
4280`else
4281`ifdef GATESIM
4282//Do Nothing
4283`else
4284`ifdef CORE_2
4285 value[82] = ^value[40:0];
4286 value[83] = ^value[81:41];
4287 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
4288 `SPC2.mmu.mra0.array.mem[9] <= value;
4289`endif
4290
4291`endif
4292
4293`endif
4294
4295 end
4296 endtask
4297
4298
4299 task slam_MraRow1_core2_thread2;
4300 input [127:0] value;
4301 reg [5:0] tid;
4302 integer junk;
4303
4304 begin
4305`ifdef AXIS_EMUL_COSIM
4306//Do Nothing
4307`else
4308`ifdef GATESIM
4309//Do Nothing
4310`else
4311`ifdef CORE_2
4312 value[82] = ^value[40:0];
4313 value[83] = ^value[81:41];
4314 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
4315 `SPC2.mmu.mra0.array.mem[17] <= value;
4316`endif
4317
4318`endif
4319
4320`endif
4321
4322 end
4323 endtask
4324
4325
4326 task slam_MraRow1_core2_thread3;
4327 input [127:0] value;
4328 reg [5:0] tid;
4329 integer junk;
4330
4331 begin
4332`ifdef AXIS_EMUL_COSIM
4333//Do Nothing
4334`else
4335`ifdef GATESIM
4336//Do Nothing
4337`else
4338`ifdef CORE_2
4339 value[82] = ^value[40:0];
4340 value[83] = ^value[81:41];
4341 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
4342 `SPC2.mmu.mra0.array.mem[25] <= value;
4343`endif
4344
4345`endif
4346
4347`endif
4348
4349 end
4350 endtask
4351
4352
4353 task slam_MraRow1_core2_thread4;
4354 input [127:0] value;
4355 reg [5:0] tid;
4356 integer junk;
4357
4358 begin
4359`ifdef AXIS_EMUL_COSIM
4360//Do Nothing
4361`else
4362`ifdef GATESIM
4363//Do Nothing
4364`else
4365`ifdef CORE_2
4366 value[82] = ^value[40:0];
4367 value[83] = ^value[81:41];
4368 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
4369 `SPC2.mmu.mra1.array.mem[1] <= value;
4370`endif
4371
4372`endif
4373
4374`endif
4375
4376 end
4377 endtask
4378
4379
4380 task slam_MraRow1_core2_thread5;
4381 input [127:0] value;
4382 reg [5:0] tid;
4383 integer junk;
4384
4385 begin
4386`ifdef AXIS_EMUL_COSIM
4387//Do Nothing
4388`else
4389`ifdef GATESIM
4390//Do Nothing
4391`else
4392`ifdef CORE_2
4393 value[82] = ^value[40:0];
4394 value[83] = ^value[81:41];
4395 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
4396 `SPC2.mmu.mra1.array.mem[9] <= value;
4397`endif
4398
4399`endif
4400
4401`endif
4402
4403 end
4404 endtask
4405
4406
4407 task slam_MraRow1_core2_thread6;
4408 input [127:0] value;
4409 reg [5:0] tid;
4410 integer junk;
4411
4412 begin
4413`ifdef AXIS_EMUL_COSIM
4414//Do Nothing
4415`else
4416`ifdef GATESIM
4417//Do Nothing
4418`else
4419`ifdef CORE_2
4420 value[82] = ^value[40:0];
4421 value[83] = ^value[81:41];
4422 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
4423 `SPC2.mmu.mra1.array.mem[17] <= value;
4424`endif
4425
4426`endif
4427
4428`endif
4429
4430 end
4431 endtask
4432
4433
4434 task slam_MraRow1_core2_thread7;
4435 input [127:0] value;
4436 reg [5:0] tid;
4437 integer junk;
4438
4439 begin
4440`ifdef AXIS_EMUL_COSIM
4441//Do Nothing
4442`else
4443`ifdef GATESIM
4444//Do Nothing
4445`else
4446`ifdef CORE_2
4447 value[82] = ^value[40:0];
4448 value[83] = ^value[81:41];
4449 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
4450 `SPC2.mmu.mra1.array.mem[25] <= value;
4451`endif
4452
4453`endif
4454
4455`endif
4456
4457 end
4458 endtask
4459
4460
4461 task slam_MraRow1_core3_thread0;
4462 input [127:0] value;
4463 reg [5:0] tid;
4464 integer junk;
4465
4466 begin
4467`ifdef AXIS_EMUL_COSIM
4468//Do Nothing
4469`else
4470`ifdef GATESIM
4471//Do Nothing
4472`else
4473`ifdef CORE_3
4474 value[82] = ^value[40:0];
4475 value[83] = ^value[81:41];
4476 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
4477 `SPC3.mmu.mra0.array.mem[1] <= value;
4478`endif
4479
4480`endif
4481
4482`endif
4483
4484 end
4485 endtask
4486
4487
4488 task slam_MraRow1_core3_thread1;
4489 input [127:0] value;
4490 reg [5:0] tid;
4491 integer junk;
4492
4493 begin
4494`ifdef AXIS_EMUL_COSIM
4495//Do Nothing
4496`else
4497`ifdef GATESIM
4498//Do Nothing
4499`else
4500`ifdef CORE_3
4501 value[82] = ^value[40:0];
4502 value[83] = ^value[81:41];
4503 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
4504 `SPC3.mmu.mra0.array.mem[9] <= value;
4505`endif
4506
4507`endif
4508
4509`endif
4510
4511 end
4512 endtask
4513
4514
4515 task slam_MraRow1_core3_thread2;
4516 input [127:0] value;
4517 reg [5:0] tid;
4518 integer junk;
4519
4520 begin
4521`ifdef AXIS_EMUL_COSIM
4522//Do Nothing
4523`else
4524`ifdef GATESIM
4525//Do Nothing
4526`else
4527`ifdef CORE_3
4528 value[82] = ^value[40:0];
4529 value[83] = ^value[81:41];
4530 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
4531 `SPC3.mmu.mra0.array.mem[17] <= value;
4532`endif
4533
4534`endif
4535
4536`endif
4537
4538 end
4539 endtask
4540
4541
4542 task slam_MraRow1_core3_thread3;
4543 input [127:0] value;
4544 reg [5:0] tid;
4545 integer junk;
4546
4547 begin
4548`ifdef AXIS_EMUL_COSIM
4549//Do Nothing
4550`else
4551`ifdef GATESIM
4552//Do Nothing
4553`else
4554`ifdef CORE_3
4555 value[82] = ^value[40:0];
4556 value[83] = ^value[81:41];
4557 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
4558 `SPC3.mmu.mra0.array.mem[25] <= value;
4559`endif
4560
4561`endif
4562
4563`endif
4564
4565 end
4566 endtask
4567
4568
4569 task slam_MraRow1_core3_thread4;
4570 input [127:0] value;
4571 reg [5:0] tid;
4572 integer junk;
4573
4574 begin
4575`ifdef AXIS_EMUL_COSIM
4576//Do Nothing
4577`else
4578`ifdef GATESIM
4579//Do Nothing
4580`else
4581`ifdef CORE_3
4582 value[82] = ^value[40:0];
4583 value[83] = ^value[81:41];
4584 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
4585 `SPC3.mmu.mra1.array.mem[1] <= value;
4586`endif
4587
4588`endif
4589
4590`endif
4591
4592 end
4593 endtask
4594
4595
4596 task slam_MraRow1_core3_thread5;
4597 input [127:0] value;
4598 reg [5:0] tid;
4599 integer junk;
4600
4601 begin
4602`ifdef AXIS_EMUL_COSIM
4603//Do Nothing
4604`else
4605`ifdef GATESIM
4606//Do Nothing
4607`else
4608`ifdef CORE_3
4609 value[82] = ^value[40:0];
4610 value[83] = ^value[81:41];
4611 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
4612 `SPC3.mmu.mra1.array.mem[9] <= value;
4613`endif
4614
4615`endif
4616
4617`endif
4618
4619 end
4620 endtask
4621
4622
4623 task slam_MraRow1_core3_thread6;
4624 input [127:0] value;
4625 reg [5:0] tid;
4626 integer junk;
4627
4628 begin
4629`ifdef AXIS_EMUL_COSIM
4630//Do Nothing
4631`else
4632`ifdef GATESIM
4633//Do Nothing
4634`else
4635`ifdef CORE_3
4636 value[82] = ^value[40:0];
4637 value[83] = ^value[81:41];
4638 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
4639 `SPC3.mmu.mra1.array.mem[17] <= value;
4640`endif
4641
4642`endif
4643
4644`endif
4645
4646 end
4647 endtask
4648
4649
4650 task slam_MraRow1_core3_thread7;
4651 input [127:0] value;
4652 reg [5:0] tid;
4653 integer junk;
4654
4655 begin
4656`ifdef AXIS_EMUL_COSIM
4657//Do Nothing
4658`else
4659`ifdef GATESIM
4660//Do Nothing
4661`else
4662`ifdef CORE_3
4663 value[82] = ^value[40:0];
4664 value[83] = ^value[81:41];
4665 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
4666 `SPC3.mmu.mra1.array.mem[25] <= value;
4667`endif
4668
4669`endif
4670
4671`endif
4672
4673 end
4674 endtask
4675
4676
4677 task slam_MraRow1_core4_thread0;
4678 input [127:0] value;
4679 reg [5:0] tid;
4680 integer junk;
4681
4682 begin
4683`ifdef AXIS_EMUL_COSIM
4684//Do Nothing
4685`else
4686`ifdef GATESIM
4687//Do Nothing
4688`else
4689`ifdef CORE_4
4690 value[82] = ^value[40:0];
4691 value[83] = ^value[81:41];
4692 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
4693 `SPC4.mmu.mra0.array.mem[1] <= value;
4694`endif
4695
4696`endif
4697
4698`endif
4699
4700 end
4701 endtask
4702
4703
4704 task slam_MraRow1_core4_thread1;
4705 input [127:0] value;
4706 reg [5:0] tid;
4707 integer junk;
4708
4709 begin
4710`ifdef AXIS_EMUL_COSIM
4711//Do Nothing
4712`else
4713`ifdef GATESIM
4714//Do Nothing
4715`else
4716`ifdef CORE_4
4717 value[82] = ^value[40:0];
4718 value[83] = ^value[81:41];
4719 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
4720 `SPC4.mmu.mra0.array.mem[9] <= value;
4721`endif
4722
4723`endif
4724
4725`endif
4726
4727 end
4728 endtask
4729
4730
4731 task slam_MraRow1_core4_thread2;
4732 input [127:0] value;
4733 reg [5:0] tid;
4734 integer junk;
4735
4736 begin
4737`ifdef AXIS_EMUL_COSIM
4738//Do Nothing
4739`else
4740`ifdef GATESIM
4741//Do Nothing
4742`else
4743`ifdef CORE_4
4744 value[82] = ^value[40:0];
4745 value[83] = ^value[81:41];
4746 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
4747 `SPC4.mmu.mra0.array.mem[17] <= value;
4748`endif
4749
4750`endif
4751
4752`endif
4753
4754 end
4755 endtask
4756
4757
4758 task slam_MraRow1_core4_thread3;
4759 input [127:0] value;
4760 reg [5:0] tid;
4761 integer junk;
4762
4763 begin
4764`ifdef AXIS_EMUL_COSIM
4765//Do Nothing
4766`else
4767`ifdef GATESIM
4768//Do Nothing
4769`else
4770`ifdef CORE_4
4771 value[82] = ^value[40:0];
4772 value[83] = ^value[81:41];
4773 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
4774 `SPC4.mmu.mra0.array.mem[25] <= value;
4775`endif
4776
4777`endif
4778
4779`endif
4780
4781 end
4782 endtask
4783
4784
4785 task slam_MraRow1_core4_thread4;
4786 input [127:0] value;
4787 reg [5:0] tid;
4788 integer junk;
4789
4790 begin
4791`ifdef AXIS_EMUL_COSIM
4792//Do Nothing
4793`else
4794`ifdef GATESIM
4795//Do Nothing
4796`else
4797`ifdef CORE_4
4798 value[82] = ^value[40:0];
4799 value[83] = ^value[81:41];
4800 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
4801 `SPC4.mmu.mra1.array.mem[1] <= value;
4802`endif
4803
4804`endif
4805
4806`endif
4807
4808 end
4809 endtask
4810
4811
4812 task slam_MraRow1_core4_thread5;
4813 input [127:0] value;
4814 reg [5:0] tid;
4815 integer junk;
4816
4817 begin
4818`ifdef AXIS_EMUL_COSIM
4819//Do Nothing
4820`else
4821`ifdef GATESIM
4822//Do Nothing
4823`else
4824`ifdef CORE_4
4825 value[82] = ^value[40:0];
4826 value[83] = ^value[81:41];
4827 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
4828 `SPC4.mmu.mra1.array.mem[9] <= value;
4829`endif
4830
4831`endif
4832
4833`endif
4834
4835 end
4836 endtask
4837
4838
4839 task slam_MraRow1_core4_thread6;
4840 input [127:0] value;
4841 reg [5:0] tid;
4842 integer junk;
4843
4844 begin
4845`ifdef AXIS_EMUL_COSIM
4846//Do Nothing
4847`else
4848`ifdef GATESIM
4849//Do Nothing
4850`else
4851`ifdef CORE_4
4852 value[82] = ^value[40:0];
4853 value[83] = ^value[81:41];
4854 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
4855 `SPC4.mmu.mra1.array.mem[17] <= value;
4856`endif
4857
4858`endif
4859
4860`endif
4861
4862 end
4863 endtask
4864
4865
4866 task slam_MraRow1_core4_thread7;
4867 input [127:0] value;
4868 reg [5:0] tid;
4869 integer junk;
4870
4871 begin
4872`ifdef AXIS_EMUL_COSIM
4873//Do Nothing
4874`else
4875`ifdef GATESIM
4876//Do Nothing
4877`else
4878`ifdef CORE_4
4879 value[82] = ^value[40:0];
4880 value[83] = ^value[81:41];
4881 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
4882 `SPC4.mmu.mra1.array.mem[25] <= value;
4883`endif
4884
4885`endif
4886
4887`endif
4888
4889 end
4890 endtask
4891
4892
4893 task slam_MraRow1_core5_thread0;
4894 input [127:0] value;
4895 reg [5:0] tid;
4896 integer junk;
4897
4898 begin
4899`ifdef AXIS_EMUL_COSIM
4900//Do Nothing
4901`else
4902`ifdef GATESIM
4903//Do Nothing
4904`else
4905`ifdef CORE_5
4906 value[82] = ^value[40:0];
4907 value[83] = ^value[81:41];
4908 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
4909 `SPC5.mmu.mra0.array.mem[1] <= value;
4910`endif
4911
4912`endif
4913
4914`endif
4915
4916 end
4917 endtask
4918
4919
4920 task slam_MraRow1_core5_thread1;
4921 input [127:0] value;
4922 reg [5:0] tid;
4923 integer junk;
4924
4925 begin
4926`ifdef AXIS_EMUL_COSIM
4927//Do Nothing
4928`else
4929`ifdef GATESIM
4930//Do Nothing
4931`else
4932`ifdef CORE_5
4933 value[82] = ^value[40:0];
4934 value[83] = ^value[81:41];
4935 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
4936 `SPC5.mmu.mra0.array.mem[9] <= value;
4937`endif
4938
4939`endif
4940
4941`endif
4942
4943 end
4944 endtask
4945
4946
4947 task slam_MraRow1_core5_thread2;
4948 input [127:0] value;
4949 reg [5:0] tid;
4950 integer junk;
4951
4952 begin
4953`ifdef AXIS_EMUL_COSIM
4954//Do Nothing
4955`else
4956`ifdef GATESIM
4957//Do Nothing
4958`else
4959`ifdef CORE_5
4960 value[82] = ^value[40:0];
4961 value[83] = ^value[81:41];
4962 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
4963 `SPC5.mmu.mra0.array.mem[17] <= value;
4964`endif
4965
4966`endif
4967
4968`endif
4969
4970 end
4971 endtask
4972
4973
4974 task slam_MraRow1_core5_thread3;
4975 input [127:0] value;
4976 reg [5:0] tid;
4977 integer junk;
4978
4979 begin
4980`ifdef AXIS_EMUL_COSIM
4981//Do Nothing
4982`else
4983`ifdef GATESIM
4984//Do Nothing
4985`else
4986`ifdef CORE_5
4987 value[82] = ^value[40:0];
4988 value[83] = ^value[81:41];
4989 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
4990 `SPC5.mmu.mra0.array.mem[25] <= value;
4991`endif
4992
4993`endif
4994
4995`endif
4996
4997 end
4998 endtask
4999
5000
5001 task slam_MraRow1_core5_thread4;
5002 input [127:0] value;
5003 reg [5:0] tid;
5004 integer junk;
5005
5006 begin
5007`ifdef AXIS_EMUL_COSIM
5008//Do Nothing
5009`else
5010`ifdef GATESIM
5011//Do Nothing
5012`else
5013`ifdef CORE_5
5014 value[82] = ^value[40:0];
5015 value[83] = ^value[81:41];
5016 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
5017 `SPC5.mmu.mra1.array.mem[1] <= value;
5018`endif
5019
5020`endif
5021
5022`endif
5023
5024 end
5025 endtask
5026
5027
5028 task slam_MraRow1_core5_thread5;
5029 input [127:0] value;
5030 reg [5:0] tid;
5031 integer junk;
5032
5033 begin
5034`ifdef AXIS_EMUL_COSIM
5035//Do Nothing
5036`else
5037`ifdef GATESIM
5038//Do Nothing
5039`else
5040`ifdef CORE_5
5041 value[82] = ^value[40:0];
5042 value[83] = ^value[81:41];
5043 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
5044 `SPC5.mmu.mra1.array.mem[9] <= value;
5045`endif
5046
5047`endif
5048
5049`endif
5050
5051 end
5052 endtask
5053
5054
5055 task slam_MraRow1_core5_thread6;
5056 input [127:0] value;
5057 reg [5:0] tid;
5058 integer junk;
5059
5060 begin
5061`ifdef AXIS_EMUL_COSIM
5062//Do Nothing
5063`else
5064`ifdef GATESIM
5065//Do Nothing
5066`else
5067`ifdef CORE_5
5068 value[82] = ^value[40:0];
5069 value[83] = ^value[81:41];
5070 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
5071 `SPC5.mmu.mra1.array.mem[17] <= value;
5072`endif
5073
5074`endif
5075
5076`endif
5077
5078 end
5079 endtask
5080
5081
5082 task slam_MraRow1_core5_thread7;
5083 input [127:0] value;
5084 reg [5:0] tid;
5085 integer junk;
5086
5087 begin
5088`ifdef AXIS_EMUL_COSIM
5089//Do Nothing
5090`else
5091`ifdef GATESIM
5092//Do Nothing
5093`else
5094`ifdef CORE_5
5095 value[82] = ^value[40:0];
5096 value[83] = ^value[81:41];
5097 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
5098 `SPC5.mmu.mra1.array.mem[25] <= value;
5099`endif
5100
5101`endif
5102
5103`endif
5104
5105 end
5106 endtask
5107
5108
5109 task slam_MraRow1_core6_thread0;
5110 input [127:0] value;
5111 reg [5:0] tid;
5112 integer junk;
5113
5114 begin
5115`ifdef AXIS_EMUL_COSIM
5116//Do Nothing
5117`else
5118`ifdef GATESIM
5119//Do Nothing
5120`else
5121`ifdef CORE_6
5122 value[82] = ^value[40:0];
5123 value[83] = ^value[81:41];
5124 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
5125 `SPC6.mmu.mra0.array.mem[1] <= value;
5126`endif
5127
5128`endif
5129
5130`endif
5131
5132 end
5133 endtask
5134
5135
5136 task slam_MraRow1_core6_thread1;
5137 input [127:0] value;
5138 reg [5:0] tid;
5139 integer junk;
5140
5141 begin
5142`ifdef AXIS_EMUL_COSIM
5143//Do Nothing
5144`else
5145`ifdef GATESIM
5146//Do Nothing
5147`else
5148`ifdef CORE_6
5149 value[82] = ^value[40:0];
5150 value[83] = ^value[81:41];
5151 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
5152 `SPC6.mmu.mra0.array.mem[9] <= value;
5153`endif
5154
5155`endif
5156
5157`endif
5158
5159 end
5160 endtask
5161
5162
5163 task slam_MraRow1_core6_thread2;
5164 input [127:0] value;
5165 reg [5:0] tid;
5166 integer junk;
5167
5168 begin
5169`ifdef AXIS_EMUL_COSIM
5170//Do Nothing
5171`else
5172`ifdef GATESIM
5173//Do Nothing
5174`else
5175`ifdef CORE_6
5176 value[82] = ^value[40:0];
5177 value[83] = ^value[81:41];
5178 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
5179 `SPC6.mmu.mra0.array.mem[17] <= value;
5180`endif
5181
5182`endif
5183
5184`endif
5185
5186 end
5187 endtask
5188
5189
5190 task slam_MraRow1_core6_thread3;
5191 input [127:0] value;
5192 reg [5:0] tid;
5193 integer junk;
5194
5195 begin
5196`ifdef AXIS_EMUL_COSIM
5197//Do Nothing
5198`else
5199`ifdef GATESIM
5200//Do Nothing
5201`else
5202`ifdef CORE_6
5203 value[82] = ^value[40:0];
5204 value[83] = ^value[81:41];
5205 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
5206 `SPC6.mmu.mra0.array.mem[25] <= value;
5207`endif
5208
5209`endif
5210
5211`endif
5212
5213 end
5214 endtask
5215
5216
5217 task slam_MraRow1_core6_thread4;
5218 input [127:0] value;
5219 reg [5:0] tid;
5220 integer junk;
5221
5222 begin
5223`ifdef AXIS_EMUL_COSIM
5224//Do Nothing
5225`else
5226`ifdef GATESIM
5227//Do Nothing
5228`else
5229`ifdef CORE_6
5230 value[82] = ^value[40:0];
5231 value[83] = ^value[81:41];
5232 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
5233 `SPC6.mmu.mra1.array.mem[1] <= value;
5234`endif
5235
5236`endif
5237
5238`endif
5239
5240 end
5241 endtask
5242
5243
5244 task slam_MraRow1_core6_thread5;
5245 input [127:0] value;
5246 reg [5:0] tid;
5247 integer junk;
5248
5249 begin
5250`ifdef AXIS_EMUL_COSIM
5251//Do Nothing
5252`else
5253`ifdef GATESIM
5254//Do Nothing
5255`else
5256`ifdef CORE_6
5257 value[82] = ^value[40:0];
5258 value[83] = ^value[81:41];
5259 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
5260 `SPC6.mmu.mra1.array.mem[9] <= value;
5261`endif
5262
5263`endif
5264
5265`endif
5266
5267 end
5268 endtask
5269
5270
5271 task slam_MraRow1_core6_thread6;
5272 input [127:0] value;
5273 reg [5:0] tid;
5274 integer junk;
5275
5276 begin
5277`ifdef AXIS_EMUL_COSIM
5278//Do Nothing
5279`else
5280`ifdef GATESIM
5281//Do Nothing
5282`else
5283`ifdef CORE_6
5284 value[82] = ^value[40:0];
5285 value[83] = ^value[81:41];
5286 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
5287 `SPC6.mmu.mra1.array.mem[17] <= value;
5288`endif
5289
5290`endif
5291
5292`endif
5293
5294 end
5295 endtask
5296
5297
5298 task slam_MraRow1_core6_thread7;
5299 input [127:0] value;
5300 reg [5:0] tid;
5301 integer junk;
5302
5303 begin
5304`ifdef AXIS_EMUL_COSIM
5305//Do Nothing
5306`else
5307`ifdef GATESIM
5308//Do Nothing
5309`else
5310`ifdef CORE_6
5311 value[82] = ^value[40:0];
5312 value[83] = ^value[81:41];
5313 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
5314 `SPC6.mmu.mra1.array.mem[25] <= value;
5315`endif
5316
5317`endif
5318
5319`endif
5320
5321 end
5322 endtask
5323
5324
5325 task slam_MraRow1_core7_thread0;
5326 input [127:0] value;
5327 reg [5:0] tid;
5328 integer junk;
5329
5330 begin
5331`ifdef AXIS_EMUL_COSIM
5332//Do Nothing
5333`else
5334`ifdef GATESIM
5335//Do Nothing
5336`else
5337`ifdef CORE_7
5338 value[82] = ^value[40:0];
5339 value[83] = ^value[81:41];
5340 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[1]" );
5341 `SPC7.mmu.mra0.array.mem[1] <= value;
5342`endif
5343
5344`endif
5345
5346`endif
5347
5348 end
5349 endtask
5350
5351
5352 task slam_MraRow1_core7_thread1;
5353 input [127:0] value;
5354 reg [5:0] tid;
5355 integer junk;
5356
5357 begin
5358`ifdef AXIS_EMUL_COSIM
5359//Do Nothing
5360`else
5361`ifdef GATESIM
5362//Do Nothing
5363`else
5364`ifdef CORE_7
5365 value[82] = ^value[40:0];
5366 value[83] = ^value[81:41];
5367 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[9]" );
5368 `SPC7.mmu.mra0.array.mem[9] <= value;
5369`endif
5370
5371`endif
5372
5373`endif
5374
5375 end
5376 endtask
5377
5378
5379 task slam_MraRow1_core7_thread2;
5380 input [127:0] value;
5381 reg [5:0] tid;
5382 integer junk;
5383
5384 begin
5385`ifdef AXIS_EMUL_COSIM
5386//Do Nothing
5387`else
5388`ifdef GATESIM
5389//Do Nothing
5390`else
5391`ifdef CORE_7
5392 value[82] = ^value[40:0];
5393 value[83] = ^value[81:41];
5394 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[17]" );
5395 `SPC7.mmu.mra0.array.mem[17] <= value;
5396`endif
5397
5398`endif
5399
5400`endif
5401
5402 end
5403 endtask
5404
5405
5406 task slam_MraRow1_core7_thread3;
5407 input [127:0] value;
5408 reg [5:0] tid;
5409 integer junk;
5410
5411 begin
5412`ifdef AXIS_EMUL_COSIM
5413//Do Nothing
5414`else
5415`ifdef GATESIM
5416//Do Nothing
5417`else
5418`ifdef CORE_7
5419 value[82] = ^value[40:0];
5420 value[83] = ^value[81:41];
5421 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[25]" );
5422 `SPC7.mmu.mra0.array.mem[25] <= value;
5423`endif
5424
5425`endif
5426
5427`endif
5428
5429 end
5430 endtask
5431
5432
5433 task slam_MraRow1_core7_thread4;
5434 input [127:0] value;
5435 reg [5:0] tid;
5436 integer junk;
5437
5438 begin
5439`ifdef AXIS_EMUL_COSIM
5440//Do Nothing
5441`else
5442`ifdef GATESIM
5443//Do Nothing
5444`else
5445`ifdef CORE_7
5446 value[82] = ^value[40:0];
5447 value[83] = ^value[81:41];
5448 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[1]" );
5449 `SPC7.mmu.mra1.array.mem[1] <= value;
5450`endif
5451
5452`endif
5453
5454`endif
5455
5456 end
5457 endtask
5458
5459
5460 task slam_MraRow1_core7_thread5;
5461 input [127:0] value;
5462 reg [5:0] tid;
5463 integer junk;
5464
5465 begin
5466`ifdef AXIS_EMUL_COSIM
5467//Do Nothing
5468`else
5469`ifdef GATESIM
5470//Do Nothing
5471`else
5472`ifdef CORE_7
5473 value[82] = ^value[40:0];
5474 value[83] = ^value[81:41];
5475 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[9]" );
5476 `SPC7.mmu.mra1.array.mem[9] <= value;
5477`endif
5478
5479`endif
5480
5481`endif
5482
5483 end
5484 endtask
5485
5486
5487 task slam_MraRow1_core7_thread6;
5488 input [127:0] value;
5489 reg [5:0] tid;
5490 integer junk;
5491
5492 begin
5493`ifdef AXIS_EMUL_COSIM
5494//Do Nothing
5495`else
5496`ifdef GATESIM
5497//Do Nothing
5498`else
5499`ifdef CORE_7
5500 value[82] = ^value[40:0];
5501 value[83] = ^value[81:41];
5502 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[17]" );
5503 `SPC7.mmu.mra1.array.mem[17] <= value;
5504`endif
5505
5506`endif
5507
5508`endif
5509
5510 end
5511 endtask
5512
5513
5514 task slam_MraRow1_core7_thread7;
5515 input [127:0] value;
5516 reg [5:0] tid;
5517 integer junk;
5518
5519 begin
5520`ifdef AXIS_EMUL_COSIM
5521//Do Nothing
5522`else
5523`ifdef GATESIM
5524//Do Nothing
5525`else
5526`ifdef CORE_7
5527 value[82] = ^value[40:0];
5528 value[83] = ^value[81:41];
5529 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[25]" );
5530 `SPC7.mmu.mra1.array.mem[25] <= value;
5531`endif
5532
5533`endif
5534
5535`endif
5536
5537 end
5538 endtask
5539
5540
5541 task slam_MraRow2_core0_thread0;
5542 input [127:0] value;
5543 reg [5:0] tid;
5544 integer junk;
5545
5546 begin
5547`ifdef AXIS_EMUL_COSIM
5548//Do Nothing
5549`else
5550`ifdef GATESIM
5551//Do Nothing
5552`else
5553`ifdef CORE_0
5554 value[82] = ^value[40:0];
5555 value[83] = ^value[81:41];
5556 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
5557 `SPC0.mmu.mra0.array.mem[2] <= value;
5558`endif
5559
5560`endif
5561
5562`endif
5563
5564 end
5565 endtask
5566
5567
5568 task slam_MraRow2_core0_thread1;
5569 input [127:0] value;
5570 reg [5:0] tid;
5571 integer junk;
5572
5573 begin
5574`ifdef AXIS_EMUL_COSIM
5575//Do Nothing
5576`else
5577`ifdef GATESIM
5578//Do Nothing
5579`else
5580`ifdef CORE_0
5581 value[82] = ^value[40:0];
5582 value[83] = ^value[81:41];
5583 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
5584 `SPC0.mmu.mra0.array.mem[10] <= value;
5585`endif
5586
5587`endif
5588
5589`endif
5590
5591 end
5592 endtask
5593
5594
5595 task slam_MraRow2_core0_thread2;
5596 input [127:0] value;
5597 reg [5:0] tid;
5598 integer junk;
5599
5600 begin
5601`ifdef AXIS_EMUL_COSIM
5602//Do Nothing
5603`else
5604`ifdef GATESIM
5605//Do Nothing
5606`else
5607`ifdef CORE_0
5608 value[82] = ^value[40:0];
5609 value[83] = ^value[81:41];
5610 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
5611 `SPC0.mmu.mra0.array.mem[18] <= value;
5612`endif
5613
5614`endif
5615
5616`endif
5617
5618 end
5619 endtask
5620
5621
5622 task slam_MraRow2_core0_thread3;
5623 input [127:0] value;
5624 reg [5:0] tid;
5625 integer junk;
5626
5627 begin
5628`ifdef AXIS_EMUL_COSIM
5629//Do Nothing
5630`else
5631`ifdef GATESIM
5632//Do Nothing
5633`else
5634`ifdef CORE_0
5635 value[82] = ^value[40:0];
5636 value[83] = ^value[81:41];
5637 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
5638 `SPC0.mmu.mra0.array.mem[26] <= value;
5639`endif
5640
5641`endif
5642
5643`endif
5644
5645 end
5646 endtask
5647
5648
5649 task slam_MraRow2_core0_thread4;
5650 input [127:0] value;
5651 reg [5:0] tid;
5652 integer junk;
5653
5654 begin
5655`ifdef AXIS_EMUL_COSIM
5656//Do Nothing
5657`else
5658`ifdef GATESIM
5659//Do Nothing
5660`else
5661`ifdef CORE_0
5662 value[82] = ^value[40:0];
5663 value[83] = ^value[81:41];
5664 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
5665 `SPC0.mmu.mra1.array.mem[2] <= value;
5666`endif
5667
5668`endif
5669
5670`endif
5671
5672 end
5673 endtask
5674
5675
5676 task slam_MraRow2_core0_thread5;
5677 input [127:0] value;
5678 reg [5:0] tid;
5679 integer junk;
5680
5681 begin
5682`ifdef AXIS_EMUL_COSIM
5683//Do Nothing
5684`else
5685`ifdef GATESIM
5686//Do Nothing
5687`else
5688`ifdef CORE_0
5689 value[82] = ^value[40:0];
5690 value[83] = ^value[81:41];
5691 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
5692 `SPC0.mmu.mra1.array.mem[10] <= value;
5693`endif
5694
5695`endif
5696
5697`endif
5698
5699 end
5700 endtask
5701
5702
5703 task slam_MraRow2_core0_thread6;
5704 input [127:0] value;
5705 reg [5:0] tid;
5706 integer junk;
5707
5708 begin
5709`ifdef AXIS_EMUL_COSIM
5710//Do Nothing
5711`else
5712`ifdef GATESIM
5713//Do Nothing
5714`else
5715`ifdef CORE_0
5716 value[82] = ^value[40:0];
5717 value[83] = ^value[81:41];
5718 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
5719 `SPC0.mmu.mra1.array.mem[18] <= value;
5720`endif
5721
5722`endif
5723
5724`endif
5725
5726 end
5727 endtask
5728
5729
5730 task slam_MraRow2_core0_thread7;
5731 input [127:0] value;
5732 reg [5:0] tid;
5733 integer junk;
5734
5735 begin
5736`ifdef AXIS_EMUL_COSIM
5737//Do Nothing
5738`else
5739`ifdef GATESIM
5740//Do Nothing
5741`else
5742`ifdef CORE_0
5743 value[82] = ^value[40:0];
5744 value[83] = ^value[81:41];
5745 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
5746 `SPC0.mmu.mra1.array.mem[26] <= value;
5747`endif
5748
5749`endif
5750
5751`endif
5752
5753 end
5754 endtask
5755
5756
5757 task slam_MraRow2_core1_thread0;
5758 input [127:0] value;
5759 reg [5:0] tid;
5760 integer junk;
5761
5762 begin
5763`ifdef AXIS_EMUL_COSIM
5764//Do Nothing
5765`else
5766`ifdef GATESIM
5767//Do Nothing
5768`else
5769`ifdef CORE_1
5770 value[82] = ^value[40:0];
5771 value[83] = ^value[81:41];
5772 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
5773 `SPC1.mmu.mra0.array.mem[2] <= value;
5774`endif
5775
5776`endif
5777
5778`endif
5779
5780 end
5781 endtask
5782
5783
5784 task slam_MraRow2_core1_thread1;
5785 input [127:0] value;
5786 reg [5:0] tid;
5787 integer junk;
5788
5789 begin
5790`ifdef AXIS_EMUL_COSIM
5791//Do Nothing
5792`else
5793`ifdef GATESIM
5794//Do Nothing
5795`else
5796`ifdef CORE_1
5797 value[82] = ^value[40:0];
5798 value[83] = ^value[81:41];
5799 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
5800 `SPC1.mmu.mra0.array.mem[10] <= value;
5801`endif
5802
5803`endif
5804
5805`endif
5806
5807 end
5808 endtask
5809
5810
5811 task slam_MraRow2_core1_thread2;
5812 input [127:0] value;
5813 reg [5:0] tid;
5814 integer junk;
5815
5816 begin
5817`ifdef AXIS_EMUL_COSIM
5818//Do Nothing
5819`else
5820`ifdef GATESIM
5821//Do Nothing
5822`else
5823`ifdef CORE_1
5824 value[82] = ^value[40:0];
5825 value[83] = ^value[81:41];
5826 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
5827 `SPC1.mmu.mra0.array.mem[18] <= value;
5828`endif
5829
5830`endif
5831
5832`endif
5833
5834 end
5835 endtask
5836
5837
5838 task slam_MraRow2_core1_thread3;
5839 input [127:0] value;
5840 reg [5:0] tid;
5841 integer junk;
5842
5843 begin
5844`ifdef AXIS_EMUL_COSIM
5845//Do Nothing
5846`else
5847`ifdef GATESIM
5848//Do Nothing
5849`else
5850`ifdef CORE_1
5851 value[82] = ^value[40:0];
5852 value[83] = ^value[81:41];
5853 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
5854 `SPC1.mmu.mra0.array.mem[26] <= value;
5855`endif
5856
5857`endif
5858
5859`endif
5860
5861 end
5862 endtask
5863
5864
5865 task slam_MraRow2_core1_thread4;
5866 input [127:0] value;
5867 reg [5:0] tid;
5868 integer junk;
5869
5870 begin
5871`ifdef AXIS_EMUL_COSIM
5872//Do Nothing
5873`else
5874`ifdef GATESIM
5875//Do Nothing
5876`else
5877`ifdef CORE_1
5878 value[82] = ^value[40:0];
5879 value[83] = ^value[81:41];
5880 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
5881 `SPC1.mmu.mra1.array.mem[2] <= value;
5882`endif
5883
5884`endif
5885
5886`endif
5887
5888 end
5889 endtask
5890
5891
5892 task slam_MraRow2_core1_thread5;
5893 input [127:0] value;
5894 reg [5:0] tid;
5895 integer junk;
5896
5897 begin
5898`ifdef AXIS_EMUL_COSIM
5899//Do Nothing
5900`else
5901`ifdef GATESIM
5902//Do Nothing
5903`else
5904`ifdef CORE_1
5905 value[82] = ^value[40:0];
5906 value[83] = ^value[81:41];
5907 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
5908 `SPC1.mmu.mra1.array.mem[10] <= value;
5909`endif
5910
5911`endif
5912
5913`endif
5914
5915 end
5916 endtask
5917
5918
5919 task slam_MraRow2_core1_thread6;
5920 input [127:0] value;
5921 reg [5:0] tid;
5922 integer junk;
5923
5924 begin
5925`ifdef AXIS_EMUL_COSIM
5926//Do Nothing
5927`else
5928`ifdef GATESIM
5929//Do Nothing
5930`else
5931`ifdef CORE_1
5932 value[82] = ^value[40:0];
5933 value[83] = ^value[81:41];
5934 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
5935 `SPC1.mmu.mra1.array.mem[18] <= value;
5936`endif
5937
5938`endif
5939
5940`endif
5941
5942 end
5943 endtask
5944
5945
5946 task slam_MraRow2_core1_thread7;
5947 input [127:0] value;
5948 reg [5:0] tid;
5949 integer junk;
5950
5951 begin
5952`ifdef AXIS_EMUL_COSIM
5953//Do Nothing
5954`else
5955`ifdef GATESIM
5956//Do Nothing
5957`else
5958`ifdef CORE_1
5959 value[82] = ^value[40:0];
5960 value[83] = ^value[81:41];
5961 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
5962 `SPC1.mmu.mra1.array.mem[26] <= value;
5963`endif
5964
5965`endif
5966
5967`endif
5968
5969 end
5970 endtask
5971
5972
5973 task slam_MraRow2_core2_thread0;
5974 input [127:0] value;
5975 reg [5:0] tid;
5976 integer junk;
5977
5978 begin
5979`ifdef AXIS_EMUL_COSIM
5980//Do Nothing
5981`else
5982`ifdef GATESIM
5983//Do Nothing
5984`else
5985`ifdef CORE_2
5986 value[82] = ^value[40:0];
5987 value[83] = ^value[81:41];
5988 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
5989 `SPC2.mmu.mra0.array.mem[2] <= value;
5990`endif
5991
5992`endif
5993
5994`endif
5995
5996 end
5997 endtask
5998
5999
6000 task slam_MraRow2_core2_thread1;
6001 input [127:0] value;
6002 reg [5:0] tid;
6003 integer junk;
6004
6005 begin
6006`ifdef AXIS_EMUL_COSIM
6007//Do Nothing
6008`else
6009`ifdef GATESIM
6010//Do Nothing
6011`else
6012`ifdef CORE_2
6013 value[82] = ^value[40:0];
6014 value[83] = ^value[81:41];
6015 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
6016 `SPC2.mmu.mra0.array.mem[10] <= value;
6017`endif
6018
6019`endif
6020
6021`endif
6022
6023 end
6024 endtask
6025
6026
6027 task slam_MraRow2_core2_thread2;
6028 input [127:0] value;
6029 reg [5:0] tid;
6030 integer junk;
6031
6032 begin
6033`ifdef AXIS_EMUL_COSIM
6034//Do Nothing
6035`else
6036`ifdef GATESIM
6037//Do Nothing
6038`else
6039`ifdef CORE_2
6040 value[82] = ^value[40:0];
6041 value[83] = ^value[81:41];
6042 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
6043 `SPC2.mmu.mra0.array.mem[18] <= value;
6044`endif
6045
6046`endif
6047
6048`endif
6049
6050 end
6051 endtask
6052
6053
6054 task slam_MraRow2_core2_thread3;
6055 input [127:0] value;
6056 reg [5:0] tid;
6057 integer junk;
6058
6059 begin
6060`ifdef AXIS_EMUL_COSIM
6061//Do Nothing
6062`else
6063`ifdef GATESIM
6064//Do Nothing
6065`else
6066`ifdef CORE_2
6067 value[82] = ^value[40:0];
6068 value[83] = ^value[81:41];
6069 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
6070 `SPC2.mmu.mra0.array.mem[26] <= value;
6071`endif
6072
6073`endif
6074
6075`endif
6076
6077 end
6078 endtask
6079
6080
6081 task slam_MraRow2_core2_thread4;
6082 input [127:0] value;
6083 reg [5:0] tid;
6084 integer junk;
6085
6086 begin
6087`ifdef AXIS_EMUL_COSIM
6088//Do Nothing
6089`else
6090`ifdef GATESIM
6091//Do Nothing
6092`else
6093`ifdef CORE_2
6094 value[82] = ^value[40:0];
6095 value[83] = ^value[81:41];
6096 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
6097 `SPC2.mmu.mra1.array.mem[2] <= value;
6098`endif
6099
6100`endif
6101
6102`endif
6103
6104 end
6105 endtask
6106
6107
6108 task slam_MraRow2_core2_thread5;
6109 input [127:0] value;
6110 reg [5:0] tid;
6111 integer junk;
6112
6113 begin
6114`ifdef AXIS_EMUL_COSIM
6115//Do Nothing
6116`else
6117`ifdef GATESIM
6118//Do Nothing
6119`else
6120`ifdef CORE_2
6121 value[82] = ^value[40:0];
6122 value[83] = ^value[81:41];
6123 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
6124 `SPC2.mmu.mra1.array.mem[10] <= value;
6125`endif
6126
6127`endif
6128
6129`endif
6130
6131 end
6132 endtask
6133
6134
6135 task slam_MraRow2_core2_thread6;
6136 input [127:0] value;
6137 reg [5:0] tid;
6138 integer junk;
6139
6140 begin
6141`ifdef AXIS_EMUL_COSIM
6142//Do Nothing
6143`else
6144`ifdef GATESIM
6145//Do Nothing
6146`else
6147`ifdef CORE_2
6148 value[82] = ^value[40:0];
6149 value[83] = ^value[81:41];
6150 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
6151 `SPC2.mmu.mra1.array.mem[18] <= value;
6152`endif
6153
6154`endif
6155
6156`endif
6157
6158 end
6159 endtask
6160
6161
6162 task slam_MraRow2_core2_thread7;
6163 input [127:0] value;
6164 reg [5:0] tid;
6165 integer junk;
6166
6167 begin
6168`ifdef AXIS_EMUL_COSIM
6169//Do Nothing
6170`else
6171`ifdef GATESIM
6172//Do Nothing
6173`else
6174`ifdef CORE_2
6175 value[82] = ^value[40:0];
6176 value[83] = ^value[81:41];
6177 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
6178 `SPC2.mmu.mra1.array.mem[26] <= value;
6179`endif
6180
6181`endif
6182
6183`endif
6184
6185 end
6186 endtask
6187
6188
6189 task slam_MraRow2_core3_thread0;
6190 input [127:0] value;
6191 reg [5:0] tid;
6192 integer junk;
6193
6194 begin
6195`ifdef AXIS_EMUL_COSIM
6196//Do Nothing
6197`else
6198`ifdef GATESIM
6199//Do Nothing
6200`else
6201`ifdef CORE_3
6202 value[82] = ^value[40:0];
6203 value[83] = ^value[81:41];
6204 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
6205 `SPC3.mmu.mra0.array.mem[2] <= value;
6206`endif
6207
6208`endif
6209
6210`endif
6211
6212 end
6213 endtask
6214
6215
6216 task slam_MraRow2_core3_thread1;
6217 input [127:0] value;
6218 reg [5:0] tid;
6219 integer junk;
6220
6221 begin
6222`ifdef AXIS_EMUL_COSIM
6223//Do Nothing
6224`else
6225`ifdef GATESIM
6226//Do Nothing
6227`else
6228`ifdef CORE_3
6229 value[82] = ^value[40:0];
6230 value[83] = ^value[81:41];
6231 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
6232 `SPC3.mmu.mra0.array.mem[10] <= value;
6233`endif
6234
6235`endif
6236
6237`endif
6238
6239 end
6240 endtask
6241
6242
6243 task slam_MraRow2_core3_thread2;
6244 input [127:0] value;
6245 reg [5:0] tid;
6246 integer junk;
6247
6248 begin
6249`ifdef AXIS_EMUL_COSIM
6250//Do Nothing
6251`else
6252`ifdef GATESIM
6253//Do Nothing
6254`else
6255`ifdef CORE_3
6256 value[82] = ^value[40:0];
6257 value[83] = ^value[81:41];
6258 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
6259 `SPC3.mmu.mra0.array.mem[18] <= value;
6260`endif
6261
6262`endif
6263
6264`endif
6265
6266 end
6267 endtask
6268
6269
6270 task slam_MraRow2_core3_thread3;
6271 input [127:0] value;
6272 reg [5:0] tid;
6273 integer junk;
6274
6275 begin
6276`ifdef AXIS_EMUL_COSIM
6277//Do Nothing
6278`else
6279`ifdef GATESIM
6280//Do Nothing
6281`else
6282`ifdef CORE_3
6283 value[82] = ^value[40:0];
6284 value[83] = ^value[81:41];
6285 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
6286 `SPC3.mmu.mra0.array.mem[26] <= value;
6287`endif
6288
6289`endif
6290
6291`endif
6292
6293 end
6294 endtask
6295
6296
6297 task slam_MraRow2_core3_thread4;
6298 input [127:0] value;
6299 reg [5:0] tid;
6300 integer junk;
6301
6302 begin
6303`ifdef AXIS_EMUL_COSIM
6304//Do Nothing
6305`else
6306`ifdef GATESIM
6307//Do Nothing
6308`else
6309`ifdef CORE_3
6310 value[82] = ^value[40:0];
6311 value[83] = ^value[81:41];
6312 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
6313 `SPC3.mmu.mra1.array.mem[2] <= value;
6314`endif
6315
6316`endif
6317
6318`endif
6319
6320 end
6321 endtask
6322
6323
6324 task slam_MraRow2_core3_thread5;
6325 input [127:0] value;
6326 reg [5:0] tid;
6327 integer junk;
6328
6329 begin
6330`ifdef AXIS_EMUL_COSIM
6331//Do Nothing
6332`else
6333`ifdef GATESIM
6334//Do Nothing
6335`else
6336`ifdef CORE_3
6337 value[82] = ^value[40:0];
6338 value[83] = ^value[81:41];
6339 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
6340 `SPC3.mmu.mra1.array.mem[10] <= value;
6341`endif
6342
6343`endif
6344
6345`endif
6346
6347 end
6348 endtask
6349
6350
6351 task slam_MraRow2_core3_thread6;
6352 input [127:0] value;
6353 reg [5:0] tid;
6354 integer junk;
6355
6356 begin
6357`ifdef AXIS_EMUL_COSIM
6358//Do Nothing
6359`else
6360`ifdef GATESIM
6361//Do Nothing
6362`else
6363`ifdef CORE_3
6364 value[82] = ^value[40:0];
6365 value[83] = ^value[81:41];
6366 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
6367 `SPC3.mmu.mra1.array.mem[18] <= value;
6368`endif
6369
6370`endif
6371
6372`endif
6373
6374 end
6375 endtask
6376
6377
6378 task slam_MraRow2_core3_thread7;
6379 input [127:0] value;
6380 reg [5:0] tid;
6381 integer junk;
6382
6383 begin
6384`ifdef AXIS_EMUL_COSIM
6385//Do Nothing
6386`else
6387`ifdef GATESIM
6388//Do Nothing
6389`else
6390`ifdef CORE_3
6391 value[82] = ^value[40:0];
6392 value[83] = ^value[81:41];
6393 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
6394 `SPC3.mmu.mra1.array.mem[26] <= value;
6395`endif
6396
6397`endif
6398
6399`endif
6400
6401 end
6402 endtask
6403
6404
6405 task slam_MraRow2_core4_thread0;
6406 input [127:0] value;
6407 reg [5:0] tid;
6408 integer junk;
6409
6410 begin
6411`ifdef AXIS_EMUL_COSIM
6412//Do Nothing
6413`else
6414`ifdef GATESIM
6415//Do Nothing
6416`else
6417`ifdef CORE_4
6418 value[82] = ^value[40:0];
6419 value[83] = ^value[81:41];
6420 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
6421 `SPC4.mmu.mra0.array.mem[2] <= value;
6422`endif
6423
6424`endif
6425
6426`endif
6427
6428 end
6429 endtask
6430
6431
6432 task slam_MraRow2_core4_thread1;
6433 input [127:0] value;
6434 reg [5:0] tid;
6435 integer junk;
6436
6437 begin
6438`ifdef AXIS_EMUL_COSIM
6439//Do Nothing
6440`else
6441`ifdef GATESIM
6442//Do Nothing
6443`else
6444`ifdef CORE_4
6445 value[82] = ^value[40:0];
6446 value[83] = ^value[81:41];
6447 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
6448 `SPC4.mmu.mra0.array.mem[10] <= value;
6449`endif
6450
6451`endif
6452
6453`endif
6454
6455 end
6456 endtask
6457
6458
6459 task slam_MraRow2_core4_thread2;
6460 input [127:0] value;
6461 reg [5:0] tid;
6462 integer junk;
6463
6464 begin
6465`ifdef AXIS_EMUL_COSIM
6466//Do Nothing
6467`else
6468`ifdef GATESIM
6469//Do Nothing
6470`else
6471`ifdef CORE_4
6472 value[82] = ^value[40:0];
6473 value[83] = ^value[81:41];
6474 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
6475 `SPC4.mmu.mra0.array.mem[18] <= value;
6476`endif
6477
6478`endif
6479
6480`endif
6481
6482 end
6483 endtask
6484
6485
6486 task slam_MraRow2_core4_thread3;
6487 input [127:0] value;
6488 reg [5:0] tid;
6489 integer junk;
6490
6491 begin
6492`ifdef AXIS_EMUL_COSIM
6493//Do Nothing
6494`else
6495`ifdef GATESIM
6496//Do Nothing
6497`else
6498`ifdef CORE_4
6499 value[82] = ^value[40:0];
6500 value[83] = ^value[81:41];
6501 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
6502 `SPC4.mmu.mra0.array.mem[26] <= value;
6503`endif
6504
6505`endif
6506
6507`endif
6508
6509 end
6510 endtask
6511
6512
6513 task slam_MraRow2_core4_thread4;
6514 input [127:0] value;
6515 reg [5:0] tid;
6516 integer junk;
6517
6518 begin
6519`ifdef AXIS_EMUL_COSIM
6520//Do Nothing
6521`else
6522`ifdef GATESIM
6523//Do Nothing
6524`else
6525`ifdef CORE_4
6526 value[82] = ^value[40:0];
6527 value[83] = ^value[81:41];
6528 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
6529 `SPC4.mmu.mra1.array.mem[2] <= value;
6530`endif
6531
6532`endif
6533
6534`endif
6535
6536 end
6537 endtask
6538
6539
6540 task slam_MraRow2_core4_thread5;
6541 input [127:0] value;
6542 reg [5:0] tid;
6543 integer junk;
6544
6545 begin
6546`ifdef AXIS_EMUL_COSIM
6547//Do Nothing
6548`else
6549`ifdef GATESIM
6550//Do Nothing
6551`else
6552`ifdef CORE_4
6553 value[82] = ^value[40:0];
6554 value[83] = ^value[81:41];
6555 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
6556 `SPC4.mmu.mra1.array.mem[10] <= value;
6557`endif
6558
6559`endif
6560
6561`endif
6562
6563 end
6564 endtask
6565
6566
6567 task slam_MraRow2_core4_thread6;
6568 input [127:0] value;
6569 reg [5:0] tid;
6570 integer junk;
6571
6572 begin
6573`ifdef AXIS_EMUL_COSIM
6574//Do Nothing
6575`else
6576`ifdef GATESIM
6577//Do Nothing
6578`else
6579`ifdef CORE_4
6580 value[82] = ^value[40:0];
6581 value[83] = ^value[81:41];
6582 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
6583 `SPC4.mmu.mra1.array.mem[18] <= value;
6584`endif
6585
6586`endif
6587
6588`endif
6589
6590 end
6591 endtask
6592
6593
6594 task slam_MraRow2_core4_thread7;
6595 input [127:0] value;
6596 reg [5:0] tid;
6597 integer junk;
6598
6599 begin
6600`ifdef AXIS_EMUL_COSIM
6601//Do Nothing
6602`else
6603`ifdef GATESIM
6604//Do Nothing
6605`else
6606`ifdef CORE_4
6607 value[82] = ^value[40:0];
6608 value[83] = ^value[81:41];
6609 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
6610 `SPC4.mmu.mra1.array.mem[26] <= value;
6611`endif
6612
6613`endif
6614
6615`endif
6616
6617 end
6618 endtask
6619
6620
6621 task slam_MraRow2_core5_thread0;
6622 input [127:0] value;
6623 reg [5:0] tid;
6624 integer junk;
6625
6626 begin
6627`ifdef AXIS_EMUL_COSIM
6628//Do Nothing
6629`else
6630`ifdef GATESIM
6631//Do Nothing
6632`else
6633`ifdef CORE_5
6634 value[82] = ^value[40:0];
6635 value[83] = ^value[81:41];
6636 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
6637 `SPC5.mmu.mra0.array.mem[2] <= value;
6638`endif
6639
6640`endif
6641
6642`endif
6643
6644 end
6645 endtask
6646
6647
6648 task slam_MraRow2_core5_thread1;
6649 input [127:0] value;
6650 reg [5:0] tid;
6651 integer junk;
6652
6653 begin
6654`ifdef AXIS_EMUL_COSIM
6655//Do Nothing
6656`else
6657`ifdef GATESIM
6658//Do Nothing
6659`else
6660`ifdef CORE_5
6661 value[82] = ^value[40:0];
6662 value[83] = ^value[81:41];
6663 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
6664 `SPC5.mmu.mra0.array.mem[10] <= value;
6665`endif
6666
6667`endif
6668
6669`endif
6670
6671 end
6672 endtask
6673
6674
6675 task slam_MraRow2_core5_thread2;
6676 input [127:0] value;
6677 reg [5:0] tid;
6678 integer junk;
6679
6680 begin
6681`ifdef AXIS_EMUL_COSIM
6682//Do Nothing
6683`else
6684`ifdef GATESIM
6685//Do Nothing
6686`else
6687`ifdef CORE_5
6688 value[82] = ^value[40:0];
6689 value[83] = ^value[81:41];
6690 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
6691 `SPC5.mmu.mra0.array.mem[18] <= value;
6692`endif
6693
6694`endif
6695
6696`endif
6697
6698 end
6699 endtask
6700
6701
6702 task slam_MraRow2_core5_thread3;
6703 input [127:0] value;
6704 reg [5:0] tid;
6705 integer junk;
6706
6707 begin
6708`ifdef AXIS_EMUL_COSIM
6709//Do Nothing
6710`else
6711`ifdef GATESIM
6712//Do Nothing
6713`else
6714`ifdef CORE_5
6715 value[82] = ^value[40:0];
6716 value[83] = ^value[81:41];
6717 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
6718 `SPC5.mmu.mra0.array.mem[26] <= value;
6719`endif
6720
6721`endif
6722
6723`endif
6724
6725 end
6726 endtask
6727
6728
6729 task slam_MraRow2_core5_thread4;
6730 input [127:0] value;
6731 reg [5:0] tid;
6732 integer junk;
6733
6734 begin
6735`ifdef AXIS_EMUL_COSIM
6736//Do Nothing
6737`else
6738`ifdef GATESIM
6739//Do Nothing
6740`else
6741`ifdef CORE_5
6742 value[82] = ^value[40:0];
6743 value[83] = ^value[81:41];
6744 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
6745 `SPC5.mmu.mra1.array.mem[2] <= value;
6746`endif
6747
6748`endif
6749
6750`endif
6751
6752 end
6753 endtask
6754
6755
6756 task slam_MraRow2_core5_thread5;
6757 input [127:0] value;
6758 reg [5:0] tid;
6759 integer junk;
6760
6761 begin
6762`ifdef AXIS_EMUL_COSIM
6763//Do Nothing
6764`else
6765`ifdef GATESIM
6766//Do Nothing
6767`else
6768`ifdef CORE_5
6769 value[82] = ^value[40:0];
6770 value[83] = ^value[81:41];
6771 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
6772 `SPC5.mmu.mra1.array.mem[10] <= value;
6773`endif
6774
6775`endif
6776
6777`endif
6778
6779 end
6780 endtask
6781
6782
6783 task slam_MraRow2_core5_thread6;
6784 input [127:0] value;
6785 reg [5:0] tid;
6786 integer junk;
6787
6788 begin
6789`ifdef AXIS_EMUL_COSIM
6790//Do Nothing
6791`else
6792`ifdef GATESIM
6793//Do Nothing
6794`else
6795`ifdef CORE_5
6796 value[82] = ^value[40:0];
6797 value[83] = ^value[81:41];
6798 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
6799 `SPC5.mmu.mra1.array.mem[18] <= value;
6800`endif
6801
6802`endif
6803
6804`endif
6805
6806 end
6807 endtask
6808
6809
6810 task slam_MraRow2_core5_thread7;
6811 input [127:0] value;
6812 reg [5:0] tid;
6813 integer junk;
6814
6815 begin
6816`ifdef AXIS_EMUL_COSIM
6817//Do Nothing
6818`else
6819`ifdef GATESIM
6820//Do Nothing
6821`else
6822`ifdef CORE_5
6823 value[82] = ^value[40:0];
6824 value[83] = ^value[81:41];
6825 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
6826 `SPC5.mmu.mra1.array.mem[26] <= value;
6827`endif
6828
6829`endif
6830
6831`endif
6832
6833 end
6834 endtask
6835
6836
6837 task slam_MraRow2_core6_thread0;
6838 input [127:0] value;
6839 reg [5:0] tid;
6840 integer junk;
6841
6842 begin
6843`ifdef AXIS_EMUL_COSIM
6844//Do Nothing
6845`else
6846`ifdef GATESIM
6847//Do Nothing
6848`else
6849`ifdef CORE_6
6850 value[82] = ^value[40:0];
6851 value[83] = ^value[81:41];
6852 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
6853 `SPC6.mmu.mra0.array.mem[2] <= value;
6854`endif
6855
6856`endif
6857
6858`endif
6859
6860 end
6861 endtask
6862
6863
6864 task slam_MraRow2_core6_thread1;
6865 input [127:0] value;
6866 reg [5:0] tid;
6867 integer junk;
6868
6869 begin
6870`ifdef AXIS_EMUL_COSIM
6871//Do Nothing
6872`else
6873`ifdef GATESIM
6874//Do Nothing
6875`else
6876`ifdef CORE_6
6877 value[82] = ^value[40:0];
6878 value[83] = ^value[81:41];
6879 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
6880 `SPC6.mmu.mra0.array.mem[10] <= value;
6881`endif
6882
6883`endif
6884
6885`endif
6886
6887 end
6888 endtask
6889
6890
6891 task slam_MraRow2_core6_thread2;
6892 input [127:0] value;
6893 reg [5:0] tid;
6894 integer junk;
6895
6896 begin
6897`ifdef AXIS_EMUL_COSIM
6898//Do Nothing
6899`else
6900`ifdef GATESIM
6901//Do Nothing
6902`else
6903`ifdef CORE_6
6904 value[82] = ^value[40:0];
6905 value[83] = ^value[81:41];
6906 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
6907 `SPC6.mmu.mra0.array.mem[18] <= value;
6908`endif
6909
6910`endif
6911
6912`endif
6913
6914 end
6915 endtask
6916
6917
6918 task slam_MraRow2_core6_thread3;
6919 input [127:0] value;
6920 reg [5:0] tid;
6921 integer junk;
6922
6923 begin
6924`ifdef AXIS_EMUL_COSIM
6925//Do Nothing
6926`else
6927`ifdef GATESIM
6928//Do Nothing
6929`else
6930`ifdef CORE_6
6931 value[82] = ^value[40:0];
6932 value[83] = ^value[81:41];
6933 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
6934 `SPC6.mmu.mra0.array.mem[26] <= value;
6935`endif
6936
6937`endif
6938
6939`endif
6940
6941 end
6942 endtask
6943
6944
6945 task slam_MraRow2_core6_thread4;
6946 input [127:0] value;
6947 reg [5:0] tid;
6948 integer junk;
6949
6950 begin
6951`ifdef AXIS_EMUL_COSIM
6952//Do Nothing
6953`else
6954`ifdef GATESIM
6955//Do Nothing
6956`else
6957`ifdef CORE_6
6958 value[82] = ^value[40:0];
6959 value[83] = ^value[81:41];
6960 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
6961 `SPC6.mmu.mra1.array.mem[2] <= value;
6962`endif
6963
6964`endif
6965
6966`endif
6967
6968 end
6969 endtask
6970
6971
6972 task slam_MraRow2_core6_thread5;
6973 input [127:0] value;
6974 reg [5:0] tid;
6975 integer junk;
6976
6977 begin
6978`ifdef AXIS_EMUL_COSIM
6979//Do Nothing
6980`else
6981`ifdef GATESIM
6982//Do Nothing
6983`else
6984`ifdef CORE_6
6985 value[82] = ^value[40:0];
6986 value[83] = ^value[81:41];
6987 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
6988 `SPC6.mmu.mra1.array.mem[10] <= value;
6989`endif
6990
6991`endif
6992
6993`endif
6994
6995 end
6996 endtask
6997
6998
6999 task slam_MraRow2_core6_thread6;
7000 input [127:0] value;
7001 reg [5:0] tid;
7002 integer junk;
7003
7004 begin
7005`ifdef AXIS_EMUL_COSIM
7006//Do Nothing
7007`else
7008`ifdef GATESIM
7009//Do Nothing
7010`else
7011`ifdef CORE_6
7012 value[82] = ^value[40:0];
7013 value[83] = ^value[81:41];
7014 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
7015 `SPC6.mmu.mra1.array.mem[18] <= value;
7016`endif
7017
7018`endif
7019
7020`endif
7021
7022 end
7023 endtask
7024
7025
7026 task slam_MraRow2_core6_thread7;
7027 input [127:0] value;
7028 reg [5:0] tid;
7029 integer junk;
7030
7031 begin
7032`ifdef AXIS_EMUL_COSIM
7033//Do Nothing
7034`else
7035`ifdef GATESIM
7036//Do Nothing
7037`else
7038`ifdef CORE_6
7039 value[82] = ^value[40:0];
7040 value[83] = ^value[81:41];
7041 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
7042 `SPC6.mmu.mra1.array.mem[26] <= value;
7043`endif
7044
7045`endif
7046
7047`endif
7048
7049 end
7050 endtask
7051
7052
7053 task slam_MraRow2_core7_thread0;
7054 input [127:0] value;
7055 reg [5:0] tid;
7056 integer junk;
7057
7058 begin
7059`ifdef AXIS_EMUL_COSIM
7060//Do Nothing
7061`else
7062`ifdef GATESIM
7063//Do Nothing
7064`else
7065`ifdef CORE_7
7066 value[82] = ^value[40:0];
7067 value[83] = ^value[81:41];
7068 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[2]" );
7069 `SPC7.mmu.mra0.array.mem[2] <= value;
7070`endif
7071
7072`endif
7073
7074`endif
7075
7076 end
7077 endtask
7078
7079
7080 task slam_MraRow2_core7_thread1;
7081 input [127:0] value;
7082 reg [5:0] tid;
7083 integer junk;
7084
7085 begin
7086`ifdef AXIS_EMUL_COSIM
7087//Do Nothing
7088`else
7089`ifdef GATESIM
7090//Do Nothing
7091`else
7092`ifdef CORE_7
7093 value[82] = ^value[40:0];
7094 value[83] = ^value[81:41];
7095 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[10]" );
7096 `SPC7.mmu.mra0.array.mem[10] <= value;
7097`endif
7098
7099`endif
7100
7101`endif
7102
7103 end
7104 endtask
7105
7106
7107 task slam_MraRow2_core7_thread2;
7108 input [127:0] value;
7109 reg [5:0] tid;
7110 integer junk;
7111
7112 begin
7113`ifdef AXIS_EMUL_COSIM
7114//Do Nothing
7115`else
7116`ifdef GATESIM
7117//Do Nothing
7118`else
7119`ifdef CORE_7
7120 value[82] = ^value[40:0];
7121 value[83] = ^value[81:41];
7122 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[18]" );
7123 `SPC7.mmu.mra0.array.mem[18] <= value;
7124`endif
7125
7126`endif
7127
7128`endif
7129
7130 end
7131 endtask
7132
7133
7134 task slam_MraRow2_core7_thread3;
7135 input [127:0] value;
7136 reg [5:0] tid;
7137 integer junk;
7138
7139 begin
7140`ifdef AXIS_EMUL_COSIM
7141//Do Nothing
7142`else
7143`ifdef GATESIM
7144//Do Nothing
7145`else
7146`ifdef CORE_7
7147 value[82] = ^value[40:0];
7148 value[83] = ^value[81:41];
7149 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[26]" );
7150 `SPC7.mmu.mra0.array.mem[26] <= value;
7151`endif
7152
7153`endif
7154
7155`endif
7156
7157 end
7158 endtask
7159
7160
7161 task slam_MraRow2_core7_thread4;
7162 input [127:0] value;
7163 reg [5:0] tid;
7164 integer junk;
7165
7166 begin
7167`ifdef AXIS_EMUL_COSIM
7168//Do Nothing
7169`else
7170`ifdef GATESIM
7171//Do Nothing
7172`else
7173`ifdef CORE_7
7174 value[82] = ^value[40:0];
7175 value[83] = ^value[81:41];
7176 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[2]" );
7177 `SPC7.mmu.mra1.array.mem[2] <= value;
7178`endif
7179
7180`endif
7181
7182`endif
7183
7184 end
7185 endtask
7186
7187
7188 task slam_MraRow2_core7_thread5;
7189 input [127:0] value;
7190 reg [5:0] tid;
7191 integer junk;
7192
7193 begin
7194`ifdef AXIS_EMUL_COSIM
7195//Do Nothing
7196`else
7197`ifdef GATESIM
7198//Do Nothing
7199`else
7200`ifdef CORE_7
7201 value[82] = ^value[40:0];
7202 value[83] = ^value[81:41];
7203 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[10]" );
7204 `SPC7.mmu.mra1.array.mem[10] <= value;
7205`endif
7206
7207`endif
7208
7209`endif
7210
7211 end
7212 endtask
7213
7214
7215 task slam_MraRow2_core7_thread6;
7216 input [127:0] value;
7217 reg [5:0] tid;
7218 integer junk;
7219
7220 begin
7221`ifdef AXIS_EMUL_COSIM
7222//Do Nothing
7223`else
7224`ifdef GATESIM
7225//Do Nothing
7226`else
7227`ifdef CORE_7
7228 value[82] = ^value[40:0];
7229 value[83] = ^value[81:41];
7230 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[18]" );
7231 `SPC7.mmu.mra1.array.mem[18] <= value;
7232`endif
7233
7234`endif
7235
7236`endif
7237
7238 end
7239 endtask
7240
7241
7242 task slam_MraRow2_core7_thread7;
7243 input [127:0] value;
7244 reg [5:0] tid;
7245 integer junk;
7246
7247 begin
7248`ifdef AXIS_EMUL_COSIM
7249//Do Nothing
7250`else
7251`ifdef GATESIM
7252//Do Nothing
7253`else
7254`ifdef CORE_7
7255 value[82] = ^value[40:0];
7256 value[83] = ^value[81:41];
7257 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[26]" );
7258 `SPC7.mmu.mra1.array.mem[26] <= value;
7259`endif
7260
7261`endif
7262
7263`endif
7264
7265 end
7266 endtask
7267
7268
7269 task slam_MraRow3_core0_thread0;
7270 input [127:0] value;
7271 reg [5:0] tid;
7272 integer junk;
7273
7274 begin
7275`ifdef AXIS_EMUL_COSIM
7276//Do Nothing
7277`else
7278`ifdef GATESIM
7279//Do Nothing
7280`else
7281`ifdef CORE_0
7282 value[82] = ^value[40:0];
7283 value[83] = ^value[81:41];
7284 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
7285 `SPC0.mmu.mra0.array.mem[3] <= value;
7286`endif
7287
7288`endif
7289
7290`endif
7291
7292 end
7293 endtask
7294
7295
7296 task slam_MraRow3_core0_thread1;
7297 input [127:0] value;
7298 reg [5:0] tid;
7299 integer junk;
7300
7301 begin
7302`ifdef AXIS_EMUL_COSIM
7303//Do Nothing
7304`else
7305`ifdef GATESIM
7306//Do Nothing
7307`else
7308`ifdef CORE_0
7309 value[82] = ^value[40:0];
7310 value[83] = ^value[81:41];
7311 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
7312 `SPC0.mmu.mra0.array.mem[11] <= value;
7313`endif
7314
7315`endif
7316
7317`endif
7318
7319 end
7320 endtask
7321
7322
7323 task slam_MraRow3_core0_thread2;
7324 input [127:0] value;
7325 reg [5:0] tid;
7326 integer junk;
7327
7328 begin
7329`ifdef AXIS_EMUL_COSIM
7330//Do Nothing
7331`else
7332`ifdef GATESIM
7333//Do Nothing
7334`else
7335`ifdef CORE_0
7336 value[82] = ^value[40:0];
7337 value[83] = ^value[81:41];
7338 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
7339 `SPC0.mmu.mra0.array.mem[19] <= value;
7340`endif
7341
7342`endif
7343
7344`endif
7345
7346 end
7347 endtask
7348
7349
7350 task slam_MraRow3_core0_thread3;
7351 input [127:0] value;
7352 reg [5:0] tid;
7353 integer junk;
7354
7355 begin
7356`ifdef AXIS_EMUL_COSIM
7357//Do Nothing
7358`else
7359`ifdef GATESIM
7360//Do Nothing
7361`else
7362`ifdef CORE_0
7363 value[82] = ^value[40:0];
7364 value[83] = ^value[81:41];
7365 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
7366 `SPC0.mmu.mra0.array.mem[27] <= value;
7367`endif
7368
7369`endif
7370
7371`endif
7372
7373 end
7374 endtask
7375
7376
7377 task slam_MraRow3_core0_thread4;
7378 input [127:0] value;
7379 reg [5:0] tid;
7380 integer junk;
7381
7382 begin
7383`ifdef AXIS_EMUL_COSIM
7384//Do Nothing
7385`else
7386`ifdef GATESIM
7387//Do Nothing
7388`else
7389`ifdef CORE_0
7390 value[82] = ^value[40:0];
7391 value[83] = ^value[81:41];
7392 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
7393 `SPC0.mmu.mra1.array.mem[3] <= value;
7394`endif
7395
7396`endif
7397
7398`endif
7399
7400 end
7401 endtask
7402
7403
7404 task slam_MraRow3_core0_thread5;
7405 input [127:0] value;
7406 reg [5:0] tid;
7407 integer junk;
7408
7409 begin
7410`ifdef AXIS_EMUL_COSIM
7411//Do Nothing
7412`else
7413`ifdef GATESIM
7414//Do Nothing
7415`else
7416`ifdef CORE_0
7417 value[82] = ^value[40:0];
7418 value[83] = ^value[81:41];
7419 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
7420 `SPC0.mmu.mra1.array.mem[11] <= value;
7421`endif
7422
7423`endif
7424
7425`endif
7426
7427 end
7428 endtask
7429
7430
7431 task slam_MraRow3_core0_thread6;
7432 input [127:0] value;
7433 reg [5:0] tid;
7434 integer junk;
7435
7436 begin
7437`ifdef AXIS_EMUL_COSIM
7438//Do Nothing
7439`else
7440`ifdef GATESIM
7441//Do Nothing
7442`else
7443`ifdef CORE_0
7444 value[82] = ^value[40:0];
7445 value[83] = ^value[81:41];
7446 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
7447 `SPC0.mmu.mra1.array.mem[19] <= value;
7448`endif
7449
7450`endif
7451
7452`endif
7453
7454 end
7455 endtask
7456
7457
7458 task slam_MraRow3_core0_thread7;
7459 input [127:0] value;
7460 reg [5:0] tid;
7461 integer junk;
7462
7463 begin
7464`ifdef AXIS_EMUL_COSIM
7465//Do Nothing
7466`else
7467`ifdef GATESIM
7468//Do Nothing
7469`else
7470`ifdef CORE_0
7471 value[82] = ^value[40:0];
7472 value[83] = ^value[81:41];
7473 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
7474 `SPC0.mmu.mra1.array.mem[27] <= value;
7475`endif
7476
7477`endif
7478
7479`endif
7480
7481 end
7482 endtask
7483
7484
7485 task slam_MraRow3_core1_thread0;
7486 input [127:0] value;
7487 reg [5:0] tid;
7488 integer junk;
7489
7490 begin
7491`ifdef AXIS_EMUL_COSIM
7492//Do Nothing
7493`else
7494`ifdef GATESIM
7495//Do Nothing
7496`else
7497`ifdef CORE_1
7498 value[82] = ^value[40:0];
7499 value[83] = ^value[81:41];
7500 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
7501 `SPC1.mmu.mra0.array.mem[3] <= value;
7502`endif
7503
7504`endif
7505
7506`endif
7507
7508 end
7509 endtask
7510
7511
7512 task slam_MraRow3_core1_thread1;
7513 input [127:0] value;
7514 reg [5:0] tid;
7515 integer junk;
7516
7517 begin
7518`ifdef AXIS_EMUL_COSIM
7519//Do Nothing
7520`else
7521`ifdef GATESIM
7522//Do Nothing
7523`else
7524`ifdef CORE_1
7525 value[82] = ^value[40:0];
7526 value[83] = ^value[81:41];
7527 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
7528 `SPC1.mmu.mra0.array.mem[11] <= value;
7529`endif
7530
7531`endif
7532
7533`endif
7534
7535 end
7536 endtask
7537
7538
7539 task slam_MraRow3_core1_thread2;
7540 input [127:0] value;
7541 reg [5:0] tid;
7542 integer junk;
7543
7544 begin
7545`ifdef AXIS_EMUL_COSIM
7546//Do Nothing
7547`else
7548`ifdef GATESIM
7549//Do Nothing
7550`else
7551`ifdef CORE_1
7552 value[82] = ^value[40:0];
7553 value[83] = ^value[81:41];
7554 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
7555 `SPC1.mmu.mra0.array.mem[19] <= value;
7556`endif
7557
7558`endif
7559
7560`endif
7561
7562 end
7563 endtask
7564
7565
7566 task slam_MraRow3_core1_thread3;
7567 input [127:0] value;
7568 reg [5:0] tid;
7569 integer junk;
7570
7571 begin
7572`ifdef AXIS_EMUL_COSIM
7573//Do Nothing
7574`else
7575`ifdef GATESIM
7576//Do Nothing
7577`else
7578`ifdef CORE_1
7579 value[82] = ^value[40:0];
7580 value[83] = ^value[81:41];
7581 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
7582 `SPC1.mmu.mra0.array.mem[27] <= value;
7583`endif
7584
7585`endif
7586
7587`endif
7588
7589 end
7590 endtask
7591
7592
7593 task slam_MraRow3_core1_thread4;
7594 input [127:0] value;
7595 reg [5:0] tid;
7596 integer junk;
7597
7598 begin
7599`ifdef AXIS_EMUL_COSIM
7600//Do Nothing
7601`else
7602`ifdef GATESIM
7603//Do Nothing
7604`else
7605`ifdef CORE_1
7606 value[82] = ^value[40:0];
7607 value[83] = ^value[81:41];
7608 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
7609 `SPC1.mmu.mra1.array.mem[3] <= value;
7610`endif
7611
7612`endif
7613
7614`endif
7615
7616 end
7617 endtask
7618
7619
7620 task slam_MraRow3_core1_thread5;
7621 input [127:0] value;
7622 reg [5:0] tid;
7623 integer junk;
7624
7625 begin
7626`ifdef AXIS_EMUL_COSIM
7627//Do Nothing
7628`else
7629`ifdef GATESIM
7630//Do Nothing
7631`else
7632`ifdef CORE_1
7633 value[82] = ^value[40:0];
7634 value[83] = ^value[81:41];
7635 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
7636 `SPC1.mmu.mra1.array.mem[11] <= value;
7637`endif
7638
7639`endif
7640
7641`endif
7642
7643 end
7644 endtask
7645
7646
7647 task slam_MraRow3_core1_thread6;
7648 input [127:0] value;
7649 reg [5:0] tid;
7650 integer junk;
7651
7652 begin
7653`ifdef AXIS_EMUL_COSIM
7654//Do Nothing
7655`else
7656`ifdef GATESIM
7657//Do Nothing
7658`else
7659`ifdef CORE_1
7660 value[82] = ^value[40:0];
7661 value[83] = ^value[81:41];
7662 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
7663 `SPC1.mmu.mra1.array.mem[19] <= value;
7664`endif
7665
7666`endif
7667
7668`endif
7669
7670 end
7671 endtask
7672
7673
7674 task slam_MraRow3_core1_thread7;
7675 input [127:0] value;
7676 reg [5:0] tid;
7677 integer junk;
7678
7679 begin
7680`ifdef AXIS_EMUL_COSIM
7681//Do Nothing
7682`else
7683`ifdef GATESIM
7684//Do Nothing
7685`else
7686`ifdef CORE_1
7687 value[82] = ^value[40:0];
7688 value[83] = ^value[81:41];
7689 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
7690 `SPC1.mmu.mra1.array.mem[27] <= value;
7691`endif
7692
7693`endif
7694
7695`endif
7696
7697 end
7698 endtask
7699
7700
7701 task slam_MraRow3_core2_thread0;
7702 input [127:0] value;
7703 reg [5:0] tid;
7704 integer junk;
7705
7706 begin
7707`ifdef AXIS_EMUL_COSIM
7708//Do Nothing
7709`else
7710`ifdef GATESIM
7711//Do Nothing
7712`else
7713`ifdef CORE_2
7714 value[82] = ^value[40:0];
7715 value[83] = ^value[81:41];
7716 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
7717 `SPC2.mmu.mra0.array.mem[3] <= value;
7718`endif
7719
7720`endif
7721
7722`endif
7723
7724 end
7725 endtask
7726
7727
7728 task slam_MraRow3_core2_thread1;
7729 input [127:0] value;
7730 reg [5:0] tid;
7731 integer junk;
7732
7733 begin
7734`ifdef AXIS_EMUL_COSIM
7735//Do Nothing
7736`else
7737`ifdef GATESIM
7738//Do Nothing
7739`else
7740`ifdef CORE_2
7741 value[82] = ^value[40:0];
7742 value[83] = ^value[81:41];
7743 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
7744 `SPC2.mmu.mra0.array.mem[11] <= value;
7745`endif
7746
7747`endif
7748
7749`endif
7750
7751 end
7752 endtask
7753
7754
7755 task slam_MraRow3_core2_thread2;
7756 input [127:0] value;
7757 reg [5:0] tid;
7758 integer junk;
7759
7760 begin
7761`ifdef AXIS_EMUL_COSIM
7762//Do Nothing
7763`else
7764`ifdef GATESIM
7765//Do Nothing
7766`else
7767`ifdef CORE_2
7768 value[82] = ^value[40:0];
7769 value[83] = ^value[81:41];
7770 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
7771 `SPC2.mmu.mra0.array.mem[19] <= value;
7772`endif
7773
7774`endif
7775
7776`endif
7777
7778 end
7779 endtask
7780
7781
7782 task slam_MraRow3_core2_thread3;
7783 input [127:0] value;
7784 reg [5:0] tid;
7785 integer junk;
7786
7787 begin
7788`ifdef AXIS_EMUL_COSIM
7789//Do Nothing
7790`else
7791`ifdef GATESIM
7792//Do Nothing
7793`else
7794`ifdef CORE_2
7795 value[82] = ^value[40:0];
7796 value[83] = ^value[81:41];
7797 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
7798 `SPC2.mmu.mra0.array.mem[27] <= value;
7799`endif
7800
7801`endif
7802
7803`endif
7804
7805 end
7806 endtask
7807
7808
7809 task slam_MraRow3_core2_thread4;
7810 input [127:0] value;
7811 reg [5:0] tid;
7812 integer junk;
7813
7814 begin
7815`ifdef AXIS_EMUL_COSIM
7816//Do Nothing
7817`else
7818`ifdef GATESIM
7819//Do Nothing
7820`else
7821`ifdef CORE_2
7822 value[82] = ^value[40:0];
7823 value[83] = ^value[81:41];
7824 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
7825 `SPC2.mmu.mra1.array.mem[3] <= value;
7826`endif
7827
7828`endif
7829
7830`endif
7831
7832 end
7833 endtask
7834
7835
7836 task slam_MraRow3_core2_thread5;
7837 input [127:0] value;
7838 reg [5:0] tid;
7839 integer junk;
7840
7841 begin
7842`ifdef AXIS_EMUL_COSIM
7843//Do Nothing
7844`else
7845`ifdef GATESIM
7846//Do Nothing
7847`else
7848`ifdef CORE_2
7849 value[82] = ^value[40:0];
7850 value[83] = ^value[81:41];
7851 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
7852 `SPC2.mmu.mra1.array.mem[11] <= value;
7853`endif
7854
7855`endif
7856
7857`endif
7858
7859 end
7860 endtask
7861
7862
7863 task slam_MraRow3_core2_thread6;
7864 input [127:0] value;
7865 reg [5:0] tid;
7866 integer junk;
7867
7868 begin
7869`ifdef AXIS_EMUL_COSIM
7870//Do Nothing
7871`else
7872`ifdef GATESIM
7873//Do Nothing
7874`else
7875`ifdef CORE_2
7876 value[82] = ^value[40:0];
7877 value[83] = ^value[81:41];
7878 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
7879 `SPC2.mmu.mra1.array.mem[19] <= value;
7880`endif
7881
7882`endif
7883
7884`endif
7885
7886 end
7887 endtask
7888
7889
7890 task slam_MraRow3_core2_thread7;
7891 input [127:0] value;
7892 reg [5:0] tid;
7893 integer junk;
7894
7895 begin
7896`ifdef AXIS_EMUL_COSIM
7897//Do Nothing
7898`else
7899`ifdef GATESIM
7900//Do Nothing
7901`else
7902`ifdef CORE_2
7903 value[82] = ^value[40:0];
7904 value[83] = ^value[81:41];
7905 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
7906 `SPC2.mmu.mra1.array.mem[27] <= value;
7907`endif
7908
7909`endif
7910
7911`endif
7912
7913 end
7914 endtask
7915
7916
7917 task slam_MraRow3_core3_thread0;
7918 input [127:0] value;
7919 reg [5:0] tid;
7920 integer junk;
7921
7922 begin
7923`ifdef AXIS_EMUL_COSIM
7924//Do Nothing
7925`else
7926`ifdef GATESIM
7927//Do Nothing
7928`else
7929`ifdef CORE_3
7930 value[82] = ^value[40:0];
7931 value[83] = ^value[81:41];
7932 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
7933 `SPC3.mmu.mra0.array.mem[3] <= value;
7934`endif
7935
7936`endif
7937
7938`endif
7939
7940 end
7941 endtask
7942
7943
7944 task slam_MraRow3_core3_thread1;
7945 input [127:0] value;
7946 reg [5:0] tid;
7947 integer junk;
7948
7949 begin
7950`ifdef AXIS_EMUL_COSIM
7951//Do Nothing
7952`else
7953`ifdef GATESIM
7954//Do Nothing
7955`else
7956`ifdef CORE_3
7957 value[82] = ^value[40:0];
7958 value[83] = ^value[81:41];
7959 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
7960 `SPC3.mmu.mra0.array.mem[11] <= value;
7961`endif
7962
7963`endif
7964
7965`endif
7966
7967 end
7968 endtask
7969
7970
7971 task slam_MraRow3_core3_thread2;
7972 input [127:0] value;
7973 reg [5:0] tid;
7974 integer junk;
7975
7976 begin
7977`ifdef AXIS_EMUL_COSIM
7978//Do Nothing
7979`else
7980`ifdef GATESIM
7981//Do Nothing
7982`else
7983`ifdef CORE_3
7984 value[82] = ^value[40:0];
7985 value[83] = ^value[81:41];
7986 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
7987 `SPC3.mmu.mra0.array.mem[19] <= value;
7988`endif
7989
7990`endif
7991
7992`endif
7993
7994 end
7995 endtask
7996
7997
7998 task slam_MraRow3_core3_thread3;
7999 input [127:0] value;
8000 reg [5:0] tid;
8001 integer junk;
8002
8003 begin
8004`ifdef AXIS_EMUL_COSIM
8005//Do Nothing
8006`else
8007`ifdef GATESIM
8008//Do Nothing
8009`else
8010`ifdef CORE_3
8011 value[82] = ^value[40:0];
8012 value[83] = ^value[81:41];
8013 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
8014 `SPC3.mmu.mra0.array.mem[27] <= value;
8015`endif
8016
8017`endif
8018
8019`endif
8020
8021 end
8022 endtask
8023
8024
8025 task slam_MraRow3_core3_thread4;
8026 input [127:0] value;
8027 reg [5:0] tid;
8028 integer junk;
8029
8030 begin
8031`ifdef AXIS_EMUL_COSIM
8032//Do Nothing
8033`else
8034`ifdef GATESIM
8035//Do Nothing
8036`else
8037`ifdef CORE_3
8038 value[82] = ^value[40:0];
8039 value[83] = ^value[81:41];
8040 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
8041 `SPC3.mmu.mra1.array.mem[3] <= value;
8042`endif
8043
8044`endif
8045
8046`endif
8047
8048 end
8049 endtask
8050
8051
8052 task slam_MraRow3_core3_thread5;
8053 input [127:0] value;
8054 reg [5:0] tid;
8055 integer junk;
8056
8057 begin
8058`ifdef AXIS_EMUL_COSIM
8059//Do Nothing
8060`else
8061`ifdef GATESIM
8062//Do Nothing
8063`else
8064`ifdef CORE_3
8065 value[82] = ^value[40:0];
8066 value[83] = ^value[81:41];
8067 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
8068 `SPC3.mmu.mra1.array.mem[11] <= value;
8069`endif
8070
8071`endif
8072
8073`endif
8074
8075 end
8076 endtask
8077
8078
8079 task slam_MraRow3_core3_thread6;
8080 input [127:0] value;
8081 reg [5:0] tid;
8082 integer junk;
8083
8084 begin
8085`ifdef AXIS_EMUL_COSIM
8086//Do Nothing
8087`else
8088`ifdef GATESIM
8089//Do Nothing
8090`else
8091`ifdef CORE_3
8092 value[82] = ^value[40:0];
8093 value[83] = ^value[81:41];
8094 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
8095 `SPC3.mmu.mra1.array.mem[19] <= value;
8096`endif
8097
8098`endif
8099
8100`endif
8101
8102 end
8103 endtask
8104
8105
8106 task slam_MraRow3_core3_thread7;
8107 input [127:0] value;
8108 reg [5:0] tid;
8109 integer junk;
8110
8111 begin
8112`ifdef AXIS_EMUL_COSIM
8113//Do Nothing
8114`else
8115`ifdef GATESIM
8116//Do Nothing
8117`else
8118`ifdef CORE_3
8119 value[82] = ^value[40:0];
8120 value[83] = ^value[81:41];
8121 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
8122 `SPC3.mmu.mra1.array.mem[27] <= value;
8123`endif
8124
8125`endif
8126
8127`endif
8128
8129 end
8130 endtask
8131
8132
8133 task slam_MraRow3_core4_thread0;
8134 input [127:0] value;
8135 reg [5:0] tid;
8136 integer junk;
8137
8138 begin
8139`ifdef AXIS_EMUL_COSIM
8140//Do Nothing
8141`else
8142`ifdef GATESIM
8143//Do Nothing
8144`else
8145`ifdef CORE_4
8146 value[82] = ^value[40:0];
8147 value[83] = ^value[81:41];
8148 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
8149 `SPC4.mmu.mra0.array.mem[3] <= value;
8150`endif
8151
8152`endif
8153
8154`endif
8155
8156 end
8157 endtask
8158
8159
8160 task slam_MraRow3_core4_thread1;
8161 input [127:0] value;
8162 reg [5:0] tid;
8163 integer junk;
8164
8165 begin
8166`ifdef AXIS_EMUL_COSIM
8167//Do Nothing
8168`else
8169`ifdef GATESIM
8170//Do Nothing
8171`else
8172`ifdef CORE_4
8173 value[82] = ^value[40:0];
8174 value[83] = ^value[81:41];
8175 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
8176 `SPC4.mmu.mra0.array.mem[11] <= value;
8177`endif
8178
8179`endif
8180
8181`endif
8182
8183 end
8184 endtask
8185
8186
8187 task slam_MraRow3_core4_thread2;
8188 input [127:0] value;
8189 reg [5:0] tid;
8190 integer junk;
8191
8192 begin
8193`ifdef AXIS_EMUL_COSIM
8194//Do Nothing
8195`else
8196`ifdef GATESIM
8197//Do Nothing
8198`else
8199`ifdef CORE_4
8200 value[82] = ^value[40:0];
8201 value[83] = ^value[81:41];
8202 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
8203 `SPC4.mmu.mra0.array.mem[19] <= value;
8204`endif
8205
8206`endif
8207
8208`endif
8209
8210 end
8211 endtask
8212
8213
8214 task slam_MraRow3_core4_thread3;
8215 input [127:0] value;
8216 reg [5:0] tid;
8217 integer junk;
8218
8219 begin
8220`ifdef AXIS_EMUL_COSIM
8221//Do Nothing
8222`else
8223`ifdef GATESIM
8224//Do Nothing
8225`else
8226`ifdef CORE_4
8227 value[82] = ^value[40:0];
8228 value[83] = ^value[81:41];
8229 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
8230 `SPC4.mmu.mra0.array.mem[27] <= value;
8231`endif
8232
8233`endif
8234
8235`endif
8236
8237 end
8238 endtask
8239
8240
8241 task slam_MraRow3_core4_thread4;
8242 input [127:0] value;
8243 reg [5:0] tid;
8244 integer junk;
8245
8246 begin
8247`ifdef AXIS_EMUL_COSIM
8248//Do Nothing
8249`else
8250`ifdef GATESIM
8251//Do Nothing
8252`else
8253`ifdef CORE_4
8254 value[82] = ^value[40:0];
8255 value[83] = ^value[81:41];
8256 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
8257 `SPC4.mmu.mra1.array.mem[3] <= value;
8258`endif
8259
8260`endif
8261
8262`endif
8263
8264 end
8265 endtask
8266
8267
8268 task slam_MraRow3_core4_thread5;
8269 input [127:0] value;
8270 reg [5:0] tid;
8271 integer junk;
8272
8273 begin
8274`ifdef AXIS_EMUL_COSIM
8275//Do Nothing
8276`else
8277`ifdef GATESIM
8278//Do Nothing
8279`else
8280`ifdef CORE_4
8281 value[82] = ^value[40:0];
8282 value[83] = ^value[81:41];
8283 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
8284 `SPC4.mmu.mra1.array.mem[11] <= value;
8285`endif
8286
8287`endif
8288
8289`endif
8290
8291 end
8292 endtask
8293
8294
8295 task slam_MraRow3_core4_thread6;
8296 input [127:0] value;
8297 reg [5:0] tid;
8298 integer junk;
8299
8300 begin
8301`ifdef AXIS_EMUL_COSIM
8302//Do Nothing
8303`else
8304`ifdef GATESIM
8305//Do Nothing
8306`else
8307`ifdef CORE_4
8308 value[82] = ^value[40:0];
8309 value[83] = ^value[81:41];
8310 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
8311 `SPC4.mmu.mra1.array.mem[19] <= value;
8312`endif
8313
8314`endif
8315
8316`endif
8317
8318 end
8319 endtask
8320
8321
8322 task slam_MraRow3_core4_thread7;
8323 input [127:0] value;
8324 reg [5:0] tid;
8325 integer junk;
8326
8327 begin
8328`ifdef AXIS_EMUL_COSIM
8329//Do Nothing
8330`else
8331`ifdef GATESIM
8332//Do Nothing
8333`else
8334`ifdef CORE_4
8335 value[82] = ^value[40:0];
8336 value[83] = ^value[81:41];
8337 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
8338 `SPC4.mmu.mra1.array.mem[27] <= value;
8339`endif
8340
8341`endif
8342
8343`endif
8344
8345 end
8346 endtask
8347
8348
8349 task slam_MraRow3_core5_thread0;
8350 input [127:0] value;
8351 reg [5:0] tid;
8352 integer junk;
8353
8354 begin
8355`ifdef AXIS_EMUL_COSIM
8356//Do Nothing
8357`else
8358`ifdef GATESIM
8359//Do Nothing
8360`else
8361`ifdef CORE_5
8362 value[82] = ^value[40:0];
8363 value[83] = ^value[81:41];
8364 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
8365 `SPC5.mmu.mra0.array.mem[3] <= value;
8366`endif
8367
8368`endif
8369
8370`endif
8371
8372 end
8373 endtask
8374
8375
8376 task slam_MraRow3_core5_thread1;
8377 input [127:0] value;
8378 reg [5:0] tid;
8379 integer junk;
8380
8381 begin
8382`ifdef AXIS_EMUL_COSIM
8383//Do Nothing
8384`else
8385`ifdef GATESIM
8386//Do Nothing
8387`else
8388`ifdef CORE_5
8389 value[82] = ^value[40:0];
8390 value[83] = ^value[81:41];
8391 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
8392 `SPC5.mmu.mra0.array.mem[11] <= value;
8393`endif
8394
8395`endif
8396
8397`endif
8398
8399 end
8400 endtask
8401
8402
8403 task slam_MraRow3_core5_thread2;
8404 input [127:0] value;
8405 reg [5:0] tid;
8406 integer junk;
8407
8408 begin
8409`ifdef AXIS_EMUL_COSIM
8410//Do Nothing
8411`else
8412`ifdef GATESIM
8413//Do Nothing
8414`else
8415`ifdef CORE_5
8416 value[82] = ^value[40:0];
8417 value[83] = ^value[81:41];
8418 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
8419 `SPC5.mmu.mra0.array.mem[19] <= value;
8420`endif
8421
8422`endif
8423
8424`endif
8425
8426 end
8427 endtask
8428
8429
8430 task slam_MraRow3_core5_thread3;
8431 input [127:0] value;
8432 reg [5:0] tid;
8433 integer junk;
8434
8435 begin
8436`ifdef AXIS_EMUL_COSIM
8437//Do Nothing
8438`else
8439`ifdef GATESIM
8440//Do Nothing
8441`else
8442`ifdef CORE_5
8443 value[82] = ^value[40:0];
8444 value[83] = ^value[81:41];
8445 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
8446 `SPC5.mmu.mra0.array.mem[27] <= value;
8447`endif
8448
8449`endif
8450
8451`endif
8452
8453 end
8454 endtask
8455
8456
8457 task slam_MraRow3_core5_thread4;
8458 input [127:0] value;
8459 reg [5:0] tid;
8460 integer junk;
8461
8462 begin
8463`ifdef AXIS_EMUL_COSIM
8464//Do Nothing
8465`else
8466`ifdef GATESIM
8467//Do Nothing
8468`else
8469`ifdef CORE_5
8470 value[82] = ^value[40:0];
8471 value[83] = ^value[81:41];
8472 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
8473 `SPC5.mmu.mra1.array.mem[3] <= value;
8474`endif
8475
8476`endif
8477
8478`endif
8479
8480 end
8481 endtask
8482
8483
8484 task slam_MraRow3_core5_thread5;
8485 input [127:0] value;
8486 reg [5:0] tid;
8487 integer junk;
8488
8489 begin
8490`ifdef AXIS_EMUL_COSIM
8491//Do Nothing
8492`else
8493`ifdef GATESIM
8494//Do Nothing
8495`else
8496`ifdef CORE_5
8497 value[82] = ^value[40:0];
8498 value[83] = ^value[81:41];
8499 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
8500 `SPC5.mmu.mra1.array.mem[11] <= value;
8501`endif
8502
8503`endif
8504
8505`endif
8506
8507 end
8508 endtask
8509
8510
8511 task slam_MraRow3_core5_thread6;
8512 input [127:0] value;
8513 reg [5:0] tid;
8514 integer junk;
8515
8516 begin
8517`ifdef AXIS_EMUL_COSIM
8518//Do Nothing
8519`else
8520`ifdef GATESIM
8521//Do Nothing
8522`else
8523`ifdef CORE_5
8524 value[82] = ^value[40:0];
8525 value[83] = ^value[81:41];
8526 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
8527 `SPC5.mmu.mra1.array.mem[19] <= value;
8528`endif
8529
8530`endif
8531
8532`endif
8533
8534 end
8535 endtask
8536
8537
8538 task slam_MraRow3_core5_thread7;
8539 input [127:0] value;
8540 reg [5:0] tid;
8541 integer junk;
8542
8543 begin
8544`ifdef AXIS_EMUL_COSIM
8545//Do Nothing
8546`else
8547`ifdef GATESIM
8548//Do Nothing
8549`else
8550`ifdef CORE_5
8551 value[82] = ^value[40:0];
8552 value[83] = ^value[81:41];
8553 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
8554 `SPC5.mmu.mra1.array.mem[27] <= value;
8555`endif
8556
8557`endif
8558
8559`endif
8560
8561 end
8562 endtask
8563
8564
8565 task slam_MraRow3_core6_thread0;
8566 input [127:0] value;
8567 reg [5:0] tid;
8568 integer junk;
8569
8570 begin
8571`ifdef AXIS_EMUL_COSIM
8572//Do Nothing
8573`else
8574`ifdef GATESIM
8575//Do Nothing
8576`else
8577`ifdef CORE_6
8578 value[82] = ^value[40:0];
8579 value[83] = ^value[81:41];
8580 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
8581 `SPC6.mmu.mra0.array.mem[3] <= value;
8582`endif
8583
8584`endif
8585
8586`endif
8587
8588 end
8589 endtask
8590
8591
8592 task slam_MraRow3_core6_thread1;
8593 input [127:0] value;
8594 reg [5:0] tid;
8595 integer junk;
8596
8597 begin
8598`ifdef AXIS_EMUL_COSIM
8599//Do Nothing
8600`else
8601`ifdef GATESIM
8602//Do Nothing
8603`else
8604`ifdef CORE_6
8605 value[82] = ^value[40:0];
8606 value[83] = ^value[81:41];
8607 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
8608 `SPC6.mmu.mra0.array.mem[11] <= value;
8609`endif
8610
8611`endif
8612
8613`endif
8614
8615 end
8616 endtask
8617
8618
8619 task slam_MraRow3_core6_thread2;
8620 input [127:0] value;
8621 reg [5:0] tid;
8622 integer junk;
8623
8624 begin
8625`ifdef AXIS_EMUL_COSIM
8626//Do Nothing
8627`else
8628`ifdef GATESIM
8629//Do Nothing
8630`else
8631`ifdef CORE_6
8632 value[82] = ^value[40:0];
8633 value[83] = ^value[81:41];
8634 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
8635 `SPC6.mmu.mra0.array.mem[19] <= value;
8636`endif
8637
8638`endif
8639
8640`endif
8641
8642 end
8643 endtask
8644
8645
8646 task slam_MraRow3_core6_thread3;
8647 input [127:0] value;
8648 reg [5:0] tid;
8649 integer junk;
8650
8651 begin
8652`ifdef AXIS_EMUL_COSIM
8653//Do Nothing
8654`else
8655`ifdef GATESIM
8656//Do Nothing
8657`else
8658`ifdef CORE_6
8659 value[82] = ^value[40:0];
8660 value[83] = ^value[81:41];
8661 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
8662 `SPC6.mmu.mra0.array.mem[27] <= value;
8663`endif
8664
8665`endif
8666
8667`endif
8668
8669 end
8670 endtask
8671
8672
8673 task slam_MraRow3_core6_thread4;
8674 input [127:0] value;
8675 reg [5:0] tid;
8676 integer junk;
8677
8678 begin
8679`ifdef AXIS_EMUL_COSIM
8680//Do Nothing
8681`else
8682`ifdef GATESIM
8683//Do Nothing
8684`else
8685`ifdef CORE_6
8686 value[82] = ^value[40:0];
8687 value[83] = ^value[81:41];
8688 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
8689 `SPC6.mmu.mra1.array.mem[3] <= value;
8690`endif
8691
8692`endif
8693
8694`endif
8695
8696 end
8697 endtask
8698
8699
8700 task slam_MraRow3_core6_thread5;
8701 input [127:0] value;
8702 reg [5:0] tid;
8703 integer junk;
8704
8705 begin
8706`ifdef AXIS_EMUL_COSIM
8707//Do Nothing
8708`else
8709`ifdef GATESIM
8710//Do Nothing
8711`else
8712`ifdef CORE_6
8713 value[82] = ^value[40:0];
8714 value[83] = ^value[81:41];
8715 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
8716 `SPC6.mmu.mra1.array.mem[11] <= value;
8717`endif
8718
8719`endif
8720
8721`endif
8722
8723 end
8724 endtask
8725
8726
8727 task slam_MraRow3_core6_thread6;
8728 input [127:0] value;
8729 reg [5:0] tid;
8730 integer junk;
8731
8732 begin
8733`ifdef AXIS_EMUL_COSIM
8734//Do Nothing
8735`else
8736`ifdef GATESIM
8737//Do Nothing
8738`else
8739`ifdef CORE_6
8740 value[82] = ^value[40:0];
8741 value[83] = ^value[81:41];
8742 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
8743 `SPC6.mmu.mra1.array.mem[19] <= value;
8744`endif
8745
8746`endif
8747
8748`endif
8749
8750 end
8751 endtask
8752
8753
8754 task slam_MraRow3_core6_thread7;
8755 input [127:0] value;
8756 reg [5:0] tid;
8757 integer junk;
8758
8759 begin
8760`ifdef AXIS_EMUL_COSIM
8761//Do Nothing
8762`else
8763`ifdef GATESIM
8764//Do Nothing
8765`else
8766`ifdef CORE_6
8767 value[82] = ^value[40:0];
8768 value[83] = ^value[81:41];
8769 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
8770 `SPC6.mmu.mra1.array.mem[27] <= value;
8771`endif
8772
8773`endif
8774
8775`endif
8776
8777 end
8778 endtask
8779
8780
8781 task slam_MraRow3_core7_thread0;
8782 input [127:0] value;
8783 reg [5:0] tid;
8784 integer junk;
8785
8786 begin
8787`ifdef AXIS_EMUL_COSIM
8788//Do Nothing
8789`else
8790`ifdef GATESIM
8791//Do Nothing
8792`else
8793`ifdef CORE_7
8794 value[82] = ^value[40:0];
8795 value[83] = ^value[81:41];
8796 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[3]" );
8797 `SPC7.mmu.mra0.array.mem[3] <= value;
8798`endif
8799
8800`endif
8801
8802`endif
8803
8804 end
8805 endtask
8806
8807
8808 task slam_MraRow3_core7_thread1;
8809 input [127:0] value;
8810 reg [5:0] tid;
8811 integer junk;
8812
8813 begin
8814`ifdef AXIS_EMUL_COSIM
8815//Do Nothing
8816`else
8817`ifdef GATESIM
8818//Do Nothing
8819`else
8820`ifdef CORE_7
8821 value[82] = ^value[40:0];
8822 value[83] = ^value[81:41];
8823 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[11]" );
8824 `SPC7.mmu.mra0.array.mem[11] <= value;
8825`endif
8826
8827`endif
8828
8829`endif
8830
8831 end
8832 endtask
8833
8834
8835 task slam_MraRow3_core7_thread2;
8836 input [127:0] value;
8837 reg [5:0] tid;
8838 integer junk;
8839
8840 begin
8841`ifdef AXIS_EMUL_COSIM
8842//Do Nothing
8843`else
8844`ifdef GATESIM
8845//Do Nothing
8846`else
8847`ifdef CORE_7
8848 value[82] = ^value[40:0];
8849 value[83] = ^value[81:41];
8850 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[19]" );
8851 `SPC7.mmu.mra0.array.mem[19] <= value;
8852`endif
8853
8854`endif
8855
8856`endif
8857
8858 end
8859 endtask
8860
8861
8862 task slam_MraRow3_core7_thread3;
8863 input [127:0] value;
8864 reg [5:0] tid;
8865 integer junk;
8866
8867 begin
8868`ifdef AXIS_EMUL_COSIM
8869//Do Nothing
8870`else
8871`ifdef GATESIM
8872//Do Nothing
8873`else
8874`ifdef CORE_7
8875 value[82] = ^value[40:0];
8876 value[83] = ^value[81:41];
8877 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[27]" );
8878 `SPC7.mmu.mra0.array.mem[27] <= value;
8879`endif
8880
8881`endif
8882
8883`endif
8884
8885 end
8886 endtask
8887
8888
8889 task slam_MraRow3_core7_thread4;
8890 input [127:0] value;
8891 reg [5:0] tid;
8892 integer junk;
8893
8894 begin
8895`ifdef AXIS_EMUL_COSIM
8896//Do Nothing
8897`else
8898`ifdef GATESIM
8899//Do Nothing
8900`else
8901`ifdef CORE_7
8902 value[82] = ^value[40:0];
8903 value[83] = ^value[81:41];
8904 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[3]" );
8905 `SPC7.mmu.mra1.array.mem[3] <= value;
8906`endif
8907
8908`endif
8909
8910`endif
8911
8912 end
8913 endtask
8914
8915
8916 task slam_MraRow3_core7_thread5;
8917 input [127:0] value;
8918 reg [5:0] tid;
8919 integer junk;
8920
8921 begin
8922`ifdef AXIS_EMUL_COSIM
8923//Do Nothing
8924`else
8925`ifdef GATESIM
8926//Do Nothing
8927`else
8928`ifdef CORE_7
8929 value[82] = ^value[40:0];
8930 value[83] = ^value[81:41];
8931 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[11]" );
8932 `SPC7.mmu.mra1.array.mem[11] <= value;
8933`endif
8934
8935`endif
8936
8937`endif
8938
8939 end
8940 endtask
8941
8942
8943 task slam_MraRow3_core7_thread6;
8944 input [127:0] value;
8945 reg [5:0] tid;
8946 integer junk;
8947
8948 begin
8949`ifdef AXIS_EMUL_COSIM
8950//Do Nothing
8951`else
8952`ifdef GATESIM
8953//Do Nothing
8954`else
8955`ifdef CORE_7
8956 value[82] = ^value[40:0];
8957 value[83] = ^value[81:41];
8958 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[19]" );
8959 `SPC7.mmu.mra1.array.mem[19] <= value;
8960`endif
8961
8962`endif
8963
8964`endif
8965
8966 end
8967 endtask
8968
8969
8970 task slam_MraRow3_core7_thread7;
8971 input [127:0] value;
8972 reg [5:0] tid;
8973 integer junk;
8974
8975 begin
8976`ifdef AXIS_EMUL_COSIM
8977//Do Nothing
8978`else
8979`ifdef GATESIM
8980//Do Nothing
8981`else
8982`ifdef CORE_7
8983 value[82] = ^value[40:0];
8984 value[83] = ^value[81:41];
8985 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[27]" );
8986 `SPC7.mmu.mra1.array.mem[27] <= value;
8987`endif
8988
8989`endif
8990
8991`endif
8992
8993 end
8994 endtask
8995
8996
8997 task slam_MraRow4_core0_thread0;
8998 input [127:0] value;
8999 reg [5:0] tid;
9000 integer junk;
9001
9002 begin
9003`ifdef AXIS_EMUL_COSIM
9004//Do Nothing
9005`else
9006`ifdef GATESIM
9007//Do Nothing
9008`else
9009`ifdef CORE_0
9010 value[82] = ^value[40:0];
9011 value[83] = ^value[81:41];
9012 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
9013 `SPC0.mmu.mra0.array.mem[4] <= value;
9014`endif
9015
9016`endif
9017
9018`endif
9019
9020 end
9021 endtask
9022
9023
9024 task slam_MraRow4_core0_thread1;
9025 input [127:0] value;
9026 reg [5:0] tid;
9027 integer junk;
9028
9029 begin
9030`ifdef AXIS_EMUL_COSIM
9031//Do Nothing
9032`else
9033`ifdef GATESIM
9034//Do Nothing
9035`else
9036`ifdef CORE_0
9037 value[82] = ^value[40:0];
9038 value[83] = ^value[81:41];
9039 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
9040 `SPC0.mmu.mra0.array.mem[12] <= value;
9041`endif
9042
9043`endif
9044
9045`endif
9046
9047 end
9048 endtask
9049
9050
9051 task slam_MraRow4_core0_thread2;
9052 input [127:0] value;
9053 reg [5:0] tid;
9054 integer junk;
9055
9056 begin
9057`ifdef AXIS_EMUL_COSIM
9058//Do Nothing
9059`else
9060`ifdef GATESIM
9061//Do Nothing
9062`else
9063`ifdef CORE_0
9064 value[82] = ^value[40:0];
9065 value[83] = ^value[81:41];
9066 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
9067 `SPC0.mmu.mra0.array.mem[20] <= value;
9068`endif
9069
9070`endif
9071
9072`endif
9073
9074 end
9075 endtask
9076
9077
9078 task slam_MraRow4_core0_thread3;
9079 input [127:0] value;
9080 reg [5:0] tid;
9081 integer junk;
9082
9083 begin
9084`ifdef AXIS_EMUL_COSIM
9085//Do Nothing
9086`else
9087`ifdef GATESIM
9088//Do Nothing
9089`else
9090`ifdef CORE_0
9091 value[82] = ^value[40:0];
9092 value[83] = ^value[81:41];
9093 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
9094 `SPC0.mmu.mra0.array.mem[28] <= value;
9095`endif
9096
9097`endif
9098
9099`endif
9100
9101 end
9102 endtask
9103
9104
9105 task slam_MraRow4_core0_thread4;
9106 input [127:0] value;
9107 reg [5:0] tid;
9108 integer junk;
9109
9110 begin
9111`ifdef AXIS_EMUL_COSIM
9112//Do Nothing
9113`else
9114`ifdef GATESIM
9115//Do Nothing
9116`else
9117`ifdef CORE_0
9118 value[82] = ^value[40:0];
9119 value[83] = ^value[81:41];
9120 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
9121 `SPC0.mmu.mra1.array.mem[4] <= value;
9122`endif
9123
9124`endif
9125
9126`endif
9127
9128 end
9129 endtask
9130
9131
9132 task slam_MraRow4_core0_thread5;
9133 input [127:0] value;
9134 reg [5:0] tid;
9135 integer junk;
9136
9137 begin
9138`ifdef AXIS_EMUL_COSIM
9139//Do Nothing
9140`else
9141`ifdef GATESIM
9142//Do Nothing
9143`else
9144`ifdef CORE_0
9145 value[82] = ^value[40:0];
9146 value[83] = ^value[81:41];
9147 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
9148 `SPC0.mmu.mra1.array.mem[12] <= value;
9149`endif
9150
9151`endif
9152
9153`endif
9154
9155 end
9156 endtask
9157
9158
9159 task slam_MraRow4_core0_thread6;
9160 input [127:0] value;
9161 reg [5:0] tid;
9162 integer junk;
9163
9164 begin
9165`ifdef AXIS_EMUL_COSIM
9166//Do Nothing
9167`else
9168`ifdef GATESIM
9169//Do Nothing
9170`else
9171`ifdef CORE_0
9172 value[82] = ^value[40:0];
9173 value[83] = ^value[81:41];
9174 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
9175 `SPC0.mmu.mra1.array.mem[20] <= value;
9176`endif
9177
9178`endif
9179
9180`endif
9181
9182 end
9183 endtask
9184
9185
9186 task slam_MraRow4_core0_thread7;
9187 input [127:0] value;
9188 reg [5:0] tid;
9189 integer junk;
9190
9191 begin
9192`ifdef AXIS_EMUL_COSIM
9193//Do Nothing
9194`else
9195`ifdef GATESIM
9196//Do Nothing
9197`else
9198`ifdef CORE_0
9199 value[82] = ^value[40:0];
9200 value[83] = ^value[81:41];
9201 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
9202 `SPC0.mmu.mra1.array.mem[28] <= value;
9203`endif
9204
9205`endif
9206
9207`endif
9208
9209 end
9210 endtask
9211
9212
9213 task slam_MraRow4_core1_thread0;
9214 input [127:0] value;
9215 reg [5:0] tid;
9216 integer junk;
9217
9218 begin
9219`ifdef AXIS_EMUL_COSIM
9220//Do Nothing
9221`else
9222`ifdef GATESIM
9223//Do Nothing
9224`else
9225`ifdef CORE_1
9226 value[82] = ^value[40:0];
9227 value[83] = ^value[81:41];
9228 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
9229 `SPC1.mmu.mra0.array.mem[4] <= value;
9230`endif
9231
9232`endif
9233
9234`endif
9235
9236 end
9237 endtask
9238
9239
9240 task slam_MraRow4_core1_thread1;
9241 input [127:0] value;
9242 reg [5:0] tid;
9243 integer junk;
9244
9245 begin
9246`ifdef AXIS_EMUL_COSIM
9247//Do Nothing
9248`else
9249`ifdef GATESIM
9250//Do Nothing
9251`else
9252`ifdef CORE_1
9253 value[82] = ^value[40:0];
9254 value[83] = ^value[81:41];
9255 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
9256 `SPC1.mmu.mra0.array.mem[12] <= value;
9257`endif
9258
9259`endif
9260
9261`endif
9262
9263 end
9264 endtask
9265
9266
9267 task slam_MraRow4_core1_thread2;
9268 input [127:0] value;
9269 reg [5:0] tid;
9270 integer junk;
9271
9272 begin
9273`ifdef AXIS_EMUL_COSIM
9274//Do Nothing
9275`else
9276`ifdef GATESIM
9277//Do Nothing
9278`else
9279`ifdef CORE_1
9280 value[82] = ^value[40:0];
9281 value[83] = ^value[81:41];
9282 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
9283 `SPC1.mmu.mra0.array.mem[20] <= value;
9284`endif
9285
9286`endif
9287
9288`endif
9289
9290 end
9291 endtask
9292
9293
9294 task slam_MraRow4_core1_thread3;
9295 input [127:0] value;
9296 reg [5:0] tid;
9297 integer junk;
9298
9299 begin
9300`ifdef AXIS_EMUL_COSIM
9301//Do Nothing
9302`else
9303`ifdef GATESIM
9304//Do Nothing
9305`else
9306`ifdef CORE_1
9307 value[82] = ^value[40:0];
9308 value[83] = ^value[81:41];
9309 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
9310 `SPC1.mmu.mra0.array.mem[28] <= value;
9311`endif
9312
9313`endif
9314
9315`endif
9316
9317 end
9318 endtask
9319
9320
9321 task slam_MraRow4_core1_thread4;
9322 input [127:0] value;
9323 reg [5:0] tid;
9324 integer junk;
9325
9326 begin
9327`ifdef AXIS_EMUL_COSIM
9328//Do Nothing
9329`else
9330`ifdef GATESIM
9331//Do Nothing
9332`else
9333`ifdef CORE_1
9334 value[82] = ^value[40:0];
9335 value[83] = ^value[81:41];
9336 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
9337 `SPC1.mmu.mra1.array.mem[4] <= value;
9338`endif
9339
9340`endif
9341
9342`endif
9343
9344 end
9345 endtask
9346
9347
9348 task slam_MraRow4_core1_thread5;
9349 input [127:0] value;
9350 reg [5:0] tid;
9351 integer junk;
9352
9353 begin
9354`ifdef AXIS_EMUL_COSIM
9355//Do Nothing
9356`else
9357`ifdef GATESIM
9358//Do Nothing
9359`else
9360`ifdef CORE_1
9361 value[82] = ^value[40:0];
9362 value[83] = ^value[81:41];
9363 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
9364 `SPC1.mmu.mra1.array.mem[12] <= value;
9365`endif
9366
9367`endif
9368
9369`endif
9370
9371 end
9372 endtask
9373
9374
9375 task slam_MraRow4_core1_thread6;
9376 input [127:0] value;
9377 reg [5:0] tid;
9378 integer junk;
9379
9380 begin
9381`ifdef AXIS_EMUL_COSIM
9382//Do Nothing
9383`else
9384`ifdef GATESIM
9385//Do Nothing
9386`else
9387`ifdef CORE_1
9388 value[82] = ^value[40:0];
9389 value[83] = ^value[81:41];
9390 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
9391 `SPC1.mmu.mra1.array.mem[20] <= value;
9392`endif
9393
9394`endif
9395
9396`endif
9397
9398 end
9399 endtask
9400
9401
9402 task slam_MraRow4_core1_thread7;
9403 input [127:0] value;
9404 reg [5:0] tid;
9405 integer junk;
9406
9407 begin
9408`ifdef AXIS_EMUL_COSIM
9409//Do Nothing
9410`else
9411`ifdef GATESIM
9412//Do Nothing
9413`else
9414`ifdef CORE_1
9415 value[82] = ^value[40:0];
9416 value[83] = ^value[81:41];
9417 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
9418 `SPC1.mmu.mra1.array.mem[28] <= value;
9419`endif
9420
9421`endif
9422
9423`endif
9424
9425 end
9426 endtask
9427
9428
9429 task slam_MraRow4_core2_thread0;
9430 input [127:0] value;
9431 reg [5:0] tid;
9432 integer junk;
9433
9434 begin
9435`ifdef AXIS_EMUL_COSIM
9436//Do Nothing
9437`else
9438`ifdef GATESIM
9439//Do Nothing
9440`else
9441`ifdef CORE_2
9442 value[82] = ^value[40:0];
9443 value[83] = ^value[81:41];
9444 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
9445 `SPC2.mmu.mra0.array.mem[4] <= value;
9446`endif
9447
9448`endif
9449
9450`endif
9451
9452 end
9453 endtask
9454
9455
9456 task slam_MraRow4_core2_thread1;
9457 input [127:0] value;
9458 reg [5:0] tid;
9459 integer junk;
9460
9461 begin
9462`ifdef AXIS_EMUL_COSIM
9463//Do Nothing
9464`else
9465`ifdef GATESIM
9466//Do Nothing
9467`else
9468`ifdef CORE_2
9469 value[82] = ^value[40:0];
9470 value[83] = ^value[81:41];
9471 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
9472 `SPC2.mmu.mra0.array.mem[12] <= value;
9473`endif
9474
9475`endif
9476
9477`endif
9478
9479 end
9480 endtask
9481
9482
9483 task slam_MraRow4_core2_thread2;
9484 input [127:0] value;
9485 reg [5:0] tid;
9486 integer junk;
9487
9488 begin
9489`ifdef AXIS_EMUL_COSIM
9490//Do Nothing
9491`else
9492`ifdef GATESIM
9493//Do Nothing
9494`else
9495`ifdef CORE_2
9496 value[82] = ^value[40:0];
9497 value[83] = ^value[81:41];
9498 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
9499 `SPC2.mmu.mra0.array.mem[20] <= value;
9500`endif
9501
9502`endif
9503
9504`endif
9505
9506 end
9507 endtask
9508
9509
9510 task slam_MraRow4_core2_thread3;
9511 input [127:0] value;
9512 reg [5:0] tid;
9513 integer junk;
9514
9515 begin
9516`ifdef AXIS_EMUL_COSIM
9517//Do Nothing
9518`else
9519`ifdef GATESIM
9520//Do Nothing
9521`else
9522`ifdef CORE_2
9523 value[82] = ^value[40:0];
9524 value[83] = ^value[81:41];
9525 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
9526 `SPC2.mmu.mra0.array.mem[28] <= value;
9527`endif
9528
9529`endif
9530
9531`endif
9532
9533 end
9534 endtask
9535
9536
9537 task slam_MraRow4_core2_thread4;
9538 input [127:0] value;
9539 reg [5:0] tid;
9540 integer junk;
9541
9542 begin
9543`ifdef AXIS_EMUL_COSIM
9544//Do Nothing
9545`else
9546`ifdef GATESIM
9547//Do Nothing
9548`else
9549`ifdef CORE_2
9550 value[82] = ^value[40:0];
9551 value[83] = ^value[81:41];
9552 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
9553 `SPC2.mmu.mra1.array.mem[4] <= value;
9554`endif
9555
9556`endif
9557
9558`endif
9559
9560 end
9561 endtask
9562
9563
9564 task slam_MraRow4_core2_thread5;
9565 input [127:0] value;
9566 reg [5:0] tid;
9567 integer junk;
9568
9569 begin
9570`ifdef AXIS_EMUL_COSIM
9571//Do Nothing
9572`else
9573`ifdef GATESIM
9574//Do Nothing
9575`else
9576`ifdef CORE_2
9577 value[82] = ^value[40:0];
9578 value[83] = ^value[81:41];
9579 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
9580 `SPC2.mmu.mra1.array.mem[12] <= value;
9581`endif
9582
9583`endif
9584
9585`endif
9586
9587 end
9588 endtask
9589
9590
9591 task slam_MraRow4_core2_thread6;
9592 input [127:0] value;
9593 reg [5:0] tid;
9594 integer junk;
9595
9596 begin
9597`ifdef AXIS_EMUL_COSIM
9598//Do Nothing
9599`else
9600`ifdef GATESIM
9601//Do Nothing
9602`else
9603`ifdef CORE_2
9604 value[82] = ^value[40:0];
9605 value[83] = ^value[81:41];
9606 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
9607 `SPC2.mmu.mra1.array.mem[20] <= value;
9608`endif
9609
9610`endif
9611
9612`endif
9613
9614 end
9615 endtask
9616
9617
9618 task slam_MraRow4_core2_thread7;
9619 input [127:0] value;
9620 reg [5:0] tid;
9621 integer junk;
9622
9623 begin
9624`ifdef AXIS_EMUL_COSIM
9625//Do Nothing
9626`else
9627`ifdef GATESIM
9628//Do Nothing
9629`else
9630`ifdef CORE_2
9631 value[82] = ^value[40:0];
9632 value[83] = ^value[81:41];
9633 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
9634 `SPC2.mmu.mra1.array.mem[28] <= value;
9635`endif
9636
9637`endif
9638
9639`endif
9640
9641 end
9642 endtask
9643
9644
9645 task slam_MraRow4_core3_thread0;
9646 input [127:0] value;
9647 reg [5:0] tid;
9648 integer junk;
9649
9650 begin
9651`ifdef AXIS_EMUL_COSIM
9652//Do Nothing
9653`else
9654`ifdef GATESIM
9655//Do Nothing
9656`else
9657`ifdef CORE_3
9658 value[82] = ^value[40:0];
9659 value[83] = ^value[81:41];
9660 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
9661 `SPC3.mmu.mra0.array.mem[4] <= value;
9662`endif
9663
9664`endif
9665
9666`endif
9667
9668 end
9669 endtask
9670
9671
9672 task slam_MraRow4_core3_thread1;
9673 input [127:0] value;
9674 reg [5:0] tid;
9675 integer junk;
9676
9677 begin
9678`ifdef AXIS_EMUL_COSIM
9679//Do Nothing
9680`else
9681`ifdef GATESIM
9682//Do Nothing
9683`else
9684`ifdef CORE_3
9685 value[82] = ^value[40:0];
9686 value[83] = ^value[81:41];
9687 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
9688 `SPC3.mmu.mra0.array.mem[12] <= value;
9689`endif
9690
9691`endif
9692
9693`endif
9694
9695 end
9696 endtask
9697
9698
9699 task slam_MraRow4_core3_thread2;
9700 input [127:0] value;
9701 reg [5:0] tid;
9702 integer junk;
9703
9704 begin
9705`ifdef AXIS_EMUL_COSIM
9706//Do Nothing
9707`else
9708`ifdef GATESIM
9709//Do Nothing
9710`else
9711`ifdef CORE_3
9712 value[82] = ^value[40:0];
9713 value[83] = ^value[81:41];
9714 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
9715 `SPC3.mmu.mra0.array.mem[20] <= value;
9716`endif
9717
9718`endif
9719
9720`endif
9721
9722 end
9723 endtask
9724
9725
9726 task slam_MraRow4_core3_thread3;
9727 input [127:0] value;
9728 reg [5:0] tid;
9729 integer junk;
9730
9731 begin
9732`ifdef AXIS_EMUL_COSIM
9733//Do Nothing
9734`else
9735`ifdef GATESIM
9736//Do Nothing
9737`else
9738`ifdef CORE_3
9739 value[82] = ^value[40:0];
9740 value[83] = ^value[81:41];
9741 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
9742 `SPC3.mmu.mra0.array.mem[28] <= value;
9743`endif
9744
9745`endif
9746
9747`endif
9748
9749 end
9750 endtask
9751
9752
9753 task slam_MraRow4_core3_thread4;
9754 input [127:0] value;
9755 reg [5:0] tid;
9756 integer junk;
9757
9758 begin
9759`ifdef AXIS_EMUL_COSIM
9760//Do Nothing
9761`else
9762`ifdef GATESIM
9763//Do Nothing
9764`else
9765`ifdef CORE_3
9766 value[82] = ^value[40:0];
9767 value[83] = ^value[81:41];
9768 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
9769 `SPC3.mmu.mra1.array.mem[4] <= value;
9770`endif
9771
9772`endif
9773
9774`endif
9775
9776 end
9777 endtask
9778
9779
9780 task slam_MraRow4_core3_thread5;
9781 input [127:0] value;
9782 reg [5:0] tid;
9783 integer junk;
9784
9785 begin
9786`ifdef AXIS_EMUL_COSIM
9787//Do Nothing
9788`else
9789`ifdef GATESIM
9790//Do Nothing
9791`else
9792`ifdef CORE_3
9793 value[82] = ^value[40:0];
9794 value[83] = ^value[81:41];
9795 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
9796 `SPC3.mmu.mra1.array.mem[12] <= value;
9797`endif
9798
9799`endif
9800
9801`endif
9802
9803 end
9804 endtask
9805
9806
9807 task slam_MraRow4_core3_thread6;
9808 input [127:0] value;
9809 reg [5:0] tid;
9810 integer junk;
9811
9812 begin
9813`ifdef AXIS_EMUL_COSIM
9814//Do Nothing
9815`else
9816`ifdef GATESIM
9817//Do Nothing
9818`else
9819`ifdef CORE_3
9820 value[82] = ^value[40:0];
9821 value[83] = ^value[81:41];
9822 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
9823 `SPC3.mmu.mra1.array.mem[20] <= value;
9824`endif
9825
9826`endif
9827
9828`endif
9829
9830 end
9831 endtask
9832
9833
9834 task slam_MraRow4_core3_thread7;
9835 input [127:0] value;
9836 reg [5:0] tid;
9837 integer junk;
9838
9839 begin
9840`ifdef AXIS_EMUL_COSIM
9841//Do Nothing
9842`else
9843`ifdef GATESIM
9844//Do Nothing
9845`else
9846`ifdef CORE_3
9847 value[82] = ^value[40:0];
9848 value[83] = ^value[81:41];
9849 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
9850 `SPC3.mmu.mra1.array.mem[28] <= value;
9851`endif
9852
9853`endif
9854
9855`endif
9856
9857 end
9858 endtask
9859
9860
9861 task slam_MraRow4_core4_thread0;
9862 input [127:0] value;
9863 reg [5:0] tid;
9864 integer junk;
9865
9866 begin
9867`ifdef AXIS_EMUL_COSIM
9868//Do Nothing
9869`else
9870`ifdef GATESIM
9871//Do Nothing
9872`else
9873`ifdef CORE_4
9874 value[82] = ^value[40:0];
9875 value[83] = ^value[81:41];
9876 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
9877 `SPC4.mmu.mra0.array.mem[4] <= value;
9878`endif
9879
9880`endif
9881
9882`endif
9883
9884 end
9885 endtask
9886
9887
9888 task slam_MraRow4_core4_thread1;
9889 input [127:0] value;
9890 reg [5:0] tid;
9891 integer junk;
9892
9893 begin
9894`ifdef AXIS_EMUL_COSIM
9895//Do Nothing
9896`else
9897`ifdef GATESIM
9898//Do Nothing
9899`else
9900`ifdef CORE_4
9901 value[82] = ^value[40:0];
9902 value[83] = ^value[81:41];
9903 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
9904 `SPC4.mmu.mra0.array.mem[12] <= value;
9905`endif
9906
9907`endif
9908
9909`endif
9910
9911 end
9912 endtask
9913
9914
9915 task slam_MraRow4_core4_thread2;
9916 input [127:0] value;
9917 reg [5:0] tid;
9918 integer junk;
9919
9920 begin
9921`ifdef AXIS_EMUL_COSIM
9922//Do Nothing
9923`else
9924`ifdef GATESIM
9925//Do Nothing
9926`else
9927`ifdef CORE_4
9928 value[82] = ^value[40:0];
9929 value[83] = ^value[81:41];
9930 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
9931 `SPC4.mmu.mra0.array.mem[20] <= value;
9932`endif
9933
9934`endif
9935
9936`endif
9937
9938 end
9939 endtask
9940
9941
9942 task slam_MraRow4_core4_thread3;
9943 input [127:0] value;
9944 reg [5:0] tid;
9945 integer junk;
9946
9947 begin
9948`ifdef AXIS_EMUL_COSIM
9949//Do Nothing
9950`else
9951`ifdef GATESIM
9952//Do Nothing
9953`else
9954`ifdef CORE_4
9955 value[82] = ^value[40:0];
9956 value[83] = ^value[81:41];
9957 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
9958 `SPC4.mmu.mra0.array.mem[28] <= value;
9959`endif
9960
9961`endif
9962
9963`endif
9964
9965 end
9966 endtask
9967
9968
9969 task slam_MraRow4_core4_thread4;
9970 input [127:0] value;
9971 reg [5:0] tid;
9972 integer junk;
9973
9974 begin
9975`ifdef AXIS_EMUL_COSIM
9976//Do Nothing
9977`else
9978`ifdef GATESIM
9979//Do Nothing
9980`else
9981`ifdef CORE_4
9982 value[82] = ^value[40:0];
9983 value[83] = ^value[81:41];
9984 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
9985 `SPC4.mmu.mra1.array.mem[4] <= value;
9986`endif
9987
9988`endif
9989
9990`endif
9991
9992 end
9993 endtask
9994
9995
9996 task slam_MraRow4_core4_thread5;
9997 input [127:0] value;
9998 reg [5:0] tid;
9999 integer junk;
10000
10001 begin
10002`ifdef AXIS_EMUL_COSIM
10003//Do Nothing
10004`else
10005`ifdef GATESIM
10006//Do Nothing
10007`else
10008`ifdef CORE_4
10009 value[82] = ^value[40:0];
10010 value[83] = ^value[81:41];
10011 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
10012 `SPC4.mmu.mra1.array.mem[12] <= value;
10013`endif
10014
10015`endif
10016
10017`endif
10018
10019 end
10020 endtask
10021
10022
10023 task slam_MraRow4_core4_thread6;
10024 input [127:0] value;
10025 reg [5:0] tid;
10026 integer junk;
10027
10028 begin
10029`ifdef AXIS_EMUL_COSIM
10030//Do Nothing
10031`else
10032`ifdef GATESIM
10033//Do Nothing
10034`else
10035`ifdef CORE_4
10036 value[82] = ^value[40:0];
10037 value[83] = ^value[81:41];
10038 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
10039 `SPC4.mmu.mra1.array.mem[20] <= value;
10040`endif
10041
10042`endif
10043
10044`endif
10045
10046 end
10047 endtask
10048
10049
10050 task slam_MraRow4_core4_thread7;
10051 input [127:0] value;
10052 reg [5:0] tid;
10053 integer junk;
10054
10055 begin
10056`ifdef AXIS_EMUL_COSIM
10057//Do Nothing
10058`else
10059`ifdef GATESIM
10060//Do Nothing
10061`else
10062`ifdef CORE_4
10063 value[82] = ^value[40:0];
10064 value[83] = ^value[81:41];
10065 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
10066 `SPC4.mmu.mra1.array.mem[28] <= value;
10067`endif
10068
10069`endif
10070
10071`endif
10072
10073 end
10074 endtask
10075
10076
10077 task slam_MraRow4_core5_thread0;
10078 input [127:0] value;
10079 reg [5:0] tid;
10080 integer junk;
10081
10082 begin
10083`ifdef AXIS_EMUL_COSIM
10084//Do Nothing
10085`else
10086`ifdef GATESIM
10087//Do Nothing
10088`else
10089`ifdef CORE_5
10090 value[82] = ^value[40:0];
10091 value[83] = ^value[81:41];
10092 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
10093 `SPC5.mmu.mra0.array.mem[4] <= value;
10094`endif
10095
10096`endif
10097
10098`endif
10099
10100 end
10101 endtask
10102
10103
10104 task slam_MraRow4_core5_thread1;
10105 input [127:0] value;
10106 reg [5:0] tid;
10107 integer junk;
10108
10109 begin
10110`ifdef AXIS_EMUL_COSIM
10111//Do Nothing
10112`else
10113`ifdef GATESIM
10114//Do Nothing
10115`else
10116`ifdef CORE_5
10117 value[82] = ^value[40:0];
10118 value[83] = ^value[81:41];
10119 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
10120 `SPC5.mmu.mra0.array.mem[12] <= value;
10121`endif
10122
10123`endif
10124
10125`endif
10126
10127 end
10128 endtask
10129
10130
10131 task slam_MraRow4_core5_thread2;
10132 input [127:0] value;
10133 reg [5:0] tid;
10134 integer junk;
10135
10136 begin
10137`ifdef AXIS_EMUL_COSIM
10138//Do Nothing
10139`else
10140`ifdef GATESIM
10141//Do Nothing
10142`else
10143`ifdef CORE_5
10144 value[82] = ^value[40:0];
10145 value[83] = ^value[81:41];
10146 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
10147 `SPC5.mmu.mra0.array.mem[20] <= value;
10148`endif
10149
10150`endif
10151
10152`endif
10153
10154 end
10155 endtask
10156
10157
10158 task slam_MraRow4_core5_thread3;
10159 input [127:0] value;
10160 reg [5:0] tid;
10161 integer junk;
10162
10163 begin
10164`ifdef AXIS_EMUL_COSIM
10165//Do Nothing
10166`else
10167`ifdef GATESIM
10168//Do Nothing
10169`else
10170`ifdef CORE_5
10171 value[82] = ^value[40:0];
10172 value[83] = ^value[81:41];
10173 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
10174 `SPC5.mmu.mra0.array.mem[28] <= value;
10175`endif
10176
10177`endif
10178
10179`endif
10180
10181 end
10182 endtask
10183
10184
10185 task slam_MraRow4_core5_thread4;
10186 input [127:0] value;
10187 reg [5:0] tid;
10188 integer junk;
10189
10190 begin
10191`ifdef AXIS_EMUL_COSIM
10192//Do Nothing
10193`else
10194`ifdef GATESIM
10195//Do Nothing
10196`else
10197`ifdef CORE_5
10198 value[82] = ^value[40:0];
10199 value[83] = ^value[81:41];
10200 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
10201 `SPC5.mmu.mra1.array.mem[4] <= value;
10202`endif
10203
10204`endif
10205
10206`endif
10207
10208 end
10209 endtask
10210
10211
10212 task slam_MraRow4_core5_thread5;
10213 input [127:0] value;
10214 reg [5:0] tid;
10215 integer junk;
10216
10217 begin
10218`ifdef AXIS_EMUL_COSIM
10219//Do Nothing
10220`else
10221`ifdef GATESIM
10222//Do Nothing
10223`else
10224`ifdef CORE_5
10225 value[82] = ^value[40:0];
10226 value[83] = ^value[81:41];
10227 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
10228 `SPC5.mmu.mra1.array.mem[12] <= value;
10229`endif
10230
10231`endif
10232
10233`endif
10234
10235 end
10236 endtask
10237
10238
10239 task slam_MraRow4_core5_thread6;
10240 input [127:0] value;
10241 reg [5:0] tid;
10242 integer junk;
10243
10244 begin
10245`ifdef AXIS_EMUL_COSIM
10246//Do Nothing
10247`else
10248`ifdef GATESIM
10249//Do Nothing
10250`else
10251`ifdef CORE_5
10252 value[82] = ^value[40:0];
10253 value[83] = ^value[81:41];
10254 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
10255 `SPC5.mmu.mra1.array.mem[20] <= value;
10256`endif
10257
10258`endif
10259
10260`endif
10261
10262 end
10263 endtask
10264
10265
10266 task slam_MraRow4_core5_thread7;
10267 input [127:0] value;
10268 reg [5:0] tid;
10269 integer junk;
10270
10271 begin
10272`ifdef AXIS_EMUL_COSIM
10273//Do Nothing
10274`else
10275`ifdef GATESIM
10276//Do Nothing
10277`else
10278`ifdef CORE_5
10279 value[82] = ^value[40:0];
10280 value[83] = ^value[81:41];
10281 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
10282 `SPC5.mmu.mra1.array.mem[28] <= value;
10283`endif
10284
10285`endif
10286
10287`endif
10288
10289 end
10290 endtask
10291
10292
10293 task slam_MraRow4_core6_thread0;
10294 input [127:0] value;
10295 reg [5:0] tid;
10296 integer junk;
10297
10298 begin
10299`ifdef AXIS_EMUL_COSIM
10300//Do Nothing
10301`else
10302`ifdef GATESIM
10303//Do Nothing
10304`else
10305`ifdef CORE_6
10306 value[82] = ^value[40:0];
10307 value[83] = ^value[81:41];
10308 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
10309 `SPC6.mmu.mra0.array.mem[4] <= value;
10310`endif
10311
10312`endif
10313
10314`endif
10315
10316 end
10317 endtask
10318
10319
10320 task slam_MraRow4_core6_thread1;
10321 input [127:0] value;
10322 reg [5:0] tid;
10323 integer junk;
10324
10325 begin
10326`ifdef AXIS_EMUL_COSIM
10327//Do Nothing
10328`else
10329`ifdef GATESIM
10330//Do Nothing
10331`else
10332`ifdef CORE_6
10333 value[82] = ^value[40:0];
10334 value[83] = ^value[81:41];
10335 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
10336 `SPC6.mmu.mra0.array.mem[12] <= value;
10337`endif
10338
10339`endif
10340
10341`endif
10342
10343 end
10344 endtask
10345
10346
10347 task slam_MraRow4_core6_thread2;
10348 input [127:0] value;
10349 reg [5:0] tid;
10350 integer junk;
10351
10352 begin
10353`ifdef AXIS_EMUL_COSIM
10354//Do Nothing
10355`else
10356`ifdef GATESIM
10357//Do Nothing
10358`else
10359`ifdef CORE_6
10360 value[82] = ^value[40:0];
10361 value[83] = ^value[81:41];
10362 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
10363 `SPC6.mmu.mra0.array.mem[20] <= value;
10364`endif
10365
10366`endif
10367
10368`endif
10369
10370 end
10371 endtask
10372
10373
10374 task slam_MraRow4_core6_thread3;
10375 input [127:0] value;
10376 reg [5:0] tid;
10377 integer junk;
10378
10379 begin
10380`ifdef AXIS_EMUL_COSIM
10381//Do Nothing
10382`else
10383`ifdef GATESIM
10384//Do Nothing
10385`else
10386`ifdef CORE_6
10387 value[82] = ^value[40:0];
10388 value[83] = ^value[81:41];
10389 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
10390 `SPC6.mmu.mra0.array.mem[28] <= value;
10391`endif
10392
10393`endif
10394
10395`endif
10396
10397 end
10398 endtask
10399
10400
10401 task slam_MraRow4_core6_thread4;
10402 input [127:0] value;
10403 reg [5:0] tid;
10404 integer junk;
10405
10406 begin
10407`ifdef AXIS_EMUL_COSIM
10408//Do Nothing
10409`else
10410`ifdef GATESIM
10411//Do Nothing
10412`else
10413`ifdef CORE_6
10414 value[82] = ^value[40:0];
10415 value[83] = ^value[81:41];
10416 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
10417 `SPC6.mmu.mra1.array.mem[4] <= value;
10418`endif
10419
10420`endif
10421
10422`endif
10423
10424 end
10425 endtask
10426
10427
10428 task slam_MraRow4_core6_thread5;
10429 input [127:0] value;
10430 reg [5:0] tid;
10431 integer junk;
10432
10433 begin
10434`ifdef AXIS_EMUL_COSIM
10435//Do Nothing
10436`else
10437`ifdef GATESIM
10438//Do Nothing
10439`else
10440`ifdef CORE_6
10441 value[82] = ^value[40:0];
10442 value[83] = ^value[81:41];
10443 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
10444 `SPC6.mmu.mra1.array.mem[12] <= value;
10445`endif
10446
10447`endif
10448
10449`endif
10450
10451 end
10452 endtask
10453
10454
10455 task slam_MraRow4_core6_thread6;
10456 input [127:0] value;
10457 reg [5:0] tid;
10458 integer junk;
10459
10460 begin
10461`ifdef AXIS_EMUL_COSIM
10462//Do Nothing
10463`else
10464`ifdef GATESIM
10465//Do Nothing
10466`else
10467`ifdef CORE_6
10468 value[82] = ^value[40:0];
10469 value[83] = ^value[81:41];
10470 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
10471 `SPC6.mmu.mra1.array.mem[20] <= value;
10472`endif
10473
10474`endif
10475
10476`endif
10477
10478 end
10479 endtask
10480
10481
10482 task slam_MraRow4_core6_thread7;
10483 input [127:0] value;
10484 reg [5:0] tid;
10485 integer junk;
10486
10487 begin
10488`ifdef AXIS_EMUL_COSIM
10489//Do Nothing
10490`else
10491`ifdef GATESIM
10492//Do Nothing
10493`else
10494`ifdef CORE_6
10495 value[82] = ^value[40:0];
10496 value[83] = ^value[81:41];
10497 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
10498 `SPC6.mmu.mra1.array.mem[28] <= value;
10499`endif
10500
10501`endif
10502
10503`endif
10504
10505 end
10506 endtask
10507
10508
10509 task slam_MraRow4_core7_thread0;
10510 input [127:0] value;
10511 reg [5:0] tid;
10512 integer junk;
10513
10514 begin
10515`ifdef AXIS_EMUL_COSIM
10516//Do Nothing
10517`else
10518`ifdef GATESIM
10519//Do Nothing
10520`else
10521`ifdef CORE_7
10522 value[82] = ^value[40:0];
10523 value[83] = ^value[81:41];
10524 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[4]" );
10525 `SPC7.mmu.mra0.array.mem[4] <= value;
10526`endif
10527
10528`endif
10529
10530`endif
10531
10532 end
10533 endtask
10534
10535
10536 task slam_MraRow4_core7_thread1;
10537 input [127:0] value;
10538 reg [5:0] tid;
10539 integer junk;
10540
10541 begin
10542`ifdef AXIS_EMUL_COSIM
10543//Do Nothing
10544`else
10545`ifdef GATESIM
10546//Do Nothing
10547`else
10548`ifdef CORE_7
10549 value[82] = ^value[40:0];
10550 value[83] = ^value[81:41];
10551 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[12]" );
10552 `SPC7.mmu.mra0.array.mem[12] <= value;
10553`endif
10554
10555`endif
10556
10557`endif
10558
10559 end
10560 endtask
10561
10562
10563 task slam_MraRow4_core7_thread2;
10564 input [127:0] value;
10565 reg [5:0] tid;
10566 integer junk;
10567
10568 begin
10569`ifdef AXIS_EMUL_COSIM
10570//Do Nothing
10571`else
10572`ifdef GATESIM
10573//Do Nothing
10574`else
10575`ifdef CORE_7
10576 value[82] = ^value[40:0];
10577 value[83] = ^value[81:41];
10578 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[20]" );
10579 `SPC7.mmu.mra0.array.mem[20] <= value;
10580`endif
10581
10582`endif
10583
10584`endif
10585
10586 end
10587 endtask
10588
10589
10590 task slam_MraRow4_core7_thread3;
10591 input [127:0] value;
10592 reg [5:0] tid;
10593 integer junk;
10594
10595 begin
10596`ifdef AXIS_EMUL_COSIM
10597//Do Nothing
10598`else
10599`ifdef GATESIM
10600//Do Nothing
10601`else
10602`ifdef CORE_7
10603 value[82] = ^value[40:0];
10604 value[83] = ^value[81:41];
10605 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[28]" );
10606 `SPC7.mmu.mra0.array.mem[28] <= value;
10607`endif
10608
10609`endif
10610
10611`endif
10612
10613 end
10614 endtask
10615
10616
10617 task slam_MraRow4_core7_thread4;
10618 input [127:0] value;
10619 reg [5:0] tid;
10620 integer junk;
10621
10622 begin
10623`ifdef AXIS_EMUL_COSIM
10624//Do Nothing
10625`else
10626`ifdef GATESIM
10627//Do Nothing
10628`else
10629`ifdef CORE_7
10630 value[82] = ^value[40:0];
10631 value[83] = ^value[81:41];
10632 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[4]" );
10633 `SPC7.mmu.mra1.array.mem[4] <= value;
10634`endif
10635
10636`endif
10637
10638`endif
10639
10640 end
10641 endtask
10642
10643
10644 task slam_MraRow4_core7_thread5;
10645 input [127:0] value;
10646 reg [5:0] tid;
10647 integer junk;
10648
10649 begin
10650`ifdef AXIS_EMUL_COSIM
10651//Do Nothing
10652`else
10653`ifdef GATESIM
10654//Do Nothing
10655`else
10656`ifdef CORE_7
10657 value[82] = ^value[40:0];
10658 value[83] = ^value[81:41];
10659 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[12]" );
10660 `SPC7.mmu.mra1.array.mem[12] <= value;
10661`endif
10662
10663`endif
10664
10665`endif
10666
10667 end
10668 endtask
10669
10670
10671 task slam_MraRow4_core7_thread6;
10672 input [127:0] value;
10673 reg [5:0] tid;
10674 integer junk;
10675
10676 begin
10677`ifdef AXIS_EMUL_COSIM
10678//Do Nothing
10679`else
10680`ifdef GATESIM
10681//Do Nothing
10682`else
10683`ifdef CORE_7
10684 value[82] = ^value[40:0];
10685 value[83] = ^value[81:41];
10686 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[20]" );
10687 `SPC7.mmu.mra1.array.mem[20] <= value;
10688`endif
10689
10690`endif
10691
10692`endif
10693
10694 end
10695 endtask
10696
10697
10698 task slam_MraRow4_core7_thread7;
10699 input [127:0] value;
10700 reg [5:0] tid;
10701 integer junk;
10702
10703 begin
10704`ifdef AXIS_EMUL_COSIM
10705//Do Nothing
10706`else
10707`ifdef GATESIM
10708//Do Nothing
10709`else
10710`ifdef CORE_7
10711 value[82] = ^value[40:0];
10712 value[83] = ^value[81:41];
10713 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[28]" );
10714 `SPC7.mmu.mra1.array.mem[28] <= value;
10715`endif
10716
10717`endif
10718
10719`endif
10720
10721 end
10722 endtask
10723
10724
10725 task slam_MraRow5_core0_thread0;
10726 input [127:0] value;
10727 reg [5:0] tid;
10728 integer junk;
10729
10730 begin
10731`ifdef AXIS_EMUL_COSIM
10732//Do Nothing
10733`else
10734`ifdef GATESIM
10735//Do Nothing
10736`else
10737`ifdef CORE_0
10738 value[82] = ^value[40:0];
10739 value[83] = ^value[81:41];
10740 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
10741 `SPC0.mmu.mra0.array.mem[5] <= value;
10742`endif
10743
10744`endif
10745
10746`endif
10747
10748 end
10749 endtask
10750
10751
10752 task slam_MraRow5_core0_thread1;
10753 input [127:0] value;
10754 reg [5:0] tid;
10755 integer junk;
10756
10757 begin
10758`ifdef AXIS_EMUL_COSIM
10759//Do Nothing
10760`else
10761`ifdef GATESIM
10762//Do Nothing
10763`else
10764`ifdef CORE_0
10765 value[82] = ^value[40:0];
10766 value[83] = ^value[81:41];
10767 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
10768 `SPC0.mmu.mra0.array.mem[13] <= value;
10769`endif
10770
10771`endif
10772
10773`endif
10774
10775 end
10776 endtask
10777
10778
10779 task slam_MraRow5_core0_thread2;
10780 input [127:0] value;
10781 reg [5:0] tid;
10782 integer junk;
10783
10784 begin
10785`ifdef AXIS_EMUL_COSIM
10786//Do Nothing
10787`else
10788`ifdef GATESIM
10789//Do Nothing
10790`else
10791`ifdef CORE_0
10792 value[82] = ^value[40:0];
10793 value[83] = ^value[81:41];
10794 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
10795 `SPC0.mmu.mra0.array.mem[21] <= value;
10796`endif
10797
10798`endif
10799
10800`endif
10801
10802 end
10803 endtask
10804
10805
10806 task slam_MraRow5_core0_thread3;
10807 input [127:0] value;
10808 reg [5:0] tid;
10809 integer junk;
10810
10811 begin
10812`ifdef AXIS_EMUL_COSIM
10813//Do Nothing
10814`else
10815`ifdef GATESIM
10816//Do Nothing
10817`else
10818`ifdef CORE_0
10819 value[82] = ^value[40:0];
10820 value[83] = ^value[81:41];
10821 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
10822 `SPC0.mmu.mra0.array.mem[29] <= value;
10823`endif
10824
10825`endif
10826
10827`endif
10828
10829 end
10830 endtask
10831
10832
10833 task slam_MraRow5_core0_thread4;
10834 input [127:0] value;
10835 reg [5:0] tid;
10836 integer junk;
10837
10838 begin
10839`ifdef AXIS_EMUL_COSIM
10840//Do Nothing
10841`else
10842`ifdef GATESIM
10843//Do Nothing
10844`else
10845`ifdef CORE_0
10846 value[82] = ^value[40:0];
10847 value[83] = ^value[81:41];
10848 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
10849 `SPC0.mmu.mra1.array.mem[5] <= value;
10850`endif
10851
10852`endif
10853
10854`endif
10855
10856 end
10857 endtask
10858
10859
10860 task slam_MraRow5_core0_thread5;
10861 input [127:0] value;
10862 reg [5:0] tid;
10863 integer junk;
10864
10865 begin
10866`ifdef AXIS_EMUL_COSIM
10867//Do Nothing
10868`else
10869`ifdef GATESIM
10870//Do Nothing
10871`else
10872`ifdef CORE_0
10873 value[82] = ^value[40:0];
10874 value[83] = ^value[81:41];
10875 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
10876 `SPC0.mmu.mra1.array.mem[13] <= value;
10877`endif
10878
10879`endif
10880
10881`endif
10882
10883 end
10884 endtask
10885
10886
10887 task slam_MraRow5_core0_thread6;
10888 input [127:0] value;
10889 reg [5:0] tid;
10890 integer junk;
10891
10892 begin
10893`ifdef AXIS_EMUL_COSIM
10894//Do Nothing
10895`else
10896`ifdef GATESIM
10897//Do Nothing
10898`else
10899`ifdef CORE_0
10900 value[82] = ^value[40:0];
10901 value[83] = ^value[81:41];
10902 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
10903 `SPC0.mmu.mra1.array.mem[21] <= value;
10904`endif
10905
10906`endif
10907
10908`endif
10909
10910 end
10911 endtask
10912
10913
10914 task slam_MraRow5_core0_thread7;
10915 input [127:0] value;
10916 reg [5:0] tid;
10917 integer junk;
10918
10919 begin
10920`ifdef AXIS_EMUL_COSIM
10921//Do Nothing
10922`else
10923`ifdef GATESIM
10924//Do Nothing
10925`else
10926`ifdef CORE_0
10927 value[82] = ^value[40:0];
10928 value[83] = ^value[81:41];
10929 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
10930 `SPC0.mmu.mra1.array.mem[29] <= value;
10931`endif
10932
10933`endif
10934
10935`endif
10936
10937 end
10938 endtask
10939
10940
10941 task slam_MraRow5_core1_thread0;
10942 input [127:0] value;
10943 reg [5:0] tid;
10944 integer junk;
10945
10946 begin
10947`ifdef AXIS_EMUL_COSIM
10948//Do Nothing
10949`else
10950`ifdef GATESIM
10951//Do Nothing
10952`else
10953`ifdef CORE_1
10954 value[82] = ^value[40:0];
10955 value[83] = ^value[81:41];
10956 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
10957 `SPC1.mmu.mra0.array.mem[5] <= value;
10958`endif
10959
10960`endif
10961
10962`endif
10963
10964 end
10965 endtask
10966
10967
10968 task slam_MraRow5_core1_thread1;
10969 input [127:0] value;
10970 reg [5:0] tid;
10971 integer junk;
10972
10973 begin
10974`ifdef AXIS_EMUL_COSIM
10975//Do Nothing
10976`else
10977`ifdef GATESIM
10978//Do Nothing
10979`else
10980`ifdef CORE_1
10981 value[82] = ^value[40:0];
10982 value[83] = ^value[81:41];
10983 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
10984 `SPC1.mmu.mra0.array.mem[13] <= value;
10985`endif
10986
10987`endif
10988
10989`endif
10990
10991 end
10992 endtask
10993
10994
10995 task slam_MraRow5_core1_thread2;
10996 input [127:0] value;
10997 reg [5:0] tid;
10998 integer junk;
10999
11000 begin
11001`ifdef AXIS_EMUL_COSIM
11002//Do Nothing
11003`else
11004`ifdef GATESIM
11005//Do Nothing
11006`else
11007`ifdef CORE_1
11008 value[82] = ^value[40:0];
11009 value[83] = ^value[81:41];
11010 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
11011 `SPC1.mmu.mra0.array.mem[21] <= value;
11012`endif
11013
11014`endif
11015
11016`endif
11017
11018 end
11019 endtask
11020
11021
11022 task slam_MraRow5_core1_thread3;
11023 input [127:0] value;
11024 reg [5:0] tid;
11025 integer junk;
11026
11027 begin
11028`ifdef AXIS_EMUL_COSIM
11029//Do Nothing
11030`else
11031`ifdef GATESIM
11032//Do Nothing
11033`else
11034`ifdef CORE_1
11035 value[82] = ^value[40:0];
11036 value[83] = ^value[81:41];
11037 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
11038 `SPC1.mmu.mra0.array.mem[29] <= value;
11039`endif
11040
11041`endif
11042
11043`endif
11044
11045 end
11046 endtask
11047
11048
11049 task slam_MraRow5_core1_thread4;
11050 input [127:0] value;
11051 reg [5:0] tid;
11052 integer junk;
11053
11054 begin
11055`ifdef AXIS_EMUL_COSIM
11056//Do Nothing
11057`else
11058`ifdef GATESIM
11059//Do Nothing
11060`else
11061`ifdef CORE_1
11062 value[82] = ^value[40:0];
11063 value[83] = ^value[81:41];
11064 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
11065 `SPC1.mmu.mra1.array.mem[5] <= value;
11066`endif
11067
11068`endif
11069
11070`endif
11071
11072 end
11073 endtask
11074
11075
11076 task slam_MraRow5_core1_thread5;
11077 input [127:0] value;
11078 reg [5:0] tid;
11079 integer junk;
11080
11081 begin
11082`ifdef AXIS_EMUL_COSIM
11083//Do Nothing
11084`else
11085`ifdef GATESIM
11086//Do Nothing
11087`else
11088`ifdef CORE_1
11089 value[82] = ^value[40:0];
11090 value[83] = ^value[81:41];
11091 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
11092 `SPC1.mmu.mra1.array.mem[13] <= value;
11093`endif
11094
11095`endif
11096
11097`endif
11098
11099 end
11100 endtask
11101
11102
11103 task slam_MraRow5_core1_thread6;
11104 input [127:0] value;
11105 reg [5:0] tid;
11106 integer junk;
11107
11108 begin
11109`ifdef AXIS_EMUL_COSIM
11110//Do Nothing
11111`else
11112`ifdef GATESIM
11113//Do Nothing
11114`else
11115`ifdef CORE_1
11116 value[82] = ^value[40:0];
11117 value[83] = ^value[81:41];
11118 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
11119 `SPC1.mmu.mra1.array.mem[21] <= value;
11120`endif
11121
11122`endif
11123
11124`endif
11125
11126 end
11127 endtask
11128
11129
11130 task slam_MraRow5_core1_thread7;
11131 input [127:0] value;
11132 reg [5:0] tid;
11133 integer junk;
11134
11135 begin
11136`ifdef AXIS_EMUL_COSIM
11137//Do Nothing
11138`else
11139`ifdef GATESIM
11140//Do Nothing
11141`else
11142`ifdef CORE_1
11143 value[82] = ^value[40:0];
11144 value[83] = ^value[81:41];
11145 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
11146 `SPC1.mmu.mra1.array.mem[29] <= value;
11147`endif
11148
11149`endif
11150
11151`endif
11152
11153 end
11154 endtask
11155
11156
11157 task slam_MraRow5_core2_thread0;
11158 input [127:0] value;
11159 reg [5:0] tid;
11160 integer junk;
11161
11162 begin
11163`ifdef AXIS_EMUL_COSIM
11164//Do Nothing
11165`else
11166`ifdef GATESIM
11167//Do Nothing
11168`else
11169`ifdef CORE_2
11170 value[82] = ^value[40:0];
11171 value[83] = ^value[81:41];
11172 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
11173 `SPC2.mmu.mra0.array.mem[5] <= value;
11174`endif
11175
11176`endif
11177
11178`endif
11179
11180 end
11181 endtask
11182
11183
11184 task slam_MraRow5_core2_thread1;
11185 input [127:0] value;
11186 reg [5:0] tid;
11187 integer junk;
11188
11189 begin
11190`ifdef AXIS_EMUL_COSIM
11191//Do Nothing
11192`else
11193`ifdef GATESIM
11194//Do Nothing
11195`else
11196`ifdef CORE_2
11197 value[82] = ^value[40:0];
11198 value[83] = ^value[81:41];
11199 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
11200 `SPC2.mmu.mra0.array.mem[13] <= value;
11201`endif
11202
11203`endif
11204
11205`endif
11206
11207 end
11208 endtask
11209
11210
11211 task slam_MraRow5_core2_thread2;
11212 input [127:0] value;
11213 reg [5:0] tid;
11214 integer junk;
11215
11216 begin
11217`ifdef AXIS_EMUL_COSIM
11218//Do Nothing
11219`else
11220`ifdef GATESIM
11221//Do Nothing
11222`else
11223`ifdef CORE_2
11224 value[82] = ^value[40:0];
11225 value[83] = ^value[81:41];
11226 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
11227 `SPC2.mmu.mra0.array.mem[21] <= value;
11228`endif
11229
11230`endif
11231
11232`endif
11233
11234 end
11235 endtask
11236
11237
11238 task slam_MraRow5_core2_thread3;
11239 input [127:0] value;
11240 reg [5:0] tid;
11241 integer junk;
11242
11243 begin
11244`ifdef AXIS_EMUL_COSIM
11245//Do Nothing
11246`else
11247`ifdef GATESIM
11248//Do Nothing
11249`else
11250`ifdef CORE_2
11251 value[82] = ^value[40:0];
11252 value[83] = ^value[81:41];
11253 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
11254 `SPC2.mmu.mra0.array.mem[29] <= value;
11255`endif
11256
11257`endif
11258
11259`endif
11260
11261 end
11262 endtask
11263
11264
11265 task slam_MraRow5_core2_thread4;
11266 input [127:0] value;
11267 reg [5:0] tid;
11268 integer junk;
11269
11270 begin
11271`ifdef AXIS_EMUL_COSIM
11272//Do Nothing
11273`else
11274`ifdef GATESIM
11275//Do Nothing
11276`else
11277`ifdef CORE_2
11278 value[82] = ^value[40:0];
11279 value[83] = ^value[81:41];
11280 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
11281 `SPC2.mmu.mra1.array.mem[5] <= value;
11282`endif
11283
11284`endif
11285
11286`endif
11287
11288 end
11289 endtask
11290
11291
11292 task slam_MraRow5_core2_thread5;
11293 input [127:0] value;
11294 reg [5:0] tid;
11295 integer junk;
11296
11297 begin
11298`ifdef AXIS_EMUL_COSIM
11299//Do Nothing
11300`else
11301`ifdef GATESIM
11302//Do Nothing
11303`else
11304`ifdef CORE_2
11305 value[82] = ^value[40:0];
11306 value[83] = ^value[81:41];
11307 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
11308 `SPC2.mmu.mra1.array.mem[13] <= value;
11309`endif
11310
11311`endif
11312
11313`endif
11314
11315 end
11316 endtask
11317
11318
11319 task slam_MraRow5_core2_thread6;
11320 input [127:0] value;
11321 reg [5:0] tid;
11322 integer junk;
11323
11324 begin
11325`ifdef AXIS_EMUL_COSIM
11326//Do Nothing
11327`else
11328`ifdef GATESIM
11329//Do Nothing
11330`else
11331`ifdef CORE_2
11332 value[82] = ^value[40:0];
11333 value[83] = ^value[81:41];
11334 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
11335 `SPC2.mmu.mra1.array.mem[21] <= value;
11336`endif
11337
11338`endif
11339
11340`endif
11341
11342 end
11343 endtask
11344
11345
11346 task slam_MraRow5_core2_thread7;
11347 input [127:0] value;
11348 reg [5:0] tid;
11349 integer junk;
11350
11351 begin
11352`ifdef AXIS_EMUL_COSIM
11353//Do Nothing
11354`else
11355`ifdef GATESIM
11356//Do Nothing
11357`else
11358`ifdef CORE_2
11359 value[82] = ^value[40:0];
11360 value[83] = ^value[81:41];
11361 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
11362 `SPC2.mmu.mra1.array.mem[29] <= value;
11363`endif
11364
11365`endif
11366
11367`endif
11368
11369 end
11370 endtask
11371
11372
11373 task slam_MraRow5_core3_thread0;
11374 input [127:0] value;
11375 reg [5:0] tid;
11376 integer junk;
11377
11378 begin
11379`ifdef AXIS_EMUL_COSIM
11380//Do Nothing
11381`else
11382`ifdef GATESIM
11383//Do Nothing
11384`else
11385`ifdef CORE_3
11386 value[82] = ^value[40:0];
11387 value[83] = ^value[81:41];
11388 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
11389 `SPC3.mmu.mra0.array.mem[5] <= value;
11390`endif
11391
11392`endif
11393
11394`endif
11395
11396 end
11397 endtask
11398
11399
11400 task slam_MraRow5_core3_thread1;
11401 input [127:0] value;
11402 reg [5:0] tid;
11403 integer junk;
11404
11405 begin
11406`ifdef AXIS_EMUL_COSIM
11407//Do Nothing
11408`else
11409`ifdef GATESIM
11410//Do Nothing
11411`else
11412`ifdef CORE_3
11413 value[82] = ^value[40:0];
11414 value[83] = ^value[81:41];
11415 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
11416 `SPC3.mmu.mra0.array.mem[13] <= value;
11417`endif
11418
11419`endif
11420
11421`endif
11422
11423 end
11424 endtask
11425
11426
11427 task slam_MraRow5_core3_thread2;
11428 input [127:0] value;
11429 reg [5:0] tid;
11430 integer junk;
11431
11432 begin
11433`ifdef AXIS_EMUL_COSIM
11434//Do Nothing
11435`else
11436`ifdef GATESIM
11437//Do Nothing
11438`else
11439`ifdef CORE_3
11440 value[82] = ^value[40:0];
11441 value[83] = ^value[81:41];
11442 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
11443 `SPC3.mmu.mra0.array.mem[21] <= value;
11444`endif
11445
11446`endif
11447
11448`endif
11449
11450 end
11451 endtask
11452
11453
11454 task slam_MraRow5_core3_thread3;
11455 input [127:0] value;
11456 reg [5:0] tid;
11457 integer junk;
11458
11459 begin
11460`ifdef AXIS_EMUL_COSIM
11461//Do Nothing
11462`else
11463`ifdef GATESIM
11464//Do Nothing
11465`else
11466`ifdef CORE_3
11467 value[82] = ^value[40:0];
11468 value[83] = ^value[81:41];
11469 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
11470 `SPC3.mmu.mra0.array.mem[29] <= value;
11471`endif
11472
11473`endif
11474
11475`endif
11476
11477 end
11478 endtask
11479
11480
11481 task slam_MraRow5_core3_thread4;
11482 input [127:0] value;
11483 reg [5:0] tid;
11484 integer junk;
11485
11486 begin
11487`ifdef AXIS_EMUL_COSIM
11488//Do Nothing
11489`else
11490`ifdef GATESIM
11491//Do Nothing
11492`else
11493`ifdef CORE_3
11494 value[82] = ^value[40:0];
11495 value[83] = ^value[81:41];
11496 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
11497 `SPC3.mmu.mra1.array.mem[5] <= value;
11498`endif
11499
11500`endif
11501
11502`endif
11503
11504 end
11505 endtask
11506
11507
11508 task slam_MraRow5_core3_thread5;
11509 input [127:0] value;
11510 reg [5:0] tid;
11511 integer junk;
11512
11513 begin
11514`ifdef AXIS_EMUL_COSIM
11515//Do Nothing
11516`else
11517`ifdef GATESIM
11518//Do Nothing
11519`else
11520`ifdef CORE_3
11521 value[82] = ^value[40:0];
11522 value[83] = ^value[81:41];
11523 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
11524 `SPC3.mmu.mra1.array.mem[13] <= value;
11525`endif
11526
11527`endif
11528
11529`endif
11530
11531 end
11532 endtask
11533
11534
11535 task slam_MraRow5_core3_thread6;
11536 input [127:0] value;
11537 reg [5:0] tid;
11538 integer junk;
11539
11540 begin
11541`ifdef AXIS_EMUL_COSIM
11542//Do Nothing
11543`else
11544`ifdef GATESIM
11545//Do Nothing
11546`else
11547`ifdef CORE_3
11548 value[82] = ^value[40:0];
11549 value[83] = ^value[81:41];
11550 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
11551 `SPC3.mmu.mra1.array.mem[21] <= value;
11552`endif
11553
11554`endif
11555
11556`endif
11557
11558 end
11559 endtask
11560
11561
11562 task slam_MraRow5_core3_thread7;
11563 input [127:0] value;
11564 reg [5:0] tid;
11565 integer junk;
11566
11567 begin
11568`ifdef AXIS_EMUL_COSIM
11569//Do Nothing
11570`else
11571`ifdef GATESIM
11572//Do Nothing
11573`else
11574`ifdef CORE_3
11575 value[82] = ^value[40:0];
11576 value[83] = ^value[81:41];
11577 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
11578 `SPC3.mmu.mra1.array.mem[29] <= value;
11579`endif
11580
11581`endif
11582
11583`endif
11584
11585 end
11586 endtask
11587
11588
11589 task slam_MraRow5_core4_thread0;
11590 input [127:0] value;
11591 reg [5:0] tid;
11592 integer junk;
11593
11594 begin
11595`ifdef AXIS_EMUL_COSIM
11596//Do Nothing
11597`else
11598`ifdef GATESIM
11599//Do Nothing
11600`else
11601`ifdef CORE_4
11602 value[82] = ^value[40:0];
11603 value[83] = ^value[81:41];
11604 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
11605 `SPC4.mmu.mra0.array.mem[5] <= value;
11606`endif
11607
11608`endif
11609
11610`endif
11611
11612 end
11613 endtask
11614
11615
11616 task slam_MraRow5_core4_thread1;
11617 input [127:0] value;
11618 reg [5:0] tid;
11619 integer junk;
11620
11621 begin
11622`ifdef AXIS_EMUL_COSIM
11623//Do Nothing
11624`else
11625`ifdef GATESIM
11626//Do Nothing
11627`else
11628`ifdef CORE_4
11629 value[82] = ^value[40:0];
11630 value[83] = ^value[81:41];
11631 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
11632 `SPC4.mmu.mra0.array.mem[13] <= value;
11633`endif
11634
11635`endif
11636
11637`endif
11638
11639 end
11640 endtask
11641
11642
11643 task slam_MraRow5_core4_thread2;
11644 input [127:0] value;
11645 reg [5:0] tid;
11646 integer junk;
11647
11648 begin
11649`ifdef AXIS_EMUL_COSIM
11650//Do Nothing
11651`else
11652`ifdef GATESIM
11653//Do Nothing
11654`else
11655`ifdef CORE_4
11656 value[82] = ^value[40:0];
11657 value[83] = ^value[81:41];
11658 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
11659 `SPC4.mmu.mra0.array.mem[21] <= value;
11660`endif
11661
11662`endif
11663
11664`endif
11665
11666 end
11667 endtask
11668
11669
11670 task slam_MraRow5_core4_thread3;
11671 input [127:0] value;
11672 reg [5:0] tid;
11673 integer junk;
11674
11675 begin
11676`ifdef AXIS_EMUL_COSIM
11677//Do Nothing
11678`else
11679`ifdef GATESIM
11680//Do Nothing
11681`else
11682`ifdef CORE_4
11683 value[82] = ^value[40:0];
11684 value[83] = ^value[81:41];
11685 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
11686 `SPC4.mmu.mra0.array.mem[29] <= value;
11687`endif
11688
11689`endif
11690
11691`endif
11692
11693 end
11694 endtask
11695
11696
11697 task slam_MraRow5_core4_thread4;
11698 input [127:0] value;
11699 reg [5:0] tid;
11700 integer junk;
11701
11702 begin
11703`ifdef AXIS_EMUL_COSIM
11704//Do Nothing
11705`else
11706`ifdef GATESIM
11707//Do Nothing
11708`else
11709`ifdef CORE_4
11710 value[82] = ^value[40:0];
11711 value[83] = ^value[81:41];
11712 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
11713 `SPC4.mmu.mra1.array.mem[5] <= value;
11714`endif
11715
11716`endif
11717
11718`endif
11719
11720 end
11721 endtask
11722
11723
11724 task slam_MraRow5_core4_thread5;
11725 input [127:0] value;
11726 reg [5:0] tid;
11727 integer junk;
11728
11729 begin
11730`ifdef AXIS_EMUL_COSIM
11731//Do Nothing
11732`else
11733`ifdef GATESIM
11734//Do Nothing
11735`else
11736`ifdef CORE_4
11737 value[82] = ^value[40:0];
11738 value[83] = ^value[81:41];
11739 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
11740 `SPC4.mmu.mra1.array.mem[13] <= value;
11741`endif
11742
11743`endif
11744
11745`endif
11746
11747 end
11748 endtask
11749
11750
11751 task slam_MraRow5_core4_thread6;
11752 input [127:0] value;
11753 reg [5:0] tid;
11754 integer junk;
11755
11756 begin
11757`ifdef AXIS_EMUL_COSIM
11758//Do Nothing
11759`else
11760`ifdef GATESIM
11761//Do Nothing
11762`else
11763`ifdef CORE_4
11764 value[82] = ^value[40:0];
11765 value[83] = ^value[81:41];
11766 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
11767 `SPC4.mmu.mra1.array.mem[21] <= value;
11768`endif
11769
11770`endif
11771
11772`endif
11773
11774 end
11775 endtask
11776
11777
11778 task slam_MraRow5_core4_thread7;
11779 input [127:0] value;
11780 reg [5:0] tid;
11781 integer junk;
11782
11783 begin
11784`ifdef AXIS_EMUL_COSIM
11785//Do Nothing
11786`else
11787`ifdef GATESIM
11788//Do Nothing
11789`else
11790`ifdef CORE_4
11791 value[82] = ^value[40:0];
11792 value[83] = ^value[81:41];
11793 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
11794 `SPC4.mmu.mra1.array.mem[29] <= value;
11795`endif
11796
11797`endif
11798
11799`endif
11800
11801 end
11802 endtask
11803
11804
11805 task slam_MraRow5_core5_thread0;
11806 input [127:0] value;
11807 reg [5:0] tid;
11808 integer junk;
11809
11810 begin
11811`ifdef AXIS_EMUL_COSIM
11812//Do Nothing
11813`else
11814`ifdef GATESIM
11815//Do Nothing
11816`else
11817`ifdef CORE_5
11818 value[82] = ^value[40:0];
11819 value[83] = ^value[81:41];
11820 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
11821 `SPC5.mmu.mra0.array.mem[5] <= value;
11822`endif
11823
11824`endif
11825
11826`endif
11827
11828 end
11829 endtask
11830
11831
11832 task slam_MraRow5_core5_thread1;
11833 input [127:0] value;
11834 reg [5:0] tid;
11835 integer junk;
11836
11837 begin
11838`ifdef AXIS_EMUL_COSIM
11839//Do Nothing
11840`else
11841`ifdef GATESIM
11842//Do Nothing
11843`else
11844`ifdef CORE_5
11845 value[82] = ^value[40:0];
11846 value[83] = ^value[81:41];
11847 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
11848 `SPC5.mmu.mra0.array.mem[13] <= value;
11849`endif
11850
11851`endif
11852
11853`endif
11854
11855 end
11856 endtask
11857
11858
11859 task slam_MraRow5_core5_thread2;
11860 input [127:0] value;
11861 reg [5:0] tid;
11862 integer junk;
11863
11864 begin
11865`ifdef AXIS_EMUL_COSIM
11866//Do Nothing
11867`else
11868`ifdef GATESIM
11869//Do Nothing
11870`else
11871`ifdef CORE_5
11872 value[82] = ^value[40:0];
11873 value[83] = ^value[81:41];
11874 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
11875 `SPC5.mmu.mra0.array.mem[21] <= value;
11876`endif
11877
11878`endif
11879
11880`endif
11881
11882 end
11883 endtask
11884
11885
11886 task slam_MraRow5_core5_thread3;
11887 input [127:0] value;
11888 reg [5:0] tid;
11889 integer junk;
11890
11891 begin
11892`ifdef AXIS_EMUL_COSIM
11893//Do Nothing
11894`else
11895`ifdef GATESIM
11896//Do Nothing
11897`else
11898`ifdef CORE_5
11899 value[82] = ^value[40:0];
11900 value[83] = ^value[81:41];
11901 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
11902 `SPC5.mmu.mra0.array.mem[29] <= value;
11903`endif
11904
11905`endif
11906
11907`endif
11908
11909 end
11910 endtask
11911
11912
11913 task slam_MraRow5_core5_thread4;
11914 input [127:0] value;
11915 reg [5:0] tid;
11916 integer junk;
11917
11918 begin
11919`ifdef AXIS_EMUL_COSIM
11920//Do Nothing
11921`else
11922`ifdef GATESIM
11923//Do Nothing
11924`else
11925`ifdef CORE_5
11926 value[82] = ^value[40:0];
11927 value[83] = ^value[81:41];
11928 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
11929 `SPC5.mmu.mra1.array.mem[5] <= value;
11930`endif
11931
11932`endif
11933
11934`endif
11935
11936 end
11937 endtask
11938
11939
11940 task slam_MraRow5_core5_thread5;
11941 input [127:0] value;
11942 reg [5:0] tid;
11943 integer junk;
11944
11945 begin
11946`ifdef AXIS_EMUL_COSIM
11947//Do Nothing
11948`else
11949`ifdef GATESIM
11950//Do Nothing
11951`else
11952`ifdef CORE_5
11953 value[82] = ^value[40:0];
11954 value[83] = ^value[81:41];
11955 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
11956 `SPC5.mmu.mra1.array.mem[13] <= value;
11957`endif
11958
11959`endif
11960
11961`endif
11962
11963 end
11964 endtask
11965
11966
11967 task slam_MraRow5_core5_thread6;
11968 input [127:0] value;
11969 reg [5:0] tid;
11970 integer junk;
11971
11972 begin
11973`ifdef AXIS_EMUL_COSIM
11974//Do Nothing
11975`else
11976`ifdef GATESIM
11977//Do Nothing
11978`else
11979`ifdef CORE_5
11980 value[82] = ^value[40:0];
11981 value[83] = ^value[81:41];
11982 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
11983 `SPC5.mmu.mra1.array.mem[21] <= value;
11984`endif
11985
11986`endif
11987
11988`endif
11989
11990 end
11991 endtask
11992
11993
11994 task slam_MraRow5_core5_thread7;
11995 input [127:0] value;
11996 reg [5:0] tid;
11997 integer junk;
11998
11999 begin
12000`ifdef AXIS_EMUL_COSIM
12001//Do Nothing
12002`else
12003`ifdef GATESIM
12004//Do Nothing
12005`else
12006`ifdef CORE_5
12007 value[82] = ^value[40:0];
12008 value[83] = ^value[81:41];
12009 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
12010 `SPC5.mmu.mra1.array.mem[29] <= value;
12011`endif
12012
12013`endif
12014
12015`endif
12016
12017 end
12018 endtask
12019
12020
12021 task slam_MraRow5_core6_thread0;
12022 input [127:0] value;
12023 reg [5:0] tid;
12024 integer junk;
12025
12026 begin
12027`ifdef AXIS_EMUL_COSIM
12028//Do Nothing
12029`else
12030`ifdef GATESIM
12031//Do Nothing
12032`else
12033`ifdef CORE_6
12034 value[82] = ^value[40:0];
12035 value[83] = ^value[81:41];
12036 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
12037 `SPC6.mmu.mra0.array.mem[5] <= value;
12038`endif
12039
12040`endif
12041
12042`endif
12043
12044 end
12045 endtask
12046
12047
12048 task slam_MraRow5_core6_thread1;
12049 input [127:0] value;
12050 reg [5:0] tid;
12051 integer junk;
12052
12053 begin
12054`ifdef AXIS_EMUL_COSIM
12055//Do Nothing
12056`else
12057`ifdef GATESIM
12058//Do Nothing
12059`else
12060`ifdef CORE_6
12061 value[82] = ^value[40:0];
12062 value[83] = ^value[81:41];
12063 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
12064 `SPC6.mmu.mra0.array.mem[13] <= value;
12065`endif
12066
12067`endif
12068
12069`endif
12070
12071 end
12072 endtask
12073
12074
12075 task slam_MraRow5_core6_thread2;
12076 input [127:0] value;
12077 reg [5:0] tid;
12078 integer junk;
12079
12080 begin
12081`ifdef AXIS_EMUL_COSIM
12082//Do Nothing
12083`else
12084`ifdef GATESIM
12085//Do Nothing
12086`else
12087`ifdef CORE_6
12088 value[82] = ^value[40:0];
12089 value[83] = ^value[81:41];
12090 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
12091 `SPC6.mmu.mra0.array.mem[21] <= value;
12092`endif
12093
12094`endif
12095
12096`endif
12097
12098 end
12099 endtask
12100
12101
12102 task slam_MraRow5_core6_thread3;
12103 input [127:0] value;
12104 reg [5:0] tid;
12105 integer junk;
12106
12107 begin
12108`ifdef AXIS_EMUL_COSIM
12109//Do Nothing
12110`else
12111`ifdef GATESIM
12112//Do Nothing
12113`else
12114`ifdef CORE_6
12115 value[82] = ^value[40:0];
12116 value[83] = ^value[81:41];
12117 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
12118 `SPC6.mmu.mra0.array.mem[29] <= value;
12119`endif
12120
12121`endif
12122
12123`endif
12124
12125 end
12126 endtask
12127
12128
12129 task slam_MraRow5_core6_thread4;
12130 input [127:0] value;
12131 reg [5:0] tid;
12132 integer junk;
12133
12134 begin
12135`ifdef AXIS_EMUL_COSIM
12136//Do Nothing
12137`else
12138`ifdef GATESIM
12139//Do Nothing
12140`else
12141`ifdef CORE_6
12142 value[82] = ^value[40:0];
12143 value[83] = ^value[81:41];
12144 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
12145 `SPC6.mmu.mra1.array.mem[5] <= value;
12146`endif
12147
12148`endif
12149
12150`endif
12151
12152 end
12153 endtask
12154
12155
12156 task slam_MraRow5_core6_thread5;
12157 input [127:0] value;
12158 reg [5:0] tid;
12159 integer junk;
12160
12161 begin
12162`ifdef AXIS_EMUL_COSIM
12163//Do Nothing
12164`else
12165`ifdef GATESIM
12166//Do Nothing
12167`else
12168`ifdef CORE_6
12169 value[82] = ^value[40:0];
12170 value[83] = ^value[81:41];
12171 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
12172 `SPC6.mmu.mra1.array.mem[13] <= value;
12173`endif
12174
12175`endif
12176
12177`endif
12178
12179 end
12180 endtask
12181
12182
12183 task slam_MraRow5_core6_thread6;
12184 input [127:0] value;
12185 reg [5:0] tid;
12186 integer junk;
12187
12188 begin
12189`ifdef AXIS_EMUL_COSIM
12190//Do Nothing
12191`else
12192`ifdef GATESIM
12193//Do Nothing
12194`else
12195`ifdef CORE_6
12196 value[82] = ^value[40:0];
12197 value[83] = ^value[81:41];
12198 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
12199 `SPC6.mmu.mra1.array.mem[21] <= value;
12200`endif
12201
12202`endif
12203
12204`endif
12205
12206 end
12207 endtask
12208
12209
12210 task slam_MraRow5_core6_thread7;
12211 input [127:0] value;
12212 reg [5:0] tid;
12213 integer junk;
12214
12215 begin
12216`ifdef AXIS_EMUL_COSIM
12217//Do Nothing
12218`else
12219`ifdef GATESIM
12220//Do Nothing
12221`else
12222`ifdef CORE_6
12223 value[82] = ^value[40:0];
12224 value[83] = ^value[81:41];
12225 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
12226 `SPC6.mmu.mra1.array.mem[29] <= value;
12227`endif
12228
12229`endif
12230
12231`endif
12232
12233 end
12234 endtask
12235
12236
12237 task slam_MraRow5_core7_thread0;
12238 input [127:0] value;
12239 reg [5:0] tid;
12240 integer junk;
12241
12242 begin
12243`ifdef AXIS_EMUL_COSIM
12244//Do Nothing
12245`else
12246`ifdef GATESIM
12247//Do Nothing
12248`else
12249`ifdef CORE_7
12250 value[82] = ^value[40:0];
12251 value[83] = ^value[81:41];
12252 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[5]" );
12253 `SPC7.mmu.mra0.array.mem[5] <= value;
12254`endif
12255
12256`endif
12257
12258`endif
12259
12260 end
12261 endtask
12262
12263
12264 task slam_MraRow5_core7_thread1;
12265 input [127:0] value;
12266 reg [5:0] tid;
12267 integer junk;
12268
12269 begin
12270`ifdef AXIS_EMUL_COSIM
12271//Do Nothing
12272`else
12273`ifdef GATESIM
12274//Do Nothing
12275`else
12276`ifdef CORE_7
12277 value[82] = ^value[40:0];
12278 value[83] = ^value[81:41];
12279 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[13]" );
12280 `SPC7.mmu.mra0.array.mem[13] <= value;
12281`endif
12282
12283`endif
12284
12285`endif
12286
12287 end
12288 endtask
12289
12290
12291 task slam_MraRow5_core7_thread2;
12292 input [127:0] value;
12293 reg [5:0] tid;
12294 integer junk;
12295
12296 begin
12297`ifdef AXIS_EMUL_COSIM
12298//Do Nothing
12299`else
12300`ifdef GATESIM
12301//Do Nothing
12302`else
12303`ifdef CORE_7
12304 value[82] = ^value[40:0];
12305 value[83] = ^value[81:41];
12306 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[21]" );
12307 `SPC7.mmu.mra0.array.mem[21] <= value;
12308`endif
12309
12310`endif
12311
12312`endif
12313
12314 end
12315 endtask
12316
12317
12318 task slam_MraRow5_core7_thread3;
12319 input [127:0] value;
12320 reg [5:0] tid;
12321 integer junk;
12322
12323 begin
12324`ifdef AXIS_EMUL_COSIM
12325//Do Nothing
12326`else
12327`ifdef GATESIM
12328//Do Nothing
12329`else
12330`ifdef CORE_7
12331 value[82] = ^value[40:0];
12332 value[83] = ^value[81:41];
12333 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[29]" );
12334 `SPC7.mmu.mra0.array.mem[29] <= value;
12335`endif
12336
12337`endif
12338
12339`endif
12340
12341 end
12342 endtask
12343
12344
12345 task slam_MraRow5_core7_thread4;
12346 input [127:0] value;
12347 reg [5:0] tid;
12348 integer junk;
12349
12350 begin
12351`ifdef AXIS_EMUL_COSIM
12352//Do Nothing
12353`else
12354`ifdef GATESIM
12355//Do Nothing
12356`else
12357`ifdef CORE_7
12358 value[82] = ^value[40:0];
12359 value[83] = ^value[81:41];
12360 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[5]" );
12361 `SPC7.mmu.mra1.array.mem[5] <= value;
12362`endif
12363
12364`endif
12365
12366`endif
12367
12368 end
12369 endtask
12370
12371
12372 task slam_MraRow5_core7_thread5;
12373 input [127:0] value;
12374 reg [5:0] tid;
12375 integer junk;
12376
12377 begin
12378`ifdef AXIS_EMUL_COSIM
12379//Do Nothing
12380`else
12381`ifdef GATESIM
12382//Do Nothing
12383`else
12384`ifdef CORE_7
12385 value[82] = ^value[40:0];
12386 value[83] = ^value[81:41];
12387 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[13]" );
12388 `SPC7.mmu.mra1.array.mem[13] <= value;
12389`endif
12390
12391`endif
12392
12393`endif
12394
12395 end
12396 endtask
12397
12398
12399 task slam_MraRow5_core7_thread6;
12400 input [127:0] value;
12401 reg [5:0] tid;
12402 integer junk;
12403
12404 begin
12405`ifdef AXIS_EMUL_COSIM
12406//Do Nothing
12407`else
12408`ifdef GATESIM
12409//Do Nothing
12410`else
12411`ifdef CORE_7
12412 value[82] = ^value[40:0];
12413 value[83] = ^value[81:41];
12414 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[21]" );
12415 `SPC7.mmu.mra1.array.mem[21] <= value;
12416`endif
12417
12418`endif
12419
12420`endif
12421
12422 end
12423 endtask
12424
12425
12426 task slam_MraRow5_core7_thread7;
12427 input [127:0] value;
12428 reg [5:0] tid;
12429 integer junk;
12430
12431 begin
12432`ifdef AXIS_EMUL_COSIM
12433//Do Nothing
12434`else
12435`ifdef GATESIM
12436//Do Nothing
12437`else
12438`ifdef CORE_7
12439 value[82] = ^value[40:0];
12440 value[83] = ^value[81:41];
12441 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[29]" );
12442 `SPC7.mmu.mra1.array.mem[29] <= value;
12443`endif
12444
12445`endif
12446
12447`endif
12448
12449 end
12450 endtask
12451
12452
12453 task slam_MraRow6_core0_thread0;
12454 input [127:0] value;
12455 reg [5:0] tid;
12456 integer junk;
12457
12458 begin
12459`ifdef AXIS_EMUL_COSIM
12460//Do Nothing
12461`else
12462`ifdef GATESIM
12463//Do Nothing
12464`else
12465`ifdef CORE_0
12466 value[82] = ^value[40:0];
12467 value[83] = ^value[81:41];
12468 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
12469 `SPC0.mmu.mra0.array.mem[6] <= value;
12470`endif
12471
12472`endif
12473
12474`endif
12475
12476 end
12477 endtask
12478
12479
12480 task slam_MraRow6_core0_thread1;
12481 input [127:0] value;
12482 reg [5:0] tid;
12483 integer junk;
12484
12485 begin
12486`ifdef AXIS_EMUL_COSIM
12487//Do Nothing
12488`else
12489`ifdef GATESIM
12490//Do Nothing
12491`else
12492`ifdef CORE_0
12493 value[82] = ^value[40:0];
12494 value[83] = ^value[81:41];
12495 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
12496 `SPC0.mmu.mra0.array.mem[14] <= value;
12497`endif
12498
12499`endif
12500
12501`endif
12502
12503 end
12504 endtask
12505
12506
12507 task slam_MraRow6_core0_thread2;
12508 input [127:0] value;
12509 reg [5:0] tid;
12510 integer junk;
12511
12512 begin
12513`ifdef AXIS_EMUL_COSIM
12514//Do Nothing
12515`else
12516`ifdef GATESIM
12517//Do Nothing
12518`else
12519`ifdef CORE_0
12520 value[82] = ^value[40:0];
12521 value[83] = ^value[81:41];
12522 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
12523 `SPC0.mmu.mra0.array.mem[22] <= value;
12524`endif
12525
12526`endif
12527
12528`endif
12529
12530 end
12531 endtask
12532
12533
12534 task slam_MraRow6_core0_thread3;
12535 input [127:0] value;
12536 reg [5:0] tid;
12537 integer junk;
12538
12539 begin
12540`ifdef AXIS_EMUL_COSIM
12541//Do Nothing
12542`else
12543`ifdef GATESIM
12544//Do Nothing
12545`else
12546`ifdef CORE_0
12547 value[82] = ^value[40:0];
12548 value[83] = ^value[81:41];
12549 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
12550 `SPC0.mmu.mra0.array.mem[30] <= value;
12551`endif
12552
12553`endif
12554
12555`endif
12556
12557 end
12558 endtask
12559
12560
12561 task slam_MraRow6_core0_thread4;
12562 input [127:0] value;
12563 reg [5:0] tid;
12564 integer junk;
12565
12566 begin
12567`ifdef AXIS_EMUL_COSIM
12568//Do Nothing
12569`else
12570`ifdef GATESIM
12571//Do Nothing
12572`else
12573`ifdef CORE_0
12574 value[82] = ^value[40:0];
12575 value[83] = ^value[81:41];
12576 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
12577 `SPC0.mmu.mra1.array.mem[6] <= value;
12578`endif
12579
12580`endif
12581
12582`endif
12583
12584 end
12585 endtask
12586
12587
12588 task slam_MraRow6_core0_thread5;
12589 input [127:0] value;
12590 reg [5:0] tid;
12591 integer junk;
12592
12593 begin
12594`ifdef AXIS_EMUL_COSIM
12595//Do Nothing
12596`else
12597`ifdef GATESIM
12598//Do Nothing
12599`else
12600`ifdef CORE_0
12601 value[82] = ^value[40:0];
12602 value[83] = ^value[81:41];
12603 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
12604 `SPC0.mmu.mra1.array.mem[14] <= value;
12605`endif
12606
12607`endif
12608
12609`endif
12610
12611 end
12612 endtask
12613
12614
12615 task slam_MraRow6_core0_thread6;
12616 input [127:0] value;
12617 reg [5:0] tid;
12618 integer junk;
12619
12620 begin
12621`ifdef AXIS_EMUL_COSIM
12622//Do Nothing
12623`else
12624`ifdef GATESIM
12625//Do Nothing
12626`else
12627`ifdef CORE_0
12628 value[82] = ^value[40:0];
12629 value[83] = ^value[81:41];
12630 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
12631 `SPC0.mmu.mra1.array.mem[22] <= value;
12632`endif
12633
12634`endif
12635
12636`endif
12637
12638 end
12639 endtask
12640
12641
12642 task slam_MraRow6_core0_thread7;
12643 input [127:0] value;
12644 reg [5:0] tid;
12645 integer junk;
12646
12647 begin
12648`ifdef AXIS_EMUL_COSIM
12649//Do Nothing
12650`else
12651`ifdef GATESIM
12652//Do Nothing
12653`else
12654`ifdef CORE_0
12655 value[82] = ^value[40:0];
12656 value[83] = ^value[81:41];
12657 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
12658 `SPC0.mmu.mra1.array.mem[30] <= value;
12659`endif
12660
12661`endif
12662
12663`endif
12664
12665 end
12666 endtask
12667
12668
12669 task slam_MraRow6_core1_thread0;
12670 input [127:0] value;
12671 reg [5:0] tid;
12672 integer junk;
12673
12674 begin
12675`ifdef AXIS_EMUL_COSIM
12676//Do Nothing
12677`else
12678`ifdef GATESIM
12679//Do Nothing
12680`else
12681`ifdef CORE_1
12682 value[82] = ^value[40:0];
12683 value[83] = ^value[81:41];
12684 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
12685 `SPC1.mmu.mra0.array.mem[6] <= value;
12686`endif
12687
12688`endif
12689
12690`endif
12691
12692 end
12693 endtask
12694
12695
12696 task slam_MraRow6_core1_thread1;
12697 input [127:0] value;
12698 reg [5:0] tid;
12699 integer junk;
12700
12701 begin
12702`ifdef AXIS_EMUL_COSIM
12703//Do Nothing
12704`else
12705`ifdef GATESIM
12706//Do Nothing
12707`else
12708`ifdef CORE_1
12709 value[82] = ^value[40:0];
12710 value[83] = ^value[81:41];
12711 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
12712 `SPC1.mmu.mra0.array.mem[14] <= value;
12713`endif
12714
12715`endif
12716
12717`endif
12718
12719 end
12720 endtask
12721
12722
12723 task slam_MraRow6_core1_thread2;
12724 input [127:0] value;
12725 reg [5:0] tid;
12726 integer junk;
12727
12728 begin
12729`ifdef AXIS_EMUL_COSIM
12730//Do Nothing
12731`else
12732`ifdef GATESIM
12733//Do Nothing
12734`else
12735`ifdef CORE_1
12736 value[82] = ^value[40:0];
12737 value[83] = ^value[81:41];
12738 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
12739 `SPC1.mmu.mra0.array.mem[22] <= value;
12740`endif
12741
12742`endif
12743
12744`endif
12745
12746 end
12747 endtask
12748
12749
12750 task slam_MraRow6_core1_thread3;
12751 input [127:0] value;
12752 reg [5:0] tid;
12753 integer junk;
12754
12755 begin
12756`ifdef AXIS_EMUL_COSIM
12757//Do Nothing
12758`else
12759`ifdef GATESIM
12760//Do Nothing
12761`else
12762`ifdef CORE_1
12763 value[82] = ^value[40:0];
12764 value[83] = ^value[81:41];
12765 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
12766 `SPC1.mmu.mra0.array.mem[30] <= value;
12767`endif
12768
12769`endif
12770
12771`endif
12772
12773 end
12774 endtask
12775
12776
12777 task slam_MraRow6_core1_thread4;
12778 input [127:0] value;
12779 reg [5:0] tid;
12780 integer junk;
12781
12782 begin
12783`ifdef AXIS_EMUL_COSIM
12784//Do Nothing
12785`else
12786`ifdef GATESIM
12787//Do Nothing
12788`else
12789`ifdef CORE_1
12790 value[82] = ^value[40:0];
12791 value[83] = ^value[81:41];
12792 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
12793 `SPC1.mmu.mra1.array.mem[6] <= value;
12794`endif
12795
12796`endif
12797
12798`endif
12799
12800 end
12801 endtask
12802
12803
12804 task slam_MraRow6_core1_thread5;
12805 input [127:0] value;
12806 reg [5:0] tid;
12807 integer junk;
12808
12809 begin
12810`ifdef AXIS_EMUL_COSIM
12811//Do Nothing
12812`else
12813`ifdef GATESIM
12814//Do Nothing
12815`else
12816`ifdef CORE_1
12817 value[82] = ^value[40:0];
12818 value[83] = ^value[81:41];
12819 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
12820 `SPC1.mmu.mra1.array.mem[14] <= value;
12821`endif
12822
12823`endif
12824
12825`endif
12826
12827 end
12828 endtask
12829
12830
12831 task slam_MraRow6_core1_thread6;
12832 input [127:0] value;
12833 reg [5:0] tid;
12834 integer junk;
12835
12836 begin
12837`ifdef AXIS_EMUL_COSIM
12838//Do Nothing
12839`else
12840`ifdef GATESIM
12841//Do Nothing
12842`else
12843`ifdef CORE_1
12844 value[82] = ^value[40:0];
12845 value[83] = ^value[81:41];
12846 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
12847 `SPC1.mmu.mra1.array.mem[22] <= value;
12848`endif
12849
12850`endif
12851
12852`endif
12853
12854 end
12855 endtask
12856
12857
12858 task slam_MraRow6_core1_thread7;
12859 input [127:0] value;
12860 reg [5:0] tid;
12861 integer junk;
12862
12863 begin
12864`ifdef AXIS_EMUL_COSIM
12865//Do Nothing
12866`else
12867`ifdef GATESIM
12868//Do Nothing
12869`else
12870`ifdef CORE_1
12871 value[82] = ^value[40:0];
12872 value[83] = ^value[81:41];
12873 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
12874 `SPC1.mmu.mra1.array.mem[30] <= value;
12875`endif
12876
12877`endif
12878
12879`endif
12880
12881 end
12882 endtask
12883
12884
12885 task slam_MraRow6_core2_thread0;
12886 input [127:0] value;
12887 reg [5:0] tid;
12888 integer junk;
12889
12890 begin
12891`ifdef AXIS_EMUL_COSIM
12892//Do Nothing
12893`else
12894`ifdef GATESIM
12895//Do Nothing
12896`else
12897`ifdef CORE_2
12898 value[82] = ^value[40:0];
12899 value[83] = ^value[81:41];
12900 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
12901 `SPC2.mmu.mra0.array.mem[6] <= value;
12902`endif
12903
12904`endif
12905
12906`endif
12907
12908 end
12909 endtask
12910
12911
12912 task slam_MraRow6_core2_thread1;
12913 input [127:0] value;
12914 reg [5:0] tid;
12915 integer junk;
12916
12917 begin
12918`ifdef AXIS_EMUL_COSIM
12919//Do Nothing
12920`else
12921`ifdef GATESIM
12922//Do Nothing
12923`else
12924`ifdef CORE_2
12925 value[82] = ^value[40:0];
12926 value[83] = ^value[81:41];
12927 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
12928 `SPC2.mmu.mra0.array.mem[14] <= value;
12929`endif
12930
12931`endif
12932
12933`endif
12934
12935 end
12936 endtask
12937
12938
12939 task slam_MraRow6_core2_thread2;
12940 input [127:0] value;
12941 reg [5:0] tid;
12942 integer junk;
12943
12944 begin
12945`ifdef AXIS_EMUL_COSIM
12946//Do Nothing
12947`else
12948`ifdef GATESIM
12949//Do Nothing
12950`else
12951`ifdef CORE_2
12952 value[82] = ^value[40:0];
12953 value[83] = ^value[81:41];
12954 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
12955 `SPC2.mmu.mra0.array.mem[22] <= value;
12956`endif
12957
12958`endif
12959
12960`endif
12961
12962 end
12963 endtask
12964
12965
12966 task slam_MraRow6_core2_thread3;
12967 input [127:0] value;
12968 reg [5:0] tid;
12969 integer junk;
12970
12971 begin
12972`ifdef AXIS_EMUL_COSIM
12973//Do Nothing
12974`else
12975`ifdef GATESIM
12976//Do Nothing
12977`else
12978`ifdef CORE_2
12979 value[82] = ^value[40:0];
12980 value[83] = ^value[81:41];
12981 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
12982 `SPC2.mmu.mra0.array.mem[30] <= value;
12983`endif
12984
12985`endif
12986
12987`endif
12988
12989 end
12990 endtask
12991
12992
12993 task slam_MraRow6_core2_thread4;
12994 input [127:0] value;
12995 reg [5:0] tid;
12996 integer junk;
12997
12998 begin
12999`ifdef AXIS_EMUL_COSIM
13000//Do Nothing
13001`else
13002`ifdef GATESIM
13003//Do Nothing
13004`else
13005`ifdef CORE_2
13006 value[82] = ^value[40:0];
13007 value[83] = ^value[81:41];
13008 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
13009 `SPC2.mmu.mra1.array.mem[6] <= value;
13010`endif
13011
13012`endif
13013
13014`endif
13015
13016 end
13017 endtask
13018
13019
13020 task slam_MraRow6_core2_thread5;
13021 input [127:0] value;
13022 reg [5:0] tid;
13023 integer junk;
13024
13025 begin
13026`ifdef AXIS_EMUL_COSIM
13027//Do Nothing
13028`else
13029`ifdef GATESIM
13030//Do Nothing
13031`else
13032`ifdef CORE_2
13033 value[82] = ^value[40:0];
13034 value[83] = ^value[81:41];
13035 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
13036 `SPC2.mmu.mra1.array.mem[14] <= value;
13037`endif
13038
13039`endif
13040
13041`endif
13042
13043 end
13044 endtask
13045
13046
13047 task slam_MraRow6_core2_thread6;
13048 input [127:0] value;
13049 reg [5:0] tid;
13050 integer junk;
13051
13052 begin
13053`ifdef AXIS_EMUL_COSIM
13054//Do Nothing
13055`else
13056`ifdef GATESIM
13057//Do Nothing
13058`else
13059`ifdef CORE_2
13060 value[82] = ^value[40:0];
13061 value[83] = ^value[81:41];
13062 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
13063 `SPC2.mmu.mra1.array.mem[22] <= value;
13064`endif
13065
13066`endif
13067
13068`endif
13069
13070 end
13071 endtask
13072
13073
13074 task slam_MraRow6_core2_thread7;
13075 input [127:0] value;
13076 reg [5:0] tid;
13077 integer junk;
13078
13079 begin
13080`ifdef AXIS_EMUL_COSIM
13081//Do Nothing
13082`else
13083`ifdef GATESIM
13084//Do Nothing
13085`else
13086`ifdef CORE_2
13087 value[82] = ^value[40:0];
13088 value[83] = ^value[81:41];
13089 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
13090 `SPC2.mmu.mra1.array.mem[30] <= value;
13091`endif
13092
13093`endif
13094
13095`endif
13096
13097 end
13098 endtask
13099
13100
13101 task slam_MraRow6_core3_thread0;
13102 input [127:0] value;
13103 reg [5:0] tid;
13104 integer junk;
13105
13106 begin
13107`ifdef AXIS_EMUL_COSIM
13108//Do Nothing
13109`else
13110`ifdef GATESIM
13111//Do Nothing
13112`else
13113`ifdef CORE_3
13114 value[82] = ^value[40:0];
13115 value[83] = ^value[81:41];
13116 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
13117 `SPC3.mmu.mra0.array.mem[6] <= value;
13118`endif
13119
13120`endif
13121
13122`endif
13123
13124 end
13125 endtask
13126
13127
13128 task slam_MraRow6_core3_thread1;
13129 input [127:0] value;
13130 reg [5:0] tid;
13131 integer junk;
13132
13133 begin
13134`ifdef AXIS_EMUL_COSIM
13135//Do Nothing
13136`else
13137`ifdef GATESIM
13138//Do Nothing
13139`else
13140`ifdef CORE_3
13141 value[82] = ^value[40:0];
13142 value[83] = ^value[81:41];
13143 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
13144 `SPC3.mmu.mra0.array.mem[14] <= value;
13145`endif
13146
13147`endif
13148
13149`endif
13150
13151 end
13152 endtask
13153
13154
13155 task slam_MraRow6_core3_thread2;
13156 input [127:0] value;
13157 reg [5:0] tid;
13158 integer junk;
13159
13160 begin
13161`ifdef AXIS_EMUL_COSIM
13162//Do Nothing
13163`else
13164`ifdef GATESIM
13165//Do Nothing
13166`else
13167`ifdef CORE_3
13168 value[82] = ^value[40:0];
13169 value[83] = ^value[81:41];
13170 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
13171 `SPC3.mmu.mra0.array.mem[22] <= value;
13172`endif
13173
13174`endif
13175
13176`endif
13177
13178 end
13179 endtask
13180
13181
13182 task slam_MraRow6_core3_thread3;
13183 input [127:0] value;
13184 reg [5:0] tid;
13185 integer junk;
13186
13187 begin
13188`ifdef AXIS_EMUL_COSIM
13189//Do Nothing
13190`else
13191`ifdef GATESIM
13192//Do Nothing
13193`else
13194`ifdef CORE_3
13195 value[82] = ^value[40:0];
13196 value[83] = ^value[81:41];
13197 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
13198 `SPC3.mmu.mra0.array.mem[30] <= value;
13199`endif
13200
13201`endif
13202
13203`endif
13204
13205 end
13206 endtask
13207
13208
13209 task slam_MraRow6_core3_thread4;
13210 input [127:0] value;
13211 reg [5:0] tid;
13212 integer junk;
13213
13214 begin
13215`ifdef AXIS_EMUL_COSIM
13216//Do Nothing
13217`else
13218`ifdef GATESIM
13219//Do Nothing
13220`else
13221`ifdef CORE_3
13222 value[82] = ^value[40:0];
13223 value[83] = ^value[81:41];
13224 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
13225 `SPC3.mmu.mra1.array.mem[6] <= value;
13226`endif
13227
13228`endif
13229
13230`endif
13231
13232 end
13233 endtask
13234
13235
13236 task slam_MraRow6_core3_thread5;
13237 input [127:0] value;
13238 reg [5:0] tid;
13239 integer junk;
13240
13241 begin
13242`ifdef AXIS_EMUL_COSIM
13243//Do Nothing
13244`else
13245`ifdef GATESIM
13246//Do Nothing
13247`else
13248`ifdef CORE_3
13249 value[82] = ^value[40:0];
13250 value[83] = ^value[81:41];
13251 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
13252 `SPC3.mmu.mra1.array.mem[14] <= value;
13253`endif
13254
13255`endif
13256
13257`endif
13258
13259 end
13260 endtask
13261
13262
13263 task slam_MraRow6_core3_thread6;
13264 input [127:0] value;
13265 reg [5:0] tid;
13266 integer junk;
13267
13268 begin
13269`ifdef AXIS_EMUL_COSIM
13270//Do Nothing
13271`else
13272`ifdef GATESIM
13273//Do Nothing
13274`else
13275`ifdef CORE_3
13276 value[82] = ^value[40:0];
13277 value[83] = ^value[81:41];
13278 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
13279 `SPC3.mmu.mra1.array.mem[22] <= value;
13280`endif
13281
13282`endif
13283
13284`endif
13285
13286 end
13287 endtask
13288
13289
13290 task slam_MraRow6_core3_thread7;
13291 input [127:0] value;
13292 reg [5:0] tid;
13293 integer junk;
13294
13295 begin
13296`ifdef AXIS_EMUL_COSIM
13297//Do Nothing
13298`else
13299`ifdef GATESIM
13300//Do Nothing
13301`else
13302`ifdef CORE_3
13303 value[82] = ^value[40:0];
13304 value[83] = ^value[81:41];
13305 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
13306 `SPC3.mmu.mra1.array.mem[30] <= value;
13307`endif
13308
13309`endif
13310
13311`endif
13312
13313 end
13314 endtask
13315
13316
13317 task slam_MraRow6_core4_thread0;
13318 input [127:0] value;
13319 reg [5:0] tid;
13320 integer junk;
13321
13322 begin
13323`ifdef AXIS_EMUL_COSIM
13324//Do Nothing
13325`else
13326`ifdef GATESIM
13327//Do Nothing
13328`else
13329`ifdef CORE_4
13330 value[82] = ^value[40:0];
13331 value[83] = ^value[81:41];
13332 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
13333 `SPC4.mmu.mra0.array.mem[6] <= value;
13334`endif
13335
13336`endif
13337
13338`endif
13339
13340 end
13341 endtask
13342
13343
13344 task slam_MraRow6_core4_thread1;
13345 input [127:0] value;
13346 reg [5:0] tid;
13347 integer junk;
13348
13349 begin
13350`ifdef AXIS_EMUL_COSIM
13351//Do Nothing
13352`else
13353`ifdef GATESIM
13354//Do Nothing
13355`else
13356`ifdef CORE_4
13357 value[82] = ^value[40:0];
13358 value[83] = ^value[81:41];
13359 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
13360 `SPC4.mmu.mra0.array.mem[14] <= value;
13361`endif
13362
13363`endif
13364
13365`endif
13366
13367 end
13368 endtask
13369
13370
13371 task slam_MraRow6_core4_thread2;
13372 input [127:0] value;
13373 reg [5:0] tid;
13374 integer junk;
13375
13376 begin
13377`ifdef AXIS_EMUL_COSIM
13378//Do Nothing
13379`else
13380`ifdef GATESIM
13381//Do Nothing
13382`else
13383`ifdef CORE_4
13384 value[82] = ^value[40:0];
13385 value[83] = ^value[81:41];
13386 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
13387 `SPC4.mmu.mra0.array.mem[22] <= value;
13388`endif
13389
13390`endif
13391
13392`endif
13393
13394 end
13395 endtask
13396
13397
13398 task slam_MraRow6_core4_thread3;
13399 input [127:0] value;
13400 reg [5:0] tid;
13401 integer junk;
13402
13403 begin
13404`ifdef AXIS_EMUL_COSIM
13405//Do Nothing
13406`else
13407`ifdef GATESIM
13408//Do Nothing
13409`else
13410`ifdef CORE_4
13411 value[82] = ^value[40:0];
13412 value[83] = ^value[81:41];
13413 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
13414 `SPC4.mmu.mra0.array.mem[30] <= value;
13415`endif
13416
13417`endif
13418
13419`endif
13420
13421 end
13422 endtask
13423
13424
13425 task slam_MraRow6_core4_thread4;
13426 input [127:0] value;
13427 reg [5:0] tid;
13428 integer junk;
13429
13430 begin
13431`ifdef AXIS_EMUL_COSIM
13432//Do Nothing
13433`else
13434`ifdef GATESIM
13435//Do Nothing
13436`else
13437`ifdef CORE_4
13438 value[82] = ^value[40:0];
13439 value[83] = ^value[81:41];
13440 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
13441 `SPC4.mmu.mra1.array.mem[6] <= value;
13442`endif
13443
13444`endif
13445
13446`endif
13447
13448 end
13449 endtask
13450
13451
13452 task slam_MraRow6_core4_thread5;
13453 input [127:0] value;
13454 reg [5:0] tid;
13455 integer junk;
13456
13457 begin
13458`ifdef AXIS_EMUL_COSIM
13459//Do Nothing
13460`else
13461`ifdef GATESIM
13462//Do Nothing
13463`else
13464`ifdef CORE_4
13465 value[82] = ^value[40:0];
13466 value[83] = ^value[81:41];
13467 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
13468 `SPC4.mmu.mra1.array.mem[14] <= value;
13469`endif
13470
13471`endif
13472
13473`endif
13474
13475 end
13476 endtask
13477
13478
13479 task slam_MraRow6_core4_thread6;
13480 input [127:0] value;
13481 reg [5:0] tid;
13482 integer junk;
13483
13484 begin
13485`ifdef AXIS_EMUL_COSIM
13486//Do Nothing
13487`else
13488`ifdef GATESIM
13489//Do Nothing
13490`else
13491`ifdef CORE_4
13492 value[82] = ^value[40:0];
13493 value[83] = ^value[81:41];
13494 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
13495 `SPC4.mmu.mra1.array.mem[22] <= value;
13496`endif
13497
13498`endif
13499
13500`endif
13501
13502 end
13503 endtask
13504
13505
13506 task slam_MraRow6_core4_thread7;
13507 input [127:0] value;
13508 reg [5:0] tid;
13509 integer junk;
13510
13511 begin
13512`ifdef AXIS_EMUL_COSIM
13513//Do Nothing
13514`else
13515`ifdef GATESIM
13516//Do Nothing
13517`else
13518`ifdef CORE_4
13519 value[82] = ^value[40:0];
13520 value[83] = ^value[81:41];
13521 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
13522 `SPC4.mmu.mra1.array.mem[30] <= value;
13523`endif
13524
13525`endif
13526
13527`endif
13528
13529 end
13530 endtask
13531
13532
13533 task slam_MraRow6_core5_thread0;
13534 input [127:0] value;
13535 reg [5:0] tid;
13536 integer junk;
13537
13538 begin
13539`ifdef AXIS_EMUL_COSIM
13540//Do Nothing
13541`else
13542`ifdef GATESIM
13543//Do Nothing
13544`else
13545`ifdef CORE_5
13546 value[82] = ^value[40:0];
13547 value[83] = ^value[81:41];
13548 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
13549 `SPC5.mmu.mra0.array.mem[6] <= value;
13550`endif
13551
13552`endif
13553
13554`endif
13555
13556 end
13557 endtask
13558
13559
13560 task slam_MraRow6_core5_thread1;
13561 input [127:0] value;
13562 reg [5:0] tid;
13563 integer junk;
13564
13565 begin
13566`ifdef AXIS_EMUL_COSIM
13567//Do Nothing
13568`else
13569`ifdef GATESIM
13570//Do Nothing
13571`else
13572`ifdef CORE_5
13573 value[82] = ^value[40:0];
13574 value[83] = ^value[81:41];
13575 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
13576 `SPC5.mmu.mra0.array.mem[14] <= value;
13577`endif
13578
13579`endif
13580
13581`endif
13582
13583 end
13584 endtask
13585
13586
13587 task slam_MraRow6_core5_thread2;
13588 input [127:0] value;
13589 reg [5:0] tid;
13590 integer junk;
13591
13592 begin
13593`ifdef AXIS_EMUL_COSIM
13594//Do Nothing
13595`else
13596`ifdef GATESIM
13597//Do Nothing
13598`else
13599`ifdef CORE_5
13600 value[82] = ^value[40:0];
13601 value[83] = ^value[81:41];
13602 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
13603 `SPC5.mmu.mra0.array.mem[22] <= value;
13604`endif
13605
13606`endif
13607
13608`endif
13609
13610 end
13611 endtask
13612
13613
13614 task slam_MraRow6_core5_thread3;
13615 input [127:0] value;
13616 reg [5:0] tid;
13617 integer junk;
13618
13619 begin
13620`ifdef AXIS_EMUL_COSIM
13621//Do Nothing
13622`else
13623`ifdef GATESIM
13624//Do Nothing
13625`else
13626`ifdef CORE_5
13627 value[82] = ^value[40:0];
13628 value[83] = ^value[81:41];
13629 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
13630 `SPC5.mmu.mra0.array.mem[30] <= value;
13631`endif
13632
13633`endif
13634
13635`endif
13636
13637 end
13638 endtask
13639
13640
13641 task slam_MraRow6_core5_thread4;
13642 input [127:0] value;
13643 reg [5:0] tid;
13644 integer junk;
13645
13646 begin
13647`ifdef AXIS_EMUL_COSIM
13648//Do Nothing
13649`else
13650`ifdef GATESIM
13651//Do Nothing
13652`else
13653`ifdef CORE_5
13654 value[82] = ^value[40:0];
13655 value[83] = ^value[81:41];
13656 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
13657 `SPC5.mmu.mra1.array.mem[6] <= value;
13658`endif
13659
13660`endif
13661
13662`endif
13663
13664 end
13665 endtask
13666
13667
13668 task slam_MraRow6_core5_thread5;
13669 input [127:0] value;
13670 reg [5:0] tid;
13671 integer junk;
13672
13673 begin
13674`ifdef AXIS_EMUL_COSIM
13675//Do Nothing
13676`else
13677`ifdef GATESIM
13678//Do Nothing
13679`else
13680`ifdef CORE_5
13681 value[82] = ^value[40:0];
13682 value[83] = ^value[81:41];
13683 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
13684 `SPC5.mmu.mra1.array.mem[14] <= value;
13685`endif
13686
13687`endif
13688
13689`endif
13690
13691 end
13692 endtask
13693
13694
13695 task slam_MraRow6_core5_thread6;
13696 input [127:0] value;
13697 reg [5:0] tid;
13698 integer junk;
13699
13700 begin
13701`ifdef AXIS_EMUL_COSIM
13702//Do Nothing
13703`else
13704`ifdef GATESIM
13705//Do Nothing
13706`else
13707`ifdef CORE_5
13708 value[82] = ^value[40:0];
13709 value[83] = ^value[81:41];
13710 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
13711 `SPC5.mmu.mra1.array.mem[22] <= value;
13712`endif
13713
13714`endif
13715
13716`endif
13717
13718 end
13719 endtask
13720
13721
13722 task slam_MraRow6_core5_thread7;
13723 input [127:0] value;
13724 reg [5:0] tid;
13725 integer junk;
13726
13727 begin
13728`ifdef AXIS_EMUL_COSIM
13729//Do Nothing
13730`else
13731`ifdef GATESIM
13732//Do Nothing
13733`else
13734`ifdef CORE_5
13735 value[82] = ^value[40:0];
13736 value[83] = ^value[81:41];
13737 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
13738 `SPC5.mmu.mra1.array.mem[30] <= value;
13739`endif
13740
13741`endif
13742
13743`endif
13744
13745 end
13746 endtask
13747
13748
13749 task slam_MraRow6_core6_thread0;
13750 input [127:0] value;
13751 reg [5:0] tid;
13752 integer junk;
13753
13754 begin
13755`ifdef AXIS_EMUL_COSIM
13756//Do Nothing
13757`else
13758`ifdef GATESIM
13759//Do Nothing
13760`else
13761`ifdef CORE_6
13762 value[82] = ^value[40:0];
13763 value[83] = ^value[81:41];
13764 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
13765 `SPC6.mmu.mra0.array.mem[6] <= value;
13766`endif
13767
13768`endif
13769
13770`endif
13771
13772 end
13773 endtask
13774
13775
13776 task slam_MraRow6_core6_thread1;
13777 input [127:0] value;
13778 reg [5:0] tid;
13779 integer junk;
13780
13781 begin
13782`ifdef AXIS_EMUL_COSIM
13783//Do Nothing
13784`else
13785`ifdef GATESIM
13786//Do Nothing
13787`else
13788`ifdef CORE_6
13789 value[82] = ^value[40:0];
13790 value[83] = ^value[81:41];
13791 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
13792 `SPC6.mmu.mra0.array.mem[14] <= value;
13793`endif
13794
13795`endif
13796
13797`endif
13798
13799 end
13800 endtask
13801
13802
13803 task slam_MraRow6_core6_thread2;
13804 input [127:0] value;
13805 reg [5:0] tid;
13806 integer junk;
13807
13808 begin
13809`ifdef AXIS_EMUL_COSIM
13810//Do Nothing
13811`else
13812`ifdef GATESIM
13813//Do Nothing
13814`else
13815`ifdef CORE_6
13816 value[82] = ^value[40:0];
13817 value[83] = ^value[81:41];
13818 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
13819 `SPC6.mmu.mra0.array.mem[22] <= value;
13820`endif
13821
13822`endif
13823
13824`endif
13825
13826 end
13827 endtask
13828
13829
13830 task slam_MraRow6_core6_thread3;
13831 input [127:0] value;
13832 reg [5:0] tid;
13833 integer junk;
13834
13835 begin
13836`ifdef AXIS_EMUL_COSIM
13837//Do Nothing
13838`else
13839`ifdef GATESIM
13840//Do Nothing
13841`else
13842`ifdef CORE_6
13843 value[82] = ^value[40:0];
13844 value[83] = ^value[81:41];
13845 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
13846 `SPC6.mmu.mra0.array.mem[30] <= value;
13847`endif
13848
13849`endif
13850
13851`endif
13852
13853 end
13854 endtask
13855
13856
13857 task slam_MraRow6_core6_thread4;
13858 input [127:0] value;
13859 reg [5:0] tid;
13860 integer junk;
13861
13862 begin
13863`ifdef AXIS_EMUL_COSIM
13864//Do Nothing
13865`else
13866`ifdef GATESIM
13867//Do Nothing
13868`else
13869`ifdef CORE_6
13870 value[82] = ^value[40:0];
13871 value[83] = ^value[81:41];
13872 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
13873 `SPC6.mmu.mra1.array.mem[6] <= value;
13874`endif
13875
13876`endif
13877
13878`endif
13879
13880 end
13881 endtask
13882
13883
13884 task slam_MraRow6_core6_thread5;
13885 input [127:0] value;
13886 reg [5:0] tid;
13887 integer junk;
13888
13889 begin
13890`ifdef AXIS_EMUL_COSIM
13891//Do Nothing
13892`else
13893`ifdef GATESIM
13894//Do Nothing
13895`else
13896`ifdef CORE_6
13897 value[82] = ^value[40:0];
13898 value[83] = ^value[81:41];
13899 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
13900 `SPC6.mmu.mra1.array.mem[14] <= value;
13901`endif
13902
13903`endif
13904
13905`endif
13906
13907 end
13908 endtask
13909
13910
13911 task slam_MraRow6_core6_thread6;
13912 input [127:0] value;
13913 reg [5:0] tid;
13914 integer junk;
13915
13916 begin
13917`ifdef AXIS_EMUL_COSIM
13918//Do Nothing
13919`else
13920`ifdef GATESIM
13921//Do Nothing
13922`else
13923`ifdef CORE_6
13924 value[82] = ^value[40:0];
13925 value[83] = ^value[81:41];
13926 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
13927 `SPC6.mmu.mra1.array.mem[22] <= value;
13928`endif
13929
13930`endif
13931
13932`endif
13933
13934 end
13935 endtask
13936
13937
13938 task slam_MraRow6_core6_thread7;
13939 input [127:0] value;
13940 reg [5:0] tid;
13941 integer junk;
13942
13943 begin
13944`ifdef AXIS_EMUL_COSIM
13945//Do Nothing
13946`else
13947`ifdef GATESIM
13948//Do Nothing
13949`else
13950`ifdef CORE_6
13951 value[82] = ^value[40:0];
13952 value[83] = ^value[81:41];
13953 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
13954 `SPC6.mmu.mra1.array.mem[30] <= value;
13955`endif
13956
13957`endif
13958
13959`endif
13960
13961 end
13962 endtask
13963
13964
13965 task slam_MraRow6_core7_thread0;
13966 input [127:0] value;
13967 reg [5:0] tid;
13968 integer junk;
13969
13970 begin
13971`ifdef AXIS_EMUL_COSIM
13972//Do Nothing
13973`else
13974`ifdef GATESIM
13975//Do Nothing
13976`else
13977`ifdef CORE_7
13978 value[82] = ^value[40:0];
13979 value[83] = ^value[81:41];
13980 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[6]" );
13981 `SPC7.mmu.mra0.array.mem[6] <= value;
13982`endif
13983
13984`endif
13985
13986`endif
13987
13988 end
13989 endtask
13990
13991
13992 task slam_MraRow6_core7_thread1;
13993 input [127:0] value;
13994 reg [5:0] tid;
13995 integer junk;
13996
13997 begin
13998`ifdef AXIS_EMUL_COSIM
13999//Do Nothing
14000`else
14001`ifdef GATESIM
14002//Do Nothing
14003`else
14004`ifdef CORE_7
14005 value[82] = ^value[40:0];
14006 value[83] = ^value[81:41];
14007 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[14]" );
14008 `SPC7.mmu.mra0.array.mem[14] <= value;
14009`endif
14010
14011`endif
14012
14013`endif
14014
14015 end
14016 endtask
14017
14018
14019 task slam_MraRow6_core7_thread2;
14020 input [127:0] value;
14021 reg [5:0] tid;
14022 integer junk;
14023
14024 begin
14025`ifdef AXIS_EMUL_COSIM
14026//Do Nothing
14027`else
14028`ifdef GATESIM
14029//Do Nothing
14030`else
14031`ifdef CORE_7
14032 value[82] = ^value[40:0];
14033 value[83] = ^value[81:41];
14034 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[22]" );
14035 `SPC7.mmu.mra0.array.mem[22] <= value;
14036`endif
14037
14038`endif
14039
14040`endif
14041
14042 end
14043 endtask
14044
14045
14046 task slam_MraRow6_core7_thread3;
14047 input [127:0] value;
14048 reg [5:0] tid;
14049 integer junk;
14050
14051 begin
14052`ifdef AXIS_EMUL_COSIM
14053//Do Nothing
14054`else
14055`ifdef GATESIM
14056//Do Nothing
14057`else
14058`ifdef CORE_7
14059 value[82] = ^value[40:0];
14060 value[83] = ^value[81:41];
14061 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[30]" );
14062 `SPC7.mmu.mra0.array.mem[30] <= value;
14063`endif
14064
14065`endif
14066
14067`endif
14068
14069 end
14070 endtask
14071
14072
14073 task slam_MraRow6_core7_thread4;
14074 input [127:0] value;
14075 reg [5:0] tid;
14076 integer junk;
14077
14078 begin
14079`ifdef AXIS_EMUL_COSIM
14080//Do Nothing
14081`else
14082`ifdef GATESIM
14083//Do Nothing
14084`else
14085`ifdef CORE_7
14086 value[82] = ^value[40:0];
14087 value[83] = ^value[81:41];
14088 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[6]" );
14089 `SPC7.mmu.mra1.array.mem[6] <= value;
14090`endif
14091
14092`endif
14093
14094`endif
14095
14096 end
14097 endtask
14098
14099
14100 task slam_MraRow6_core7_thread5;
14101 input [127:0] value;
14102 reg [5:0] tid;
14103 integer junk;
14104
14105 begin
14106`ifdef AXIS_EMUL_COSIM
14107//Do Nothing
14108`else
14109`ifdef GATESIM
14110//Do Nothing
14111`else
14112`ifdef CORE_7
14113 value[82] = ^value[40:0];
14114 value[83] = ^value[81:41];
14115 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[14]" );
14116 `SPC7.mmu.mra1.array.mem[14] <= value;
14117`endif
14118
14119`endif
14120
14121`endif
14122
14123 end
14124 endtask
14125
14126
14127 task slam_MraRow6_core7_thread6;
14128 input [127:0] value;
14129 reg [5:0] tid;
14130 integer junk;
14131
14132 begin
14133`ifdef AXIS_EMUL_COSIM
14134//Do Nothing
14135`else
14136`ifdef GATESIM
14137//Do Nothing
14138`else
14139`ifdef CORE_7
14140 value[82] = ^value[40:0];
14141 value[83] = ^value[81:41];
14142 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[22]" );
14143 `SPC7.mmu.mra1.array.mem[22] <= value;
14144`endif
14145
14146`endif
14147
14148`endif
14149
14150 end
14151 endtask
14152
14153
14154 task slam_MraRow6_core7_thread7;
14155 input [127:0] value;
14156 reg [5:0] tid;
14157 integer junk;
14158
14159 begin
14160`ifdef AXIS_EMUL_COSIM
14161//Do Nothing
14162`else
14163`ifdef GATESIM
14164//Do Nothing
14165`else
14166`ifdef CORE_7
14167 value[82] = ^value[40:0];
14168 value[83] = ^value[81:41];
14169 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[30]" );
14170 `SPC7.mmu.mra1.array.mem[30] <= value;
14171`endif
14172
14173`endif
14174
14175`endif
14176
14177 end
14178 endtask
14179
14180
14181 task slam_MraRow7_core0_thread0;
14182 input [127:0] value;
14183 reg [5:0] tid;
14184 integer junk;
14185
14186 begin
14187`ifdef AXIS_EMUL_COSIM
14188//Do Nothing
14189`else
14190`ifdef GATESIM
14191//Do Nothing
14192`else
14193`ifdef CORE_0
14194 value[82] = ^value[40:0];
14195 value[83] = ^value[81:41];
14196 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
14197 `SPC0.mmu.mra0.array.mem[7] <= value;
14198`endif
14199
14200`endif
14201
14202`endif
14203
14204 end
14205 endtask
14206
14207
14208 task slam_MraRow7_core0_thread1;
14209 input [127:0] value;
14210 reg [5:0] tid;
14211 integer junk;
14212
14213 begin
14214`ifdef AXIS_EMUL_COSIM
14215//Do Nothing
14216`else
14217`ifdef GATESIM
14218//Do Nothing
14219`else
14220`ifdef CORE_0
14221 value[82] = ^value[40:0];
14222 value[83] = ^value[81:41];
14223 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
14224 `SPC0.mmu.mra0.array.mem[15] <= value;
14225`endif
14226
14227`endif
14228
14229`endif
14230
14231 end
14232 endtask
14233
14234
14235 task slam_MraRow7_core0_thread2;
14236 input [127:0] value;
14237 reg [5:0] tid;
14238 integer junk;
14239
14240 begin
14241`ifdef AXIS_EMUL_COSIM
14242//Do Nothing
14243`else
14244`ifdef GATESIM
14245//Do Nothing
14246`else
14247`ifdef CORE_0
14248 value[82] = ^value[40:0];
14249 value[83] = ^value[81:41];
14250 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
14251 `SPC0.mmu.mra0.array.mem[23] <= value;
14252`endif
14253
14254`endif
14255
14256`endif
14257
14258 end
14259 endtask
14260
14261
14262 task slam_MraRow7_core0_thread3;
14263 input [127:0] value;
14264 reg [5:0] tid;
14265 integer junk;
14266
14267 begin
14268`ifdef AXIS_EMUL_COSIM
14269//Do Nothing
14270`else
14271`ifdef GATESIM
14272//Do Nothing
14273`else
14274`ifdef CORE_0
14275 value[82] = ^value[40:0];
14276 value[83] = ^value[81:41];
14277 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
14278 `SPC0.mmu.mra0.array.mem[31] <= value;
14279`endif
14280
14281`endif
14282
14283`endif
14284
14285 end
14286 endtask
14287
14288
14289 task slam_MraRow7_core0_thread4;
14290 input [127:0] value;
14291 reg [5:0] tid;
14292 integer junk;
14293
14294 begin
14295`ifdef AXIS_EMUL_COSIM
14296//Do Nothing
14297`else
14298`ifdef GATESIM
14299//Do Nothing
14300`else
14301`ifdef CORE_0
14302 value[82] = ^value[40:0];
14303 value[83] = ^value[81:41];
14304 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
14305 `SPC0.mmu.mra1.array.mem[7] <= value;
14306`endif
14307
14308`endif
14309
14310`endif
14311
14312 end
14313 endtask
14314
14315
14316 task slam_MraRow7_core0_thread5;
14317 input [127:0] value;
14318 reg [5:0] tid;
14319 integer junk;
14320
14321 begin
14322`ifdef AXIS_EMUL_COSIM
14323//Do Nothing
14324`else
14325`ifdef GATESIM
14326//Do Nothing
14327`else
14328`ifdef CORE_0
14329 value[82] = ^value[40:0];
14330 value[83] = ^value[81:41];
14331 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
14332 `SPC0.mmu.mra1.array.mem[15] <= value;
14333`endif
14334
14335`endif
14336
14337`endif
14338
14339 end
14340 endtask
14341
14342
14343 task slam_MraRow7_core0_thread6;
14344 input [127:0] value;
14345 reg [5:0] tid;
14346 integer junk;
14347
14348 begin
14349`ifdef AXIS_EMUL_COSIM
14350//Do Nothing
14351`else
14352`ifdef GATESIM
14353//Do Nothing
14354`else
14355`ifdef CORE_0
14356 value[82] = ^value[40:0];
14357 value[83] = ^value[81:41];
14358 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
14359 `SPC0.mmu.mra1.array.mem[23] <= value;
14360`endif
14361
14362`endif
14363
14364`endif
14365
14366 end
14367 endtask
14368
14369
14370 task slam_MraRow7_core0_thread7;
14371 input [127:0] value;
14372 reg [5:0] tid;
14373 integer junk;
14374
14375 begin
14376`ifdef AXIS_EMUL_COSIM
14377//Do Nothing
14378`else
14379`ifdef GATESIM
14380//Do Nothing
14381`else
14382`ifdef CORE_0
14383 value[82] = ^value[40:0];
14384 value[83] = ^value[81:41];
14385 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
14386 `SPC0.mmu.mra1.array.mem[31] <= value;
14387`endif
14388
14389`endif
14390
14391`endif
14392
14393 end
14394 endtask
14395
14396
14397 task slam_MraRow7_core1_thread0;
14398 input [127:0] value;
14399 reg [5:0] tid;
14400 integer junk;
14401
14402 begin
14403`ifdef AXIS_EMUL_COSIM
14404//Do Nothing
14405`else
14406`ifdef GATESIM
14407//Do Nothing
14408`else
14409`ifdef CORE_1
14410 value[82] = ^value[40:0];
14411 value[83] = ^value[81:41];
14412 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
14413 `SPC1.mmu.mra0.array.mem[7] <= value;
14414`endif
14415
14416`endif
14417
14418`endif
14419
14420 end
14421 endtask
14422
14423
14424 task slam_MraRow7_core1_thread1;
14425 input [127:0] value;
14426 reg [5:0] tid;
14427 integer junk;
14428
14429 begin
14430`ifdef AXIS_EMUL_COSIM
14431//Do Nothing
14432`else
14433`ifdef GATESIM
14434//Do Nothing
14435`else
14436`ifdef CORE_1
14437 value[82] = ^value[40:0];
14438 value[83] = ^value[81:41];
14439 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
14440 `SPC1.mmu.mra0.array.mem[15] <= value;
14441`endif
14442
14443`endif
14444
14445`endif
14446
14447 end
14448 endtask
14449
14450
14451 task slam_MraRow7_core1_thread2;
14452 input [127:0] value;
14453 reg [5:0] tid;
14454 integer junk;
14455
14456 begin
14457`ifdef AXIS_EMUL_COSIM
14458//Do Nothing
14459`else
14460`ifdef GATESIM
14461//Do Nothing
14462`else
14463`ifdef CORE_1
14464 value[82] = ^value[40:0];
14465 value[83] = ^value[81:41];
14466 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
14467 `SPC1.mmu.mra0.array.mem[23] <= value;
14468`endif
14469
14470`endif
14471
14472`endif
14473
14474 end
14475 endtask
14476
14477
14478 task slam_MraRow7_core1_thread3;
14479 input [127:0] value;
14480 reg [5:0] tid;
14481 integer junk;
14482
14483 begin
14484`ifdef AXIS_EMUL_COSIM
14485//Do Nothing
14486`else
14487`ifdef GATESIM
14488//Do Nothing
14489`else
14490`ifdef CORE_1
14491 value[82] = ^value[40:0];
14492 value[83] = ^value[81:41];
14493 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
14494 `SPC1.mmu.mra0.array.mem[31] <= value;
14495`endif
14496
14497`endif
14498
14499`endif
14500
14501 end
14502 endtask
14503
14504
14505 task slam_MraRow7_core1_thread4;
14506 input [127:0] value;
14507 reg [5:0] tid;
14508 integer junk;
14509
14510 begin
14511`ifdef AXIS_EMUL_COSIM
14512//Do Nothing
14513`else
14514`ifdef GATESIM
14515//Do Nothing
14516`else
14517`ifdef CORE_1
14518 value[82] = ^value[40:0];
14519 value[83] = ^value[81:41];
14520 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
14521 `SPC1.mmu.mra1.array.mem[7] <= value;
14522`endif
14523
14524`endif
14525
14526`endif
14527
14528 end
14529 endtask
14530
14531
14532 task slam_MraRow7_core1_thread5;
14533 input [127:0] value;
14534 reg [5:0] tid;
14535 integer junk;
14536
14537 begin
14538`ifdef AXIS_EMUL_COSIM
14539//Do Nothing
14540`else
14541`ifdef GATESIM
14542//Do Nothing
14543`else
14544`ifdef CORE_1
14545 value[82] = ^value[40:0];
14546 value[83] = ^value[81:41];
14547 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
14548 `SPC1.mmu.mra1.array.mem[15] <= value;
14549`endif
14550
14551`endif
14552
14553`endif
14554
14555 end
14556 endtask
14557
14558
14559 task slam_MraRow7_core1_thread6;
14560 input [127:0] value;
14561 reg [5:0] tid;
14562 integer junk;
14563
14564 begin
14565`ifdef AXIS_EMUL_COSIM
14566//Do Nothing
14567`else
14568`ifdef GATESIM
14569//Do Nothing
14570`else
14571`ifdef CORE_1
14572 value[82] = ^value[40:0];
14573 value[83] = ^value[81:41];
14574 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
14575 `SPC1.mmu.mra1.array.mem[23] <= value;
14576`endif
14577
14578`endif
14579
14580`endif
14581
14582 end
14583 endtask
14584
14585
14586 task slam_MraRow7_core1_thread7;
14587 input [127:0] value;
14588 reg [5:0] tid;
14589 integer junk;
14590
14591 begin
14592`ifdef AXIS_EMUL_COSIM
14593//Do Nothing
14594`else
14595`ifdef GATESIM
14596//Do Nothing
14597`else
14598`ifdef CORE_1
14599 value[82] = ^value[40:0];
14600 value[83] = ^value[81:41];
14601 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
14602 `SPC1.mmu.mra1.array.mem[31] <= value;
14603`endif
14604
14605`endif
14606
14607`endif
14608
14609 end
14610 endtask
14611
14612
14613 task slam_MraRow7_core2_thread0;
14614 input [127:0] value;
14615 reg [5:0] tid;
14616 integer junk;
14617
14618 begin
14619`ifdef AXIS_EMUL_COSIM
14620//Do Nothing
14621`else
14622`ifdef GATESIM
14623//Do Nothing
14624`else
14625`ifdef CORE_2
14626 value[82] = ^value[40:0];
14627 value[83] = ^value[81:41];
14628 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
14629 `SPC2.mmu.mra0.array.mem[7] <= value;
14630`endif
14631
14632`endif
14633
14634`endif
14635
14636 end
14637 endtask
14638
14639
14640 task slam_MraRow7_core2_thread1;
14641 input [127:0] value;
14642 reg [5:0] tid;
14643 integer junk;
14644
14645 begin
14646`ifdef AXIS_EMUL_COSIM
14647//Do Nothing
14648`else
14649`ifdef GATESIM
14650//Do Nothing
14651`else
14652`ifdef CORE_2
14653 value[82] = ^value[40:0];
14654 value[83] = ^value[81:41];
14655 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
14656 `SPC2.mmu.mra0.array.mem[15] <= value;
14657`endif
14658
14659`endif
14660
14661`endif
14662
14663 end
14664 endtask
14665
14666
14667 task slam_MraRow7_core2_thread2;
14668 input [127:0] value;
14669 reg [5:0] tid;
14670 integer junk;
14671
14672 begin
14673`ifdef AXIS_EMUL_COSIM
14674//Do Nothing
14675`else
14676`ifdef GATESIM
14677//Do Nothing
14678`else
14679`ifdef CORE_2
14680 value[82] = ^value[40:0];
14681 value[83] = ^value[81:41];
14682 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
14683 `SPC2.mmu.mra0.array.mem[23] <= value;
14684`endif
14685
14686`endif
14687
14688`endif
14689
14690 end
14691 endtask
14692
14693
14694 task slam_MraRow7_core2_thread3;
14695 input [127:0] value;
14696 reg [5:0] tid;
14697 integer junk;
14698
14699 begin
14700`ifdef AXIS_EMUL_COSIM
14701//Do Nothing
14702`else
14703`ifdef GATESIM
14704//Do Nothing
14705`else
14706`ifdef CORE_2
14707 value[82] = ^value[40:0];
14708 value[83] = ^value[81:41];
14709 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
14710 `SPC2.mmu.mra0.array.mem[31] <= value;
14711`endif
14712
14713`endif
14714
14715`endif
14716
14717 end
14718 endtask
14719
14720
14721 task slam_MraRow7_core2_thread4;
14722 input [127:0] value;
14723 reg [5:0] tid;
14724 integer junk;
14725
14726 begin
14727`ifdef AXIS_EMUL_COSIM
14728//Do Nothing
14729`else
14730`ifdef GATESIM
14731//Do Nothing
14732`else
14733`ifdef CORE_2
14734 value[82] = ^value[40:0];
14735 value[83] = ^value[81:41];
14736 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
14737 `SPC2.mmu.mra1.array.mem[7] <= value;
14738`endif
14739
14740`endif
14741
14742`endif
14743
14744 end
14745 endtask
14746
14747
14748 task slam_MraRow7_core2_thread5;
14749 input [127:0] value;
14750 reg [5:0] tid;
14751 integer junk;
14752
14753 begin
14754`ifdef AXIS_EMUL_COSIM
14755//Do Nothing
14756`else
14757`ifdef GATESIM
14758//Do Nothing
14759`else
14760`ifdef CORE_2
14761 value[82] = ^value[40:0];
14762 value[83] = ^value[81:41];
14763 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
14764 `SPC2.mmu.mra1.array.mem[15] <= value;
14765`endif
14766
14767`endif
14768
14769`endif
14770
14771 end
14772 endtask
14773
14774
14775 task slam_MraRow7_core2_thread6;
14776 input [127:0] value;
14777 reg [5:0] tid;
14778 integer junk;
14779
14780 begin
14781`ifdef AXIS_EMUL_COSIM
14782//Do Nothing
14783`else
14784`ifdef GATESIM
14785//Do Nothing
14786`else
14787`ifdef CORE_2
14788 value[82] = ^value[40:0];
14789 value[83] = ^value[81:41];
14790 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
14791 `SPC2.mmu.mra1.array.mem[23] <= value;
14792`endif
14793
14794`endif
14795
14796`endif
14797
14798 end
14799 endtask
14800
14801
14802 task slam_MraRow7_core2_thread7;
14803 input [127:0] value;
14804 reg [5:0] tid;
14805 integer junk;
14806
14807 begin
14808`ifdef AXIS_EMUL_COSIM
14809//Do Nothing
14810`else
14811`ifdef GATESIM
14812//Do Nothing
14813`else
14814`ifdef CORE_2
14815 value[82] = ^value[40:0];
14816 value[83] = ^value[81:41];
14817 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
14818 `SPC2.mmu.mra1.array.mem[31] <= value;
14819`endif
14820
14821`endif
14822
14823`endif
14824
14825 end
14826 endtask
14827
14828
14829 task slam_MraRow7_core3_thread0;
14830 input [127:0] value;
14831 reg [5:0] tid;
14832 integer junk;
14833
14834 begin
14835`ifdef AXIS_EMUL_COSIM
14836//Do Nothing
14837`else
14838`ifdef GATESIM
14839//Do Nothing
14840`else
14841`ifdef CORE_3
14842 value[82] = ^value[40:0];
14843 value[83] = ^value[81:41];
14844 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
14845 `SPC3.mmu.mra0.array.mem[7] <= value;
14846`endif
14847
14848`endif
14849
14850`endif
14851
14852 end
14853 endtask
14854
14855
14856 task slam_MraRow7_core3_thread1;
14857 input [127:0] value;
14858 reg [5:0] tid;
14859 integer junk;
14860
14861 begin
14862`ifdef AXIS_EMUL_COSIM
14863//Do Nothing
14864`else
14865`ifdef GATESIM
14866//Do Nothing
14867`else
14868`ifdef CORE_3
14869 value[82] = ^value[40:0];
14870 value[83] = ^value[81:41];
14871 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
14872 `SPC3.mmu.mra0.array.mem[15] <= value;
14873`endif
14874
14875`endif
14876
14877`endif
14878
14879 end
14880 endtask
14881
14882
14883 task slam_MraRow7_core3_thread2;
14884 input [127:0] value;
14885 reg [5:0] tid;
14886 integer junk;
14887
14888 begin
14889`ifdef AXIS_EMUL_COSIM
14890//Do Nothing
14891`else
14892`ifdef GATESIM
14893//Do Nothing
14894`else
14895`ifdef CORE_3
14896 value[82] = ^value[40:0];
14897 value[83] = ^value[81:41];
14898 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
14899 `SPC3.mmu.mra0.array.mem[23] <= value;
14900`endif
14901
14902`endif
14903
14904`endif
14905
14906 end
14907 endtask
14908
14909
14910 task slam_MraRow7_core3_thread3;
14911 input [127:0] value;
14912 reg [5:0] tid;
14913 integer junk;
14914
14915 begin
14916`ifdef AXIS_EMUL_COSIM
14917//Do Nothing
14918`else
14919`ifdef GATESIM
14920//Do Nothing
14921`else
14922`ifdef CORE_3
14923 value[82] = ^value[40:0];
14924 value[83] = ^value[81:41];
14925 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
14926 `SPC3.mmu.mra0.array.mem[31] <= value;
14927`endif
14928
14929`endif
14930
14931`endif
14932
14933 end
14934 endtask
14935
14936
14937 task slam_MraRow7_core3_thread4;
14938 input [127:0] value;
14939 reg [5:0] tid;
14940 integer junk;
14941
14942 begin
14943`ifdef AXIS_EMUL_COSIM
14944//Do Nothing
14945`else
14946`ifdef GATESIM
14947//Do Nothing
14948`else
14949`ifdef CORE_3
14950 value[82] = ^value[40:0];
14951 value[83] = ^value[81:41];
14952 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
14953 `SPC3.mmu.mra1.array.mem[7] <= value;
14954`endif
14955
14956`endif
14957
14958`endif
14959
14960 end
14961 endtask
14962
14963
14964 task slam_MraRow7_core3_thread5;
14965 input [127:0] value;
14966 reg [5:0] tid;
14967 integer junk;
14968
14969 begin
14970`ifdef AXIS_EMUL_COSIM
14971//Do Nothing
14972`else
14973`ifdef GATESIM
14974//Do Nothing
14975`else
14976`ifdef CORE_3
14977 value[82] = ^value[40:0];
14978 value[83] = ^value[81:41];
14979 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
14980 `SPC3.mmu.mra1.array.mem[15] <= value;
14981`endif
14982
14983`endif
14984
14985`endif
14986
14987 end
14988 endtask
14989
14990
14991 task slam_MraRow7_core3_thread6;
14992 input [127:0] value;
14993 reg [5:0] tid;
14994 integer junk;
14995
14996 begin
14997`ifdef AXIS_EMUL_COSIM
14998//Do Nothing
14999`else
15000`ifdef GATESIM
15001//Do Nothing
15002`else
15003`ifdef CORE_3
15004 value[82] = ^value[40:0];
15005 value[83] = ^value[81:41];
15006 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
15007 `SPC3.mmu.mra1.array.mem[23] <= value;
15008`endif
15009
15010`endif
15011
15012`endif
15013
15014 end
15015 endtask
15016
15017
15018 task slam_MraRow7_core3_thread7;
15019 input [127:0] value;
15020 reg [5:0] tid;
15021 integer junk;
15022
15023 begin
15024`ifdef AXIS_EMUL_COSIM
15025//Do Nothing
15026`else
15027`ifdef GATESIM
15028//Do Nothing
15029`else
15030`ifdef CORE_3
15031 value[82] = ^value[40:0];
15032 value[83] = ^value[81:41];
15033 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
15034 `SPC3.mmu.mra1.array.mem[31] <= value;
15035`endif
15036
15037`endif
15038
15039`endif
15040
15041 end
15042 endtask
15043
15044
15045 task slam_MraRow7_core4_thread0;
15046 input [127:0] value;
15047 reg [5:0] tid;
15048 integer junk;
15049
15050 begin
15051`ifdef AXIS_EMUL_COSIM
15052//Do Nothing
15053`else
15054`ifdef GATESIM
15055//Do Nothing
15056`else
15057`ifdef CORE_4
15058 value[82] = ^value[40:0];
15059 value[83] = ^value[81:41];
15060 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
15061 `SPC4.mmu.mra0.array.mem[7] <= value;
15062`endif
15063
15064`endif
15065
15066`endif
15067
15068 end
15069 endtask
15070
15071
15072 task slam_MraRow7_core4_thread1;
15073 input [127:0] value;
15074 reg [5:0] tid;
15075 integer junk;
15076
15077 begin
15078`ifdef AXIS_EMUL_COSIM
15079//Do Nothing
15080`else
15081`ifdef GATESIM
15082//Do Nothing
15083`else
15084`ifdef CORE_4
15085 value[82] = ^value[40:0];
15086 value[83] = ^value[81:41];
15087 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
15088 `SPC4.mmu.mra0.array.mem[15] <= value;
15089`endif
15090
15091`endif
15092
15093`endif
15094
15095 end
15096 endtask
15097
15098
15099 task slam_MraRow7_core4_thread2;
15100 input [127:0] value;
15101 reg [5:0] tid;
15102 integer junk;
15103
15104 begin
15105`ifdef AXIS_EMUL_COSIM
15106//Do Nothing
15107`else
15108`ifdef GATESIM
15109//Do Nothing
15110`else
15111`ifdef CORE_4
15112 value[82] = ^value[40:0];
15113 value[83] = ^value[81:41];
15114 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
15115 `SPC4.mmu.mra0.array.mem[23] <= value;
15116`endif
15117
15118`endif
15119
15120`endif
15121
15122 end
15123 endtask
15124
15125
15126 task slam_MraRow7_core4_thread3;
15127 input [127:0] value;
15128 reg [5:0] tid;
15129 integer junk;
15130
15131 begin
15132`ifdef AXIS_EMUL_COSIM
15133//Do Nothing
15134`else
15135`ifdef GATESIM
15136//Do Nothing
15137`else
15138`ifdef CORE_4
15139 value[82] = ^value[40:0];
15140 value[83] = ^value[81:41];
15141 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
15142 `SPC4.mmu.mra0.array.mem[31] <= value;
15143`endif
15144
15145`endif
15146
15147`endif
15148
15149 end
15150 endtask
15151
15152
15153 task slam_MraRow7_core4_thread4;
15154 input [127:0] value;
15155 reg [5:0] tid;
15156 integer junk;
15157
15158 begin
15159`ifdef AXIS_EMUL_COSIM
15160//Do Nothing
15161`else
15162`ifdef GATESIM
15163//Do Nothing
15164`else
15165`ifdef CORE_4
15166 value[82] = ^value[40:0];
15167 value[83] = ^value[81:41];
15168 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
15169 `SPC4.mmu.mra1.array.mem[7] <= value;
15170`endif
15171
15172`endif
15173
15174`endif
15175
15176 end
15177 endtask
15178
15179
15180 task slam_MraRow7_core4_thread5;
15181 input [127:0] value;
15182 reg [5:0] tid;
15183 integer junk;
15184
15185 begin
15186`ifdef AXIS_EMUL_COSIM
15187//Do Nothing
15188`else
15189`ifdef GATESIM
15190//Do Nothing
15191`else
15192`ifdef CORE_4
15193 value[82] = ^value[40:0];
15194 value[83] = ^value[81:41];
15195 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
15196 `SPC4.mmu.mra1.array.mem[15] <= value;
15197`endif
15198
15199`endif
15200
15201`endif
15202
15203 end
15204 endtask
15205
15206
15207 task slam_MraRow7_core4_thread6;
15208 input [127:0] value;
15209 reg [5:0] tid;
15210 integer junk;
15211
15212 begin
15213`ifdef AXIS_EMUL_COSIM
15214//Do Nothing
15215`else
15216`ifdef GATESIM
15217//Do Nothing
15218`else
15219`ifdef CORE_4
15220 value[82] = ^value[40:0];
15221 value[83] = ^value[81:41];
15222 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
15223 `SPC4.mmu.mra1.array.mem[23] <= value;
15224`endif
15225
15226`endif
15227
15228`endif
15229
15230 end
15231 endtask
15232
15233
15234 task slam_MraRow7_core4_thread7;
15235 input [127:0] value;
15236 reg [5:0] tid;
15237 integer junk;
15238
15239 begin
15240`ifdef AXIS_EMUL_COSIM
15241//Do Nothing
15242`else
15243`ifdef GATESIM
15244//Do Nothing
15245`else
15246`ifdef CORE_4
15247 value[82] = ^value[40:0];
15248 value[83] = ^value[81:41];
15249 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
15250 `SPC4.mmu.mra1.array.mem[31] <= value;
15251`endif
15252
15253`endif
15254
15255`endif
15256
15257 end
15258 endtask
15259
15260
15261 task slam_MraRow7_core5_thread0;
15262 input [127:0] value;
15263 reg [5:0] tid;
15264 integer junk;
15265
15266 begin
15267`ifdef AXIS_EMUL_COSIM
15268//Do Nothing
15269`else
15270`ifdef GATESIM
15271//Do Nothing
15272`else
15273`ifdef CORE_5
15274 value[82] = ^value[40:0];
15275 value[83] = ^value[81:41];
15276 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
15277 `SPC5.mmu.mra0.array.mem[7] <= value;
15278`endif
15279
15280`endif
15281
15282`endif
15283
15284 end
15285 endtask
15286
15287
15288 task slam_MraRow7_core5_thread1;
15289 input [127:0] value;
15290 reg [5:0] tid;
15291 integer junk;
15292
15293 begin
15294`ifdef AXIS_EMUL_COSIM
15295//Do Nothing
15296`else
15297`ifdef GATESIM
15298//Do Nothing
15299`else
15300`ifdef CORE_5
15301 value[82] = ^value[40:0];
15302 value[83] = ^value[81:41];
15303 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
15304 `SPC5.mmu.mra0.array.mem[15] <= value;
15305`endif
15306
15307`endif
15308
15309`endif
15310
15311 end
15312 endtask
15313
15314
15315 task slam_MraRow7_core5_thread2;
15316 input [127:0] value;
15317 reg [5:0] tid;
15318 integer junk;
15319
15320 begin
15321`ifdef AXIS_EMUL_COSIM
15322//Do Nothing
15323`else
15324`ifdef GATESIM
15325//Do Nothing
15326`else
15327`ifdef CORE_5
15328 value[82] = ^value[40:0];
15329 value[83] = ^value[81:41];
15330 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
15331 `SPC5.mmu.mra0.array.mem[23] <= value;
15332`endif
15333
15334`endif
15335
15336`endif
15337
15338 end
15339 endtask
15340
15341
15342 task slam_MraRow7_core5_thread3;
15343 input [127:0] value;
15344 reg [5:0] tid;
15345 integer junk;
15346
15347 begin
15348`ifdef AXIS_EMUL_COSIM
15349//Do Nothing
15350`else
15351`ifdef GATESIM
15352//Do Nothing
15353`else
15354`ifdef CORE_5
15355 value[82] = ^value[40:0];
15356 value[83] = ^value[81:41];
15357 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
15358 `SPC5.mmu.mra0.array.mem[31] <= value;
15359`endif
15360
15361`endif
15362
15363`endif
15364
15365 end
15366 endtask
15367
15368
15369 task slam_MraRow7_core5_thread4;
15370 input [127:0] value;
15371 reg [5:0] tid;
15372 integer junk;
15373
15374 begin
15375`ifdef AXIS_EMUL_COSIM
15376//Do Nothing
15377`else
15378`ifdef GATESIM
15379//Do Nothing
15380`else
15381`ifdef CORE_5
15382 value[82] = ^value[40:0];
15383 value[83] = ^value[81:41];
15384 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
15385 `SPC5.mmu.mra1.array.mem[7] <= value;
15386`endif
15387
15388`endif
15389
15390`endif
15391
15392 end
15393 endtask
15394
15395
15396 task slam_MraRow7_core5_thread5;
15397 input [127:0] value;
15398 reg [5:0] tid;
15399 integer junk;
15400
15401 begin
15402`ifdef AXIS_EMUL_COSIM
15403//Do Nothing
15404`else
15405`ifdef GATESIM
15406//Do Nothing
15407`else
15408`ifdef CORE_5
15409 value[82] = ^value[40:0];
15410 value[83] = ^value[81:41];
15411 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
15412 `SPC5.mmu.mra1.array.mem[15] <= value;
15413`endif
15414
15415`endif
15416
15417`endif
15418
15419 end
15420 endtask
15421
15422
15423 task slam_MraRow7_core5_thread6;
15424 input [127:0] value;
15425 reg [5:0] tid;
15426 integer junk;
15427
15428 begin
15429`ifdef AXIS_EMUL_COSIM
15430//Do Nothing
15431`else
15432`ifdef GATESIM
15433//Do Nothing
15434`else
15435`ifdef CORE_5
15436 value[82] = ^value[40:0];
15437 value[83] = ^value[81:41];
15438 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
15439 `SPC5.mmu.mra1.array.mem[23] <= value;
15440`endif
15441
15442`endif
15443
15444`endif
15445
15446 end
15447 endtask
15448
15449
15450 task slam_MraRow7_core5_thread7;
15451 input [127:0] value;
15452 reg [5:0] tid;
15453 integer junk;
15454
15455 begin
15456`ifdef AXIS_EMUL_COSIM
15457//Do Nothing
15458`else
15459`ifdef GATESIM
15460//Do Nothing
15461`else
15462`ifdef CORE_5
15463 value[82] = ^value[40:0];
15464 value[83] = ^value[81:41];
15465 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
15466 `SPC5.mmu.mra1.array.mem[31] <= value;
15467`endif
15468
15469`endif
15470
15471`endif
15472
15473 end
15474 endtask
15475
15476
15477 task slam_MraRow7_core6_thread0;
15478 input [127:0] value;
15479 reg [5:0] tid;
15480 integer junk;
15481
15482 begin
15483`ifdef AXIS_EMUL_COSIM
15484//Do Nothing
15485`else
15486`ifdef GATESIM
15487//Do Nothing
15488`else
15489`ifdef CORE_6
15490 value[82] = ^value[40:0];
15491 value[83] = ^value[81:41];
15492 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
15493 `SPC6.mmu.mra0.array.mem[7] <= value;
15494`endif
15495
15496`endif
15497
15498`endif
15499
15500 end
15501 endtask
15502
15503
15504 task slam_MraRow7_core6_thread1;
15505 input [127:0] value;
15506 reg [5:0] tid;
15507 integer junk;
15508
15509 begin
15510`ifdef AXIS_EMUL_COSIM
15511//Do Nothing
15512`else
15513`ifdef GATESIM
15514//Do Nothing
15515`else
15516`ifdef CORE_6
15517 value[82] = ^value[40:0];
15518 value[83] = ^value[81:41];
15519 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
15520 `SPC6.mmu.mra0.array.mem[15] <= value;
15521`endif
15522
15523`endif
15524
15525`endif
15526
15527 end
15528 endtask
15529
15530
15531 task slam_MraRow7_core6_thread2;
15532 input [127:0] value;
15533 reg [5:0] tid;
15534 integer junk;
15535
15536 begin
15537`ifdef AXIS_EMUL_COSIM
15538//Do Nothing
15539`else
15540`ifdef GATESIM
15541//Do Nothing
15542`else
15543`ifdef CORE_6
15544 value[82] = ^value[40:0];
15545 value[83] = ^value[81:41];
15546 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
15547 `SPC6.mmu.mra0.array.mem[23] <= value;
15548`endif
15549
15550`endif
15551
15552`endif
15553
15554 end
15555 endtask
15556
15557
15558 task slam_MraRow7_core6_thread3;
15559 input [127:0] value;
15560 reg [5:0] tid;
15561 integer junk;
15562
15563 begin
15564`ifdef AXIS_EMUL_COSIM
15565//Do Nothing
15566`else
15567`ifdef GATESIM
15568//Do Nothing
15569`else
15570`ifdef CORE_6
15571 value[82] = ^value[40:0];
15572 value[83] = ^value[81:41];
15573 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
15574 `SPC6.mmu.mra0.array.mem[31] <= value;
15575`endif
15576
15577`endif
15578
15579`endif
15580
15581 end
15582 endtask
15583
15584
15585 task slam_MraRow7_core6_thread4;
15586 input [127:0] value;
15587 reg [5:0] tid;
15588 integer junk;
15589
15590 begin
15591`ifdef AXIS_EMUL_COSIM
15592//Do Nothing
15593`else
15594`ifdef GATESIM
15595//Do Nothing
15596`else
15597`ifdef CORE_6
15598 value[82] = ^value[40:0];
15599 value[83] = ^value[81:41];
15600 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
15601 `SPC6.mmu.mra1.array.mem[7] <= value;
15602`endif
15603
15604`endif
15605
15606`endif
15607
15608 end
15609 endtask
15610
15611
15612 task slam_MraRow7_core6_thread5;
15613 input [127:0] value;
15614 reg [5:0] tid;
15615 integer junk;
15616
15617 begin
15618`ifdef AXIS_EMUL_COSIM
15619//Do Nothing
15620`else
15621`ifdef GATESIM
15622//Do Nothing
15623`else
15624`ifdef CORE_6
15625 value[82] = ^value[40:0];
15626 value[83] = ^value[81:41];
15627 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
15628 `SPC6.mmu.mra1.array.mem[15] <= value;
15629`endif
15630
15631`endif
15632
15633`endif
15634
15635 end
15636 endtask
15637
15638
15639 task slam_MraRow7_core6_thread6;
15640 input [127:0] value;
15641 reg [5:0] tid;
15642 integer junk;
15643
15644 begin
15645`ifdef AXIS_EMUL_COSIM
15646//Do Nothing
15647`else
15648`ifdef GATESIM
15649//Do Nothing
15650`else
15651`ifdef CORE_6
15652 value[82] = ^value[40:0];
15653 value[83] = ^value[81:41];
15654 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
15655 `SPC6.mmu.mra1.array.mem[23] <= value;
15656`endif
15657
15658`endif
15659
15660`endif
15661
15662 end
15663 endtask
15664
15665
15666 task slam_MraRow7_core6_thread7;
15667 input [127:0] value;
15668 reg [5:0] tid;
15669 integer junk;
15670
15671 begin
15672`ifdef AXIS_EMUL_COSIM
15673//Do Nothing
15674`else
15675`ifdef GATESIM
15676//Do Nothing
15677`else
15678`ifdef CORE_6
15679 value[82] = ^value[40:0];
15680 value[83] = ^value[81:41];
15681 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
15682 `SPC6.mmu.mra1.array.mem[31] <= value;
15683`endif
15684
15685`endif
15686
15687`endif
15688
15689 end
15690 endtask
15691
15692
15693 task slam_MraRow7_core7_thread0;
15694 input [127:0] value;
15695 reg [5:0] tid;
15696 integer junk;
15697
15698 begin
15699`ifdef AXIS_EMUL_COSIM
15700//Do Nothing
15701`else
15702`ifdef GATESIM
15703//Do Nothing
15704`else
15705`ifdef CORE_7
15706 value[82] = ^value[40:0];
15707 value[83] = ^value[81:41];
15708 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[7]" );
15709 `SPC7.mmu.mra0.array.mem[7] <= value;
15710`endif
15711
15712`endif
15713
15714`endif
15715
15716 end
15717 endtask
15718
15719
15720 task slam_MraRow7_core7_thread1;
15721 input [127:0] value;
15722 reg [5:0] tid;
15723 integer junk;
15724
15725 begin
15726`ifdef AXIS_EMUL_COSIM
15727//Do Nothing
15728`else
15729`ifdef GATESIM
15730//Do Nothing
15731`else
15732`ifdef CORE_7
15733 value[82] = ^value[40:0];
15734 value[83] = ^value[81:41];
15735 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[15]" );
15736 `SPC7.mmu.mra0.array.mem[15] <= value;
15737`endif
15738
15739`endif
15740
15741`endif
15742
15743 end
15744 endtask
15745
15746
15747 task slam_MraRow7_core7_thread2;
15748 input [127:0] value;
15749 reg [5:0] tid;
15750 integer junk;
15751
15752 begin
15753`ifdef AXIS_EMUL_COSIM
15754//Do Nothing
15755`else
15756`ifdef GATESIM
15757//Do Nothing
15758`else
15759`ifdef CORE_7
15760 value[82] = ^value[40:0];
15761 value[83] = ^value[81:41];
15762 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[23]" );
15763 `SPC7.mmu.mra0.array.mem[23] <= value;
15764`endif
15765
15766`endif
15767
15768`endif
15769
15770 end
15771 endtask
15772
15773
15774 task slam_MraRow7_core7_thread3;
15775 input [127:0] value;
15776 reg [5:0] tid;
15777 integer junk;
15778
15779 begin
15780`ifdef AXIS_EMUL_COSIM
15781//Do Nothing
15782`else
15783`ifdef GATESIM
15784//Do Nothing
15785`else
15786`ifdef CORE_7
15787 value[82] = ^value[40:0];
15788 value[83] = ^value[81:41];
15789 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra0.array.mem[31]" );
15790 `SPC7.mmu.mra0.array.mem[31] <= value;
15791`endif
15792
15793`endif
15794
15795`endif
15796
15797 end
15798 endtask
15799
15800
15801 task slam_MraRow7_core7_thread4;
15802 input [127:0] value;
15803 reg [5:0] tid;
15804 integer junk;
15805
15806 begin
15807`ifdef AXIS_EMUL_COSIM
15808//Do Nothing
15809`else
15810`ifdef GATESIM
15811//Do Nothing
15812`else
15813`ifdef CORE_7
15814 value[82] = ^value[40:0];
15815 value[83] = ^value[81:41];
15816 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[7]" );
15817 `SPC7.mmu.mra1.array.mem[7] <= value;
15818`endif
15819
15820`endif
15821
15822`endif
15823
15824 end
15825 endtask
15826
15827
15828 task slam_MraRow7_core7_thread5;
15829 input [127:0] value;
15830 reg [5:0] tid;
15831 integer junk;
15832
15833 begin
15834`ifdef AXIS_EMUL_COSIM
15835//Do Nothing
15836`else
15837`ifdef GATESIM
15838//Do Nothing
15839`else
15840`ifdef CORE_7
15841 value[82] = ^value[40:0];
15842 value[83] = ^value[81:41];
15843 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[15]" );
15844 `SPC7.mmu.mra1.array.mem[15] <= value;
15845`endif
15846
15847`endif
15848
15849`endif
15850
15851 end
15852 endtask
15853
15854
15855 task slam_MraRow7_core7_thread6;
15856 input [127:0] value;
15857 reg [5:0] tid;
15858 integer junk;
15859
15860 begin
15861`ifdef AXIS_EMUL_COSIM
15862//Do Nothing
15863`else
15864`ifdef GATESIM
15865//Do Nothing
15866`else
15867`ifdef CORE_7
15868 value[82] = ^value[40:0];
15869 value[83] = ^value[81:41];
15870 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[23]" );
15871 `SPC7.mmu.mra1.array.mem[23] <= value;
15872`endif
15873
15874`endif
15875
15876`endif
15877
15878 end
15879 endtask
15880
15881
15882 task slam_MraRow7_core7_thread7;
15883 input [127:0] value;
15884 reg [5:0] tid;
15885 integer junk;
15886
15887 begin
15888`ifdef AXIS_EMUL_COSIM
15889//Do Nothing
15890`else
15891`ifdef GATESIM
15892//Do Nothing
15893`else
15894`ifdef CORE_7
15895 value[82] = ^value[40:0];
15896 value[83] = ^value[81:41];
15897 $display("Writing a value of %0h to MRA %s\n", value," mmu.mra1.array.mem[31]" );
15898 `SPC7.mmu.mra1.array.mem[31] <= value;
15899`endif
15900
15901`endif
15902
15903`endif
15904
15905 end
15906 endtask
15907
15908
15909 task slam_ZeroTsbConfig0_core0_thread0;
15910 input [63:0] value;
15911 reg [5:0] tid;
15912 integer junk;
15913
15914 begin
15915`ifdef AXIS_EMUL_COSIM
15916//Do Nothing
15917`else
15918`ifdef GATESIM
15919//Do Nothing
15920`else
15921`ifdef CORE_0
15922 if (`PARGS.nas_check_on) begin
15923 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
15924 tid = 0
15925; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
15926 end
15927`endif
15928
15929`endif
15930
15931`endif
15932
15933 end
15934 endtask
15935
15936
15937 task slam_ZeroTsbConfig0_core0_thread1;
15938 input [63:0] value;
15939 reg [5:0] tid;
15940 integer junk;
15941
15942 begin
15943`ifdef AXIS_EMUL_COSIM
15944//Do Nothing
15945`else
15946`ifdef GATESIM
15947//Do Nothing
15948`else
15949`ifdef CORE_0
15950 if (`PARGS.nas_check_on) begin
15951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
15952 tid = 1
15953; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
15954 end
15955`endif
15956
15957`endif
15958
15959`endif
15960
15961 end
15962 endtask
15963
15964
15965 task slam_ZeroTsbConfig0_core0_thread2;
15966 input [63:0] value;
15967 reg [5:0] tid;
15968 integer junk;
15969
15970 begin
15971`ifdef AXIS_EMUL_COSIM
15972//Do Nothing
15973`else
15974`ifdef GATESIM
15975//Do Nothing
15976`else
15977`ifdef CORE_0
15978 if (`PARGS.nas_check_on) begin
15979 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
15980 tid = 2
15981; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
15982 end
15983`endif
15984
15985`endif
15986
15987`endif
15988
15989 end
15990 endtask
15991
15992
15993 task slam_ZeroTsbConfig0_core0_thread3;
15994 input [63:0] value;
15995 reg [5:0] tid;
15996 integer junk;
15997
15998 begin
15999`ifdef AXIS_EMUL_COSIM
16000//Do Nothing
16001`else
16002`ifdef GATESIM
16003//Do Nothing
16004`else
16005`ifdef CORE_0
16006 if (`PARGS.nas_check_on) begin
16007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
16008 tid = 3
16009; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16010 end
16011`endif
16012
16013`endif
16014
16015`endif
16016
16017 end
16018 endtask
16019
16020
16021 task slam_ZeroTsbConfig0_core0_thread4;
16022 input [63:0] value;
16023 reg [5:0] tid;
16024 integer junk;
16025
16026 begin
16027`ifdef AXIS_EMUL_COSIM
16028//Do Nothing
16029`else
16030`ifdef GATESIM
16031//Do Nothing
16032`else
16033`ifdef CORE_0
16034 if (`PARGS.nas_check_on) begin
16035 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
16036 tid = 4
16037; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16038 end
16039`endif
16040
16041`endif
16042
16043`endif
16044
16045 end
16046 endtask
16047
16048
16049 task slam_ZeroTsbConfig0_core0_thread5;
16050 input [63:0] value;
16051 reg [5:0] tid;
16052 integer junk;
16053
16054 begin
16055`ifdef AXIS_EMUL_COSIM
16056//Do Nothing
16057`else
16058`ifdef GATESIM
16059//Do Nothing
16060`else
16061`ifdef CORE_0
16062 if (`PARGS.nas_check_on) begin
16063 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
16064 tid = 5
16065; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16066 end
16067`endif
16068
16069`endif
16070
16071`endif
16072
16073 end
16074 endtask
16075
16076
16077 task slam_ZeroTsbConfig0_core0_thread6;
16078 input [63:0] value;
16079 reg [5:0] tid;
16080 integer junk;
16081
16082 begin
16083`ifdef AXIS_EMUL_COSIM
16084//Do Nothing
16085`else
16086`ifdef GATESIM
16087//Do Nothing
16088`else
16089`ifdef CORE_0
16090 if (`PARGS.nas_check_on) begin
16091 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
16092 tid = 6
16093; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16094 end
16095`endif
16096
16097`endif
16098
16099`endif
16100
16101 end
16102 endtask
16103
16104
16105 task slam_ZeroTsbConfig0_core0_thread7;
16106 input [63:0] value;
16107 reg [5:0] tid;
16108 integer junk;
16109
16110 begin
16111`ifdef AXIS_EMUL_COSIM
16112//Do Nothing
16113`else
16114`ifdef GATESIM
16115//Do Nothing
16116`else
16117`ifdef CORE_0
16118 if (`PARGS.nas_check_on) begin
16119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
16120 tid = 7
16121; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16122 end
16123`endif
16124
16125`endif
16126
16127`endif
16128
16129 end
16130 endtask
16131
16132
16133 task slam_ZeroTsbConfig0_core1_thread0;
16134 input [63:0] value;
16135 reg [5:0] tid;
16136 integer junk;
16137
16138 begin
16139`ifdef AXIS_EMUL_COSIM
16140//Do Nothing
16141`else
16142`ifdef GATESIM
16143//Do Nothing
16144`else
16145`ifdef CORE_1
16146 if (`PARGS.nas_check_on) begin
16147 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
16148 tid = 0
16149; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16150 end
16151`endif
16152
16153`endif
16154
16155`endif
16156
16157 end
16158 endtask
16159
16160
16161 task slam_ZeroTsbConfig0_core1_thread1;
16162 input [63:0] value;
16163 reg [5:0] tid;
16164 integer junk;
16165
16166 begin
16167`ifdef AXIS_EMUL_COSIM
16168//Do Nothing
16169`else
16170`ifdef GATESIM
16171//Do Nothing
16172`else
16173`ifdef CORE_1
16174 if (`PARGS.nas_check_on) begin
16175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
16176 tid = 1
16177; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16178 end
16179`endif
16180
16181`endif
16182
16183`endif
16184
16185 end
16186 endtask
16187
16188
16189 task slam_ZeroTsbConfig0_core1_thread2;
16190 input [63:0] value;
16191 reg [5:0] tid;
16192 integer junk;
16193
16194 begin
16195`ifdef AXIS_EMUL_COSIM
16196//Do Nothing
16197`else
16198`ifdef GATESIM
16199//Do Nothing
16200`else
16201`ifdef CORE_1
16202 if (`PARGS.nas_check_on) begin
16203 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
16204 tid = 2
16205; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16206 end
16207`endif
16208
16209`endif
16210
16211`endif
16212
16213 end
16214 endtask
16215
16216
16217 task slam_ZeroTsbConfig0_core1_thread3;
16218 input [63:0] value;
16219 reg [5:0] tid;
16220 integer junk;
16221
16222 begin
16223`ifdef AXIS_EMUL_COSIM
16224//Do Nothing
16225`else
16226`ifdef GATESIM
16227//Do Nothing
16228`else
16229`ifdef CORE_1
16230 if (`PARGS.nas_check_on) begin
16231 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
16232 tid = 3
16233; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16234 end
16235`endif
16236
16237`endif
16238
16239`endif
16240
16241 end
16242 endtask
16243
16244
16245 task slam_ZeroTsbConfig0_core1_thread4;
16246 input [63:0] value;
16247 reg [5:0] tid;
16248 integer junk;
16249
16250 begin
16251`ifdef AXIS_EMUL_COSIM
16252//Do Nothing
16253`else
16254`ifdef GATESIM
16255//Do Nothing
16256`else
16257`ifdef CORE_1
16258 if (`PARGS.nas_check_on) begin
16259 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
16260 tid = 4
16261; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16262 end
16263`endif
16264
16265`endif
16266
16267`endif
16268
16269 end
16270 endtask
16271
16272
16273 task slam_ZeroTsbConfig0_core1_thread5;
16274 input [63:0] value;
16275 reg [5:0] tid;
16276 integer junk;
16277
16278 begin
16279`ifdef AXIS_EMUL_COSIM
16280//Do Nothing
16281`else
16282`ifdef GATESIM
16283//Do Nothing
16284`else
16285`ifdef CORE_1
16286 if (`PARGS.nas_check_on) begin
16287 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
16288 tid = 5
16289; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16290 end
16291`endif
16292
16293`endif
16294
16295`endif
16296
16297 end
16298 endtask
16299
16300
16301 task slam_ZeroTsbConfig0_core1_thread6;
16302 input [63:0] value;
16303 reg [5:0] tid;
16304 integer junk;
16305
16306 begin
16307`ifdef AXIS_EMUL_COSIM
16308//Do Nothing
16309`else
16310`ifdef GATESIM
16311//Do Nothing
16312`else
16313`ifdef CORE_1
16314 if (`PARGS.nas_check_on) begin
16315 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
16316 tid = 6
16317; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16318 end
16319`endif
16320
16321`endif
16322
16323`endif
16324
16325 end
16326 endtask
16327
16328
16329 task slam_ZeroTsbConfig0_core1_thread7;
16330 input [63:0] value;
16331 reg [5:0] tid;
16332 integer junk;
16333
16334 begin
16335`ifdef AXIS_EMUL_COSIM
16336//Do Nothing
16337`else
16338`ifdef GATESIM
16339//Do Nothing
16340`else
16341`ifdef CORE_1
16342 if (`PARGS.nas_check_on) begin
16343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
16344 tid = 7
16345; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16346 end
16347`endif
16348
16349`endif
16350
16351`endif
16352
16353 end
16354 endtask
16355
16356
16357 task slam_ZeroTsbConfig0_core2_thread0;
16358 input [63:0] value;
16359 reg [5:0] tid;
16360 integer junk;
16361
16362 begin
16363`ifdef AXIS_EMUL_COSIM
16364//Do Nothing
16365`else
16366`ifdef GATESIM
16367//Do Nothing
16368`else
16369`ifdef CORE_2
16370 if (`PARGS.nas_check_on) begin
16371 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
16372 tid = 0
16373; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16374 end
16375`endif
16376
16377`endif
16378
16379`endif
16380
16381 end
16382 endtask
16383
16384
16385 task slam_ZeroTsbConfig0_core2_thread1;
16386 input [63:0] value;
16387 reg [5:0] tid;
16388 integer junk;
16389
16390 begin
16391`ifdef AXIS_EMUL_COSIM
16392//Do Nothing
16393`else
16394`ifdef GATESIM
16395//Do Nothing
16396`else
16397`ifdef CORE_2
16398 if (`PARGS.nas_check_on) begin
16399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
16400 tid = 1
16401; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16402 end
16403`endif
16404
16405`endif
16406
16407`endif
16408
16409 end
16410 endtask
16411
16412
16413 task slam_ZeroTsbConfig0_core2_thread2;
16414 input [63:0] value;
16415 reg [5:0] tid;
16416 integer junk;
16417
16418 begin
16419`ifdef AXIS_EMUL_COSIM
16420//Do Nothing
16421`else
16422`ifdef GATESIM
16423//Do Nothing
16424`else
16425`ifdef CORE_2
16426 if (`PARGS.nas_check_on) begin
16427 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
16428 tid = 2
16429; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16430 end
16431`endif
16432
16433`endif
16434
16435`endif
16436
16437 end
16438 endtask
16439
16440
16441 task slam_ZeroTsbConfig0_core2_thread3;
16442 input [63:0] value;
16443 reg [5:0] tid;
16444 integer junk;
16445
16446 begin
16447`ifdef AXIS_EMUL_COSIM
16448//Do Nothing
16449`else
16450`ifdef GATESIM
16451//Do Nothing
16452`else
16453`ifdef CORE_2
16454 if (`PARGS.nas_check_on) begin
16455 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
16456 tid = 3
16457; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16458 end
16459`endif
16460
16461`endif
16462
16463`endif
16464
16465 end
16466 endtask
16467
16468
16469 task slam_ZeroTsbConfig0_core2_thread4;
16470 input [63:0] value;
16471 reg [5:0] tid;
16472 integer junk;
16473
16474 begin
16475`ifdef AXIS_EMUL_COSIM
16476//Do Nothing
16477`else
16478`ifdef GATESIM
16479//Do Nothing
16480`else
16481`ifdef CORE_2
16482 if (`PARGS.nas_check_on) begin
16483 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
16484 tid = 4
16485; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16486 end
16487`endif
16488
16489`endif
16490
16491`endif
16492
16493 end
16494 endtask
16495
16496
16497 task slam_ZeroTsbConfig0_core2_thread5;
16498 input [63:0] value;
16499 reg [5:0] tid;
16500 integer junk;
16501
16502 begin
16503`ifdef AXIS_EMUL_COSIM
16504//Do Nothing
16505`else
16506`ifdef GATESIM
16507//Do Nothing
16508`else
16509`ifdef CORE_2
16510 if (`PARGS.nas_check_on) begin
16511 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
16512 tid = 5
16513; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16514 end
16515`endif
16516
16517`endif
16518
16519`endif
16520
16521 end
16522 endtask
16523
16524
16525 task slam_ZeroTsbConfig0_core2_thread6;
16526 input [63:0] value;
16527 reg [5:0] tid;
16528 integer junk;
16529
16530 begin
16531`ifdef AXIS_EMUL_COSIM
16532//Do Nothing
16533`else
16534`ifdef GATESIM
16535//Do Nothing
16536`else
16537`ifdef CORE_2
16538 if (`PARGS.nas_check_on) begin
16539 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
16540 tid = 6
16541; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16542 end
16543`endif
16544
16545`endif
16546
16547`endif
16548
16549 end
16550 endtask
16551
16552
16553 task slam_ZeroTsbConfig0_core2_thread7;
16554 input [63:0] value;
16555 reg [5:0] tid;
16556 integer junk;
16557
16558 begin
16559`ifdef AXIS_EMUL_COSIM
16560//Do Nothing
16561`else
16562`ifdef GATESIM
16563//Do Nothing
16564`else
16565`ifdef CORE_2
16566 if (`PARGS.nas_check_on) begin
16567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
16568 tid = 7
16569; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16570 end
16571`endif
16572
16573`endif
16574
16575`endif
16576
16577 end
16578 endtask
16579
16580
16581 task slam_ZeroTsbConfig0_core3_thread0;
16582 input [63:0] value;
16583 reg [5:0] tid;
16584 integer junk;
16585
16586 begin
16587`ifdef AXIS_EMUL_COSIM
16588//Do Nothing
16589`else
16590`ifdef GATESIM
16591//Do Nothing
16592`else
16593`ifdef CORE_3
16594 if (`PARGS.nas_check_on) begin
16595 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
16596 tid = 0
16597; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16598 end
16599`endif
16600
16601`endif
16602
16603`endif
16604
16605 end
16606 endtask
16607
16608
16609 task slam_ZeroTsbConfig0_core3_thread1;
16610 input [63:0] value;
16611 reg [5:0] tid;
16612 integer junk;
16613
16614 begin
16615`ifdef AXIS_EMUL_COSIM
16616//Do Nothing
16617`else
16618`ifdef GATESIM
16619//Do Nothing
16620`else
16621`ifdef CORE_3
16622 if (`PARGS.nas_check_on) begin
16623 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
16624 tid = 1
16625; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16626 end
16627`endif
16628
16629`endif
16630
16631`endif
16632
16633 end
16634 endtask
16635
16636
16637 task slam_ZeroTsbConfig0_core3_thread2;
16638 input [63:0] value;
16639 reg [5:0] tid;
16640 integer junk;
16641
16642 begin
16643`ifdef AXIS_EMUL_COSIM
16644//Do Nothing
16645`else
16646`ifdef GATESIM
16647//Do Nothing
16648`else
16649`ifdef CORE_3
16650 if (`PARGS.nas_check_on) begin
16651 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
16652 tid = 2
16653; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16654 end
16655`endif
16656
16657`endif
16658
16659`endif
16660
16661 end
16662 endtask
16663
16664
16665 task slam_ZeroTsbConfig0_core3_thread3;
16666 input [63:0] value;
16667 reg [5:0] tid;
16668 integer junk;
16669
16670 begin
16671`ifdef AXIS_EMUL_COSIM
16672//Do Nothing
16673`else
16674`ifdef GATESIM
16675//Do Nothing
16676`else
16677`ifdef CORE_3
16678 if (`PARGS.nas_check_on) begin
16679 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
16680 tid = 3
16681; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16682 end
16683`endif
16684
16685`endif
16686
16687`endif
16688
16689 end
16690 endtask
16691
16692
16693 task slam_ZeroTsbConfig0_core3_thread4;
16694 input [63:0] value;
16695 reg [5:0] tid;
16696 integer junk;
16697
16698 begin
16699`ifdef AXIS_EMUL_COSIM
16700//Do Nothing
16701`else
16702`ifdef GATESIM
16703//Do Nothing
16704`else
16705`ifdef CORE_3
16706 if (`PARGS.nas_check_on) begin
16707 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
16708 tid = 4
16709; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16710 end
16711`endif
16712
16713`endif
16714
16715`endif
16716
16717 end
16718 endtask
16719
16720
16721 task slam_ZeroTsbConfig0_core3_thread5;
16722 input [63:0] value;
16723 reg [5:0] tid;
16724 integer junk;
16725
16726 begin
16727`ifdef AXIS_EMUL_COSIM
16728//Do Nothing
16729`else
16730`ifdef GATESIM
16731//Do Nothing
16732`else
16733`ifdef CORE_3
16734 if (`PARGS.nas_check_on) begin
16735 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
16736 tid = 5
16737; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16738 end
16739`endif
16740
16741`endif
16742
16743`endif
16744
16745 end
16746 endtask
16747
16748
16749 task slam_ZeroTsbConfig0_core3_thread6;
16750 input [63:0] value;
16751 reg [5:0] tid;
16752 integer junk;
16753
16754 begin
16755`ifdef AXIS_EMUL_COSIM
16756//Do Nothing
16757`else
16758`ifdef GATESIM
16759//Do Nothing
16760`else
16761`ifdef CORE_3
16762 if (`PARGS.nas_check_on) begin
16763 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
16764 tid = 6
16765; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16766 end
16767`endif
16768
16769`endif
16770
16771`endif
16772
16773 end
16774 endtask
16775
16776
16777 task slam_ZeroTsbConfig0_core3_thread7;
16778 input [63:0] value;
16779 reg [5:0] tid;
16780 integer junk;
16781
16782 begin
16783`ifdef AXIS_EMUL_COSIM
16784//Do Nothing
16785`else
16786`ifdef GATESIM
16787//Do Nothing
16788`else
16789`ifdef CORE_3
16790 if (`PARGS.nas_check_on) begin
16791 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
16792 tid = 7
16793; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16794 end
16795`endif
16796
16797`endif
16798
16799`endif
16800
16801 end
16802 endtask
16803
16804
16805 task slam_ZeroTsbConfig0_core4_thread0;
16806 input [63:0] value;
16807 reg [5:0] tid;
16808 integer junk;
16809
16810 begin
16811`ifdef AXIS_EMUL_COSIM
16812//Do Nothing
16813`else
16814`ifdef GATESIM
16815//Do Nothing
16816`else
16817`ifdef CORE_4
16818 if (`PARGS.nas_check_on) begin
16819 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
16820 tid = 0
16821; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16822 end
16823`endif
16824
16825`endif
16826
16827`endif
16828
16829 end
16830 endtask
16831
16832
16833 task slam_ZeroTsbConfig0_core4_thread1;
16834 input [63:0] value;
16835 reg [5:0] tid;
16836 integer junk;
16837
16838 begin
16839`ifdef AXIS_EMUL_COSIM
16840//Do Nothing
16841`else
16842`ifdef GATESIM
16843//Do Nothing
16844`else
16845`ifdef CORE_4
16846 if (`PARGS.nas_check_on) begin
16847 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
16848 tid = 1
16849; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16850 end
16851`endif
16852
16853`endif
16854
16855`endif
16856
16857 end
16858 endtask
16859
16860
16861 task slam_ZeroTsbConfig0_core4_thread2;
16862 input [63:0] value;
16863 reg [5:0] tid;
16864 integer junk;
16865
16866 begin
16867`ifdef AXIS_EMUL_COSIM
16868//Do Nothing
16869`else
16870`ifdef GATESIM
16871//Do Nothing
16872`else
16873`ifdef CORE_4
16874 if (`PARGS.nas_check_on) begin
16875 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
16876 tid = 2
16877; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16878 end
16879`endif
16880
16881`endif
16882
16883`endif
16884
16885 end
16886 endtask
16887
16888
16889 task slam_ZeroTsbConfig0_core4_thread3;
16890 input [63:0] value;
16891 reg [5:0] tid;
16892 integer junk;
16893
16894 begin
16895`ifdef AXIS_EMUL_COSIM
16896//Do Nothing
16897`else
16898`ifdef GATESIM
16899//Do Nothing
16900`else
16901`ifdef CORE_4
16902 if (`PARGS.nas_check_on) begin
16903 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
16904 tid = 3
16905; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16906 end
16907`endif
16908
16909`endif
16910
16911`endif
16912
16913 end
16914 endtask
16915
16916
16917 task slam_ZeroTsbConfig0_core4_thread4;
16918 input [63:0] value;
16919 reg [5:0] tid;
16920 integer junk;
16921
16922 begin
16923`ifdef AXIS_EMUL_COSIM
16924//Do Nothing
16925`else
16926`ifdef GATESIM
16927//Do Nothing
16928`else
16929`ifdef CORE_4
16930 if (`PARGS.nas_check_on) begin
16931 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
16932 tid = 4
16933; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16934 end
16935`endif
16936
16937`endif
16938
16939`endif
16940
16941 end
16942 endtask
16943
16944
16945 task slam_ZeroTsbConfig0_core4_thread5;
16946 input [63:0] value;
16947 reg [5:0] tid;
16948 integer junk;
16949
16950 begin
16951`ifdef AXIS_EMUL_COSIM
16952//Do Nothing
16953`else
16954`ifdef GATESIM
16955//Do Nothing
16956`else
16957`ifdef CORE_4
16958 if (`PARGS.nas_check_on) begin
16959 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
16960 tid = 5
16961; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16962 end
16963`endif
16964
16965`endif
16966
16967`endif
16968
16969 end
16970 endtask
16971
16972
16973 task slam_ZeroTsbConfig0_core4_thread6;
16974 input [63:0] value;
16975 reg [5:0] tid;
16976 integer junk;
16977
16978 begin
16979`ifdef AXIS_EMUL_COSIM
16980//Do Nothing
16981`else
16982`ifdef GATESIM
16983//Do Nothing
16984`else
16985`ifdef CORE_4
16986 if (`PARGS.nas_check_on) begin
16987 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
16988 tid = 6
16989; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
16990 end
16991`endif
16992
16993`endif
16994
16995`endif
16996
16997 end
16998 endtask
16999
17000
17001 task slam_ZeroTsbConfig0_core4_thread7;
17002 input [63:0] value;
17003 reg [5:0] tid;
17004 integer junk;
17005
17006 begin
17007`ifdef AXIS_EMUL_COSIM
17008//Do Nothing
17009`else
17010`ifdef GATESIM
17011//Do Nothing
17012`else
17013`ifdef CORE_4
17014 if (`PARGS.nas_check_on) begin
17015 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
17016 tid = 7
17017; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17018 end
17019`endif
17020
17021`endif
17022
17023`endif
17024
17025 end
17026 endtask
17027
17028
17029 task slam_ZeroTsbConfig0_core5_thread0;
17030 input [63:0] value;
17031 reg [5:0] tid;
17032 integer junk;
17033
17034 begin
17035`ifdef AXIS_EMUL_COSIM
17036//Do Nothing
17037`else
17038`ifdef GATESIM
17039//Do Nothing
17040`else
17041`ifdef CORE_5
17042 if (`PARGS.nas_check_on) begin
17043 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
17044 tid = 0
17045; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17046 end
17047`endif
17048
17049`endif
17050
17051`endif
17052
17053 end
17054 endtask
17055
17056
17057 task slam_ZeroTsbConfig0_core5_thread1;
17058 input [63:0] value;
17059 reg [5:0] tid;
17060 integer junk;
17061
17062 begin
17063`ifdef AXIS_EMUL_COSIM
17064//Do Nothing
17065`else
17066`ifdef GATESIM
17067//Do Nothing
17068`else
17069`ifdef CORE_5
17070 if (`PARGS.nas_check_on) begin
17071 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
17072 tid = 1
17073; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17074 end
17075`endif
17076
17077`endif
17078
17079`endif
17080
17081 end
17082 endtask
17083
17084
17085 task slam_ZeroTsbConfig0_core5_thread2;
17086 input [63:0] value;
17087 reg [5:0] tid;
17088 integer junk;
17089
17090 begin
17091`ifdef AXIS_EMUL_COSIM
17092//Do Nothing
17093`else
17094`ifdef GATESIM
17095//Do Nothing
17096`else
17097`ifdef CORE_5
17098 if (`PARGS.nas_check_on) begin
17099 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
17100 tid = 2
17101; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17102 end
17103`endif
17104
17105`endif
17106
17107`endif
17108
17109 end
17110 endtask
17111
17112
17113 task slam_ZeroTsbConfig0_core5_thread3;
17114 input [63:0] value;
17115 reg [5:0] tid;
17116 integer junk;
17117
17118 begin
17119`ifdef AXIS_EMUL_COSIM
17120//Do Nothing
17121`else
17122`ifdef GATESIM
17123//Do Nothing
17124`else
17125`ifdef CORE_5
17126 if (`PARGS.nas_check_on) begin
17127 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
17128 tid = 3
17129; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17130 end
17131`endif
17132
17133`endif
17134
17135`endif
17136
17137 end
17138 endtask
17139
17140
17141 task slam_ZeroTsbConfig0_core5_thread4;
17142 input [63:0] value;
17143 reg [5:0] tid;
17144 integer junk;
17145
17146 begin
17147`ifdef AXIS_EMUL_COSIM
17148//Do Nothing
17149`else
17150`ifdef GATESIM
17151//Do Nothing
17152`else
17153`ifdef CORE_5
17154 if (`PARGS.nas_check_on) begin
17155 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
17156 tid = 4
17157; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17158 end
17159`endif
17160
17161`endif
17162
17163`endif
17164
17165 end
17166 endtask
17167
17168
17169 task slam_ZeroTsbConfig0_core5_thread5;
17170 input [63:0] value;
17171 reg [5:0] tid;
17172 integer junk;
17173
17174 begin
17175`ifdef AXIS_EMUL_COSIM
17176//Do Nothing
17177`else
17178`ifdef GATESIM
17179//Do Nothing
17180`else
17181`ifdef CORE_5
17182 if (`PARGS.nas_check_on) begin
17183 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
17184 tid = 5
17185; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17186 end
17187`endif
17188
17189`endif
17190
17191`endif
17192
17193 end
17194 endtask
17195
17196
17197 task slam_ZeroTsbConfig0_core5_thread6;
17198 input [63:0] value;
17199 reg [5:0] tid;
17200 integer junk;
17201
17202 begin
17203`ifdef AXIS_EMUL_COSIM
17204//Do Nothing
17205`else
17206`ifdef GATESIM
17207//Do Nothing
17208`else
17209`ifdef CORE_5
17210 if (`PARGS.nas_check_on) begin
17211 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
17212 tid = 6
17213; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17214 end
17215`endif
17216
17217`endif
17218
17219`endif
17220
17221 end
17222 endtask
17223
17224
17225 task slam_ZeroTsbConfig0_core5_thread7;
17226 input [63:0] value;
17227 reg [5:0] tid;
17228 integer junk;
17229
17230 begin
17231`ifdef AXIS_EMUL_COSIM
17232//Do Nothing
17233`else
17234`ifdef GATESIM
17235//Do Nothing
17236`else
17237`ifdef CORE_5
17238 if (`PARGS.nas_check_on) begin
17239 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
17240 tid = 7
17241; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17242 end
17243`endif
17244
17245`endif
17246
17247`endif
17248
17249 end
17250 endtask
17251
17252
17253 task slam_ZeroTsbConfig0_core6_thread0;
17254 input [63:0] value;
17255 reg [5:0] tid;
17256 integer junk;
17257
17258 begin
17259`ifdef AXIS_EMUL_COSIM
17260//Do Nothing
17261`else
17262`ifdef GATESIM
17263//Do Nothing
17264`else
17265`ifdef CORE_6
17266 if (`PARGS.nas_check_on) begin
17267 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
17268 tid = 0
17269; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17270 end
17271`endif
17272
17273`endif
17274
17275`endif
17276
17277 end
17278 endtask
17279
17280
17281 task slam_ZeroTsbConfig0_core6_thread1;
17282 input [63:0] value;
17283 reg [5:0] tid;
17284 integer junk;
17285
17286 begin
17287`ifdef AXIS_EMUL_COSIM
17288//Do Nothing
17289`else
17290`ifdef GATESIM
17291//Do Nothing
17292`else
17293`ifdef CORE_6
17294 if (`PARGS.nas_check_on) begin
17295 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
17296 tid = 1
17297; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17298 end
17299`endif
17300
17301`endif
17302
17303`endif
17304
17305 end
17306 endtask
17307
17308
17309 task slam_ZeroTsbConfig0_core6_thread2;
17310 input [63:0] value;
17311 reg [5:0] tid;
17312 integer junk;
17313
17314 begin
17315`ifdef AXIS_EMUL_COSIM
17316//Do Nothing
17317`else
17318`ifdef GATESIM
17319//Do Nothing
17320`else
17321`ifdef CORE_6
17322 if (`PARGS.nas_check_on) begin
17323 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
17324 tid = 2
17325; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17326 end
17327`endif
17328
17329`endif
17330
17331`endif
17332
17333 end
17334 endtask
17335
17336
17337 task slam_ZeroTsbConfig0_core6_thread3;
17338 input [63:0] value;
17339 reg [5:0] tid;
17340 integer junk;
17341
17342 begin
17343`ifdef AXIS_EMUL_COSIM
17344//Do Nothing
17345`else
17346`ifdef GATESIM
17347//Do Nothing
17348`else
17349`ifdef CORE_6
17350 if (`PARGS.nas_check_on) begin
17351 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
17352 tid = 3
17353; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17354 end
17355`endif
17356
17357`endif
17358
17359`endif
17360
17361 end
17362 endtask
17363
17364
17365 task slam_ZeroTsbConfig0_core6_thread4;
17366 input [63:0] value;
17367 reg [5:0] tid;
17368 integer junk;
17369
17370 begin
17371`ifdef AXIS_EMUL_COSIM
17372//Do Nothing
17373`else
17374`ifdef GATESIM
17375//Do Nothing
17376`else
17377`ifdef CORE_6
17378 if (`PARGS.nas_check_on) begin
17379 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
17380 tid = 4
17381; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17382 end
17383`endif
17384
17385`endif
17386
17387`endif
17388
17389 end
17390 endtask
17391
17392
17393 task slam_ZeroTsbConfig0_core6_thread5;
17394 input [63:0] value;
17395 reg [5:0] tid;
17396 integer junk;
17397
17398 begin
17399`ifdef AXIS_EMUL_COSIM
17400//Do Nothing
17401`else
17402`ifdef GATESIM
17403//Do Nothing
17404`else
17405`ifdef CORE_6
17406 if (`PARGS.nas_check_on) begin
17407 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
17408 tid = 5
17409; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17410 end
17411`endif
17412
17413`endif
17414
17415`endif
17416
17417 end
17418 endtask
17419
17420
17421 task slam_ZeroTsbConfig0_core6_thread6;
17422 input [63:0] value;
17423 reg [5:0] tid;
17424 integer junk;
17425
17426 begin
17427`ifdef AXIS_EMUL_COSIM
17428//Do Nothing
17429`else
17430`ifdef GATESIM
17431//Do Nothing
17432`else
17433`ifdef CORE_6
17434 if (`PARGS.nas_check_on) begin
17435 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
17436 tid = 6
17437; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17438 end
17439`endif
17440
17441`endif
17442
17443`endif
17444
17445 end
17446 endtask
17447
17448
17449 task slam_ZeroTsbConfig0_core6_thread7;
17450 input [63:0] value;
17451 reg [5:0] tid;
17452 integer junk;
17453
17454 begin
17455`ifdef AXIS_EMUL_COSIM
17456//Do Nothing
17457`else
17458`ifdef GATESIM
17459//Do Nothing
17460`else
17461`ifdef CORE_6
17462 if (`PARGS.nas_check_on) begin
17463 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
17464 tid = 7
17465; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17466 end
17467`endif
17468
17469`endif
17470
17471`endif
17472
17473 end
17474 endtask
17475
17476
17477 task slam_ZeroTsbConfig0_core7_thread0;
17478 input [63:0] value;
17479 reg [5:0] tid;
17480 integer junk;
17481
17482 begin
17483`ifdef AXIS_EMUL_COSIM
17484//Do Nothing
17485`else
17486`ifdef GATESIM
17487//Do Nothing
17488`else
17489`ifdef CORE_7
17490 if (`PARGS.nas_check_on) begin
17491 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
17492 tid = 0
17493; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17494 end
17495`endif
17496
17497`endif
17498
17499`endif
17500
17501 end
17502 endtask
17503
17504
17505 task slam_ZeroTsbConfig0_core7_thread1;
17506 input [63:0] value;
17507 reg [5:0] tid;
17508 integer junk;
17509
17510 begin
17511`ifdef AXIS_EMUL_COSIM
17512//Do Nothing
17513`else
17514`ifdef GATESIM
17515//Do Nothing
17516`else
17517`ifdef CORE_7
17518 if (`PARGS.nas_check_on) begin
17519 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
17520 tid = 1
17521; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17522 end
17523`endif
17524
17525`endif
17526
17527`endif
17528
17529 end
17530 endtask
17531
17532
17533 task slam_ZeroTsbConfig0_core7_thread2;
17534 input [63:0] value;
17535 reg [5:0] tid;
17536 integer junk;
17537
17538 begin
17539`ifdef AXIS_EMUL_COSIM
17540//Do Nothing
17541`else
17542`ifdef GATESIM
17543//Do Nothing
17544`else
17545`ifdef CORE_7
17546 if (`PARGS.nas_check_on) begin
17547 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
17548 tid = 2
17549; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17550 end
17551`endif
17552
17553`endif
17554
17555`endif
17556
17557 end
17558 endtask
17559
17560
17561 task slam_ZeroTsbConfig0_core7_thread3;
17562 input [63:0] value;
17563 reg [5:0] tid;
17564 integer junk;
17565
17566 begin
17567`ifdef AXIS_EMUL_COSIM
17568//Do Nothing
17569`else
17570`ifdef GATESIM
17571//Do Nothing
17572`else
17573`ifdef CORE_7
17574 if (`PARGS.nas_check_on) begin
17575 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
17576 tid = 3
17577; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17578 end
17579`endif
17580
17581`endif
17582
17583`endif
17584
17585 end
17586 endtask
17587
17588
17589 task slam_ZeroTsbConfig0_core7_thread4;
17590 input [63:0] value;
17591 reg [5:0] tid;
17592 integer junk;
17593
17594 begin
17595`ifdef AXIS_EMUL_COSIM
17596//Do Nothing
17597`else
17598`ifdef GATESIM
17599//Do Nothing
17600`else
17601`ifdef CORE_7
17602 if (`PARGS.nas_check_on) begin
17603 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
17604 tid = 4
17605; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17606 end
17607`endif
17608
17609`endif
17610
17611`endif
17612
17613 end
17614 endtask
17615
17616
17617 task slam_ZeroTsbConfig0_core7_thread5;
17618 input [63:0] value;
17619 reg [5:0] tid;
17620 integer junk;
17621
17622 begin
17623`ifdef AXIS_EMUL_COSIM
17624//Do Nothing
17625`else
17626`ifdef GATESIM
17627//Do Nothing
17628`else
17629`ifdef CORE_7
17630 if (`PARGS.nas_check_on) begin
17631 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
17632 tid = 5
17633; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17634 end
17635`endif
17636
17637`endif
17638
17639`endif
17640
17641 end
17642 endtask
17643
17644
17645 task slam_ZeroTsbConfig0_core7_thread6;
17646 input [63:0] value;
17647 reg [5:0] tid;
17648 integer junk;
17649
17650 begin
17651`ifdef AXIS_EMUL_COSIM
17652//Do Nothing
17653`else
17654`ifdef GATESIM
17655//Do Nothing
17656`else
17657`ifdef CORE_7
17658 if (`PARGS.nas_check_on) begin
17659 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
17660 tid = 6
17661; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17662 end
17663`endif
17664
17665`endif
17666
17667`endif
17668
17669 end
17670 endtask
17671
17672
17673 task slam_ZeroTsbConfig0_core7_thread7;
17674 input [63:0] value;
17675 reg [5:0] tid;
17676 integer junk;
17677
17678 begin
17679`ifdef AXIS_EMUL_COSIM
17680//Do Nothing
17681`else
17682`ifdef GATESIM
17683//Do Nothing
17684`else
17685`ifdef CORE_7
17686 if (`PARGS.nas_check_on) begin
17687 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
17688 tid = 7
17689; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h10, value);
17690 end
17691`endif
17692
17693`endif
17694
17695`endif
17696
17697 end
17698 endtask
17699
17700
17701 task slam_ZeroTsbConfig1_core0_thread0;
17702 input [63:0] value;
17703 reg [5:0] tid;
17704 integer junk;
17705
17706 begin
17707`ifdef AXIS_EMUL_COSIM
17708//Do Nothing
17709`else
17710`ifdef GATESIM
17711//Do Nothing
17712`else
17713`ifdef CORE_0
17714 if (`PARGS.nas_check_on) begin
17715 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
17716 tid = 0
17717; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17718 end
17719`endif
17720
17721`endif
17722
17723`endif
17724
17725 end
17726 endtask
17727
17728
17729 task slam_ZeroTsbConfig1_core0_thread1;
17730 input [63:0] value;
17731 reg [5:0] tid;
17732 integer junk;
17733
17734 begin
17735`ifdef AXIS_EMUL_COSIM
17736//Do Nothing
17737`else
17738`ifdef GATESIM
17739//Do Nothing
17740`else
17741`ifdef CORE_0
17742 if (`PARGS.nas_check_on) begin
17743 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
17744 tid = 1
17745; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17746 end
17747`endif
17748
17749`endif
17750
17751`endif
17752
17753 end
17754 endtask
17755
17756
17757 task slam_ZeroTsbConfig1_core0_thread2;
17758 input [63:0] value;
17759 reg [5:0] tid;
17760 integer junk;
17761
17762 begin
17763`ifdef AXIS_EMUL_COSIM
17764//Do Nothing
17765`else
17766`ifdef GATESIM
17767//Do Nothing
17768`else
17769`ifdef CORE_0
17770 if (`PARGS.nas_check_on) begin
17771 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
17772 tid = 2
17773; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17774 end
17775`endif
17776
17777`endif
17778
17779`endif
17780
17781 end
17782 endtask
17783
17784
17785 task slam_ZeroTsbConfig1_core0_thread3;
17786 input [63:0] value;
17787 reg [5:0] tid;
17788 integer junk;
17789
17790 begin
17791`ifdef AXIS_EMUL_COSIM
17792//Do Nothing
17793`else
17794`ifdef GATESIM
17795//Do Nothing
17796`else
17797`ifdef CORE_0
17798 if (`PARGS.nas_check_on) begin
17799 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
17800 tid = 3
17801; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17802 end
17803`endif
17804
17805`endif
17806
17807`endif
17808
17809 end
17810 endtask
17811
17812
17813 task slam_ZeroTsbConfig1_core0_thread4;
17814 input [63:0] value;
17815 reg [5:0] tid;
17816 integer junk;
17817
17818 begin
17819`ifdef AXIS_EMUL_COSIM
17820//Do Nothing
17821`else
17822`ifdef GATESIM
17823//Do Nothing
17824`else
17825`ifdef CORE_0
17826 if (`PARGS.nas_check_on) begin
17827 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
17828 tid = 4
17829; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17830 end
17831`endif
17832
17833`endif
17834
17835`endif
17836
17837 end
17838 endtask
17839
17840
17841 task slam_ZeroTsbConfig1_core0_thread5;
17842 input [63:0] value;
17843 reg [5:0] tid;
17844 integer junk;
17845
17846 begin
17847`ifdef AXIS_EMUL_COSIM
17848//Do Nothing
17849`else
17850`ifdef GATESIM
17851//Do Nothing
17852`else
17853`ifdef CORE_0
17854 if (`PARGS.nas_check_on) begin
17855 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
17856 tid = 5
17857; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17858 end
17859`endif
17860
17861`endif
17862
17863`endif
17864
17865 end
17866 endtask
17867
17868
17869 task slam_ZeroTsbConfig1_core0_thread6;
17870 input [63:0] value;
17871 reg [5:0] tid;
17872 integer junk;
17873
17874 begin
17875`ifdef AXIS_EMUL_COSIM
17876//Do Nothing
17877`else
17878`ifdef GATESIM
17879//Do Nothing
17880`else
17881`ifdef CORE_0
17882 if (`PARGS.nas_check_on) begin
17883 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
17884 tid = 6
17885; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17886 end
17887`endif
17888
17889`endif
17890
17891`endif
17892
17893 end
17894 endtask
17895
17896
17897 task slam_ZeroTsbConfig1_core0_thread7;
17898 input [63:0] value;
17899 reg [5:0] tid;
17900 integer junk;
17901
17902 begin
17903`ifdef AXIS_EMUL_COSIM
17904//Do Nothing
17905`else
17906`ifdef GATESIM
17907//Do Nothing
17908`else
17909`ifdef CORE_0
17910 if (`PARGS.nas_check_on) begin
17911 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
17912 tid = 7
17913; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17914 end
17915`endif
17916
17917`endif
17918
17919`endif
17920
17921 end
17922 endtask
17923
17924
17925 task slam_ZeroTsbConfig1_core1_thread0;
17926 input [63:0] value;
17927 reg [5:0] tid;
17928 integer junk;
17929
17930 begin
17931`ifdef AXIS_EMUL_COSIM
17932//Do Nothing
17933`else
17934`ifdef GATESIM
17935//Do Nothing
17936`else
17937`ifdef CORE_1
17938 if (`PARGS.nas_check_on) begin
17939 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
17940 tid = 0
17941; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17942 end
17943`endif
17944
17945`endif
17946
17947`endif
17948
17949 end
17950 endtask
17951
17952
17953 task slam_ZeroTsbConfig1_core1_thread1;
17954 input [63:0] value;
17955 reg [5:0] tid;
17956 integer junk;
17957
17958 begin
17959`ifdef AXIS_EMUL_COSIM
17960//Do Nothing
17961`else
17962`ifdef GATESIM
17963//Do Nothing
17964`else
17965`ifdef CORE_1
17966 if (`PARGS.nas_check_on) begin
17967 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
17968 tid = 1
17969; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17970 end
17971`endif
17972
17973`endif
17974
17975`endif
17976
17977 end
17978 endtask
17979
17980
17981 task slam_ZeroTsbConfig1_core1_thread2;
17982 input [63:0] value;
17983 reg [5:0] tid;
17984 integer junk;
17985
17986 begin
17987`ifdef AXIS_EMUL_COSIM
17988//Do Nothing
17989`else
17990`ifdef GATESIM
17991//Do Nothing
17992`else
17993`ifdef CORE_1
17994 if (`PARGS.nas_check_on) begin
17995 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
17996 tid = 2
17997; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
17998 end
17999`endif
18000
18001`endif
18002
18003`endif
18004
18005 end
18006 endtask
18007
18008
18009 task slam_ZeroTsbConfig1_core1_thread3;
18010 input [63:0] value;
18011 reg [5:0] tid;
18012 integer junk;
18013
18014 begin
18015`ifdef AXIS_EMUL_COSIM
18016//Do Nothing
18017`else
18018`ifdef GATESIM
18019//Do Nothing
18020`else
18021`ifdef CORE_1
18022 if (`PARGS.nas_check_on) begin
18023 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
18024 tid = 3
18025; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18026 end
18027`endif
18028
18029`endif
18030
18031`endif
18032
18033 end
18034 endtask
18035
18036
18037 task slam_ZeroTsbConfig1_core1_thread4;
18038 input [63:0] value;
18039 reg [5:0] tid;
18040 integer junk;
18041
18042 begin
18043`ifdef AXIS_EMUL_COSIM
18044//Do Nothing
18045`else
18046`ifdef GATESIM
18047//Do Nothing
18048`else
18049`ifdef CORE_1
18050 if (`PARGS.nas_check_on) begin
18051 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
18052 tid = 4
18053; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18054 end
18055`endif
18056
18057`endif
18058
18059`endif
18060
18061 end
18062 endtask
18063
18064
18065 task slam_ZeroTsbConfig1_core1_thread5;
18066 input [63:0] value;
18067 reg [5:0] tid;
18068 integer junk;
18069
18070 begin
18071`ifdef AXIS_EMUL_COSIM
18072//Do Nothing
18073`else
18074`ifdef GATESIM
18075//Do Nothing
18076`else
18077`ifdef CORE_1
18078 if (`PARGS.nas_check_on) begin
18079 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
18080 tid = 5
18081; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18082 end
18083`endif
18084
18085`endif
18086
18087`endif
18088
18089 end
18090 endtask
18091
18092
18093 task slam_ZeroTsbConfig1_core1_thread6;
18094 input [63:0] value;
18095 reg [5:0] tid;
18096 integer junk;
18097
18098 begin
18099`ifdef AXIS_EMUL_COSIM
18100//Do Nothing
18101`else
18102`ifdef GATESIM
18103//Do Nothing
18104`else
18105`ifdef CORE_1
18106 if (`PARGS.nas_check_on) begin
18107 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
18108 tid = 6
18109; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18110 end
18111`endif
18112
18113`endif
18114
18115`endif
18116
18117 end
18118 endtask
18119
18120
18121 task slam_ZeroTsbConfig1_core1_thread7;
18122 input [63:0] value;
18123 reg [5:0] tid;
18124 integer junk;
18125
18126 begin
18127`ifdef AXIS_EMUL_COSIM
18128//Do Nothing
18129`else
18130`ifdef GATESIM
18131//Do Nothing
18132`else
18133`ifdef CORE_1
18134 if (`PARGS.nas_check_on) begin
18135 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
18136 tid = 7
18137; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18138 end
18139`endif
18140
18141`endif
18142
18143`endif
18144
18145 end
18146 endtask
18147
18148
18149 task slam_ZeroTsbConfig1_core2_thread0;
18150 input [63:0] value;
18151 reg [5:0] tid;
18152 integer junk;
18153
18154 begin
18155`ifdef AXIS_EMUL_COSIM
18156//Do Nothing
18157`else
18158`ifdef GATESIM
18159//Do Nothing
18160`else
18161`ifdef CORE_2
18162 if (`PARGS.nas_check_on) begin
18163 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
18164 tid = 0
18165; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18166 end
18167`endif
18168
18169`endif
18170
18171`endif
18172
18173 end
18174 endtask
18175
18176
18177 task slam_ZeroTsbConfig1_core2_thread1;
18178 input [63:0] value;
18179 reg [5:0] tid;
18180 integer junk;
18181
18182 begin
18183`ifdef AXIS_EMUL_COSIM
18184//Do Nothing
18185`else
18186`ifdef GATESIM
18187//Do Nothing
18188`else
18189`ifdef CORE_2
18190 if (`PARGS.nas_check_on) begin
18191 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
18192 tid = 1
18193; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18194 end
18195`endif
18196
18197`endif
18198
18199`endif
18200
18201 end
18202 endtask
18203
18204
18205 task slam_ZeroTsbConfig1_core2_thread2;
18206 input [63:0] value;
18207 reg [5:0] tid;
18208 integer junk;
18209
18210 begin
18211`ifdef AXIS_EMUL_COSIM
18212//Do Nothing
18213`else
18214`ifdef GATESIM
18215//Do Nothing
18216`else
18217`ifdef CORE_2
18218 if (`PARGS.nas_check_on) begin
18219 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
18220 tid = 2
18221; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18222 end
18223`endif
18224
18225`endif
18226
18227`endif
18228
18229 end
18230 endtask
18231
18232
18233 task slam_ZeroTsbConfig1_core2_thread3;
18234 input [63:0] value;
18235 reg [5:0] tid;
18236 integer junk;
18237
18238 begin
18239`ifdef AXIS_EMUL_COSIM
18240//Do Nothing
18241`else
18242`ifdef GATESIM
18243//Do Nothing
18244`else
18245`ifdef CORE_2
18246 if (`PARGS.nas_check_on) begin
18247 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
18248 tid = 3
18249; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18250 end
18251`endif
18252
18253`endif
18254
18255`endif
18256
18257 end
18258 endtask
18259
18260
18261 task slam_ZeroTsbConfig1_core2_thread4;
18262 input [63:0] value;
18263 reg [5:0] tid;
18264 integer junk;
18265
18266 begin
18267`ifdef AXIS_EMUL_COSIM
18268//Do Nothing
18269`else
18270`ifdef GATESIM
18271//Do Nothing
18272`else
18273`ifdef CORE_2
18274 if (`PARGS.nas_check_on) begin
18275 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
18276 tid = 4
18277; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18278 end
18279`endif
18280
18281`endif
18282
18283`endif
18284
18285 end
18286 endtask
18287
18288
18289 task slam_ZeroTsbConfig1_core2_thread5;
18290 input [63:0] value;
18291 reg [5:0] tid;
18292 integer junk;
18293
18294 begin
18295`ifdef AXIS_EMUL_COSIM
18296//Do Nothing
18297`else
18298`ifdef GATESIM
18299//Do Nothing
18300`else
18301`ifdef CORE_2
18302 if (`PARGS.nas_check_on) begin
18303 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
18304 tid = 5
18305; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18306 end
18307`endif
18308
18309`endif
18310
18311`endif
18312
18313 end
18314 endtask
18315
18316
18317 task slam_ZeroTsbConfig1_core2_thread6;
18318 input [63:0] value;
18319 reg [5:0] tid;
18320 integer junk;
18321
18322 begin
18323`ifdef AXIS_EMUL_COSIM
18324//Do Nothing
18325`else
18326`ifdef GATESIM
18327//Do Nothing
18328`else
18329`ifdef CORE_2
18330 if (`PARGS.nas_check_on) begin
18331 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
18332 tid = 6
18333; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18334 end
18335`endif
18336
18337`endif
18338
18339`endif
18340
18341 end
18342 endtask
18343
18344
18345 task slam_ZeroTsbConfig1_core2_thread7;
18346 input [63:0] value;
18347 reg [5:0] tid;
18348 integer junk;
18349
18350 begin
18351`ifdef AXIS_EMUL_COSIM
18352//Do Nothing
18353`else
18354`ifdef GATESIM
18355//Do Nothing
18356`else
18357`ifdef CORE_2
18358 if (`PARGS.nas_check_on) begin
18359 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
18360 tid = 7
18361; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18362 end
18363`endif
18364
18365`endif
18366
18367`endif
18368
18369 end
18370 endtask
18371
18372
18373 task slam_ZeroTsbConfig1_core3_thread0;
18374 input [63:0] value;
18375 reg [5:0] tid;
18376 integer junk;
18377
18378 begin
18379`ifdef AXIS_EMUL_COSIM
18380//Do Nothing
18381`else
18382`ifdef GATESIM
18383//Do Nothing
18384`else
18385`ifdef CORE_3
18386 if (`PARGS.nas_check_on) begin
18387 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
18388 tid = 0
18389; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18390 end
18391`endif
18392
18393`endif
18394
18395`endif
18396
18397 end
18398 endtask
18399
18400
18401 task slam_ZeroTsbConfig1_core3_thread1;
18402 input [63:0] value;
18403 reg [5:0] tid;
18404 integer junk;
18405
18406 begin
18407`ifdef AXIS_EMUL_COSIM
18408//Do Nothing
18409`else
18410`ifdef GATESIM
18411//Do Nothing
18412`else
18413`ifdef CORE_3
18414 if (`PARGS.nas_check_on) begin
18415 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
18416 tid = 1
18417; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18418 end
18419`endif
18420
18421`endif
18422
18423`endif
18424
18425 end
18426 endtask
18427
18428
18429 task slam_ZeroTsbConfig1_core3_thread2;
18430 input [63:0] value;
18431 reg [5:0] tid;
18432 integer junk;
18433
18434 begin
18435`ifdef AXIS_EMUL_COSIM
18436//Do Nothing
18437`else
18438`ifdef GATESIM
18439//Do Nothing
18440`else
18441`ifdef CORE_3
18442 if (`PARGS.nas_check_on) begin
18443 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
18444 tid = 2
18445; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18446 end
18447`endif
18448
18449`endif
18450
18451`endif
18452
18453 end
18454 endtask
18455
18456
18457 task slam_ZeroTsbConfig1_core3_thread3;
18458 input [63:0] value;
18459 reg [5:0] tid;
18460 integer junk;
18461
18462 begin
18463`ifdef AXIS_EMUL_COSIM
18464//Do Nothing
18465`else
18466`ifdef GATESIM
18467//Do Nothing
18468`else
18469`ifdef CORE_3
18470 if (`PARGS.nas_check_on) begin
18471 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
18472 tid = 3
18473; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18474 end
18475`endif
18476
18477`endif
18478
18479`endif
18480
18481 end
18482 endtask
18483
18484
18485 task slam_ZeroTsbConfig1_core3_thread4;
18486 input [63:0] value;
18487 reg [5:0] tid;
18488 integer junk;
18489
18490 begin
18491`ifdef AXIS_EMUL_COSIM
18492//Do Nothing
18493`else
18494`ifdef GATESIM
18495//Do Nothing
18496`else
18497`ifdef CORE_3
18498 if (`PARGS.nas_check_on) begin
18499 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
18500 tid = 4
18501; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18502 end
18503`endif
18504
18505`endif
18506
18507`endif
18508
18509 end
18510 endtask
18511
18512
18513 task slam_ZeroTsbConfig1_core3_thread5;
18514 input [63:0] value;
18515 reg [5:0] tid;
18516 integer junk;
18517
18518 begin
18519`ifdef AXIS_EMUL_COSIM
18520//Do Nothing
18521`else
18522`ifdef GATESIM
18523//Do Nothing
18524`else
18525`ifdef CORE_3
18526 if (`PARGS.nas_check_on) begin
18527 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
18528 tid = 5
18529; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18530 end
18531`endif
18532
18533`endif
18534
18535`endif
18536
18537 end
18538 endtask
18539
18540
18541 task slam_ZeroTsbConfig1_core3_thread6;
18542 input [63:0] value;
18543 reg [5:0] tid;
18544 integer junk;
18545
18546 begin
18547`ifdef AXIS_EMUL_COSIM
18548//Do Nothing
18549`else
18550`ifdef GATESIM
18551//Do Nothing
18552`else
18553`ifdef CORE_3
18554 if (`PARGS.nas_check_on) begin
18555 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
18556 tid = 6
18557; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18558 end
18559`endif
18560
18561`endif
18562
18563`endif
18564
18565 end
18566 endtask
18567
18568
18569 task slam_ZeroTsbConfig1_core3_thread7;
18570 input [63:0] value;
18571 reg [5:0] tid;
18572 integer junk;
18573
18574 begin
18575`ifdef AXIS_EMUL_COSIM
18576//Do Nothing
18577`else
18578`ifdef GATESIM
18579//Do Nothing
18580`else
18581`ifdef CORE_3
18582 if (`PARGS.nas_check_on) begin
18583 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
18584 tid = 7
18585; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18586 end
18587`endif
18588
18589`endif
18590
18591`endif
18592
18593 end
18594 endtask
18595
18596
18597 task slam_ZeroTsbConfig1_core4_thread0;
18598 input [63:0] value;
18599 reg [5:0] tid;
18600 integer junk;
18601
18602 begin
18603`ifdef AXIS_EMUL_COSIM
18604//Do Nothing
18605`else
18606`ifdef GATESIM
18607//Do Nothing
18608`else
18609`ifdef CORE_4
18610 if (`PARGS.nas_check_on) begin
18611 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
18612 tid = 0
18613; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18614 end
18615`endif
18616
18617`endif
18618
18619`endif
18620
18621 end
18622 endtask
18623
18624
18625 task slam_ZeroTsbConfig1_core4_thread1;
18626 input [63:0] value;
18627 reg [5:0] tid;
18628 integer junk;
18629
18630 begin
18631`ifdef AXIS_EMUL_COSIM
18632//Do Nothing
18633`else
18634`ifdef GATESIM
18635//Do Nothing
18636`else
18637`ifdef CORE_4
18638 if (`PARGS.nas_check_on) begin
18639 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
18640 tid = 1
18641; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18642 end
18643`endif
18644
18645`endif
18646
18647`endif
18648
18649 end
18650 endtask
18651
18652
18653 task slam_ZeroTsbConfig1_core4_thread2;
18654 input [63:0] value;
18655 reg [5:0] tid;
18656 integer junk;
18657
18658 begin
18659`ifdef AXIS_EMUL_COSIM
18660//Do Nothing
18661`else
18662`ifdef GATESIM
18663//Do Nothing
18664`else
18665`ifdef CORE_4
18666 if (`PARGS.nas_check_on) begin
18667 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
18668 tid = 2
18669; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18670 end
18671`endif
18672
18673`endif
18674
18675`endif
18676
18677 end
18678 endtask
18679
18680
18681 task slam_ZeroTsbConfig1_core4_thread3;
18682 input [63:0] value;
18683 reg [5:0] tid;
18684 integer junk;
18685
18686 begin
18687`ifdef AXIS_EMUL_COSIM
18688//Do Nothing
18689`else
18690`ifdef GATESIM
18691//Do Nothing
18692`else
18693`ifdef CORE_4
18694 if (`PARGS.nas_check_on) begin
18695 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
18696 tid = 3
18697; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18698 end
18699`endif
18700
18701`endif
18702
18703`endif
18704
18705 end
18706 endtask
18707
18708
18709 task slam_ZeroTsbConfig1_core4_thread4;
18710 input [63:0] value;
18711 reg [5:0] tid;
18712 integer junk;
18713
18714 begin
18715`ifdef AXIS_EMUL_COSIM
18716//Do Nothing
18717`else
18718`ifdef GATESIM
18719//Do Nothing
18720`else
18721`ifdef CORE_4
18722 if (`PARGS.nas_check_on) begin
18723 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
18724 tid = 4
18725; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18726 end
18727`endif
18728
18729`endif
18730
18731`endif
18732
18733 end
18734 endtask
18735
18736
18737 task slam_ZeroTsbConfig1_core4_thread5;
18738 input [63:0] value;
18739 reg [5:0] tid;
18740 integer junk;
18741
18742 begin
18743`ifdef AXIS_EMUL_COSIM
18744//Do Nothing
18745`else
18746`ifdef GATESIM
18747//Do Nothing
18748`else
18749`ifdef CORE_4
18750 if (`PARGS.nas_check_on) begin
18751 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
18752 tid = 5
18753; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18754 end
18755`endif
18756
18757`endif
18758
18759`endif
18760
18761 end
18762 endtask
18763
18764
18765 task slam_ZeroTsbConfig1_core4_thread6;
18766 input [63:0] value;
18767 reg [5:0] tid;
18768 integer junk;
18769
18770 begin
18771`ifdef AXIS_EMUL_COSIM
18772//Do Nothing
18773`else
18774`ifdef GATESIM
18775//Do Nothing
18776`else
18777`ifdef CORE_4
18778 if (`PARGS.nas_check_on) begin
18779 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
18780 tid = 6
18781; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18782 end
18783`endif
18784
18785`endif
18786
18787`endif
18788
18789 end
18790 endtask
18791
18792
18793 task slam_ZeroTsbConfig1_core4_thread7;
18794 input [63:0] value;
18795 reg [5:0] tid;
18796 integer junk;
18797
18798 begin
18799`ifdef AXIS_EMUL_COSIM
18800//Do Nothing
18801`else
18802`ifdef GATESIM
18803//Do Nothing
18804`else
18805`ifdef CORE_4
18806 if (`PARGS.nas_check_on) begin
18807 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
18808 tid = 7
18809; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18810 end
18811`endif
18812
18813`endif
18814
18815`endif
18816
18817 end
18818 endtask
18819
18820
18821 task slam_ZeroTsbConfig1_core5_thread0;
18822 input [63:0] value;
18823 reg [5:0] tid;
18824 integer junk;
18825
18826 begin
18827`ifdef AXIS_EMUL_COSIM
18828//Do Nothing
18829`else
18830`ifdef GATESIM
18831//Do Nothing
18832`else
18833`ifdef CORE_5
18834 if (`PARGS.nas_check_on) begin
18835 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
18836 tid = 0
18837; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18838 end
18839`endif
18840
18841`endif
18842
18843`endif
18844
18845 end
18846 endtask
18847
18848
18849 task slam_ZeroTsbConfig1_core5_thread1;
18850 input [63:0] value;
18851 reg [5:0] tid;
18852 integer junk;
18853
18854 begin
18855`ifdef AXIS_EMUL_COSIM
18856//Do Nothing
18857`else
18858`ifdef GATESIM
18859//Do Nothing
18860`else
18861`ifdef CORE_5
18862 if (`PARGS.nas_check_on) begin
18863 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
18864 tid = 1
18865; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18866 end
18867`endif
18868
18869`endif
18870
18871`endif
18872
18873 end
18874 endtask
18875
18876
18877 task slam_ZeroTsbConfig1_core5_thread2;
18878 input [63:0] value;
18879 reg [5:0] tid;
18880 integer junk;
18881
18882 begin
18883`ifdef AXIS_EMUL_COSIM
18884//Do Nothing
18885`else
18886`ifdef GATESIM
18887//Do Nothing
18888`else
18889`ifdef CORE_5
18890 if (`PARGS.nas_check_on) begin
18891 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
18892 tid = 2
18893; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18894 end
18895`endif
18896
18897`endif
18898
18899`endif
18900
18901 end
18902 endtask
18903
18904
18905 task slam_ZeroTsbConfig1_core5_thread3;
18906 input [63:0] value;
18907 reg [5:0] tid;
18908 integer junk;
18909
18910 begin
18911`ifdef AXIS_EMUL_COSIM
18912//Do Nothing
18913`else
18914`ifdef GATESIM
18915//Do Nothing
18916`else
18917`ifdef CORE_5
18918 if (`PARGS.nas_check_on) begin
18919 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
18920 tid = 3
18921; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18922 end
18923`endif
18924
18925`endif
18926
18927`endif
18928
18929 end
18930 endtask
18931
18932
18933 task slam_ZeroTsbConfig1_core5_thread4;
18934 input [63:0] value;
18935 reg [5:0] tid;
18936 integer junk;
18937
18938 begin
18939`ifdef AXIS_EMUL_COSIM
18940//Do Nothing
18941`else
18942`ifdef GATESIM
18943//Do Nothing
18944`else
18945`ifdef CORE_5
18946 if (`PARGS.nas_check_on) begin
18947 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
18948 tid = 4
18949; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18950 end
18951`endif
18952
18953`endif
18954
18955`endif
18956
18957 end
18958 endtask
18959
18960
18961 task slam_ZeroTsbConfig1_core5_thread5;
18962 input [63:0] value;
18963 reg [5:0] tid;
18964 integer junk;
18965
18966 begin
18967`ifdef AXIS_EMUL_COSIM
18968//Do Nothing
18969`else
18970`ifdef GATESIM
18971//Do Nothing
18972`else
18973`ifdef CORE_5
18974 if (`PARGS.nas_check_on) begin
18975 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
18976 tid = 5
18977; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
18978 end
18979`endif
18980
18981`endif
18982
18983`endif
18984
18985 end
18986 endtask
18987
18988
18989 task slam_ZeroTsbConfig1_core5_thread6;
18990 input [63:0] value;
18991 reg [5:0] tid;
18992 integer junk;
18993
18994 begin
18995`ifdef AXIS_EMUL_COSIM
18996//Do Nothing
18997`else
18998`ifdef GATESIM
18999//Do Nothing
19000`else
19001`ifdef CORE_5
19002 if (`PARGS.nas_check_on) begin
19003 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
19004 tid = 6
19005; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19006 end
19007`endif
19008
19009`endif
19010
19011`endif
19012
19013 end
19014 endtask
19015
19016
19017 task slam_ZeroTsbConfig1_core5_thread7;
19018 input [63:0] value;
19019 reg [5:0] tid;
19020 integer junk;
19021
19022 begin
19023`ifdef AXIS_EMUL_COSIM
19024//Do Nothing
19025`else
19026`ifdef GATESIM
19027//Do Nothing
19028`else
19029`ifdef CORE_5
19030 if (`PARGS.nas_check_on) begin
19031 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
19032 tid = 7
19033; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19034 end
19035`endif
19036
19037`endif
19038
19039`endif
19040
19041 end
19042 endtask
19043
19044
19045 task slam_ZeroTsbConfig1_core6_thread0;
19046 input [63:0] value;
19047 reg [5:0] tid;
19048 integer junk;
19049
19050 begin
19051`ifdef AXIS_EMUL_COSIM
19052//Do Nothing
19053`else
19054`ifdef GATESIM
19055//Do Nothing
19056`else
19057`ifdef CORE_6
19058 if (`PARGS.nas_check_on) begin
19059 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
19060 tid = 0
19061; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19062 end
19063`endif
19064
19065`endif
19066
19067`endif
19068
19069 end
19070 endtask
19071
19072
19073 task slam_ZeroTsbConfig1_core6_thread1;
19074 input [63:0] value;
19075 reg [5:0] tid;
19076 integer junk;
19077
19078 begin
19079`ifdef AXIS_EMUL_COSIM
19080//Do Nothing
19081`else
19082`ifdef GATESIM
19083//Do Nothing
19084`else
19085`ifdef CORE_6
19086 if (`PARGS.nas_check_on) begin
19087 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
19088 tid = 1
19089; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19090 end
19091`endif
19092
19093`endif
19094
19095`endif
19096
19097 end
19098 endtask
19099
19100
19101 task slam_ZeroTsbConfig1_core6_thread2;
19102 input [63:0] value;
19103 reg [5:0] tid;
19104 integer junk;
19105
19106 begin
19107`ifdef AXIS_EMUL_COSIM
19108//Do Nothing
19109`else
19110`ifdef GATESIM
19111//Do Nothing
19112`else
19113`ifdef CORE_6
19114 if (`PARGS.nas_check_on) begin
19115 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
19116 tid = 2
19117; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19118 end
19119`endif
19120
19121`endif
19122
19123`endif
19124
19125 end
19126 endtask
19127
19128
19129 task slam_ZeroTsbConfig1_core6_thread3;
19130 input [63:0] value;
19131 reg [5:0] tid;
19132 integer junk;
19133
19134 begin
19135`ifdef AXIS_EMUL_COSIM
19136//Do Nothing
19137`else
19138`ifdef GATESIM
19139//Do Nothing
19140`else
19141`ifdef CORE_6
19142 if (`PARGS.nas_check_on) begin
19143 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
19144 tid = 3
19145; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19146 end
19147`endif
19148
19149`endif
19150
19151`endif
19152
19153 end
19154 endtask
19155
19156
19157 task slam_ZeroTsbConfig1_core6_thread4;
19158 input [63:0] value;
19159 reg [5:0] tid;
19160 integer junk;
19161
19162 begin
19163`ifdef AXIS_EMUL_COSIM
19164//Do Nothing
19165`else
19166`ifdef GATESIM
19167//Do Nothing
19168`else
19169`ifdef CORE_6
19170 if (`PARGS.nas_check_on) begin
19171 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
19172 tid = 4
19173; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19174 end
19175`endif
19176
19177`endif
19178
19179`endif
19180
19181 end
19182 endtask
19183
19184
19185 task slam_ZeroTsbConfig1_core6_thread5;
19186 input [63:0] value;
19187 reg [5:0] tid;
19188 integer junk;
19189
19190 begin
19191`ifdef AXIS_EMUL_COSIM
19192//Do Nothing
19193`else
19194`ifdef GATESIM
19195//Do Nothing
19196`else
19197`ifdef CORE_6
19198 if (`PARGS.nas_check_on) begin
19199 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
19200 tid = 5
19201; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19202 end
19203`endif
19204
19205`endif
19206
19207`endif
19208
19209 end
19210 endtask
19211
19212
19213 task slam_ZeroTsbConfig1_core6_thread6;
19214 input [63:0] value;
19215 reg [5:0] tid;
19216 integer junk;
19217
19218 begin
19219`ifdef AXIS_EMUL_COSIM
19220//Do Nothing
19221`else
19222`ifdef GATESIM
19223//Do Nothing
19224`else
19225`ifdef CORE_6
19226 if (`PARGS.nas_check_on) begin
19227 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
19228 tid = 6
19229; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19230 end
19231`endif
19232
19233`endif
19234
19235`endif
19236
19237 end
19238 endtask
19239
19240
19241 task slam_ZeroTsbConfig1_core6_thread7;
19242 input [63:0] value;
19243 reg [5:0] tid;
19244 integer junk;
19245
19246 begin
19247`ifdef AXIS_EMUL_COSIM
19248//Do Nothing
19249`else
19250`ifdef GATESIM
19251//Do Nothing
19252`else
19253`ifdef CORE_6
19254 if (`PARGS.nas_check_on) begin
19255 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
19256 tid = 7
19257; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19258 end
19259`endif
19260
19261`endif
19262
19263`endif
19264
19265 end
19266 endtask
19267
19268
19269 task slam_ZeroTsbConfig1_core7_thread0;
19270 input [63:0] value;
19271 reg [5:0] tid;
19272 integer junk;
19273
19274 begin
19275`ifdef AXIS_EMUL_COSIM
19276//Do Nothing
19277`else
19278`ifdef GATESIM
19279//Do Nothing
19280`else
19281`ifdef CORE_7
19282 if (`PARGS.nas_check_on) begin
19283 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
19284 tid = 0
19285; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19286 end
19287`endif
19288
19289`endif
19290
19291`endif
19292
19293 end
19294 endtask
19295
19296
19297 task slam_ZeroTsbConfig1_core7_thread1;
19298 input [63:0] value;
19299 reg [5:0] tid;
19300 integer junk;
19301
19302 begin
19303`ifdef AXIS_EMUL_COSIM
19304//Do Nothing
19305`else
19306`ifdef GATESIM
19307//Do Nothing
19308`else
19309`ifdef CORE_7
19310 if (`PARGS.nas_check_on) begin
19311 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
19312 tid = 1
19313; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19314 end
19315`endif
19316
19317`endif
19318
19319`endif
19320
19321 end
19322 endtask
19323
19324
19325 task slam_ZeroTsbConfig1_core7_thread2;
19326 input [63:0] value;
19327 reg [5:0] tid;
19328 integer junk;
19329
19330 begin
19331`ifdef AXIS_EMUL_COSIM
19332//Do Nothing
19333`else
19334`ifdef GATESIM
19335//Do Nothing
19336`else
19337`ifdef CORE_7
19338 if (`PARGS.nas_check_on) begin
19339 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
19340 tid = 2
19341; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19342 end
19343`endif
19344
19345`endif
19346
19347`endif
19348
19349 end
19350 endtask
19351
19352
19353 task slam_ZeroTsbConfig1_core7_thread3;
19354 input [63:0] value;
19355 reg [5:0] tid;
19356 integer junk;
19357
19358 begin
19359`ifdef AXIS_EMUL_COSIM
19360//Do Nothing
19361`else
19362`ifdef GATESIM
19363//Do Nothing
19364`else
19365`ifdef CORE_7
19366 if (`PARGS.nas_check_on) begin
19367 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
19368 tid = 3
19369; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19370 end
19371`endif
19372
19373`endif
19374
19375`endif
19376
19377 end
19378 endtask
19379
19380
19381 task slam_ZeroTsbConfig1_core7_thread4;
19382 input [63:0] value;
19383 reg [5:0] tid;
19384 integer junk;
19385
19386 begin
19387`ifdef AXIS_EMUL_COSIM
19388//Do Nothing
19389`else
19390`ifdef GATESIM
19391//Do Nothing
19392`else
19393`ifdef CORE_7
19394 if (`PARGS.nas_check_on) begin
19395 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
19396 tid = 4
19397; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19398 end
19399`endif
19400
19401`endif
19402
19403`endif
19404
19405 end
19406 endtask
19407
19408
19409 task slam_ZeroTsbConfig1_core7_thread5;
19410 input [63:0] value;
19411 reg [5:0] tid;
19412 integer junk;
19413
19414 begin
19415`ifdef AXIS_EMUL_COSIM
19416//Do Nothing
19417`else
19418`ifdef GATESIM
19419//Do Nothing
19420`else
19421`ifdef CORE_7
19422 if (`PARGS.nas_check_on) begin
19423 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
19424 tid = 5
19425; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19426 end
19427`endif
19428
19429`endif
19430
19431`endif
19432
19433 end
19434 endtask
19435
19436
19437 task slam_ZeroTsbConfig1_core7_thread6;
19438 input [63:0] value;
19439 reg [5:0] tid;
19440 integer junk;
19441
19442 begin
19443`ifdef AXIS_EMUL_COSIM
19444//Do Nothing
19445`else
19446`ifdef GATESIM
19447//Do Nothing
19448`else
19449`ifdef CORE_7
19450 if (`PARGS.nas_check_on) begin
19451 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
19452 tid = 6
19453; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19454 end
19455`endif
19456
19457`endif
19458
19459`endif
19460
19461 end
19462 endtask
19463
19464
19465 task slam_ZeroTsbConfig1_core7_thread7;
19466 input [63:0] value;
19467 reg [5:0] tid;
19468 integer junk;
19469
19470 begin
19471`ifdef AXIS_EMUL_COSIM
19472//Do Nothing
19473`else
19474`ifdef GATESIM
19475//Do Nothing
19476`else
19477`ifdef CORE_7
19478 if (`PARGS.nas_check_on) begin
19479 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
19480 tid = 7
19481; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h18, value);
19482 end
19483`endif
19484
19485`endif
19486
19487`endif
19488
19489 end
19490 endtask
19491
19492
19493 task slam_ZeroTsbConfig2_core0_thread0;
19494 input [63:0] value;
19495 reg [5:0] tid;
19496 integer junk;
19497
19498 begin
19499`ifdef AXIS_EMUL_COSIM
19500//Do Nothing
19501`else
19502`ifdef GATESIM
19503//Do Nothing
19504`else
19505`ifdef CORE_0
19506 if (`PARGS.nas_check_on) begin
19507 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
19508 tid = 0
19509; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19510 end
19511`endif
19512
19513`endif
19514
19515`endif
19516
19517 end
19518 endtask
19519
19520
19521 task slam_ZeroTsbConfig2_core0_thread1;
19522 input [63:0] value;
19523 reg [5:0] tid;
19524 integer junk;
19525
19526 begin
19527`ifdef AXIS_EMUL_COSIM
19528//Do Nothing
19529`else
19530`ifdef GATESIM
19531//Do Nothing
19532`else
19533`ifdef CORE_0
19534 if (`PARGS.nas_check_on) begin
19535 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
19536 tid = 1
19537; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19538 end
19539`endif
19540
19541`endif
19542
19543`endif
19544
19545 end
19546 endtask
19547
19548
19549 task slam_ZeroTsbConfig2_core0_thread2;
19550 input [63:0] value;
19551 reg [5:0] tid;
19552 integer junk;
19553
19554 begin
19555`ifdef AXIS_EMUL_COSIM
19556//Do Nothing
19557`else
19558`ifdef GATESIM
19559//Do Nothing
19560`else
19561`ifdef CORE_0
19562 if (`PARGS.nas_check_on) begin
19563 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
19564 tid = 2
19565; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19566 end
19567`endif
19568
19569`endif
19570
19571`endif
19572
19573 end
19574 endtask
19575
19576
19577 task slam_ZeroTsbConfig2_core0_thread3;
19578 input [63:0] value;
19579 reg [5:0] tid;
19580 integer junk;
19581
19582 begin
19583`ifdef AXIS_EMUL_COSIM
19584//Do Nothing
19585`else
19586`ifdef GATESIM
19587//Do Nothing
19588`else
19589`ifdef CORE_0
19590 if (`PARGS.nas_check_on) begin
19591 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
19592 tid = 3
19593; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19594 end
19595`endif
19596
19597`endif
19598
19599`endif
19600
19601 end
19602 endtask
19603
19604
19605 task slam_ZeroTsbConfig2_core0_thread4;
19606 input [63:0] value;
19607 reg [5:0] tid;
19608 integer junk;
19609
19610 begin
19611`ifdef AXIS_EMUL_COSIM
19612//Do Nothing
19613`else
19614`ifdef GATESIM
19615//Do Nothing
19616`else
19617`ifdef CORE_0
19618 if (`PARGS.nas_check_on) begin
19619 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
19620 tid = 4
19621; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19622 end
19623`endif
19624
19625`endif
19626
19627`endif
19628
19629 end
19630 endtask
19631
19632
19633 task slam_ZeroTsbConfig2_core0_thread5;
19634 input [63:0] value;
19635 reg [5:0] tid;
19636 integer junk;
19637
19638 begin
19639`ifdef AXIS_EMUL_COSIM
19640//Do Nothing
19641`else
19642`ifdef GATESIM
19643//Do Nothing
19644`else
19645`ifdef CORE_0
19646 if (`PARGS.nas_check_on) begin
19647 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
19648 tid = 5
19649; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19650 end
19651`endif
19652
19653`endif
19654
19655`endif
19656
19657 end
19658 endtask
19659
19660
19661 task slam_ZeroTsbConfig2_core0_thread6;
19662 input [63:0] value;
19663 reg [5:0] tid;
19664 integer junk;
19665
19666 begin
19667`ifdef AXIS_EMUL_COSIM
19668//Do Nothing
19669`else
19670`ifdef GATESIM
19671//Do Nothing
19672`else
19673`ifdef CORE_0
19674 if (`PARGS.nas_check_on) begin
19675 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
19676 tid = 6
19677; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19678 end
19679`endif
19680
19681`endif
19682
19683`endif
19684
19685 end
19686 endtask
19687
19688
19689 task slam_ZeroTsbConfig2_core0_thread7;
19690 input [63:0] value;
19691 reg [5:0] tid;
19692 integer junk;
19693
19694 begin
19695`ifdef AXIS_EMUL_COSIM
19696//Do Nothing
19697`else
19698`ifdef GATESIM
19699//Do Nothing
19700`else
19701`ifdef CORE_0
19702 if (`PARGS.nas_check_on) begin
19703 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
19704 tid = 7
19705; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19706 end
19707`endif
19708
19709`endif
19710
19711`endif
19712
19713 end
19714 endtask
19715
19716
19717 task slam_ZeroTsbConfig2_core1_thread0;
19718 input [63:0] value;
19719 reg [5:0] tid;
19720 integer junk;
19721
19722 begin
19723`ifdef AXIS_EMUL_COSIM
19724//Do Nothing
19725`else
19726`ifdef GATESIM
19727//Do Nothing
19728`else
19729`ifdef CORE_1
19730 if (`PARGS.nas_check_on) begin
19731 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
19732 tid = 0
19733; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19734 end
19735`endif
19736
19737`endif
19738
19739`endif
19740
19741 end
19742 endtask
19743
19744
19745 task slam_ZeroTsbConfig2_core1_thread1;
19746 input [63:0] value;
19747 reg [5:0] tid;
19748 integer junk;
19749
19750 begin
19751`ifdef AXIS_EMUL_COSIM
19752//Do Nothing
19753`else
19754`ifdef GATESIM
19755//Do Nothing
19756`else
19757`ifdef CORE_1
19758 if (`PARGS.nas_check_on) begin
19759 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
19760 tid = 1
19761; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19762 end
19763`endif
19764
19765`endif
19766
19767`endif
19768
19769 end
19770 endtask
19771
19772
19773 task slam_ZeroTsbConfig2_core1_thread2;
19774 input [63:0] value;
19775 reg [5:0] tid;
19776 integer junk;
19777
19778 begin
19779`ifdef AXIS_EMUL_COSIM
19780//Do Nothing
19781`else
19782`ifdef GATESIM
19783//Do Nothing
19784`else
19785`ifdef CORE_1
19786 if (`PARGS.nas_check_on) begin
19787 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
19788 tid = 2
19789; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19790 end
19791`endif
19792
19793`endif
19794
19795`endif
19796
19797 end
19798 endtask
19799
19800
19801 task slam_ZeroTsbConfig2_core1_thread3;
19802 input [63:0] value;
19803 reg [5:0] tid;
19804 integer junk;
19805
19806 begin
19807`ifdef AXIS_EMUL_COSIM
19808//Do Nothing
19809`else
19810`ifdef GATESIM
19811//Do Nothing
19812`else
19813`ifdef CORE_1
19814 if (`PARGS.nas_check_on) begin
19815 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
19816 tid = 3
19817; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19818 end
19819`endif
19820
19821`endif
19822
19823`endif
19824
19825 end
19826 endtask
19827
19828
19829 task slam_ZeroTsbConfig2_core1_thread4;
19830 input [63:0] value;
19831 reg [5:0] tid;
19832 integer junk;
19833
19834 begin
19835`ifdef AXIS_EMUL_COSIM
19836//Do Nothing
19837`else
19838`ifdef GATESIM
19839//Do Nothing
19840`else
19841`ifdef CORE_1
19842 if (`PARGS.nas_check_on) begin
19843 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
19844 tid = 4
19845; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19846 end
19847`endif
19848
19849`endif
19850
19851`endif
19852
19853 end
19854 endtask
19855
19856
19857 task slam_ZeroTsbConfig2_core1_thread5;
19858 input [63:0] value;
19859 reg [5:0] tid;
19860 integer junk;
19861
19862 begin
19863`ifdef AXIS_EMUL_COSIM
19864//Do Nothing
19865`else
19866`ifdef GATESIM
19867//Do Nothing
19868`else
19869`ifdef CORE_1
19870 if (`PARGS.nas_check_on) begin
19871 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
19872 tid = 5
19873; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19874 end
19875`endif
19876
19877`endif
19878
19879`endif
19880
19881 end
19882 endtask
19883
19884
19885 task slam_ZeroTsbConfig2_core1_thread6;
19886 input [63:0] value;
19887 reg [5:0] tid;
19888 integer junk;
19889
19890 begin
19891`ifdef AXIS_EMUL_COSIM
19892//Do Nothing
19893`else
19894`ifdef GATESIM
19895//Do Nothing
19896`else
19897`ifdef CORE_1
19898 if (`PARGS.nas_check_on) begin
19899 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
19900 tid = 6
19901; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19902 end
19903`endif
19904
19905`endif
19906
19907`endif
19908
19909 end
19910 endtask
19911
19912
19913 task slam_ZeroTsbConfig2_core1_thread7;
19914 input [63:0] value;
19915 reg [5:0] tid;
19916 integer junk;
19917
19918 begin
19919`ifdef AXIS_EMUL_COSIM
19920//Do Nothing
19921`else
19922`ifdef GATESIM
19923//Do Nothing
19924`else
19925`ifdef CORE_1
19926 if (`PARGS.nas_check_on) begin
19927 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
19928 tid = 7
19929; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19930 end
19931`endif
19932
19933`endif
19934
19935`endif
19936
19937 end
19938 endtask
19939
19940
19941 task slam_ZeroTsbConfig2_core2_thread0;
19942 input [63:0] value;
19943 reg [5:0] tid;
19944 integer junk;
19945
19946 begin
19947`ifdef AXIS_EMUL_COSIM
19948//Do Nothing
19949`else
19950`ifdef GATESIM
19951//Do Nothing
19952`else
19953`ifdef CORE_2
19954 if (`PARGS.nas_check_on) begin
19955 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
19956 tid = 0
19957; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19958 end
19959`endif
19960
19961`endif
19962
19963`endif
19964
19965 end
19966 endtask
19967
19968
19969 task slam_ZeroTsbConfig2_core2_thread1;
19970 input [63:0] value;
19971 reg [5:0] tid;
19972 integer junk;
19973
19974 begin
19975`ifdef AXIS_EMUL_COSIM
19976//Do Nothing
19977`else
19978`ifdef GATESIM
19979//Do Nothing
19980`else
19981`ifdef CORE_2
19982 if (`PARGS.nas_check_on) begin
19983 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
19984 tid = 1
19985; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
19986 end
19987`endif
19988
19989`endif
19990
19991`endif
19992
19993 end
19994 endtask
19995
19996
19997 task slam_ZeroTsbConfig2_core2_thread2;
19998 input [63:0] value;
19999 reg [5:0] tid;
20000 integer junk;
20001
20002 begin
20003`ifdef AXIS_EMUL_COSIM
20004//Do Nothing
20005`else
20006`ifdef GATESIM
20007//Do Nothing
20008`else
20009`ifdef CORE_2
20010 if (`PARGS.nas_check_on) begin
20011 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
20012 tid = 2
20013; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20014 end
20015`endif
20016
20017`endif
20018
20019`endif
20020
20021 end
20022 endtask
20023
20024
20025 task slam_ZeroTsbConfig2_core2_thread3;
20026 input [63:0] value;
20027 reg [5:0] tid;
20028 integer junk;
20029
20030 begin
20031`ifdef AXIS_EMUL_COSIM
20032//Do Nothing
20033`else
20034`ifdef GATESIM
20035//Do Nothing
20036`else
20037`ifdef CORE_2
20038 if (`PARGS.nas_check_on) begin
20039 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
20040 tid = 3
20041; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20042 end
20043`endif
20044
20045`endif
20046
20047`endif
20048
20049 end
20050 endtask
20051
20052
20053 task slam_ZeroTsbConfig2_core2_thread4;
20054 input [63:0] value;
20055 reg [5:0] tid;
20056 integer junk;
20057
20058 begin
20059`ifdef AXIS_EMUL_COSIM
20060//Do Nothing
20061`else
20062`ifdef GATESIM
20063//Do Nothing
20064`else
20065`ifdef CORE_2
20066 if (`PARGS.nas_check_on) begin
20067 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
20068 tid = 4
20069; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20070 end
20071`endif
20072
20073`endif
20074
20075`endif
20076
20077 end
20078 endtask
20079
20080
20081 task slam_ZeroTsbConfig2_core2_thread5;
20082 input [63:0] value;
20083 reg [5:0] tid;
20084 integer junk;
20085
20086 begin
20087`ifdef AXIS_EMUL_COSIM
20088//Do Nothing
20089`else
20090`ifdef GATESIM
20091//Do Nothing
20092`else
20093`ifdef CORE_2
20094 if (`PARGS.nas_check_on) begin
20095 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
20096 tid = 5
20097; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20098 end
20099`endif
20100
20101`endif
20102
20103`endif
20104
20105 end
20106 endtask
20107
20108
20109 task slam_ZeroTsbConfig2_core2_thread6;
20110 input [63:0] value;
20111 reg [5:0] tid;
20112 integer junk;
20113
20114 begin
20115`ifdef AXIS_EMUL_COSIM
20116//Do Nothing
20117`else
20118`ifdef GATESIM
20119//Do Nothing
20120`else
20121`ifdef CORE_2
20122 if (`PARGS.nas_check_on) begin
20123 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
20124 tid = 6
20125; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20126 end
20127`endif
20128
20129`endif
20130
20131`endif
20132
20133 end
20134 endtask
20135
20136
20137 task slam_ZeroTsbConfig2_core2_thread7;
20138 input [63:0] value;
20139 reg [5:0] tid;
20140 integer junk;
20141
20142 begin
20143`ifdef AXIS_EMUL_COSIM
20144//Do Nothing
20145`else
20146`ifdef GATESIM
20147//Do Nothing
20148`else
20149`ifdef CORE_2
20150 if (`PARGS.nas_check_on) begin
20151 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
20152 tid = 7
20153; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20154 end
20155`endif
20156
20157`endif
20158
20159`endif
20160
20161 end
20162 endtask
20163
20164
20165 task slam_ZeroTsbConfig2_core3_thread0;
20166 input [63:0] value;
20167 reg [5:0] tid;
20168 integer junk;
20169
20170 begin
20171`ifdef AXIS_EMUL_COSIM
20172//Do Nothing
20173`else
20174`ifdef GATESIM
20175//Do Nothing
20176`else
20177`ifdef CORE_3
20178 if (`PARGS.nas_check_on) begin
20179 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
20180 tid = 0
20181; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20182 end
20183`endif
20184
20185`endif
20186
20187`endif
20188
20189 end
20190 endtask
20191
20192
20193 task slam_ZeroTsbConfig2_core3_thread1;
20194 input [63:0] value;
20195 reg [5:0] tid;
20196 integer junk;
20197
20198 begin
20199`ifdef AXIS_EMUL_COSIM
20200//Do Nothing
20201`else
20202`ifdef GATESIM
20203//Do Nothing
20204`else
20205`ifdef CORE_3
20206 if (`PARGS.nas_check_on) begin
20207 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
20208 tid = 1
20209; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20210 end
20211`endif
20212
20213`endif
20214
20215`endif
20216
20217 end
20218 endtask
20219
20220
20221 task slam_ZeroTsbConfig2_core3_thread2;
20222 input [63:0] value;
20223 reg [5:0] tid;
20224 integer junk;
20225
20226 begin
20227`ifdef AXIS_EMUL_COSIM
20228//Do Nothing
20229`else
20230`ifdef GATESIM
20231//Do Nothing
20232`else
20233`ifdef CORE_3
20234 if (`PARGS.nas_check_on) begin
20235 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
20236 tid = 2
20237; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20238 end
20239`endif
20240
20241`endif
20242
20243`endif
20244
20245 end
20246 endtask
20247
20248
20249 task slam_ZeroTsbConfig2_core3_thread3;
20250 input [63:0] value;
20251 reg [5:0] tid;
20252 integer junk;
20253
20254 begin
20255`ifdef AXIS_EMUL_COSIM
20256//Do Nothing
20257`else
20258`ifdef GATESIM
20259//Do Nothing
20260`else
20261`ifdef CORE_3
20262 if (`PARGS.nas_check_on) begin
20263 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
20264 tid = 3
20265; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20266 end
20267`endif
20268
20269`endif
20270
20271`endif
20272
20273 end
20274 endtask
20275
20276
20277 task slam_ZeroTsbConfig2_core3_thread4;
20278 input [63:0] value;
20279 reg [5:0] tid;
20280 integer junk;
20281
20282 begin
20283`ifdef AXIS_EMUL_COSIM
20284//Do Nothing
20285`else
20286`ifdef GATESIM
20287//Do Nothing
20288`else
20289`ifdef CORE_3
20290 if (`PARGS.nas_check_on) begin
20291 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
20292 tid = 4
20293; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20294 end
20295`endif
20296
20297`endif
20298
20299`endif
20300
20301 end
20302 endtask
20303
20304
20305 task slam_ZeroTsbConfig2_core3_thread5;
20306 input [63:0] value;
20307 reg [5:0] tid;
20308 integer junk;
20309
20310 begin
20311`ifdef AXIS_EMUL_COSIM
20312//Do Nothing
20313`else
20314`ifdef GATESIM
20315//Do Nothing
20316`else
20317`ifdef CORE_3
20318 if (`PARGS.nas_check_on) begin
20319 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
20320 tid = 5
20321; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20322 end
20323`endif
20324
20325`endif
20326
20327`endif
20328
20329 end
20330 endtask
20331
20332
20333 task slam_ZeroTsbConfig2_core3_thread6;
20334 input [63:0] value;
20335 reg [5:0] tid;
20336 integer junk;
20337
20338 begin
20339`ifdef AXIS_EMUL_COSIM
20340//Do Nothing
20341`else
20342`ifdef GATESIM
20343//Do Nothing
20344`else
20345`ifdef CORE_3
20346 if (`PARGS.nas_check_on) begin
20347 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
20348 tid = 6
20349; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20350 end
20351`endif
20352
20353`endif
20354
20355`endif
20356
20357 end
20358 endtask
20359
20360
20361 task slam_ZeroTsbConfig2_core3_thread7;
20362 input [63:0] value;
20363 reg [5:0] tid;
20364 integer junk;
20365
20366 begin
20367`ifdef AXIS_EMUL_COSIM
20368//Do Nothing
20369`else
20370`ifdef GATESIM
20371//Do Nothing
20372`else
20373`ifdef CORE_3
20374 if (`PARGS.nas_check_on) begin
20375 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
20376 tid = 7
20377; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20378 end
20379`endif
20380
20381`endif
20382
20383`endif
20384
20385 end
20386 endtask
20387
20388
20389 task slam_ZeroTsbConfig2_core4_thread0;
20390 input [63:0] value;
20391 reg [5:0] tid;
20392 integer junk;
20393
20394 begin
20395`ifdef AXIS_EMUL_COSIM
20396//Do Nothing
20397`else
20398`ifdef GATESIM
20399//Do Nothing
20400`else
20401`ifdef CORE_4
20402 if (`PARGS.nas_check_on) begin
20403 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
20404 tid = 0
20405; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20406 end
20407`endif
20408
20409`endif
20410
20411`endif
20412
20413 end
20414 endtask
20415
20416
20417 task slam_ZeroTsbConfig2_core4_thread1;
20418 input [63:0] value;
20419 reg [5:0] tid;
20420 integer junk;
20421
20422 begin
20423`ifdef AXIS_EMUL_COSIM
20424//Do Nothing
20425`else
20426`ifdef GATESIM
20427//Do Nothing
20428`else
20429`ifdef CORE_4
20430 if (`PARGS.nas_check_on) begin
20431 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
20432 tid = 1
20433; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20434 end
20435`endif
20436
20437`endif
20438
20439`endif
20440
20441 end
20442 endtask
20443
20444
20445 task slam_ZeroTsbConfig2_core4_thread2;
20446 input [63:0] value;
20447 reg [5:0] tid;
20448 integer junk;
20449
20450 begin
20451`ifdef AXIS_EMUL_COSIM
20452//Do Nothing
20453`else
20454`ifdef GATESIM
20455//Do Nothing
20456`else
20457`ifdef CORE_4
20458 if (`PARGS.nas_check_on) begin
20459 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
20460 tid = 2
20461; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20462 end
20463`endif
20464
20465`endif
20466
20467`endif
20468
20469 end
20470 endtask
20471
20472
20473 task slam_ZeroTsbConfig2_core4_thread3;
20474 input [63:0] value;
20475 reg [5:0] tid;
20476 integer junk;
20477
20478 begin
20479`ifdef AXIS_EMUL_COSIM
20480//Do Nothing
20481`else
20482`ifdef GATESIM
20483//Do Nothing
20484`else
20485`ifdef CORE_4
20486 if (`PARGS.nas_check_on) begin
20487 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
20488 tid = 3
20489; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20490 end
20491`endif
20492
20493`endif
20494
20495`endif
20496
20497 end
20498 endtask
20499
20500
20501 task slam_ZeroTsbConfig2_core4_thread4;
20502 input [63:0] value;
20503 reg [5:0] tid;
20504 integer junk;
20505
20506 begin
20507`ifdef AXIS_EMUL_COSIM
20508//Do Nothing
20509`else
20510`ifdef GATESIM
20511//Do Nothing
20512`else
20513`ifdef CORE_4
20514 if (`PARGS.nas_check_on) begin
20515 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
20516 tid = 4
20517; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20518 end
20519`endif
20520
20521`endif
20522
20523`endif
20524
20525 end
20526 endtask
20527
20528
20529 task slam_ZeroTsbConfig2_core4_thread5;
20530 input [63:0] value;
20531 reg [5:0] tid;
20532 integer junk;
20533
20534 begin
20535`ifdef AXIS_EMUL_COSIM
20536//Do Nothing
20537`else
20538`ifdef GATESIM
20539//Do Nothing
20540`else
20541`ifdef CORE_4
20542 if (`PARGS.nas_check_on) begin
20543 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
20544 tid = 5
20545; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20546 end
20547`endif
20548
20549`endif
20550
20551`endif
20552
20553 end
20554 endtask
20555
20556
20557 task slam_ZeroTsbConfig2_core4_thread6;
20558 input [63:0] value;
20559 reg [5:0] tid;
20560 integer junk;
20561
20562 begin
20563`ifdef AXIS_EMUL_COSIM
20564//Do Nothing
20565`else
20566`ifdef GATESIM
20567//Do Nothing
20568`else
20569`ifdef CORE_4
20570 if (`PARGS.nas_check_on) begin
20571 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
20572 tid = 6
20573; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20574 end
20575`endif
20576
20577`endif
20578
20579`endif
20580
20581 end
20582 endtask
20583
20584
20585 task slam_ZeroTsbConfig2_core4_thread7;
20586 input [63:0] value;
20587 reg [5:0] tid;
20588 integer junk;
20589
20590 begin
20591`ifdef AXIS_EMUL_COSIM
20592//Do Nothing
20593`else
20594`ifdef GATESIM
20595//Do Nothing
20596`else
20597`ifdef CORE_4
20598 if (`PARGS.nas_check_on) begin
20599 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
20600 tid = 7
20601; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20602 end
20603`endif
20604
20605`endif
20606
20607`endif
20608
20609 end
20610 endtask
20611
20612
20613 task slam_ZeroTsbConfig2_core5_thread0;
20614 input [63:0] value;
20615 reg [5:0] tid;
20616 integer junk;
20617
20618 begin
20619`ifdef AXIS_EMUL_COSIM
20620//Do Nothing
20621`else
20622`ifdef GATESIM
20623//Do Nothing
20624`else
20625`ifdef CORE_5
20626 if (`PARGS.nas_check_on) begin
20627 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
20628 tid = 0
20629; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20630 end
20631`endif
20632
20633`endif
20634
20635`endif
20636
20637 end
20638 endtask
20639
20640
20641 task slam_ZeroTsbConfig2_core5_thread1;
20642 input [63:0] value;
20643 reg [5:0] tid;
20644 integer junk;
20645
20646 begin
20647`ifdef AXIS_EMUL_COSIM
20648//Do Nothing
20649`else
20650`ifdef GATESIM
20651//Do Nothing
20652`else
20653`ifdef CORE_5
20654 if (`PARGS.nas_check_on) begin
20655 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
20656 tid = 1
20657; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20658 end
20659`endif
20660
20661`endif
20662
20663`endif
20664
20665 end
20666 endtask
20667
20668
20669 task slam_ZeroTsbConfig2_core5_thread2;
20670 input [63:0] value;
20671 reg [5:0] tid;
20672 integer junk;
20673
20674 begin
20675`ifdef AXIS_EMUL_COSIM
20676//Do Nothing
20677`else
20678`ifdef GATESIM
20679//Do Nothing
20680`else
20681`ifdef CORE_5
20682 if (`PARGS.nas_check_on) begin
20683 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
20684 tid = 2
20685; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20686 end
20687`endif
20688
20689`endif
20690
20691`endif
20692
20693 end
20694 endtask
20695
20696
20697 task slam_ZeroTsbConfig2_core5_thread3;
20698 input [63:0] value;
20699 reg [5:0] tid;
20700 integer junk;
20701
20702 begin
20703`ifdef AXIS_EMUL_COSIM
20704//Do Nothing
20705`else
20706`ifdef GATESIM
20707//Do Nothing
20708`else
20709`ifdef CORE_5
20710 if (`PARGS.nas_check_on) begin
20711 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
20712 tid = 3
20713; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20714 end
20715`endif
20716
20717`endif
20718
20719`endif
20720
20721 end
20722 endtask
20723
20724
20725 task slam_ZeroTsbConfig2_core5_thread4;
20726 input [63:0] value;
20727 reg [5:0] tid;
20728 integer junk;
20729
20730 begin
20731`ifdef AXIS_EMUL_COSIM
20732//Do Nothing
20733`else
20734`ifdef GATESIM
20735//Do Nothing
20736`else
20737`ifdef CORE_5
20738 if (`PARGS.nas_check_on) begin
20739 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
20740 tid = 4
20741; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20742 end
20743`endif
20744
20745`endif
20746
20747`endif
20748
20749 end
20750 endtask
20751
20752
20753 task slam_ZeroTsbConfig2_core5_thread5;
20754 input [63:0] value;
20755 reg [5:0] tid;
20756 integer junk;
20757
20758 begin
20759`ifdef AXIS_EMUL_COSIM
20760//Do Nothing
20761`else
20762`ifdef GATESIM
20763//Do Nothing
20764`else
20765`ifdef CORE_5
20766 if (`PARGS.nas_check_on) begin
20767 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
20768 tid = 5
20769; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20770 end
20771`endif
20772
20773`endif
20774
20775`endif
20776
20777 end
20778 endtask
20779
20780
20781 task slam_ZeroTsbConfig2_core5_thread6;
20782 input [63:0] value;
20783 reg [5:0] tid;
20784 integer junk;
20785
20786 begin
20787`ifdef AXIS_EMUL_COSIM
20788//Do Nothing
20789`else
20790`ifdef GATESIM
20791//Do Nothing
20792`else
20793`ifdef CORE_5
20794 if (`PARGS.nas_check_on) begin
20795 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
20796 tid = 6
20797; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20798 end
20799`endif
20800
20801`endif
20802
20803`endif
20804
20805 end
20806 endtask
20807
20808
20809 task slam_ZeroTsbConfig2_core5_thread7;
20810 input [63:0] value;
20811 reg [5:0] tid;
20812 integer junk;
20813
20814 begin
20815`ifdef AXIS_EMUL_COSIM
20816//Do Nothing
20817`else
20818`ifdef GATESIM
20819//Do Nothing
20820`else
20821`ifdef CORE_5
20822 if (`PARGS.nas_check_on) begin
20823 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
20824 tid = 7
20825; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20826 end
20827`endif
20828
20829`endif
20830
20831`endif
20832
20833 end
20834 endtask
20835
20836
20837 task slam_ZeroTsbConfig2_core6_thread0;
20838 input [63:0] value;
20839 reg [5:0] tid;
20840 integer junk;
20841
20842 begin
20843`ifdef AXIS_EMUL_COSIM
20844//Do Nothing
20845`else
20846`ifdef GATESIM
20847//Do Nothing
20848`else
20849`ifdef CORE_6
20850 if (`PARGS.nas_check_on) begin
20851 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
20852 tid = 0
20853; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20854 end
20855`endif
20856
20857`endif
20858
20859`endif
20860
20861 end
20862 endtask
20863
20864
20865 task slam_ZeroTsbConfig2_core6_thread1;
20866 input [63:0] value;
20867 reg [5:0] tid;
20868 integer junk;
20869
20870 begin
20871`ifdef AXIS_EMUL_COSIM
20872//Do Nothing
20873`else
20874`ifdef GATESIM
20875//Do Nothing
20876`else
20877`ifdef CORE_6
20878 if (`PARGS.nas_check_on) begin
20879 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
20880 tid = 1
20881; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20882 end
20883`endif
20884
20885`endif
20886
20887`endif
20888
20889 end
20890 endtask
20891
20892
20893 task slam_ZeroTsbConfig2_core6_thread2;
20894 input [63:0] value;
20895 reg [5:0] tid;
20896 integer junk;
20897
20898 begin
20899`ifdef AXIS_EMUL_COSIM
20900//Do Nothing
20901`else
20902`ifdef GATESIM
20903//Do Nothing
20904`else
20905`ifdef CORE_6
20906 if (`PARGS.nas_check_on) begin
20907 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
20908 tid = 2
20909; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20910 end
20911`endif
20912
20913`endif
20914
20915`endif
20916
20917 end
20918 endtask
20919
20920
20921 task slam_ZeroTsbConfig2_core6_thread3;
20922 input [63:0] value;
20923 reg [5:0] tid;
20924 integer junk;
20925
20926 begin
20927`ifdef AXIS_EMUL_COSIM
20928//Do Nothing
20929`else
20930`ifdef GATESIM
20931//Do Nothing
20932`else
20933`ifdef CORE_6
20934 if (`PARGS.nas_check_on) begin
20935 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
20936 tid = 3
20937; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20938 end
20939`endif
20940
20941`endif
20942
20943`endif
20944
20945 end
20946 endtask
20947
20948
20949 task slam_ZeroTsbConfig2_core6_thread4;
20950 input [63:0] value;
20951 reg [5:0] tid;
20952 integer junk;
20953
20954 begin
20955`ifdef AXIS_EMUL_COSIM
20956//Do Nothing
20957`else
20958`ifdef GATESIM
20959//Do Nothing
20960`else
20961`ifdef CORE_6
20962 if (`PARGS.nas_check_on) begin
20963 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
20964 tid = 4
20965; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20966 end
20967`endif
20968
20969`endif
20970
20971`endif
20972
20973 end
20974 endtask
20975
20976
20977 task slam_ZeroTsbConfig2_core6_thread5;
20978 input [63:0] value;
20979 reg [5:0] tid;
20980 integer junk;
20981
20982 begin
20983`ifdef AXIS_EMUL_COSIM
20984//Do Nothing
20985`else
20986`ifdef GATESIM
20987//Do Nothing
20988`else
20989`ifdef CORE_6
20990 if (`PARGS.nas_check_on) begin
20991 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
20992 tid = 5
20993; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
20994 end
20995`endif
20996
20997`endif
20998
20999`endif
21000
21001 end
21002 endtask
21003
21004
21005 task slam_ZeroTsbConfig2_core6_thread6;
21006 input [63:0] value;
21007 reg [5:0] tid;
21008 integer junk;
21009
21010 begin
21011`ifdef AXIS_EMUL_COSIM
21012//Do Nothing
21013`else
21014`ifdef GATESIM
21015//Do Nothing
21016`else
21017`ifdef CORE_6
21018 if (`PARGS.nas_check_on) begin
21019 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
21020 tid = 6
21021; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21022 end
21023`endif
21024
21025`endif
21026
21027`endif
21028
21029 end
21030 endtask
21031
21032
21033 task slam_ZeroTsbConfig2_core6_thread7;
21034 input [63:0] value;
21035 reg [5:0] tid;
21036 integer junk;
21037
21038 begin
21039`ifdef AXIS_EMUL_COSIM
21040//Do Nothing
21041`else
21042`ifdef GATESIM
21043//Do Nothing
21044`else
21045`ifdef CORE_6
21046 if (`PARGS.nas_check_on) begin
21047 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
21048 tid = 7
21049; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21050 end
21051`endif
21052
21053`endif
21054
21055`endif
21056
21057 end
21058 endtask
21059
21060
21061 task slam_ZeroTsbConfig2_core7_thread0;
21062 input [63:0] value;
21063 reg [5:0] tid;
21064 integer junk;
21065
21066 begin
21067`ifdef AXIS_EMUL_COSIM
21068//Do Nothing
21069`else
21070`ifdef GATESIM
21071//Do Nothing
21072`else
21073`ifdef CORE_7
21074 if (`PARGS.nas_check_on) begin
21075 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
21076 tid = 0
21077; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21078 end
21079`endif
21080
21081`endif
21082
21083`endif
21084
21085 end
21086 endtask
21087
21088
21089 task slam_ZeroTsbConfig2_core7_thread1;
21090 input [63:0] value;
21091 reg [5:0] tid;
21092 integer junk;
21093
21094 begin
21095`ifdef AXIS_EMUL_COSIM
21096//Do Nothing
21097`else
21098`ifdef GATESIM
21099//Do Nothing
21100`else
21101`ifdef CORE_7
21102 if (`PARGS.nas_check_on) begin
21103 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
21104 tid = 1
21105; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21106 end
21107`endif
21108
21109`endif
21110
21111`endif
21112
21113 end
21114 endtask
21115
21116
21117 task slam_ZeroTsbConfig2_core7_thread2;
21118 input [63:0] value;
21119 reg [5:0] tid;
21120 integer junk;
21121
21122 begin
21123`ifdef AXIS_EMUL_COSIM
21124//Do Nothing
21125`else
21126`ifdef GATESIM
21127//Do Nothing
21128`else
21129`ifdef CORE_7
21130 if (`PARGS.nas_check_on) begin
21131 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
21132 tid = 2
21133; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21134 end
21135`endif
21136
21137`endif
21138
21139`endif
21140
21141 end
21142 endtask
21143
21144
21145 task slam_ZeroTsbConfig2_core7_thread3;
21146 input [63:0] value;
21147 reg [5:0] tid;
21148 integer junk;
21149
21150 begin
21151`ifdef AXIS_EMUL_COSIM
21152//Do Nothing
21153`else
21154`ifdef GATESIM
21155//Do Nothing
21156`else
21157`ifdef CORE_7
21158 if (`PARGS.nas_check_on) begin
21159 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
21160 tid = 3
21161; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21162 end
21163`endif
21164
21165`endif
21166
21167`endif
21168
21169 end
21170 endtask
21171
21172
21173 task slam_ZeroTsbConfig2_core7_thread4;
21174 input [63:0] value;
21175 reg [5:0] tid;
21176 integer junk;
21177
21178 begin
21179`ifdef AXIS_EMUL_COSIM
21180//Do Nothing
21181`else
21182`ifdef GATESIM
21183//Do Nothing
21184`else
21185`ifdef CORE_7
21186 if (`PARGS.nas_check_on) begin
21187 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
21188 tid = 4
21189; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21190 end
21191`endif
21192
21193`endif
21194
21195`endif
21196
21197 end
21198 endtask
21199
21200
21201 task slam_ZeroTsbConfig2_core7_thread5;
21202 input [63:0] value;
21203 reg [5:0] tid;
21204 integer junk;
21205
21206 begin
21207`ifdef AXIS_EMUL_COSIM
21208//Do Nothing
21209`else
21210`ifdef GATESIM
21211//Do Nothing
21212`else
21213`ifdef CORE_7
21214 if (`PARGS.nas_check_on) begin
21215 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
21216 tid = 5
21217; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21218 end
21219`endif
21220
21221`endif
21222
21223`endif
21224
21225 end
21226 endtask
21227
21228
21229 task slam_ZeroTsbConfig2_core7_thread6;
21230 input [63:0] value;
21231 reg [5:0] tid;
21232 integer junk;
21233
21234 begin
21235`ifdef AXIS_EMUL_COSIM
21236//Do Nothing
21237`else
21238`ifdef GATESIM
21239//Do Nothing
21240`else
21241`ifdef CORE_7
21242 if (`PARGS.nas_check_on) begin
21243 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
21244 tid = 6
21245; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21246 end
21247`endif
21248
21249`endif
21250
21251`endif
21252
21253 end
21254 endtask
21255
21256
21257 task slam_ZeroTsbConfig2_core7_thread7;
21258 input [63:0] value;
21259 reg [5:0] tid;
21260 integer junk;
21261
21262 begin
21263`ifdef AXIS_EMUL_COSIM
21264//Do Nothing
21265`else
21266`ifdef GATESIM
21267//Do Nothing
21268`else
21269`ifdef CORE_7
21270 if (`PARGS.nas_check_on) begin
21271 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
21272 tid = 7
21273; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h20, value);
21274 end
21275`endif
21276
21277`endif
21278
21279`endif
21280
21281 end
21282 endtask
21283
21284
21285 task slam_ZeroTsbConfig3_core0_thread0;
21286 input [63:0] value;
21287 reg [5:0] tid;
21288 integer junk;
21289
21290 begin
21291`ifdef AXIS_EMUL_COSIM
21292//Do Nothing
21293`else
21294`ifdef GATESIM
21295//Do Nothing
21296`else
21297`ifdef CORE_0
21298 if (`PARGS.nas_check_on) begin
21299 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
21300 tid = 0
21301; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21302 end
21303`endif
21304
21305`endif
21306
21307`endif
21308
21309 end
21310 endtask
21311
21312
21313 task slam_ZeroTsbConfig3_core0_thread1;
21314 input [63:0] value;
21315 reg [5:0] tid;
21316 integer junk;
21317
21318 begin
21319`ifdef AXIS_EMUL_COSIM
21320//Do Nothing
21321`else
21322`ifdef GATESIM
21323//Do Nothing
21324`else
21325`ifdef CORE_0
21326 if (`PARGS.nas_check_on) begin
21327 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
21328 tid = 1
21329; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21330 end
21331`endif
21332
21333`endif
21334
21335`endif
21336
21337 end
21338 endtask
21339
21340
21341 task slam_ZeroTsbConfig3_core0_thread2;
21342 input [63:0] value;
21343 reg [5:0] tid;
21344 integer junk;
21345
21346 begin
21347`ifdef AXIS_EMUL_COSIM
21348//Do Nothing
21349`else
21350`ifdef GATESIM
21351//Do Nothing
21352`else
21353`ifdef CORE_0
21354 if (`PARGS.nas_check_on) begin
21355 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
21356 tid = 2
21357; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21358 end
21359`endif
21360
21361`endif
21362
21363`endif
21364
21365 end
21366 endtask
21367
21368
21369 task slam_ZeroTsbConfig3_core0_thread3;
21370 input [63:0] value;
21371 reg [5:0] tid;
21372 integer junk;
21373
21374 begin
21375`ifdef AXIS_EMUL_COSIM
21376//Do Nothing
21377`else
21378`ifdef GATESIM
21379//Do Nothing
21380`else
21381`ifdef CORE_0
21382 if (`PARGS.nas_check_on) begin
21383 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
21384 tid = 3
21385; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21386 end
21387`endif
21388
21389`endif
21390
21391`endif
21392
21393 end
21394 endtask
21395
21396
21397 task slam_ZeroTsbConfig3_core0_thread4;
21398 input [63:0] value;
21399 reg [5:0] tid;
21400 integer junk;
21401
21402 begin
21403`ifdef AXIS_EMUL_COSIM
21404//Do Nothing
21405`else
21406`ifdef GATESIM
21407//Do Nothing
21408`else
21409`ifdef CORE_0
21410 if (`PARGS.nas_check_on) begin
21411 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
21412 tid = 4
21413; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21414 end
21415`endif
21416
21417`endif
21418
21419`endif
21420
21421 end
21422 endtask
21423
21424
21425 task slam_ZeroTsbConfig3_core0_thread5;
21426 input [63:0] value;
21427 reg [5:0] tid;
21428 integer junk;
21429
21430 begin
21431`ifdef AXIS_EMUL_COSIM
21432//Do Nothing
21433`else
21434`ifdef GATESIM
21435//Do Nothing
21436`else
21437`ifdef CORE_0
21438 if (`PARGS.nas_check_on) begin
21439 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
21440 tid = 5
21441; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21442 end
21443`endif
21444
21445`endif
21446
21447`endif
21448
21449 end
21450 endtask
21451
21452
21453 task slam_ZeroTsbConfig3_core0_thread6;
21454 input [63:0] value;
21455 reg [5:0] tid;
21456 integer junk;
21457
21458 begin
21459`ifdef AXIS_EMUL_COSIM
21460//Do Nothing
21461`else
21462`ifdef GATESIM
21463//Do Nothing
21464`else
21465`ifdef CORE_0
21466 if (`PARGS.nas_check_on) begin
21467 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
21468 tid = 6
21469; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21470 end
21471`endif
21472
21473`endif
21474
21475`endif
21476
21477 end
21478 endtask
21479
21480
21481 task slam_ZeroTsbConfig3_core0_thread7;
21482 input [63:0] value;
21483 reg [5:0] tid;
21484 integer junk;
21485
21486 begin
21487`ifdef AXIS_EMUL_COSIM
21488//Do Nothing
21489`else
21490`ifdef GATESIM
21491//Do Nothing
21492`else
21493`ifdef CORE_0
21494 if (`PARGS.nas_check_on) begin
21495 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
21496 tid = 7
21497; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21498 end
21499`endif
21500
21501`endif
21502
21503`endif
21504
21505 end
21506 endtask
21507
21508
21509 task slam_ZeroTsbConfig3_core1_thread0;
21510 input [63:0] value;
21511 reg [5:0] tid;
21512 integer junk;
21513
21514 begin
21515`ifdef AXIS_EMUL_COSIM
21516//Do Nothing
21517`else
21518`ifdef GATESIM
21519//Do Nothing
21520`else
21521`ifdef CORE_1
21522 if (`PARGS.nas_check_on) begin
21523 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
21524 tid = 0
21525; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21526 end
21527`endif
21528
21529`endif
21530
21531`endif
21532
21533 end
21534 endtask
21535
21536
21537 task slam_ZeroTsbConfig3_core1_thread1;
21538 input [63:0] value;
21539 reg [5:0] tid;
21540 integer junk;
21541
21542 begin
21543`ifdef AXIS_EMUL_COSIM
21544//Do Nothing
21545`else
21546`ifdef GATESIM
21547//Do Nothing
21548`else
21549`ifdef CORE_1
21550 if (`PARGS.nas_check_on) begin
21551 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
21552 tid = 1
21553; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21554 end
21555`endif
21556
21557`endif
21558
21559`endif
21560
21561 end
21562 endtask
21563
21564
21565 task slam_ZeroTsbConfig3_core1_thread2;
21566 input [63:0] value;
21567 reg [5:0] tid;
21568 integer junk;
21569
21570 begin
21571`ifdef AXIS_EMUL_COSIM
21572//Do Nothing
21573`else
21574`ifdef GATESIM
21575//Do Nothing
21576`else
21577`ifdef CORE_1
21578 if (`PARGS.nas_check_on) begin
21579 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
21580 tid = 2
21581; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21582 end
21583`endif
21584
21585`endif
21586
21587`endif
21588
21589 end
21590 endtask
21591
21592
21593 task slam_ZeroTsbConfig3_core1_thread3;
21594 input [63:0] value;
21595 reg [5:0] tid;
21596 integer junk;
21597
21598 begin
21599`ifdef AXIS_EMUL_COSIM
21600//Do Nothing
21601`else
21602`ifdef GATESIM
21603//Do Nothing
21604`else
21605`ifdef CORE_1
21606 if (`PARGS.nas_check_on) begin
21607 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
21608 tid = 3
21609; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21610 end
21611`endif
21612
21613`endif
21614
21615`endif
21616
21617 end
21618 endtask
21619
21620
21621 task slam_ZeroTsbConfig3_core1_thread4;
21622 input [63:0] value;
21623 reg [5:0] tid;
21624 integer junk;
21625
21626 begin
21627`ifdef AXIS_EMUL_COSIM
21628//Do Nothing
21629`else
21630`ifdef GATESIM
21631//Do Nothing
21632`else
21633`ifdef CORE_1
21634 if (`PARGS.nas_check_on) begin
21635 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
21636 tid = 4
21637; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21638 end
21639`endif
21640
21641`endif
21642
21643`endif
21644
21645 end
21646 endtask
21647
21648
21649 task slam_ZeroTsbConfig3_core1_thread5;
21650 input [63:0] value;
21651 reg [5:0] tid;
21652 integer junk;
21653
21654 begin
21655`ifdef AXIS_EMUL_COSIM
21656//Do Nothing
21657`else
21658`ifdef GATESIM
21659//Do Nothing
21660`else
21661`ifdef CORE_1
21662 if (`PARGS.nas_check_on) begin
21663 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
21664 tid = 5
21665; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21666 end
21667`endif
21668
21669`endif
21670
21671`endif
21672
21673 end
21674 endtask
21675
21676
21677 task slam_ZeroTsbConfig3_core1_thread6;
21678 input [63:0] value;
21679 reg [5:0] tid;
21680 integer junk;
21681
21682 begin
21683`ifdef AXIS_EMUL_COSIM
21684//Do Nothing
21685`else
21686`ifdef GATESIM
21687//Do Nothing
21688`else
21689`ifdef CORE_1
21690 if (`PARGS.nas_check_on) begin
21691 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
21692 tid = 6
21693; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21694 end
21695`endif
21696
21697`endif
21698
21699`endif
21700
21701 end
21702 endtask
21703
21704
21705 task slam_ZeroTsbConfig3_core1_thread7;
21706 input [63:0] value;
21707 reg [5:0] tid;
21708 integer junk;
21709
21710 begin
21711`ifdef AXIS_EMUL_COSIM
21712//Do Nothing
21713`else
21714`ifdef GATESIM
21715//Do Nothing
21716`else
21717`ifdef CORE_1
21718 if (`PARGS.nas_check_on) begin
21719 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
21720 tid = 7
21721; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21722 end
21723`endif
21724
21725`endif
21726
21727`endif
21728
21729 end
21730 endtask
21731
21732
21733 task slam_ZeroTsbConfig3_core2_thread0;
21734 input [63:0] value;
21735 reg [5:0] tid;
21736 integer junk;
21737
21738 begin
21739`ifdef AXIS_EMUL_COSIM
21740//Do Nothing
21741`else
21742`ifdef GATESIM
21743//Do Nothing
21744`else
21745`ifdef CORE_2
21746 if (`PARGS.nas_check_on) begin
21747 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
21748 tid = 0
21749; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21750 end
21751`endif
21752
21753`endif
21754
21755`endif
21756
21757 end
21758 endtask
21759
21760
21761 task slam_ZeroTsbConfig3_core2_thread1;
21762 input [63:0] value;
21763 reg [5:0] tid;
21764 integer junk;
21765
21766 begin
21767`ifdef AXIS_EMUL_COSIM
21768//Do Nothing
21769`else
21770`ifdef GATESIM
21771//Do Nothing
21772`else
21773`ifdef CORE_2
21774 if (`PARGS.nas_check_on) begin
21775 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
21776 tid = 1
21777; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21778 end
21779`endif
21780
21781`endif
21782
21783`endif
21784
21785 end
21786 endtask
21787
21788
21789 task slam_ZeroTsbConfig3_core2_thread2;
21790 input [63:0] value;
21791 reg [5:0] tid;
21792 integer junk;
21793
21794 begin
21795`ifdef AXIS_EMUL_COSIM
21796//Do Nothing
21797`else
21798`ifdef GATESIM
21799//Do Nothing
21800`else
21801`ifdef CORE_2
21802 if (`PARGS.nas_check_on) begin
21803 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
21804 tid = 2
21805; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21806 end
21807`endif
21808
21809`endif
21810
21811`endif
21812
21813 end
21814 endtask
21815
21816
21817 task slam_ZeroTsbConfig3_core2_thread3;
21818 input [63:0] value;
21819 reg [5:0] tid;
21820 integer junk;
21821
21822 begin
21823`ifdef AXIS_EMUL_COSIM
21824//Do Nothing
21825`else
21826`ifdef GATESIM
21827//Do Nothing
21828`else
21829`ifdef CORE_2
21830 if (`PARGS.nas_check_on) begin
21831 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
21832 tid = 3
21833; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21834 end
21835`endif
21836
21837`endif
21838
21839`endif
21840
21841 end
21842 endtask
21843
21844
21845 task slam_ZeroTsbConfig3_core2_thread4;
21846 input [63:0] value;
21847 reg [5:0] tid;
21848 integer junk;
21849
21850 begin
21851`ifdef AXIS_EMUL_COSIM
21852//Do Nothing
21853`else
21854`ifdef GATESIM
21855//Do Nothing
21856`else
21857`ifdef CORE_2
21858 if (`PARGS.nas_check_on) begin
21859 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
21860 tid = 4
21861; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21862 end
21863`endif
21864
21865`endif
21866
21867`endif
21868
21869 end
21870 endtask
21871
21872
21873 task slam_ZeroTsbConfig3_core2_thread5;
21874 input [63:0] value;
21875 reg [5:0] tid;
21876 integer junk;
21877
21878 begin
21879`ifdef AXIS_EMUL_COSIM
21880//Do Nothing
21881`else
21882`ifdef GATESIM
21883//Do Nothing
21884`else
21885`ifdef CORE_2
21886 if (`PARGS.nas_check_on) begin
21887 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
21888 tid = 5
21889; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21890 end
21891`endif
21892
21893`endif
21894
21895`endif
21896
21897 end
21898 endtask
21899
21900
21901 task slam_ZeroTsbConfig3_core2_thread6;
21902 input [63:0] value;
21903 reg [5:0] tid;
21904 integer junk;
21905
21906 begin
21907`ifdef AXIS_EMUL_COSIM
21908//Do Nothing
21909`else
21910`ifdef GATESIM
21911//Do Nothing
21912`else
21913`ifdef CORE_2
21914 if (`PARGS.nas_check_on) begin
21915 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
21916 tid = 6
21917; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21918 end
21919`endif
21920
21921`endif
21922
21923`endif
21924
21925 end
21926 endtask
21927
21928
21929 task slam_ZeroTsbConfig3_core2_thread7;
21930 input [63:0] value;
21931 reg [5:0] tid;
21932 integer junk;
21933
21934 begin
21935`ifdef AXIS_EMUL_COSIM
21936//Do Nothing
21937`else
21938`ifdef GATESIM
21939//Do Nothing
21940`else
21941`ifdef CORE_2
21942 if (`PARGS.nas_check_on) begin
21943 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
21944 tid = 7
21945; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21946 end
21947`endif
21948
21949`endif
21950
21951`endif
21952
21953 end
21954 endtask
21955
21956
21957 task slam_ZeroTsbConfig3_core3_thread0;
21958 input [63:0] value;
21959 reg [5:0] tid;
21960 integer junk;
21961
21962 begin
21963`ifdef AXIS_EMUL_COSIM
21964//Do Nothing
21965`else
21966`ifdef GATESIM
21967//Do Nothing
21968`else
21969`ifdef CORE_3
21970 if (`PARGS.nas_check_on) begin
21971 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
21972 tid = 0
21973; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
21974 end
21975`endif
21976
21977`endif
21978
21979`endif
21980
21981 end
21982 endtask
21983
21984
21985 task slam_ZeroTsbConfig3_core3_thread1;
21986 input [63:0] value;
21987 reg [5:0] tid;
21988 integer junk;
21989
21990 begin
21991`ifdef AXIS_EMUL_COSIM
21992//Do Nothing
21993`else
21994`ifdef GATESIM
21995//Do Nothing
21996`else
21997`ifdef CORE_3
21998 if (`PARGS.nas_check_on) begin
21999 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
22000 tid = 1
22001; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22002 end
22003`endif
22004
22005`endif
22006
22007`endif
22008
22009 end
22010 endtask
22011
22012
22013 task slam_ZeroTsbConfig3_core3_thread2;
22014 input [63:0] value;
22015 reg [5:0] tid;
22016 integer junk;
22017
22018 begin
22019`ifdef AXIS_EMUL_COSIM
22020//Do Nothing
22021`else
22022`ifdef GATESIM
22023//Do Nothing
22024`else
22025`ifdef CORE_3
22026 if (`PARGS.nas_check_on) begin
22027 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
22028 tid = 2
22029; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22030 end
22031`endif
22032
22033`endif
22034
22035`endif
22036
22037 end
22038 endtask
22039
22040
22041 task slam_ZeroTsbConfig3_core3_thread3;
22042 input [63:0] value;
22043 reg [5:0] tid;
22044 integer junk;
22045
22046 begin
22047`ifdef AXIS_EMUL_COSIM
22048//Do Nothing
22049`else
22050`ifdef GATESIM
22051//Do Nothing
22052`else
22053`ifdef CORE_3
22054 if (`PARGS.nas_check_on) begin
22055 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
22056 tid = 3
22057; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22058 end
22059`endif
22060
22061`endif
22062
22063`endif
22064
22065 end
22066 endtask
22067
22068
22069 task slam_ZeroTsbConfig3_core3_thread4;
22070 input [63:0] value;
22071 reg [5:0] tid;
22072 integer junk;
22073
22074 begin
22075`ifdef AXIS_EMUL_COSIM
22076//Do Nothing
22077`else
22078`ifdef GATESIM
22079//Do Nothing
22080`else
22081`ifdef CORE_3
22082 if (`PARGS.nas_check_on) begin
22083 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
22084 tid = 4
22085; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22086 end
22087`endif
22088
22089`endif
22090
22091`endif
22092
22093 end
22094 endtask
22095
22096
22097 task slam_ZeroTsbConfig3_core3_thread5;
22098 input [63:0] value;
22099 reg [5:0] tid;
22100 integer junk;
22101
22102 begin
22103`ifdef AXIS_EMUL_COSIM
22104//Do Nothing
22105`else
22106`ifdef GATESIM
22107//Do Nothing
22108`else
22109`ifdef CORE_3
22110 if (`PARGS.nas_check_on) begin
22111 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
22112 tid = 5
22113; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22114 end
22115`endif
22116
22117`endif
22118
22119`endif
22120
22121 end
22122 endtask
22123
22124
22125 task slam_ZeroTsbConfig3_core3_thread6;
22126 input [63:0] value;
22127 reg [5:0] tid;
22128 integer junk;
22129
22130 begin
22131`ifdef AXIS_EMUL_COSIM
22132//Do Nothing
22133`else
22134`ifdef GATESIM
22135//Do Nothing
22136`else
22137`ifdef CORE_3
22138 if (`PARGS.nas_check_on) begin
22139 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
22140 tid = 6
22141; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22142 end
22143`endif
22144
22145`endif
22146
22147`endif
22148
22149 end
22150 endtask
22151
22152
22153 task slam_ZeroTsbConfig3_core3_thread7;
22154 input [63:0] value;
22155 reg [5:0] tid;
22156 integer junk;
22157
22158 begin
22159`ifdef AXIS_EMUL_COSIM
22160//Do Nothing
22161`else
22162`ifdef GATESIM
22163//Do Nothing
22164`else
22165`ifdef CORE_3
22166 if (`PARGS.nas_check_on) begin
22167 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
22168 tid = 7
22169; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22170 end
22171`endif
22172
22173`endif
22174
22175`endif
22176
22177 end
22178 endtask
22179
22180
22181 task slam_ZeroTsbConfig3_core4_thread0;
22182 input [63:0] value;
22183 reg [5:0] tid;
22184 integer junk;
22185
22186 begin
22187`ifdef AXIS_EMUL_COSIM
22188//Do Nothing
22189`else
22190`ifdef GATESIM
22191//Do Nothing
22192`else
22193`ifdef CORE_4
22194 if (`PARGS.nas_check_on) begin
22195 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
22196 tid = 0
22197; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22198 end
22199`endif
22200
22201`endif
22202
22203`endif
22204
22205 end
22206 endtask
22207
22208
22209 task slam_ZeroTsbConfig3_core4_thread1;
22210 input [63:0] value;
22211 reg [5:0] tid;
22212 integer junk;
22213
22214 begin
22215`ifdef AXIS_EMUL_COSIM
22216//Do Nothing
22217`else
22218`ifdef GATESIM
22219//Do Nothing
22220`else
22221`ifdef CORE_4
22222 if (`PARGS.nas_check_on) begin
22223 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
22224 tid = 1
22225; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22226 end
22227`endif
22228
22229`endif
22230
22231`endif
22232
22233 end
22234 endtask
22235
22236
22237 task slam_ZeroTsbConfig3_core4_thread2;
22238 input [63:0] value;
22239 reg [5:0] tid;
22240 integer junk;
22241
22242 begin
22243`ifdef AXIS_EMUL_COSIM
22244//Do Nothing
22245`else
22246`ifdef GATESIM
22247//Do Nothing
22248`else
22249`ifdef CORE_4
22250 if (`PARGS.nas_check_on) begin
22251 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
22252 tid = 2
22253; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22254 end
22255`endif
22256
22257`endif
22258
22259`endif
22260
22261 end
22262 endtask
22263
22264
22265 task slam_ZeroTsbConfig3_core4_thread3;
22266 input [63:0] value;
22267 reg [5:0] tid;
22268 integer junk;
22269
22270 begin
22271`ifdef AXIS_EMUL_COSIM
22272//Do Nothing
22273`else
22274`ifdef GATESIM
22275//Do Nothing
22276`else
22277`ifdef CORE_4
22278 if (`PARGS.nas_check_on) begin
22279 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
22280 tid = 3
22281; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22282 end
22283`endif
22284
22285`endif
22286
22287`endif
22288
22289 end
22290 endtask
22291
22292
22293 task slam_ZeroTsbConfig3_core4_thread4;
22294 input [63:0] value;
22295 reg [5:0] tid;
22296 integer junk;
22297
22298 begin
22299`ifdef AXIS_EMUL_COSIM
22300//Do Nothing
22301`else
22302`ifdef GATESIM
22303//Do Nothing
22304`else
22305`ifdef CORE_4
22306 if (`PARGS.nas_check_on) begin
22307 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
22308 tid = 4
22309; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22310 end
22311`endif
22312
22313`endif
22314
22315`endif
22316
22317 end
22318 endtask
22319
22320
22321 task slam_ZeroTsbConfig3_core4_thread5;
22322 input [63:0] value;
22323 reg [5:0] tid;
22324 integer junk;
22325
22326 begin
22327`ifdef AXIS_EMUL_COSIM
22328//Do Nothing
22329`else
22330`ifdef GATESIM
22331//Do Nothing
22332`else
22333`ifdef CORE_4
22334 if (`PARGS.nas_check_on) begin
22335 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
22336 tid = 5
22337; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22338 end
22339`endif
22340
22341`endif
22342
22343`endif
22344
22345 end
22346 endtask
22347
22348
22349 task slam_ZeroTsbConfig3_core4_thread6;
22350 input [63:0] value;
22351 reg [5:0] tid;
22352 integer junk;
22353
22354 begin
22355`ifdef AXIS_EMUL_COSIM
22356//Do Nothing
22357`else
22358`ifdef GATESIM
22359//Do Nothing
22360`else
22361`ifdef CORE_4
22362 if (`PARGS.nas_check_on) begin
22363 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
22364 tid = 6
22365; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22366 end
22367`endif
22368
22369`endif
22370
22371`endif
22372
22373 end
22374 endtask
22375
22376
22377 task slam_ZeroTsbConfig3_core4_thread7;
22378 input [63:0] value;
22379 reg [5:0] tid;
22380 integer junk;
22381
22382 begin
22383`ifdef AXIS_EMUL_COSIM
22384//Do Nothing
22385`else
22386`ifdef GATESIM
22387//Do Nothing
22388`else
22389`ifdef CORE_4
22390 if (`PARGS.nas_check_on) begin
22391 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
22392 tid = 7
22393; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22394 end
22395`endif
22396
22397`endif
22398
22399`endif
22400
22401 end
22402 endtask
22403
22404
22405 task slam_ZeroTsbConfig3_core5_thread0;
22406 input [63:0] value;
22407 reg [5:0] tid;
22408 integer junk;
22409
22410 begin
22411`ifdef AXIS_EMUL_COSIM
22412//Do Nothing
22413`else
22414`ifdef GATESIM
22415//Do Nothing
22416`else
22417`ifdef CORE_5
22418 if (`PARGS.nas_check_on) begin
22419 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
22420 tid = 0
22421; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22422 end
22423`endif
22424
22425`endif
22426
22427`endif
22428
22429 end
22430 endtask
22431
22432
22433 task slam_ZeroTsbConfig3_core5_thread1;
22434 input [63:0] value;
22435 reg [5:0] tid;
22436 integer junk;
22437
22438 begin
22439`ifdef AXIS_EMUL_COSIM
22440//Do Nothing
22441`else
22442`ifdef GATESIM
22443//Do Nothing
22444`else
22445`ifdef CORE_5
22446 if (`PARGS.nas_check_on) begin
22447 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
22448 tid = 1
22449; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22450 end
22451`endif
22452
22453`endif
22454
22455`endif
22456
22457 end
22458 endtask
22459
22460
22461 task slam_ZeroTsbConfig3_core5_thread2;
22462 input [63:0] value;
22463 reg [5:0] tid;
22464 integer junk;
22465
22466 begin
22467`ifdef AXIS_EMUL_COSIM
22468//Do Nothing
22469`else
22470`ifdef GATESIM
22471//Do Nothing
22472`else
22473`ifdef CORE_5
22474 if (`PARGS.nas_check_on) begin
22475 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
22476 tid = 2
22477; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22478 end
22479`endif
22480
22481`endif
22482
22483`endif
22484
22485 end
22486 endtask
22487
22488
22489 task slam_ZeroTsbConfig3_core5_thread3;
22490 input [63:0] value;
22491 reg [5:0] tid;
22492 integer junk;
22493
22494 begin
22495`ifdef AXIS_EMUL_COSIM
22496//Do Nothing
22497`else
22498`ifdef GATESIM
22499//Do Nothing
22500`else
22501`ifdef CORE_5
22502 if (`PARGS.nas_check_on) begin
22503 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
22504 tid = 3
22505; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22506 end
22507`endif
22508
22509`endif
22510
22511`endif
22512
22513 end
22514 endtask
22515
22516
22517 task slam_ZeroTsbConfig3_core5_thread4;
22518 input [63:0] value;
22519 reg [5:0] tid;
22520 integer junk;
22521
22522 begin
22523`ifdef AXIS_EMUL_COSIM
22524//Do Nothing
22525`else
22526`ifdef GATESIM
22527//Do Nothing
22528`else
22529`ifdef CORE_5
22530 if (`PARGS.nas_check_on) begin
22531 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
22532 tid = 4
22533; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22534 end
22535`endif
22536
22537`endif
22538
22539`endif
22540
22541 end
22542 endtask
22543
22544
22545 task slam_ZeroTsbConfig3_core5_thread5;
22546 input [63:0] value;
22547 reg [5:0] tid;
22548 integer junk;
22549
22550 begin
22551`ifdef AXIS_EMUL_COSIM
22552//Do Nothing
22553`else
22554`ifdef GATESIM
22555//Do Nothing
22556`else
22557`ifdef CORE_5
22558 if (`PARGS.nas_check_on) begin
22559 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
22560 tid = 5
22561; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22562 end
22563`endif
22564
22565`endif
22566
22567`endif
22568
22569 end
22570 endtask
22571
22572
22573 task slam_ZeroTsbConfig3_core5_thread6;
22574 input [63:0] value;
22575 reg [5:0] tid;
22576 integer junk;
22577
22578 begin
22579`ifdef AXIS_EMUL_COSIM
22580//Do Nothing
22581`else
22582`ifdef GATESIM
22583//Do Nothing
22584`else
22585`ifdef CORE_5
22586 if (`PARGS.nas_check_on) begin
22587 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
22588 tid = 6
22589; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22590 end
22591`endif
22592
22593`endif
22594
22595`endif
22596
22597 end
22598 endtask
22599
22600
22601 task slam_ZeroTsbConfig3_core5_thread7;
22602 input [63:0] value;
22603 reg [5:0] tid;
22604 integer junk;
22605
22606 begin
22607`ifdef AXIS_EMUL_COSIM
22608//Do Nothing
22609`else
22610`ifdef GATESIM
22611//Do Nothing
22612`else
22613`ifdef CORE_5
22614 if (`PARGS.nas_check_on) begin
22615 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
22616 tid = 7
22617; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22618 end
22619`endif
22620
22621`endif
22622
22623`endif
22624
22625 end
22626 endtask
22627
22628
22629 task slam_ZeroTsbConfig3_core6_thread0;
22630 input [63:0] value;
22631 reg [5:0] tid;
22632 integer junk;
22633
22634 begin
22635`ifdef AXIS_EMUL_COSIM
22636//Do Nothing
22637`else
22638`ifdef GATESIM
22639//Do Nothing
22640`else
22641`ifdef CORE_6
22642 if (`PARGS.nas_check_on) begin
22643 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
22644 tid = 0
22645; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22646 end
22647`endif
22648
22649`endif
22650
22651`endif
22652
22653 end
22654 endtask
22655
22656
22657 task slam_ZeroTsbConfig3_core6_thread1;
22658 input [63:0] value;
22659 reg [5:0] tid;
22660 integer junk;
22661
22662 begin
22663`ifdef AXIS_EMUL_COSIM
22664//Do Nothing
22665`else
22666`ifdef GATESIM
22667//Do Nothing
22668`else
22669`ifdef CORE_6
22670 if (`PARGS.nas_check_on) begin
22671 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
22672 tid = 1
22673; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22674 end
22675`endif
22676
22677`endif
22678
22679`endif
22680
22681 end
22682 endtask
22683
22684
22685 task slam_ZeroTsbConfig3_core6_thread2;
22686 input [63:0] value;
22687 reg [5:0] tid;
22688 integer junk;
22689
22690 begin
22691`ifdef AXIS_EMUL_COSIM
22692//Do Nothing
22693`else
22694`ifdef GATESIM
22695//Do Nothing
22696`else
22697`ifdef CORE_6
22698 if (`PARGS.nas_check_on) begin
22699 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
22700 tid = 2
22701; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22702 end
22703`endif
22704
22705`endif
22706
22707`endif
22708
22709 end
22710 endtask
22711
22712
22713 task slam_ZeroTsbConfig3_core6_thread3;
22714 input [63:0] value;
22715 reg [5:0] tid;
22716 integer junk;
22717
22718 begin
22719`ifdef AXIS_EMUL_COSIM
22720//Do Nothing
22721`else
22722`ifdef GATESIM
22723//Do Nothing
22724`else
22725`ifdef CORE_6
22726 if (`PARGS.nas_check_on) begin
22727 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
22728 tid = 3
22729; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22730 end
22731`endif
22732
22733`endif
22734
22735`endif
22736
22737 end
22738 endtask
22739
22740
22741 task slam_ZeroTsbConfig3_core6_thread4;
22742 input [63:0] value;
22743 reg [5:0] tid;
22744 integer junk;
22745
22746 begin
22747`ifdef AXIS_EMUL_COSIM
22748//Do Nothing
22749`else
22750`ifdef GATESIM
22751//Do Nothing
22752`else
22753`ifdef CORE_6
22754 if (`PARGS.nas_check_on) begin
22755 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
22756 tid = 4
22757; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22758 end
22759`endif
22760
22761`endif
22762
22763`endif
22764
22765 end
22766 endtask
22767
22768
22769 task slam_ZeroTsbConfig3_core6_thread5;
22770 input [63:0] value;
22771 reg [5:0] tid;
22772 integer junk;
22773
22774 begin
22775`ifdef AXIS_EMUL_COSIM
22776//Do Nothing
22777`else
22778`ifdef GATESIM
22779//Do Nothing
22780`else
22781`ifdef CORE_6
22782 if (`PARGS.nas_check_on) begin
22783 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
22784 tid = 5
22785; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22786 end
22787`endif
22788
22789`endif
22790
22791`endif
22792
22793 end
22794 endtask
22795
22796
22797 task slam_ZeroTsbConfig3_core6_thread6;
22798 input [63:0] value;
22799 reg [5:0] tid;
22800 integer junk;
22801
22802 begin
22803`ifdef AXIS_EMUL_COSIM
22804//Do Nothing
22805`else
22806`ifdef GATESIM
22807//Do Nothing
22808`else
22809`ifdef CORE_6
22810 if (`PARGS.nas_check_on) begin
22811 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
22812 tid = 6
22813; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22814 end
22815`endif
22816
22817`endif
22818
22819`endif
22820
22821 end
22822 endtask
22823
22824
22825 task slam_ZeroTsbConfig3_core6_thread7;
22826 input [63:0] value;
22827 reg [5:0] tid;
22828 integer junk;
22829
22830 begin
22831`ifdef AXIS_EMUL_COSIM
22832//Do Nothing
22833`else
22834`ifdef GATESIM
22835//Do Nothing
22836`else
22837`ifdef CORE_6
22838 if (`PARGS.nas_check_on) begin
22839 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
22840 tid = 7
22841; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22842 end
22843`endif
22844
22845`endif
22846
22847`endif
22848
22849 end
22850 endtask
22851
22852
22853 task slam_ZeroTsbConfig3_core7_thread0;
22854 input [63:0] value;
22855 reg [5:0] tid;
22856 integer junk;
22857
22858 begin
22859`ifdef AXIS_EMUL_COSIM
22860//Do Nothing
22861`else
22862`ifdef GATESIM
22863//Do Nothing
22864`else
22865`ifdef CORE_7
22866 if (`PARGS.nas_check_on) begin
22867 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
22868 tid = 0
22869; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22870 end
22871`endif
22872
22873`endif
22874
22875`endif
22876
22877 end
22878 endtask
22879
22880
22881 task slam_ZeroTsbConfig3_core7_thread1;
22882 input [63:0] value;
22883 reg [5:0] tid;
22884 integer junk;
22885
22886 begin
22887`ifdef AXIS_EMUL_COSIM
22888//Do Nothing
22889`else
22890`ifdef GATESIM
22891//Do Nothing
22892`else
22893`ifdef CORE_7
22894 if (`PARGS.nas_check_on) begin
22895 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
22896 tid = 1
22897; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22898 end
22899`endif
22900
22901`endif
22902
22903`endif
22904
22905 end
22906 endtask
22907
22908
22909 task slam_ZeroTsbConfig3_core7_thread2;
22910 input [63:0] value;
22911 reg [5:0] tid;
22912 integer junk;
22913
22914 begin
22915`ifdef AXIS_EMUL_COSIM
22916//Do Nothing
22917`else
22918`ifdef GATESIM
22919//Do Nothing
22920`else
22921`ifdef CORE_7
22922 if (`PARGS.nas_check_on) begin
22923 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
22924 tid = 2
22925; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22926 end
22927`endif
22928
22929`endif
22930
22931`endif
22932
22933 end
22934 endtask
22935
22936
22937 task slam_ZeroTsbConfig3_core7_thread3;
22938 input [63:0] value;
22939 reg [5:0] tid;
22940 integer junk;
22941
22942 begin
22943`ifdef AXIS_EMUL_COSIM
22944//Do Nothing
22945`else
22946`ifdef GATESIM
22947//Do Nothing
22948`else
22949`ifdef CORE_7
22950 if (`PARGS.nas_check_on) begin
22951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
22952 tid = 3
22953; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22954 end
22955`endif
22956
22957`endif
22958
22959`endif
22960
22961 end
22962 endtask
22963
22964
22965 task slam_ZeroTsbConfig3_core7_thread4;
22966 input [63:0] value;
22967 reg [5:0] tid;
22968 integer junk;
22969
22970 begin
22971`ifdef AXIS_EMUL_COSIM
22972//Do Nothing
22973`else
22974`ifdef GATESIM
22975//Do Nothing
22976`else
22977`ifdef CORE_7
22978 if (`PARGS.nas_check_on) begin
22979 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
22980 tid = 4
22981; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
22982 end
22983`endif
22984
22985`endif
22986
22987`endif
22988
22989 end
22990 endtask
22991
22992
22993 task slam_ZeroTsbConfig3_core7_thread5;
22994 input [63:0] value;
22995 reg [5:0] tid;
22996 integer junk;
22997
22998 begin
22999`ifdef AXIS_EMUL_COSIM
23000//Do Nothing
23001`else
23002`ifdef GATESIM
23003//Do Nothing
23004`else
23005`ifdef CORE_7
23006 if (`PARGS.nas_check_on) begin
23007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
23008 tid = 5
23009; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
23010 end
23011`endif
23012
23013`endif
23014
23015`endif
23016
23017 end
23018 endtask
23019
23020
23021 task slam_ZeroTsbConfig3_core7_thread6;
23022 input [63:0] value;
23023 reg [5:0] tid;
23024 integer junk;
23025
23026 begin
23027`ifdef AXIS_EMUL_COSIM
23028//Do Nothing
23029`else
23030`ifdef GATESIM
23031//Do Nothing
23032`else
23033`ifdef CORE_7
23034 if (`PARGS.nas_check_on) begin
23035 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
23036 tid = 6
23037; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
23038 end
23039`endif
23040
23041`endif
23042
23043`endif
23044
23045 end
23046 endtask
23047
23048
23049 task slam_ZeroTsbConfig3_core7_thread7;
23050 input [63:0] value;
23051 reg [5:0] tid;
23052 integer junk;
23053
23054 begin
23055`ifdef AXIS_EMUL_COSIM
23056//Do Nothing
23057`else
23058`ifdef GATESIM
23059//Do Nothing
23060`else
23061`ifdef CORE_7
23062 if (`PARGS.nas_check_on) begin
23063 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
23064 tid = 7
23065; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h28, value);
23066 end
23067`endif
23068
23069`endif
23070
23071`endif
23072
23073 end
23074 endtask
23075
23076
23077 task slam_NonZeroTsbConfig0_core0_thread0;
23078 input [63:0] value;
23079 reg [5:0] tid;
23080 integer junk;
23081
23082 begin
23083`ifdef AXIS_EMUL_COSIM
23084//Do Nothing
23085`else
23086`ifdef GATESIM
23087//Do Nothing
23088`else
23089`ifdef CORE_0
23090 if (`PARGS.nas_check_on) begin
23091 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
23092 tid = 0
23093; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23094 end
23095`endif
23096
23097`endif
23098
23099`endif
23100
23101 end
23102 endtask
23103
23104
23105 task slam_NonZeroTsbConfig0_core0_thread1;
23106 input [63:0] value;
23107 reg [5:0] tid;
23108 integer junk;
23109
23110 begin
23111`ifdef AXIS_EMUL_COSIM
23112//Do Nothing
23113`else
23114`ifdef GATESIM
23115//Do Nothing
23116`else
23117`ifdef CORE_0
23118 if (`PARGS.nas_check_on) begin
23119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
23120 tid = 1
23121; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23122 end
23123`endif
23124
23125`endif
23126
23127`endif
23128
23129 end
23130 endtask
23131
23132
23133 task slam_NonZeroTsbConfig0_core0_thread2;
23134 input [63:0] value;
23135 reg [5:0] tid;
23136 integer junk;
23137
23138 begin
23139`ifdef AXIS_EMUL_COSIM
23140//Do Nothing
23141`else
23142`ifdef GATESIM
23143//Do Nothing
23144`else
23145`ifdef CORE_0
23146 if (`PARGS.nas_check_on) begin
23147 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
23148 tid = 2
23149; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23150 end
23151`endif
23152
23153`endif
23154
23155`endif
23156
23157 end
23158 endtask
23159
23160
23161 task slam_NonZeroTsbConfig0_core0_thread3;
23162 input [63:0] value;
23163 reg [5:0] tid;
23164 integer junk;
23165
23166 begin
23167`ifdef AXIS_EMUL_COSIM
23168//Do Nothing
23169`else
23170`ifdef GATESIM
23171//Do Nothing
23172`else
23173`ifdef CORE_0
23174 if (`PARGS.nas_check_on) begin
23175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
23176 tid = 3
23177; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23178 end
23179`endif
23180
23181`endif
23182
23183`endif
23184
23185 end
23186 endtask
23187
23188
23189 task slam_NonZeroTsbConfig0_core0_thread4;
23190 input [63:0] value;
23191 reg [5:0] tid;
23192 integer junk;
23193
23194 begin
23195`ifdef AXIS_EMUL_COSIM
23196//Do Nothing
23197`else
23198`ifdef GATESIM
23199//Do Nothing
23200`else
23201`ifdef CORE_0
23202 if (`PARGS.nas_check_on) begin
23203 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
23204 tid = 4
23205; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23206 end
23207`endif
23208
23209`endif
23210
23211`endif
23212
23213 end
23214 endtask
23215
23216
23217 task slam_NonZeroTsbConfig0_core0_thread5;
23218 input [63:0] value;
23219 reg [5:0] tid;
23220 integer junk;
23221
23222 begin
23223`ifdef AXIS_EMUL_COSIM
23224//Do Nothing
23225`else
23226`ifdef GATESIM
23227//Do Nothing
23228`else
23229`ifdef CORE_0
23230 if (`PARGS.nas_check_on) begin
23231 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
23232 tid = 5
23233; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23234 end
23235`endif
23236
23237`endif
23238
23239`endif
23240
23241 end
23242 endtask
23243
23244
23245 task slam_NonZeroTsbConfig0_core0_thread6;
23246 input [63:0] value;
23247 reg [5:0] tid;
23248 integer junk;
23249
23250 begin
23251`ifdef AXIS_EMUL_COSIM
23252//Do Nothing
23253`else
23254`ifdef GATESIM
23255//Do Nothing
23256`else
23257`ifdef CORE_0
23258 if (`PARGS.nas_check_on) begin
23259 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
23260 tid = 6
23261; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23262 end
23263`endif
23264
23265`endif
23266
23267`endif
23268
23269 end
23270 endtask
23271
23272
23273 task slam_NonZeroTsbConfig0_core0_thread7;
23274 input [63:0] value;
23275 reg [5:0] tid;
23276 integer junk;
23277
23278 begin
23279`ifdef AXIS_EMUL_COSIM
23280//Do Nothing
23281`else
23282`ifdef GATESIM
23283//Do Nothing
23284`else
23285`ifdef CORE_0
23286 if (`PARGS.nas_check_on) begin
23287 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
23288 tid = 7
23289; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23290 end
23291`endif
23292
23293`endif
23294
23295`endif
23296
23297 end
23298 endtask
23299
23300
23301 task slam_NonZeroTsbConfig0_core1_thread0;
23302 input [63:0] value;
23303 reg [5:0] tid;
23304 integer junk;
23305
23306 begin
23307`ifdef AXIS_EMUL_COSIM
23308//Do Nothing
23309`else
23310`ifdef GATESIM
23311//Do Nothing
23312`else
23313`ifdef CORE_1
23314 if (`PARGS.nas_check_on) begin
23315 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
23316 tid = 0
23317; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23318 end
23319`endif
23320
23321`endif
23322
23323`endif
23324
23325 end
23326 endtask
23327
23328
23329 task slam_NonZeroTsbConfig0_core1_thread1;
23330 input [63:0] value;
23331 reg [5:0] tid;
23332 integer junk;
23333
23334 begin
23335`ifdef AXIS_EMUL_COSIM
23336//Do Nothing
23337`else
23338`ifdef GATESIM
23339//Do Nothing
23340`else
23341`ifdef CORE_1
23342 if (`PARGS.nas_check_on) begin
23343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
23344 tid = 1
23345; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23346 end
23347`endif
23348
23349`endif
23350
23351`endif
23352
23353 end
23354 endtask
23355
23356
23357 task slam_NonZeroTsbConfig0_core1_thread2;
23358 input [63:0] value;
23359 reg [5:0] tid;
23360 integer junk;
23361
23362 begin
23363`ifdef AXIS_EMUL_COSIM
23364//Do Nothing
23365`else
23366`ifdef GATESIM
23367//Do Nothing
23368`else
23369`ifdef CORE_1
23370 if (`PARGS.nas_check_on) begin
23371 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
23372 tid = 2
23373; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23374 end
23375`endif
23376
23377`endif
23378
23379`endif
23380
23381 end
23382 endtask
23383
23384
23385 task slam_NonZeroTsbConfig0_core1_thread3;
23386 input [63:0] value;
23387 reg [5:0] tid;
23388 integer junk;
23389
23390 begin
23391`ifdef AXIS_EMUL_COSIM
23392//Do Nothing
23393`else
23394`ifdef GATESIM
23395//Do Nothing
23396`else
23397`ifdef CORE_1
23398 if (`PARGS.nas_check_on) begin
23399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
23400 tid = 3
23401; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23402 end
23403`endif
23404
23405`endif
23406
23407`endif
23408
23409 end
23410 endtask
23411
23412
23413 task slam_NonZeroTsbConfig0_core1_thread4;
23414 input [63:0] value;
23415 reg [5:0] tid;
23416 integer junk;
23417
23418 begin
23419`ifdef AXIS_EMUL_COSIM
23420//Do Nothing
23421`else
23422`ifdef GATESIM
23423//Do Nothing
23424`else
23425`ifdef CORE_1
23426 if (`PARGS.nas_check_on) begin
23427 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
23428 tid = 4
23429; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23430 end
23431`endif
23432
23433`endif
23434
23435`endif
23436
23437 end
23438 endtask
23439
23440
23441 task slam_NonZeroTsbConfig0_core1_thread5;
23442 input [63:0] value;
23443 reg [5:0] tid;
23444 integer junk;
23445
23446 begin
23447`ifdef AXIS_EMUL_COSIM
23448//Do Nothing
23449`else
23450`ifdef GATESIM
23451//Do Nothing
23452`else
23453`ifdef CORE_1
23454 if (`PARGS.nas_check_on) begin
23455 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
23456 tid = 5
23457; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23458 end
23459`endif
23460
23461`endif
23462
23463`endif
23464
23465 end
23466 endtask
23467
23468
23469 task slam_NonZeroTsbConfig0_core1_thread6;
23470 input [63:0] value;
23471 reg [5:0] tid;
23472 integer junk;
23473
23474 begin
23475`ifdef AXIS_EMUL_COSIM
23476//Do Nothing
23477`else
23478`ifdef GATESIM
23479//Do Nothing
23480`else
23481`ifdef CORE_1
23482 if (`PARGS.nas_check_on) begin
23483 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
23484 tid = 6
23485; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23486 end
23487`endif
23488
23489`endif
23490
23491`endif
23492
23493 end
23494 endtask
23495
23496
23497 task slam_NonZeroTsbConfig0_core1_thread7;
23498 input [63:0] value;
23499 reg [5:0] tid;
23500 integer junk;
23501
23502 begin
23503`ifdef AXIS_EMUL_COSIM
23504//Do Nothing
23505`else
23506`ifdef GATESIM
23507//Do Nothing
23508`else
23509`ifdef CORE_1
23510 if (`PARGS.nas_check_on) begin
23511 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
23512 tid = 7
23513; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23514 end
23515`endif
23516
23517`endif
23518
23519`endif
23520
23521 end
23522 endtask
23523
23524
23525 task slam_NonZeroTsbConfig0_core2_thread0;
23526 input [63:0] value;
23527 reg [5:0] tid;
23528 integer junk;
23529
23530 begin
23531`ifdef AXIS_EMUL_COSIM
23532//Do Nothing
23533`else
23534`ifdef GATESIM
23535//Do Nothing
23536`else
23537`ifdef CORE_2
23538 if (`PARGS.nas_check_on) begin
23539 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
23540 tid = 0
23541; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23542 end
23543`endif
23544
23545`endif
23546
23547`endif
23548
23549 end
23550 endtask
23551
23552
23553 task slam_NonZeroTsbConfig0_core2_thread1;
23554 input [63:0] value;
23555 reg [5:0] tid;
23556 integer junk;
23557
23558 begin
23559`ifdef AXIS_EMUL_COSIM
23560//Do Nothing
23561`else
23562`ifdef GATESIM
23563//Do Nothing
23564`else
23565`ifdef CORE_2
23566 if (`PARGS.nas_check_on) begin
23567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
23568 tid = 1
23569; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23570 end
23571`endif
23572
23573`endif
23574
23575`endif
23576
23577 end
23578 endtask
23579
23580
23581 task slam_NonZeroTsbConfig0_core2_thread2;
23582 input [63:0] value;
23583 reg [5:0] tid;
23584 integer junk;
23585
23586 begin
23587`ifdef AXIS_EMUL_COSIM
23588//Do Nothing
23589`else
23590`ifdef GATESIM
23591//Do Nothing
23592`else
23593`ifdef CORE_2
23594 if (`PARGS.nas_check_on) begin
23595 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
23596 tid = 2
23597; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23598 end
23599`endif
23600
23601`endif
23602
23603`endif
23604
23605 end
23606 endtask
23607
23608
23609 task slam_NonZeroTsbConfig0_core2_thread3;
23610 input [63:0] value;
23611 reg [5:0] tid;
23612 integer junk;
23613
23614 begin
23615`ifdef AXIS_EMUL_COSIM
23616//Do Nothing
23617`else
23618`ifdef GATESIM
23619//Do Nothing
23620`else
23621`ifdef CORE_2
23622 if (`PARGS.nas_check_on) begin
23623 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
23624 tid = 3
23625; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23626 end
23627`endif
23628
23629`endif
23630
23631`endif
23632
23633 end
23634 endtask
23635
23636
23637 task slam_NonZeroTsbConfig0_core2_thread4;
23638 input [63:0] value;
23639 reg [5:0] tid;
23640 integer junk;
23641
23642 begin
23643`ifdef AXIS_EMUL_COSIM
23644//Do Nothing
23645`else
23646`ifdef GATESIM
23647//Do Nothing
23648`else
23649`ifdef CORE_2
23650 if (`PARGS.nas_check_on) begin
23651 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
23652 tid = 4
23653; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23654 end
23655`endif
23656
23657`endif
23658
23659`endif
23660
23661 end
23662 endtask
23663
23664
23665 task slam_NonZeroTsbConfig0_core2_thread5;
23666 input [63:0] value;
23667 reg [5:0] tid;
23668 integer junk;
23669
23670 begin
23671`ifdef AXIS_EMUL_COSIM
23672//Do Nothing
23673`else
23674`ifdef GATESIM
23675//Do Nothing
23676`else
23677`ifdef CORE_2
23678 if (`PARGS.nas_check_on) begin
23679 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
23680 tid = 5
23681; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23682 end
23683`endif
23684
23685`endif
23686
23687`endif
23688
23689 end
23690 endtask
23691
23692
23693 task slam_NonZeroTsbConfig0_core2_thread6;
23694 input [63:0] value;
23695 reg [5:0] tid;
23696 integer junk;
23697
23698 begin
23699`ifdef AXIS_EMUL_COSIM
23700//Do Nothing
23701`else
23702`ifdef GATESIM
23703//Do Nothing
23704`else
23705`ifdef CORE_2
23706 if (`PARGS.nas_check_on) begin
23707 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
23708 tid = 6
23709; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23710 end
23711`endif
23712
23713`endif
23714
23715`endif
23716
23717 end
23718 endtask
23719
23720
23721 task slam_NonZeroTsbConfig0_core2_thread7;
23722 input [63:0] value;
23723 reg [5:0] tid;
23724 integer junk;
23725
23726 begin
23727`ifdef AXIS_EMUL_COSIM
23728//Do Nothing
23729`else
23730`ifdef GATESIM
23731//Do Nothing
23732`else
23733`ifdef CORE_2
23734 if (`PARGS.nas_check_on) begin
23735 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
23736 tid = 7
23737; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23738 end
23739`endif
23740
23741`endif
23742
23743`endif
23744
23745 end
23746 endtask
23747
23748
23749 task slam_NonZeroTsbConfig0_core3_thread0;
23750 input [63:0] value;
23751 reg [5:0] tid;
23752 integer junk;
23753
23754 begin
23755`ifdef AXIS_EMUL_COSIM
23756//Do Nothing
23757`else
23758`ifdef GATESIM
23759//Do Nothing
23760`else
23761`ifdef CORE_3
23762 if (`PARGS.nas_check_on) begin
23763 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
23764 tid = 0
23765; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23766 end
23767`endif
23768
23769`endif
23770
23771`endif
23772
23773 end
23774 endtask
23775
23776
23777 task slam_NonZeroTsbConfig0_core3_thread1;
23778 input [63:0] value;
23779 reg [5:0] tid;
23780 integer junk;
23781
23782 begin
23783`ifdef AXIS_EMUL_COSIM
23784//Do Nothing
23785`else
23786`ifdef GATESIM
23787//Do Nothing
23788`else
23789`ifdef CORE_3
23790 if (`PARGS.nas_check_on) begin
23791 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
23792 tid = 1
23793; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23794 end
23795`endif
23796
23797`endif
23798
23799`endif
23800
23801 end
23802 endtask
23803
23804
23805 task slam_NonZeroTsbConfig0_core3_thread2;
23806 input [63:0] value;
23807 reg [5:0] tid;
23808 integer junk;
23809
23810 begin
23811`ifdef AXIS_EMUL_COSIM
23812//Do Nothing
23813`else
23814`ifdef GATESIM
23815//Do Nothing
23816`else
23817`ifdef CORE_3
23818 if (`PARGS.nas_check_on) begin
23819 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
23820 tid = 2
23821; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23822 end
23823`endif
23824
23825`endif
23826
23827`endif
23828
23829 end
23830 endtask
23831
23832
23833 task slam_NonZeroTsbConfig0_core3_thread3;
23834 input [63:0] value;
23835 reg [5:0] tid;
23836 integer junk;
23837
23838 begin
23839`ifdef AXIS_EMUL_COSIM
23840//Do Nothing
23841`else
23842`ifdef GATESIM
23843//Do Nothing
23844`else
23845`ifdef CORE_3
23846 if (`PARGS.nas_check_on) begin
23847 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
23848 tid = 3
23849; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23850 end
23851`endif
23852
23853`endif
23854
23855`endif
23856
23857 end
23858 endtask
23859
23860
23861 task slam_NonZeroTsbConfig0_core3_thread4;
23862 input [63:0] value;
23863 reg [5:0] tid;
23864 integer junk;
23865
23866 begin
23867`ifdef AXIS_EMUL_COSIM
23868//Do Nothing
23869`else
23870`ifdef GATESIM
23871//Do Nothing
23872`else
23873`ifdef CORE_3
23874 if (`PARGS.nas_check_on) begin
23875 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
23876 tid = 4
23877; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23878 end
23879`endif
23880
23881`endif
23882
23883`endif
23884
23885 end
23886 endtask
23887
23888
23889 task slam_NonZeroTsbConfig0_core3_thread5;
23890 input [63:0] value;
23891 reg [5:0] tid;
23892 integer junk;
23893
23894 begin
23895`ifdef AXIS_EMUL_COSIM
23896//Do Nothing
23897`else
23898`ifdef GATESIM
23899//Do Nothing
23900`else
23901`ifdef CORE_3
23902 if (`PARGS.nas_check_on) begin
23903 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
23904 tid = 5
23905; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23906 end
23907`endif
23908
23909`endif
23910
23911`endif
23912
23913 end
23914 endtask
23915
23916
23917 task slam_NonZeroTsbConfig0_core3_thread6;
23918 input [63:0] value;
23919 reg [5:0] tid;
23920 integer junk;
23921
23922 begin
23923`ifdef AXIS_EMUL_COSIM
23924//Do Nothing
23925`else
23926`ifdef GATESIM
23927//Do Nothing
23928`else
23929`ifdef CORE_3
23930 if (`PARGS.nas_check_on) begin
23931 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
23932 tid = 6
23933; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23934 end
23935`endif
23936
23937`endif
23938
23939`endif
23940
23941 end
23942 endtask
23943
23944
23945 task slam_NonZeroTsbConfig0_core3_thread7;
23946 input [63:0] value;
23947 reg [5:0] tid;
23948 integer junk;
23949
23950 begin
23951`ifdef AXIS_EMUL_COSIM
23952//Do Nothing
23953`else
23954`ifdef GATESIM
23955//Do Nothing
23956`else
23957`ifdef CORE_3
23958 if (`PARGS.nas_check_on) begin
23959 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
23960 tid = 7
23961; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23962 end
23963`endif
23964
23965`endif
23966
23967`endif
23968
23969 end
23970 endtask
23971
23972
23973 task slam_NonZeroTsbConfig0_core4_thread0;
23974 input [63:0] value;
23975 reg [5:0] tid;
23976 integer junk;
23977
23978 begin
23979`ifdef AXIS_EMUL_COSIM
23980//Do Nothing
23981`else
23982`ifdef GATESIM
23983//Do Nothing
23984`else
23985`ifdef CORE_4
23986 if (`PARGS.nas_check_on) begin
23987 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
23988 tid = 0
23989; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
23990 end
23991`endif
23992
23993`endif
23994
23995`endif
23996
23997 end
23998 endtask
23999
24000
24001 task slam_NonZeroTsbConfig0_core4_thread1;
24002 input [63:0] value;
24003 reg [5:0] tid;
24004 integer junk;
24005
24006 begin
24007`ifdef AXIS_EMUL_COSIM
24008//Do Nothing
24009`else
24010`ifdef GATESIM
24011//Do Nothing
24012`else
24013`ifdef CORE_4
24014 if (`PARGS.nas_check_on) begin
24015 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
24016 tid = 1
24017; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24018 end
24019`endif
24020
24021`endif
24022
24023`endif
24024
24025 end
24026 endtask
24027
24028
24029 task slam_NonZeroTsbConfig0_core4_thread2;
24030 input [63:0] value;
24031 reg [5:0] tid;
24032 integer junk;
24033
24034 begin
24035`ifdef AXIS_EMUL_COSIM
24036//Do Nothing
24037`else
24038`ifdef GATESIM
24039//Do Nothing
24040`else
24041`ifdef CORE_4
24042 if (`PARGS.nas_check_on) begin
24043 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
24044 tid = 2
24045; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24046 end
24047`endif
24048
24049`endif
24050
24051`endif
24052
24053 end
24054 endtask
24055
24056
24057 task slam_NonZeroTsbConfig0_core4_thread3;
24058 input [63:0] value;
24059 reg [5:0] tid;
24060 integer junk;
24061
24062 begin
24063`ifdef AXIS_EMUL_COSIM
24064//Do Nothing
24065`else
24066`ifdef GATESIM
24067//Do Nothing
24068`else
24069`ifdef CORE_4
24070 if (`PARGS.nas_check_on) begin
24071 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
24072 tid = 3
24073; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24074 end
24075`endif
24076
24077`endif
24078
24079`endif
24080
24081 end
24082 endtask
24083
24084
24085 task slam_NonZeroTsbConfig0_core4_thread4;
24086 input [63:0] value;
24087 reg [5:0] tid;
24088 integer junk;
24089
24090 begin
24091`ifdef AXIS_EMUL_COSIM
24092//Do Nothing
24093`else
24094`ifdef GATESIM
24095//Do Nothing
24096`else
24097`ifdef CORE_4
24098 if (`PARGS.nas_check_on) begin
24099 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
24100 tid = 4
24101; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24102 end
24103`endif
24104
24105`endif
24106
24107`endif
24108
24109 end
24110 endtask
24111
24112
24113 task slam_NonZeroTsbConfig0_core4_thread5;
24114 input [63:0] value;
24115 reg [5:0] tid;
24116 integer junk;
24117
24118 begin
24119`ifdef AXIS_EMUL_COSIM
24120//Do Nothing
24121`else
24122`ifdef GATESIM
24123//Do Nothing
24124`else
24125`ifdef CORE_4
24126 if (`PARGS.nas_check_on) begin
24127 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
24128 tid = 5
24129; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24130 end
24131`endif
24132
24133`endif
24134
24135`endif
24136
24137 end
24138 endtask
24139
24140
24141 task slam_NonZeroTsbConfig0_core4_thread6;
24142 input [63:0] value;
24143 reg [5:0] tid;
24144 integer junk;
24145
24146 begin
24147`ifdef AXIS_EMUL_COSIM
24148//Do Nothing
24149`else
24150`ifdef GATESIM
24151//Do Nothing
24152`else
24153`ifdef CORE_4
24154 if (`PARGS.nas_check_on) begin
24155 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
24156 tid = 6
24157; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24158 end
24159`endif
24160
24161`endif
24162
24163`endif
24164
24165 end
24166 endtask
24167
24168
24169 task slam_NonZeroTsbConfig0_core4_thread7;
24170 input [63:0] value;
24171 reg [5:0] tid;
24172 integer junk;
24173
24174 begin
24175`ifdef AXIS_EMUL_COSIM
24176//Do Nothing
24177`else
24178`ifdef GATESIM
24179//Do Nothing
24180`else
24181`ifdef CORE_4
24182 if (`PARGS.nas_check_on) begin
24183 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
24184 tid = 7
24185; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24186 end
24187`endif
24188
24189`endif
24190
24191`endif
24192
24193 end
24194 endtask
24195
24196
24197 task slam_NonZeroTsbConfig0_core5_thread0;
24198 input [63:0] value;
24199 reg [5:0] tid;
24200 integer junk;
24201
24202 begin
24203`ifdef AXIS_EMUL_COSIM
24204//Do Nothing
24205`else
24206`ifdef GATESIM
24207//Do Nothing
24208`else
24209`ifdef CORE_5
24210 if (`PARGS.nas_check_on) begin
24211 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
24212 tid = 0
24213; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24214 end
24215`endif
24216
24217`endif
24218
24219`endif
24220
24221 end
24222 endtask
24223
24224
24225 task slam_NonZeroTsbConfig0_core5_thread1;
24226 input [63:0] value;
24227 reg [5:0] tid;
24228 integer junk;
24229
24230 begin
24231`ifdef AXIS_EMUL_COSIM
24232//Do Nothing
24233`else
24234`ifdef GATESIM
24235//Do Nothing
24236`else
24237`ifdef CORE_5
24238 if (`PARGS.nas_check_on) begin
24239 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
24240 tid = 1
24241; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24242 end
24243`endif
24244
24245`endif
24246
24247`endif
24248
24249 end
24250 endtask
24251
24252
24253 task slam_NonZeroTsbConfig0_core5_thread2;
24254 input [63:0] value;
24255 reg [5:0] tid;
24256 integer junk;
24257
24258 begin
24259`ifdef AXIS_EMUL_COSIM
24260//Do Nothing
24261`else
24262`ifdef GATESIM
24263//Do Nothing
24264`else
24265`ifdef CORE_5
24266 if (`PARGS.nas_check_on) begin
24267 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
24268 tid = 2
24269; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24270 end
24271`endif
24272
24273`endif
24274
24275`endif
24276
24277 end
24278 endtask
24279
24280
24281 task slam_NonZeroTsbConfig0_core5_thread3;
24282 input [63:0] value;
24283 reg [5:0] tid;
24284 integer junk;
24285
24286 begin
24287`ifdef AXIS_EMUL_COSIM
24288//Do Nothing
24289`else
24290`ifdef GATESIM
24291//Do Nothing
24292`else
24293`ifdef CORE_5
24294 if (`PARGS.nas_check_on) begin
24295 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
24296 tid = 3
24297; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24298 end
24299`endif
24300
24301`endif
24302
24303`endif
24304
24305 end
24306 endtask
24307
24308
24309 task slam_NonZeroTsbConfig0_core5_thread4;
24310 input [63:0] value;
24311 reg [5:0] tid;
24312 integer junk;
24313
24314 begin
24315`ifdef AXIS_EMUL_COSIM
24316//Do Nothing
24317`else
24318`ifdef GATESIM
24319//Do Nothing
24320`else
24321`ifdef CORE_5
24322 if (`PARGS.nas_check_on) begin
24323 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
24324 tid = 4
24325; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24326 end
24327`endif
24328
24329`endif
24330
24331`endif
24332
24333 end
24334 endtask
24335
24336
24337 task slam_NonZeroTsbConfig0_core5_thread5;
24338 input [63:0] value;
24339 reg [5:0] tid;
24340 integer junk;
24341
24342 begin
24343`ifdef AXIS_EMUL_COSIM
24344//Do Nothing
24345`else
24346`ifdef GATESIM
24347//Do Nothing
24348`else
24349`ifdef CORE_5
24350 if (`PARGS.nas_check_on) begin
24351 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
24352 tid = 5
24353; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24354 end
24355`endif
24356
24357`endif
24358
24359`endif
24360
24361 end
24362 endtask
24363
24364
24365 task slam_NonZeroTsbConfig0_core5_thread6;
24366 input [63:0] value;
24367 reg [5:0] tid;
24368 integer junk;
24369
24370 begin
24371`ifdef AXIS_EMUL_COSIM
24372//Do Nothing
24373`else
24374`ifdef GATESIM
24375//Do Nothing
24376`else
24377`ifdef CORE_5
24378 if (`PARGS.nas_check_on) begin
24379 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
24380 tid = 6
24381; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24382 end
24383`endif
24384
24385`endif
24386
24387`endif
24388
24389 end
24390 endtask
24391
24392
24393 task slam_NonZeroTsbConfig0_core5_thread7;
24394 input [63:0] value;
24395 reg [5:0] tid;
24396 integer junk;
24397
24398 begin
24399`ifdef AXIS_EMUL_COSIM
24400//Do Nothing
24401`else
24402`ifdef GATESIM
24403//Do Nothing
24404`else
24405`ifdef CORE_5
24406 if (`PARGS.nas_check_on) begin
24407 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
24408 tid = 7
24409; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24410 end
24411`endif
24412
24413`endif
24414
24415`endif
24416
24417 end
24418 endtask
24419
24420
24421 task slam_NonZeroTsbConfig0_core6_thread0;
24422 input [63:0] value;
24423 reg [5:0] tid;
24424 integer junk;
24425
24426 begin
24427`ifdef AXIS_EMUL_COSIM
24428//Do Nothing
24429`else
24430`ifdef GATESIM
24431//Do Nothing
24432`else
24433`ifdef CORE_6
24434 if (`PARGS.nas_check_on) begin
24435 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
24436 tid = 0
24437; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24438 end
24439`endif
24440
24441`endif
24442
24443`endif
24444
24445 end
24446 endtask
24447
24448
24449 task slam_NonZeroTsbConfig0_core6_thread1;
24450 input [63:0] value;
24451 reg [5:0] tid;
24452 integer junk;
24453
24454 begin
24455`ifdef AXIS_EMUL_COSIM
24456//Do Nothing
24457`else
24458`ifdef GATESIM
24459//Do Nothing
24460`else
24461`ifdef CORE_6
24462 if (`PARGS.nas_check_on) begin
24463 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
24464 tid = 1
24465; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24466 end
24467`endif
24468
24469`endif
24470
24471`endif
24472
24473 end
24474 endtask
24475
24476
24477 task slam_NonZeroTsbConfig0_core6_thread2;
24478 input [63:0] value;
24479 reg [5:0] tid;
24480 integer junk;
24481
24482 begin
24483`ifdef AXIS_EMUL_COSIM
24484//Do Nothing
24485`else
24486`ifdef GATESIM
24487//Do Nothing
24488`else
24489`ifdef CORE_6
24490 if (`PARGS.nas_check_on) begin
24491 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
24492 tid = 2
24493; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24494 end
24495`endif
24496
24497`endif
24498
24499`endif
24500
24501 end
24502 endtask
24503
24504
24505 task slam_NonZeroTsbConfig0_core6_thread3;
24506 input [63:0] value;
24507 reg [5:0] tid;
24508 integer junk;
24509
24510 begin
24511`ifdef AXIS_EMUL_COSIM
24512//Do Nothing
24513`else
24514`ifdef GATESIM
24515//Do Nothing
24516`else
24517`ifdef CORE_6
24518 if (`PARGS.nas_check_on) begin
24519 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
24520 tid = 3
24521; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24522 end
24523`endif
24524
24525`endif
24526
24527`endif
24528
24529 end
24530 endtask
24531
24532
24533 task slam_NonZeroTsbConfig0_core6_thread4;
24534 input [63:0] value;
24535 reg [5:0] tid;
24536 integer junk;
24537
24538 begin
24539`ifdef AXIS_EMUL_COSIM
24540//Do Nothing
24541`else
24542`ifdef GATESIM
24543//Do Nothing
24544`else
24545`ifdef CORE_6
24546 if (`PARGS.nas_check_on) begin
24547 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
24548 tid = 4
24549; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24550 end
24551`endif
24552
24553`endif
24554
24555`endif
24556
24557 end
24558 endtask
24559
24560
24561 task slam_NonZeroTsbConfig0_core6_thread5;
24562 input [63:0] value;
24563 reg [5:0] tid;
24564 integer junk;
24565
24566 begin
24567`ifdef AXIS_EMUL_COSIM
24568//Do Nothing
24569`else
24570`ifdef GATESIM
24571//Do Nothing
24572`else
24573`ifdef CORE_6
24574 if (`PARGS.nas_check_on) begin
24575 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
24576 tid = 5
24577; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24578 end
24579`endif
24580
24581`endif
24582
24583`endif
24584
24585 end
24586 endtask
24587
24588
24589 task slam_NonZeroTsbConfig0_core6_thread6;
24590 input [63:0] value;
24591 reg [5:0] tid;
24592 integer junk;
24593
24594 begin
24595`ifdef AXIS_EMUL_COSIM
24596//Do Nothing
24597`else
24598`ifdef GATESIM
24599//Do Nothing
24600`else
24601`ifdef CORE_6
24602 if (`PARGS.nas_check_on) begin
24603 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
24604 tid = 6
24605; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24606 end
24607`endif
24608
24609`endif
24610
24611`endif
24612
24613 end
24614 endtask
24615
24616
24617 task slam_NonZeroTsbConfig0_core6_thread7;
24618 input [63:0] value;
24619 reg [5:0] tid;
24620 integer junk;
24621
24622 begin
24623`ifdef AXIS_EMUL_COSIM
24624//Do Nothing
24625`else
24626`ifdef GATESIM
24627//Do Nothing
24628`else
24629`ifdef CORE_6
24630 if (`PARGS.nas_check_on) begin
24631 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
24632 tid = 7
24633; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24634 end
24635`endif
24636
24637`endif
24638
24639`endif
24640
24641 end
24642 endtask
24643
24644
24645 task slam_NonZeroTsbConfig0_core7_thread0;
24646 input [63:0] value;
24647 reg [5:0] tid;
24648 integer junk;
24649
24650 begin
24651`ifdef AXIS_EMUL_COSIM
24652//Do Nothing
24653`else
24654`ifdef GATESIM
24655//Do Nothing
24656`else
24657`ifdef CORE_7
24658 if (`PARGS.nas_check_on) begin
24659 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
24660 tid = 0
24661; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24662 end
24663`endif
24664
24665`endif
24666
24667`endif
24668
24669 end
24670 endtask
24671
24672
24673 task slam_NonZeroTsbConfig0_core7_thread1;
24674 input [63:0] value;
24675 reg [5:0] tid;
24676 integer junk;
24677
24678 begin
24679`ifdef AXIS_EMUL_COSIM
24680//Do Nothing
24681`else
24682`ifdef GATESIM
24683//Do Nothing
24684`else
24685`ifdef CORE_7
24686 if (`PARGS.nas_check_on) begin
24687 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
24688 tid = 1
24689; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24690 end
24691`endif
24692
24693`endif
24694
24695`endif
24696
24697 end
24698 endtask
24699
24700
24701 task slam_NonZeroTsbConfig0_core7_thread2;
24702 input [63:0] value;
24703 reg [5:0] tid;
24704 integer junk;
24705
24706 begin
24707`ifdef AXIS_EMUL_COSIM
24708//Do Nothing
24709`else
24710`ifdef GATESIM
24711//Do Nothing
24712`else
24713`ifdef CORE_7
24714 if (`PARGS.nas_check_on) begin
24715 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
24716 tid = 2
24717; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24718 end
24719`endif
24720
24721`endif
24722
24723`endif
24724
24725 end
24726 endtask
24727
24728
24729 task slam_NonZeroTsbConfig0_core7_thread3;
24730 input [63:0] value;
24731 reg [5:0] tid;
24732 integer junk;
24733
24734 begin
24735`ifdef AXIS_EMUL_COSIM
24736//Do Nothing
24737`else
24738`ifdef GATESIM
24739//Do Nothing
24740`else
24741`ifdef CORE_7
24742 if (`PARGS.nas_check_on) begin
24743 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
24744 tid = 3
24745; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24746 end
24747`endif
24748
24749`endif
24750
24751`endif
24752
24753 end
24754 endtask
24755
24756
24757 task slam_NonZeroTsbConfig0_core7_thread4;
24758 input [63:0] value;
24759 reg [5:0] tid;
24760 integer junk;
24761
24762 begin
24763`ifdef AXIS_EMUL_COSIM
24764//Do Nothing
24765`else
24766`ifdef GATESIM
24767//Do Nothing
24768`else
24769`ifdef CORE_7
24770 if (`PARGS.nas_check_on) begin
24771 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
24772 tid = 4
24773; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24774 end
24775`endif
24776
24777`endif
24778
24779`endif
24780
24781 end
24782 endtask
24783
24784
24785 task slam_NonZeroTsbConfig0_core7_thread5;
24786 input [63:0] value;
24787 reg [5:0] tid;
24788 integer junk;
24789
24790 begin
24791`ifdef AXIS_EMUL_COSIM
24792//Do Nothing
24793`else
24794`ifdef GATESIM
24795//Do Nothing
24796`else
24797`ifdef CORE_7
24798 if (`PARGS.nas_check_on) begin
24799 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
24800 tid = 5
24801; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24802 end
24803`endif
24804
24805`endif
24806
24807`endif
24808
24809 end
24810 endtask
24811
24812
24813 task slam_NonZeroTsbConfig0_core7_thread6;
24814 input [63:0] value;
24815 reg [5:0] tid;
24816 integer junk;
24817
24818 begin
24819`ifdef AXIS_EMUL_COSIM
24820//Do Nothing
24821`else
24822`ifdef GATESIM
24823//Do Nothing
24824`else
24825`ifdef CORE_7
24826 if (`PARGS.nas_check_on) begin
24827 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
24828 tid = 6
24829; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24830 end
24831`endif
24832
24833`endif
24834
24835`endif
24836
24837 end
24838 endtask
24839
24840
24841 task slam_NonZeroTsbConfig0_core7_thread7;
24842 input [63:0] value;
24843 reg [5:0] tid;
24844 integer junk;
24845
24846 begin
24847`ifdef AXIS_EMUL_COSIM
24848//Do Nothing
24849`else
24850`ifdef GATESIM
24851//Do Nothing
24852`else
24853`ifdef CORE_7
24854 if (`PARGS.nas_check_on) begin
24855 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
24856 tid = 7
24857; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h30, value);
24858 end
24859`endif
24860
24861`endif
24862
24863`endif
24864
24865 end
24866 endtask
24867
24868
24869 task slam_NonZeroTsbConfig1_core0_thread0;
24870 input [63:0] value;
24871 reg [5:0] tid;
24872 integer junk;
24873
24874 begin
24875`ifdef AXIS_EMUL_COSIM
24876//Do Nothing
24877`else
24878`ifdef GATESIM
24879//Do Nothing
24880`else
24881`ifdef CORE_0
24882 if (`PARGS.nas_check_on) begin
24883 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
24884 tid = 0
24885; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
24886 end
24887`endif
24888
24889`endif
24890
24891`endif
24892
24893 end
24894 endtask
24895
24896
24897 task slam_NonZeroTsbConfig1_core0_thread1;
24898 input [63:0] value;
24899 reg [5:0] tid;
24900 integer junk;
24901
24902 begin
24903`ifdef AXIS_EMUL_COSIM
24904//Do Nothing
24905`else
24906`ifdef GATESIM
24907//Do Nothing
24908`else
24909`ifdef CORE_0
24910 if (`PARGS.nas_check_on) begin
24911 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
24912 tid = 1
24913; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
24914 end
24915`endif
24916
24917`endif
24918
24919`endif
24920
24921 end
24922 endtask
24923
24924
24925 task slam_NonZeroTsbConfig1_core0_thread2;
24926 input [63:0] value;
24927 reg [5:0] tid;
24928 integer junk;
24929
24930 begin
24931`ifdef AXIS_EMUL_COSIM
24932//Do Nothing
24933`else
24934`ifdef GATESIM
24935//Do Nothing
24936`else
24937`ifdef CORE_0
24938 if (`PARGS.nas_check_on) begin
24939 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
24940 tid = 2
24941; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
24942 end
24943`endif
24944
24945`endif
24946
24947`endif
24948
24949 end
24950 endtask
24951
24952
24953 task slam_NonZeroTsbConfig1_core0_thread3;
24954 input [63:0] value;
24955 reg [5:0] tid;
24956 integer junk;
24957
24958 begin
24959`ifdef AXIS_EMUL_COSIM
24960//Do Nothing
24961`else
24962`ifdef GATESIM
24963//Do Nothing
24964`else
24965`ifdef CORE_0
24966 if (`PARGS.nas_check_on) begin
24967 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
24968 tid = 3
24969; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
24970 end
24971`endif
24972
24973`endif
24974
24975`endif
24976
24977 end
24978 endtask
24979
24980
24981 task slam_NonZeroTsbConfig1_core0_thread4;
24982 input [63:0] value;
24983 reg [5:0] tid;
24984 integer junk;
24985
24986 begin
24987`ifdef AXIS_EMUL_COSIM
24988//Do Nothing
24989`else
24990`ifdef GATESIM
24991//Do Nothing
24992`else
24993`ifdef CORE_0
24994 if (`PARGS.nas_check_on) begin
24995 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
24996 tid = 4
24997; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
24998 end
24999`endif
25000
25001`endif
25002
25003`endif
25004
25005 end
25006 endtask
25007
25008
25009 task slam_NonZeroTsbConfig1_core0_thread5;
25010 input [63:0] value;
25011 reg [5:0] tid;
25012 integer junk;
25013
25014 begin
25015`ifdef AXIS_EMUL_COSIM
25016//Do Nothing
25017`else
25018`ifdef GATESIM
25019//Do Nothing
25020`else
25021`ifdef CORE_0
25022 if (`PARGS.nas_check_on) begin
25023 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
25024 tid = 5
25025; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25026 end
25027`endif
25028
25029`endif
25030
25031`endif
25032
25033 end
25034 endtask
25035
25036
25037 task slam_NonZeroTsbConfig1_core0_thread6;
25038 input [63:0] value;
25039 reg [5:0] tid;
25040 integer junk;
25041
25042 begin
25043`ifdef AXIS_EMUL_COSIM
25044//Do Nothing
25045`else
25046`ifdef GATESIM
25047//Do Nothing
25048`else
25049`ifdef CORE_0
25050 if (`PARGS.nas_check_on) begin
25051 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
25052 tid = 6
25053; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25054 end
25055`endif
25056
25057`endif
25058
25059`endif
25060
25061 end
25062 endtask
25063
25064
25065 task slam_NonZeroTsbConfig1_core0_thread7;
25066 input [63:0] value;
25067 reg [5:0] tid;
25068 integer junk;
25069
25070 begin
25071`ifdef AXIS_EMUL_COSIM
25072//Do Nothing
25073`else
25074`ifdef GATESIM
25075//Do Nothing
25076`else
25077`ifdef CORE_0
25078 if (`PARGS.nas_check_on) begin
25079 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
25080 tid = 7
25081; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25082 end
25083`endif
25084
25085`endif
25086
25087`endif
25088
25089 end
25090 endtask
25091
25092
25093 task slam_NonZeroTsbConfig1_core1_thread0;
25094 input [63:0] value;
25095 reg [5:0] tid;
25096 integer junk;
25097
25098 begin
25099`ifdef AXIS_EMUL_COSIM
25100//Do Nothing
25101`else
25102`ifdef GATESIM
25103//Do Nothing
25104`else
25105`ifdef CORE_1
25106 if (`PARGS.nas_check_on) begin
25107 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
25108 tid = 0
25109; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25110 end
25111`endif
25112
25113`endif
25114
25115`endif
25116
25117 end
25118 endtask
25119
25120
25121 task slam_NonZeroTsbConfig1_core1_thread1;
25122 input [63:0] value;
25123 reg [5:0] tid;
25124 integer junk;
25125
25126 begin
25127`ifdef AXIS_EMUL_COSIM
25128//Do Nothing
25129`else
25130`ifdef GATESIM
25131//Do Nothing
25132`else
25133`ifdef CORE_1
25134 if (`PARGS.nas_check_on) begin
25135 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
25136 tid = 1
25137; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25138 end
25139`endif
25140
25141`endif
25142
25143`endif
25144
25145 end
25146 endtask
25147
25148
25149 task slam_NonZeroTsbConfig1_core1_thread2;
25150 input [63:0] value;
25151 reg [5:0] tid;
25152 integer junk;
25153
25154 begin
25155`ifdef AXIS_EMUL_COSIM
25156//Do Nothing
25157`else
25158`ifdef GATESIM
25159//Do Nothing
25160`else
25161`ifdef CORE_1
25162 if (`PARGS.nas_check_on) begin
25163 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
25164 tid = 2
25165; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25166 end
25167`endif
25168
25169`endif
25170
25171`endif
25172
25173 end
25174 endtask
25175
25176
25177 task slam_NonZeroTsbConfig1_core1_thread3;
25178 input [63:0] value;
25179 reg [5:0] tid;
25180 integer junk;
25181
25182 begin
25183`ifdef AXIS_EMUL_COSIM
25184//Do Nothing
25185`else
25186`ifdef GATESIM
25187//Do Nothing
25188`else
25189`ifdef CORE_1
25190 if (`PARGS.nas_check_on) begin
25191 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
25192 tid = 3
25193; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25194 end
25195`endif
25196
25197`endif
25198
25199`endif
25200
25201 end
25202 endtask
25203
25204
25205 task slam_NonZeroTsbConfig1_core1_thread4;
25206 input [63:0] value;
25207 reg [5:0] tid;
25208 integer junk;
25209
25210 begin
25211`ifdef AXIS_EMUL_COSIM
25212//Do Nothing
25213`else
25214`ifdef GATESIM
25215//Do Nothing
25216`else
25217`ifdef CORE_1
25218 if (`PARGS.nas_check_on) begin
25219 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
25220 tid = 4
25221; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25222 end
25223`endif
25224
25225`endif
25226
25227`endif
25228
25229 end
25230 endtask
25231
25232
25233 task slam_NonZeroTsbConfig1_core1_thread5;
25234 input [63:0] value;
25235 reg [5:0] tid;
25236 integer junk;
25237
25238 begin
25239`ifdef AXIS_EMUL_COSIM
25240//Do Nothing
25241`else
25242`ifdef GATESIM
25243//Do Nothing
25244`else
25245`ifdef CORE_1
25246 if (`PARGS.nas_check_on) begin
25247 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
25248 tid = 5
25249; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25250 end
25251`endif
25252
25253`endif
25254
25255`endif
25256
25257 end
25258 endtask
25259
25260
25261 task slam_NonZeroTsbConfig1_core1_thread6;
25262 input [63:0] value;
25263 reg [5:0] tid;
25264 integer junk;
25265
25266 begin
25267`ifdef AXIS_EMUL_COSIM
25268//Do Nothing
25269`else
25270`ifdef GATESIM
25271//Do Nothing
25272`else
25273`ifdef CORE_1
25274 if (`PARGS.nas_check_on) begin
25275 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
25276 tid = 6
25277; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25278 end
25279`endif
25280
25281`endif
25282
25283`endif
25284
25285 end
25286 endtask
25287
25288
25289 task slam_NonZeroTsbConfig1_core1_thread7;
25290 input [63:0] value;
25291 reg [5:0] tid;
25292 integer junk;
25293
25294 begin
25295`ifdef AXIS_EMUL_COSIM
25296//Do Nothing
25297`else
25298`ifdef GATESIM
25299//Do Nothing
25300`else
25301`ifdef CORE_1
25302 if (`PARGS.nas_check_on) begin
25303 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
25304 tid = 7
25305; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25306 end
25307`endif
25308
25309`endif
25310
25311`endif
25312
25313 end
25314 endtask
25315
25316
25317 task slam_NonZeroTsbConfig1_core2_thread0;
25318 input [63:0] value;
25319 reg [5:0] tid;
25320 integer junk;
25321
25322 begin
25323`ifdef AXIS_EMUL_COSIM
25324//Do Nothing
25325`else
25326`ifdef GATESIM
25327//Do Nothing
25328`else
25329`ifdef CORE_2
25330 if (`PARGS.nas_check_on) begin
25331 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
25332 tid = 0
25333; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25334 end
25335`endif
25336
25337`endif
25338
25339`endif
25340
25341 end
25342 endtask
25343
25344
25345 task slam_NonZeroTsbConfig1_core2_thread1;
25346 input [63:0] value;
25347 reg [5:0] tid;
25348 integer junk;
25349
25350 begin
25351`ifdef AXIS_EMUL_COSIM
25352//Do Nothing
25353`else
25354`ifdef GATESIM
25355//Do Nothing
25356`else
25357`ifdef CORE_2
25358 if (`PARGS.nas_check_on) begin
25359 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
25360 tid = 1
25361; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25362 end
25363`endif
25364
25365`endif
25366
25367`endif
25368
25369 end
25370 endtask
25371
25372
25373 task slam_NonZeroTsbConfig1_core2_thread2;
25374 input [63:0] value;
25375 reg [5:0] tid;
25376 integer junk;
25377
25378 begin
25379`ifdef AXIS_EMUL_COSIM
25380//Do Nothing
25381`else
25382`ifdef GATESIM
25383//Do Nothing
25384`else
25385`ifdef CORE_2
25386 if (`PARGS.nas_check_on) begin
25387 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
25388 tid = 2
25389; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25390 end
25391`endif
25392
25393`endif
25394
25395`endif
25396
25397 end
25398 endtask
25399
25400
25401 task slam_NonZeroTsbConfig1_core2_thread3;
25402 input [63:0] value;
25403 reg [5:0] tid;
25404 integer junk;
25405
25406 begin
25407`ifdef AXIS_EMUL_COSIM
25408//Do Nothing
25409`else
25410`ifdef GATESIM
25411//Do Nothing
25412`else
25413`ifdef CORE_2
25414 if (`PARGS.nas_check_on) begin
25415 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
25416 tid = 3
25417; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25418 end
25419`endif
25420
25421`endif
25422
25423`endif
25424
25425 end
25426 endtask
25427
25428
25429 task slam_NonZeroTsbConfig1_core2_thread4;
25430 input [63:0] value;
25431 reg [5:0] tid;
25432 integer junk;
25433
25434 begin
25435`ifdef AXIS_EMUL_COSIM
25436//Do Nothing
25437`else
25438`ifdef GATESIM
25439//Do Nothing
25440`else
25441`ifdef CORE_2
25442 if (`PARGS.nas_check_on) begin
25443 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
25444 tid = 4
25445; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25446 end
25447`endif
25448
25449`endif
25450
25451`endif
25452
25453 end
25454 endtask
25455
25456
25457 task slam_NonZeroTsbConfig1_core2_thread5;
25458 input [63:0] value;
25459 reg [5:0] tid;
25460 integer junk;
25461
25462 begin
25463`ifdef AXIS_EMUL_COSIM
25464//Do Nothing
25465`else
25466`ifdef GATESIM
25467//Do Nothing
25468`else
25469`ifdef CORE_2
25470 if (`PARGS.nas_check_on) begin
25471 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
25472 tid = 5
25473; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25474 end
25475`endif
25476
25477`endif
25478
25479`endif
25480
25481 end
25482 endtask
25483
25484
25485 task slam_NonZeroTsbConfig1_core2_thread6;
25486 input [63:0] value;
25487 reg [5:0] tid;
25488 integer junk;
25489
25490 begin
25491`ifdef AXIS_EMUL_COSIM
25492//Do Nothing
25493`else
25494`ifdef GATESIM
25495//Do Nothing
25496`else
25497`ifdef CORE_2
25498 if (`PARGS.nas_check_on) begin
25499 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
25500 tid = 6
25501; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25502 end
25503`endif
25504
25505`endif
25506
25507`endif
25508
25509 end
25510 endtask
25511
25512
25513 task slam_NonZeroTsbConfig1_core2_thread7;
25514 input [63:0] value;
25515 reg [5:0] tid;
25516 integer junk;
25517
25518 begin
25519`ifdef AXIS_EMUL_COSIM
25520//Do Nothing
25521`else
25522`ifdef GATESIM
25523//Do Nothing
25524`else
25525`ifdef CORE_2
25526 if (`PARGS.nas_check_on) begin
25527 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
25528 tid = 7
25529; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25530 end
25531`endif
25532
25533`endif
25534
25535`endif
25536
25537 end
25538 endtask
25539
25540
25541 task slam_NonZeroTsbConfig1_core3_thread0;
25542 input [63:0] value;
25543 reg [5:0] tid;
25544 integer junk;
25545
25546 begin
25547`ifdef AXIS_EMUL_COSIM
25548//Do Nothing
25549`else
25550`ifdef GATESIM
25551//Do Nothing
25552`else
25553`ifdef CORE_3
25554 if (`PARGS.nas_check_on) begin
25555 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
25556 tid = 0
25557; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25558 end
25559`endif
25560
25561`endif
25562
25563`endif
25564
25565 end
25566 endtask
25567
25568
25569 task slam_NonZeroTsbConfig1_core3_thread1;
25570 input [63:0] value;
25571 reg [5:0] tid;
25572 integer junk;
25573
25574 begin
25575`ifdef AXIS_EMUL_COSIM
25576//Do Nothing
25577`else
25578`ifdef GATESIM
25579//Do Nothing
25580`else
25581`ifdef CORE_3
25582 if (`PARGS.nas_check_on) begin
25583 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
25584 tid = 1
25585; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25586 end
25587`endif
25588
25589`endif
25590
25591`endif
25592
25593 end
25594 endtask
25595
25596
25597 task slam_NonZeroTsbConfig1_core3_thread2;
25598 input [63:0] value;
25599 reg [5:0] tid;
25600 integer junk;
25601
25602 begin
25603`ifdef AXIS_EMUL_COSIM
25604//Do Nothing
25605`else
25606`ifdef GATESIM
25607//Do Nothing
25608`else
25609`ifdef CORE_3
25610 if (`PARGS.nas_check_on) begin
25611 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
25612 tid = 2
25613; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25614 end
25615`endif
25616
25617`endif
25618
25619`endif
25620
25621 end
25622 endtask
25623
25624
25625 task slam_NonZeroTsbConfig1_core3_thread3;
25626 input [63:0] value;
25627 reg [5:0] tid;
25628 integer junk;
25629
25630 begin
25631`ifdef AXIS_EMUL_COSIM
25632//Do Nothing
25633`else
25634`ifdef GATESIM
25635//Do Nothing
25636`else
25637`ifdef CORE_3
25638 if (`PARGS.nas_check_on) begin
25639 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
25640 tid = 3
25641; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25642 end
25643`endif
25644
25645`endif
25646
25647`endif
25648
25649 end
25650 endtask
25651
25652
25653 task slam_NonZeroTsbConfig1_core3_thread4;
25654 input [63:0] value;
25655 reg [5:0] tid;
25656 integer junk;
25657
25658 begin
25659`ifdef AXIS_EMUL_COSIM
25660//Do Nothing
25661`else
25662`ifdef GATESIM
25663//Do Nothing
25664`else
25665`ifdef CORE_3
25666 if (`PARGS.nas_check_on) begin
25667 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
25668 tid = 4
25669; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25670 end
25671`endif
25672
25673`endif
25674
25675`endif
25676
25677 end
25678 endtask
25679
25680
25681 task slam_NonZeroTsbConfig1_core3_thread5;
25682 input [63:0] value;
25683 reg [5:0] tid;
25684 integer junk;
25685
25686 begin
25687`ifdef AXIS_EMUL_COSIM
25688//Do Nothing
25689`else
25690`ifdef GATESIM
25691//Do Nothing
25692`else
25693`ifdef CORE_3
25694 if (`PARGS.nas_check_on) begin
25695 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
25696 tid = 5
25697; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25698 end
25699`endif
25700
25701`endif
25702
25703`endif
25704
25705 end
25706 endtask
25707
25708
25709 task slam_NonZeroTsbConfig1_core3_thread6;
25710 input [63:0] value;
25711 reg [5:0] tid;
25712 integer junk;
25713
25714 begin
25715`ifdef AXIS_EMUL_COSIM
25716//Do Nothing
25717`else
25718`ifdef GATESIM
25719//Do Nothing
25720`else
25721`ifdef CORE_3
25722 if (`PARGS.nas_check_on) begin
25723 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
25724 tid = 6
25725; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25726 end
25727`endif
25728
25729`endif
25730
25731`endif
25732
25733 end
25734 endtask
25735
25736
25737 task slam_NonZeroTsbConfig1_core3_thread7;
25738 input [63:0] value;
25739 reg [5:0] tid;
25740 integer junk;
25741
25742 begin
25743`ifdef AXIS_EMUL_COSIM
25744//Do Nothing
25745`else
25746`ifdef GATESIM
25747//Do Nothing
25748`else
25749`ifdef CORE_3
25750 if (`PARGS.nas_check_on) begin
25751 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
25752 tid = 7
25753; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25754 end
25755`endif
25756
25757`endif
25758
25759`endif
25760
25761 end
25762 endtask
25763
25764
25765 task slam_NonZeroTsbConfig1_core4_thread0;
25766 input [63:0] value;
25767 reg [5:0] tid;
25768 integer junk;
25769
25770 begin
25771`ifdef AXIS_EMUL_COSIM
25772//Do Nothing
25773`else
25774`ifdef GATESIM
25775//Do Nothing
25776`else
25777`ifdef CORE_4
25778 if (`PARGS.nas_check_on) begin
25779 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
25780 tid = 0
25781; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25782 end
25783`endif
25784
25785`endif
25786
25787`endif
25788
25789 end
25790 endtask
25791
25792
25793 task slam_NonZeroTsbConfig1_core4_thread1;
25794 input [63:0] value;
25795 reg [5:0] tid;
25796 integer junk;
25797
25798 begin
25799`ifdef AXIS_EMUL_COSIM
25800//Do Nothing
25801`else
25802`ifdef GATESIM
25803//Do Nothing
25804`else
25805`ifdef CORE_4
25806 if (`PARGS.nas_check_on) begin
25807 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
25808 tid = 1
25809; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25810 end
25811`endif
25812
25813`endif
25814
25815`endif
25816
25817 end
25818 endtask
25819
25820
25821 task slam_NonZeroTsbConfig1_core4_thread2;
25822 input [63:0] value;
25823 reg [5:0] tid;
25824 integer junk;
25825
25826 begin
25827`ifdef AXIS_EMUL_COSIM
25828//Do Nothing
25829`else
25830`ifdef GATESIM
25831//Do Nothing
25832`else
25833`ifdef CORE_4
25834 if (`PARGS.nas_check_on) begin
25835 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
25836 tid = 2
25837; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25838 end
25839`endif
25840
25841`endif
25842
25843`endif
25844
25845 end
25846 endtask
25847
25848
25849 task slam_NonZeroTsbConfig1_core4_thread3;
25850 input [63:0] value;
25851 reg [5:0] tid;
25852 integer junk;
25853
25854 begin
25855`ifdef AXIS_EMUL_COSIM
25856//Do Nothing
25857`else
25858`ifdef GATESIM
25859//Do Nothing
25860`else
25861`ifdef CORE_4
25862 if (`PARGS.nas_check_on) begin
25863 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
25864 tid = 3
25865; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25866 end
25867`endif
25868
25869`endif
25870
25871`endif
25872
25873 end
25874 endtask
25875
25876
25877 task slam_NonZeroTsbConfig1_core4_thread4;
25878 input [63:0] value;
25879 reg [5:0] tid;
25880 integer junk;
25881
25882 begin
25883`ifdef AXIS_EMUL_COSIM
25884//Do Nothing
25885`else
25886`ifdef GATESIM
25887//Do Nothing
25888`else
25889`ifdef CORE_4
25890 if (`PARGS.nas_check_on) begin
25891 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
25892 tid = 4
25893; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25894 end
25895`endif
25896
25897`endif
25898
25899`endif
25900
25901 end
25902 endtask
25903
25904
25905 task slam_NonZeroTsbConfig1_core4_thread5;
25906 input [63:0] value;
25907 reg [5:0] tid;
25908 integer junk;
25909
25910 begin
25911`ifdef AXIS_EMUL_COSIM
25912//Do Nothing
25913`else
25914`ifdef GATESIM
25915//Do Nothing
25916`else
25917`ifdef CORE_4
25918 if (`PARGS.nas_check_on) begin
25919 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
25920 tid = 5
25921; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25922 end
25923`endif
25924
25925`endif
25926
25927`endif
25928
25929 end
25930 endtask
25931
25932
25933 task slam_NonZeroTsbConfig1_core4_thread6;
25934 input [63:0] value;
25935 reg [5:0] tid;
25936 integer junk;
25937
25938 begin
25939`ifdef AXIS_EMUL_COSIM
25940//Do Nothing
25941`else
25942`ifdef GATESIM
25943//Do Nothing
25944`else
25945`ifdef CORE_4
25946 if (`PARGS.nas_check_on) begin
25947 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
25948 tid = 6
25949; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25950 end
25951`endif
25952
25953`endif
25954
25955`endif
25956
25957 end
25958 endtask
25959
25960
25961 task slam_NonZeroTsbConfig1_core4_thread7;
25962 input [63:0] value;
25963 reg [5:0] tid;
25964 integer junk;
25965
25966 begin
25967`ifdef AXIS_EMUL_COSIM
25968//Do Nothing
25969`else
25970`ifdef GATESIM
25971//Do Nothing
25972`else
25973`ifdef CORE_4
25974 if (`PARGS.nas_check_on) begin
25975 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
25976 tid = 7
25977; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
25978 end
25979`endif
25980
25981`endif
25982
25983`endif
25984
25985 end
25986 endtask
25987
25988
25989 task slam_NonZeroTsbConfig1_core5_thread0;
25990 input [63:0] value;
25991 reg [5:0] tid;
25992 integer junk;
25993
25994 begin
25995`ifdef AXIS_EMUL_COSIM
25996//Do Nothing
25997`else
25998`ifdef GATESIM
25999//Do Nothing
26000`else
26001`ifdef CORE_5
26002 if (`PARGS.nas_check_on) begin
26003 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
26004 tid = 0
26005; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26006 end
26007`endif
26008
26009`endif
26010
26011`endif
26012
26013 end
26014 endtask
26015
26016
26017 task slam_NonZeroTsbConfig1_core5_thread1;
26018 input [63:0] value;
26019 reg [5:0] tid;
26020 integer junk;
26021
26022 begin
26023`ifdef AXIS_EMUL_COSIM
26024//Do Nothing
26025`else
26026`ifdef GATESIM
26027//Do Nothing
26028`else
26029`ifdef CORE_5
26030 if (`PARGS.nas_check_on) begin
26031 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
26032 tid = 1
26033; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26034 end
26035`endif
26036
26037`endif
26038
26039`endif
26040
26041 end
26042 endtask
26043
26044
26045 task slam_NonZeroTsbConfig1_core5_thread2;
26046 input [63:0] value;
26047 reg [5:0] tid;
26048 integer junk;
26049
26050 begin
26051`ifdef AXIS_EMUL_COSIM
26052//Do Nothing
26053`else
26054`ifdef GATESIM
26055//Do Nothing
26056`else
26057`ifdef CORE_5
26058 if (`PARGS.nas_check_on) begin
26059 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
26060 tid = 2
26061; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26062 end
26063`endif
26064
26065`endif
26066
26067`endif
26068
26069 end
26070 endtask
26071
26072
26073 task slam_NonZeroTsbConfig1_core5_thread3;
26074 input [63:0] value;
26075 reg [5:0] tid;
26076 integer junk;
26077
26078 begin
26079`ifdef AXIS_EMUL_COSIM
26080//Do Nothing
26081`else
26082`ifdef GATESIM
26083//Do Nothing
26084`else
26085`ifdef CORE_5
26086 if (`PARGS.nas_check_on) begin
26087 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
26088 tid = 3
26089; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26090 end
26091`endif
26092
26093`endif
26094
26095`endif
26096
26097 end
26098 endtask
26099
26100
26101 task slam_NonZeroTsbConfig1_core5_thread4;
26102 input [63:0] value;
26103 reg [5:0] tid;
26104 integer junk;
26105
26106 begin
26107`ifdef AXIS_EMUL_COSIM
26108//Do Nothing
26109`else
26110`ifdef GATESIM
26111//Do Nothing
26112`else
26113`ifdef CORE_5
26114 if (`PARGS.nas_check_on) begin
26115 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
26116 tid = 4
26117; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26118 end
26119`endif
26120
26121`endif
26122
26123`endif
26124
26125 end
26126 endtask
26127
26128
26129 task slam_NonZeroTsbConfig1_core5_thread5;
26130 input [63:0] value;
26131 reg [5:0] tid;
26132 integer junk;
26133
26134 begin
26135`ifdef AXIS_EMUL_COSIM
26136//Do Nothing
26137`else
26138`ifdef GATESIM
26139//Do Nothing
26140`else
26141`ifdef CORE_5
26142 if (`PARGS.nas_check_on) begin
26143 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
26144 tid = 5
26145; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26146 end
26147`endif
26148
26149`endif
26150
26151`endif
26152
26153 end
26154 endtask
26155
26156
26157 task slam_NonZeroTsbConfig1_core5_thread6;
26158 input [63:0] value;
26159 reg [5:0] tid;
26160 integer junk;
26161
26162 begin
26163`ifdef AXIS_EMUL_COSIM
26164//Do Nothing
26165`else
26166`ifdef GATESIM
26167//Do Nothing
26168`else
26169`ifdef CORE_5
26170 if (`PARGS.nas_check_on) begin
26171 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
26172 tid = 6
26173; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26174 end
26175`endif
26176
26177`endif
26178
26179`endif
26180
26181 end
26182 endtask
26183
26184
26185 task slam_NonZeroTsbConfig1_core5_thread7;
26186 input [63:0] value;
26187 reg [5:0] tid;
26188 integer junk;
26189
26190 begin
26191`ifdef AXIS_EMUL_COSIM
26192//Do Nothing
26193`else
26194`ifdef GATESIM
26195//Do Nothing
26196`else
26197`ifdef CORE_5
26198 if (`PARGS.nas_check_on) begin
26199 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
26200 tid = 7
26201; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26202 end
26203`endif
26204
26205`endif
26206
26207`endif
26208
26209 end
26210 endtask
26211
26212
26213 task slam_NonZeroTsbConfig1_core6_thread0;
26214 input [63:0] value;
26215 reg [5:0] tid;
26216 integer junk;
26217
26218 begin
26219`ifdef AXIS_EMUL_COSIM
26220//Do Nothing
26221`else
26222`ifdef GATESIM
26223//Do Nothing
26224`else
26225`ifdef CORE_6
26226 if (`PARGS.nas_check_on) begin
26227 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
26228 tid = 0
26229; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26230 end
26231`endif
26232
26233`endif
26234
26235`endif
26236
26237 end
26238 endtask
26239
26240
26241 task slam_NonZeroTsbConfig1_core6_thread1;
26242 input [63:0] value;
26243 reg [5:0] tid;
26244 integer junk;
26245
26246 begin
26247`ifdef AXIS_EMUL_COSIM
26248//Do Nothing
26249`else
26250`ifdef GATESIM
26251//Do Nothing
26252`else
26253`ifdef CORE_6
26254 if (`PARGS.nas_check_on) begin
26255 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
26256 tid = 1
26257; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26258 end
26259`endif
26260
26261`endif
26262
26263`endif
26264
26265 end
26266 endtask
26267
26268
26269 task slam_NonZeroTsbConfig1_core6_thread2;
26270 input [63:0] value;
26271 reg [5:0] tid;
26272 integer junk;
26273
26274 begin
26275`ifdef AXIS_EMUL_COSIM
26276//Do Nothing
26277`else
26278`ifdef GATESIM
26279//Do Nothing
26280`else
26281`ifdef CORE_6
26282 if (`PARGS.nas_check_on) begin
26283 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
26284 tid = 2
26285; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26286 end
26287`endif
26288
26289`endif
26290
26291`endif
26292
26293 end
26294 endtask
26295
26296
26297 task slam_NonZeroTsbConfig1_core6_thread3;
26298 input [63:0] value;
26299 reg [5:0] tid;
26300 integer junk;
26301
26302 begin
26303`ifdef AXIS_EMUL_COSIM
26304//Do Nothing
26305`else
26306`ifdef GATESIM
26307//Do Nothing
26308`else
26309`ifdef CORE_6
26310 if (`PARGS.nas_check_on) begin
26311 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
26312 tid = 3
26313; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26314 end
26315`endif
26316
26317`endif
26318
26319`endif
26320
26321 end
26322 endtask
26323
26324
26325 task slam_NonZeroTsbConfig1_core6_thread4;
26326 input [63:0] value;
26327 reg [5:0] tid;
26328 integer junk;
26329
26330 begin
26331`ifdef AXIS_EMUL_COSIM
26332//Do Nothing
26333`else
26334`ifdef GATESIM
26335//Do Nothing
26336`else
26337`ifdef CORE_6
26338 if (`PARGS.nas_check_on) begin
26339 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
26340 tid = 4
26341; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26342 end
26343`endif
26344
26345`endif
26346
26347`endif
26348
26349 end
26350 endtask
26351
26352
26353 task slam_NonZeroTsbConfig1_core6_thread5;
26354 input [63:0] value;
26355 reg [5:0] tid;
26356 integer junk;
26357
26358 begin
26359`ifdef AXIS_EMUL_COSIM
26360//Do Nothing
26361`else
26362`ifdef GATESIM
26363//Do Nothing
26364`else
26365`ifdef CORE_6
26366 if (`PARGS.nas_check_on) begin
26367 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
26368 tid = 5
26369; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26370 end
26371`endif
26372
26373`endif
26374
26375`endif
26376
26377 end
26378 endtask
26379
26380
26381 task slam_NonZeroTsbConfig1_core6_thread6;
26382 input [63:0] value;
26383 reg [5:0] tid;
26384 integer junk;
26385
26386 begin
26387`ifdef AXIS_EMUL_COSIM
26388//Do Nothing
26389`else
26390`ifdef GATESIM
26391//Do Nothing
26392`else
26393`ifdef CORE_6
26394 if (`PARGS.nas_check_on) begin
26395 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
26396 tid = 6
26397; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26398 end
26399`endif
26400
26401`endif
26402
26403`endif
26404
26405 end
26406 endtask
26407
26408
26409 task slam_NonZeroTsbConfig1_core6_thread7;
26410 input [63:0] value;
26411 reg [5:0] tid;
26412 integer junk;
26413
26414 begin
26415`ifdef AXIS_EMUL_COSIM
26416//Do Nothing
26417`else
26418`ifdef GATESIM
26419//Do Nothing
26420`else
26421`ifdef CORE_6
26422 if (`PARGS.nas_check_on) begin
26423 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
26424 tid = 7
26425; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26426 end
26427`endif
26428
26429`endif
26430
26431`endif
26432
26433 end
26434 endtask
26435
26436
26437 task slam_NonZeroTsbConfig1_core7_thread0;
26438 input [63:0] value;
26439 reg [5:0] tid;
26440 integer junk;
26441
26442 begin
26443`ifdef AXIS_EMUL_COSIM
26444//Do Nothing
26445`else
26446`ifdef GATESIM
26447//Do Nothing
26448`else
26449`ifdef CORE_7
26450 if (`PARGS.nas_check_on) begin
26451 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
26452 tid = 0
26453; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26454 end
26455`endif
26456
26457`endif
26458
26459`endif
26460
26461 end
26462 endtask
26463
26464
26465 task slam_NonZeroTsbConfig1_core7_thread1;
26466 input [63:0] value;
26467 reg [5:0] tid;
26468 integer junk;
26469
26470 begin
26471`ifdef AXIS_EMUL_COSIM
26472//Do Nothing
26473`else
26474`ifdef GATESIM
26475//Do Nothing
26476`else
26477`ifdef CORE_7
26478 if (`PARGS.nas_check_on) begin
26479 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
26480 tid = 1
26481; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26482 end
26483`endif
26484
26485`endif
26486
26487`endif
26488
26489 end
26490 endtask
26491
26492
26493 task slam_NonZeroTsbConfig1_core7_thread2;
26494 input [63:0] value;
26495 reg [5:0] tid;
26496 integer junk;
26497
26498 begin
26499`ifdef AXIS_EMUL_COSIM
26500//Do Nothing
26501`else
26502`ifdef GATESIM
26503//Do Nothing
26504`else
26505`ifdef CORE_7
26506 if (`PARGS.nas_check_on) begin
26507 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
26508 tid = 2
26509; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26510 end
26511`endif
26512
26513`endif
26514
26515`endif
26516
26517 end
26518 endtask
26519
26520
26521 task slam_NonZeroTsbConfig1_core7_thread3;
26522 input [63:0] value;
26523 reg [5:0] tid;
26524 integer junk;
26525
26526 begin
26527`ifdef AXIS_EMUL_COSIM
26528//Do Nothing
26529`else
26530`ifdef GATESIM
26531//Do Nothing
26532`else
26533`ifdef CORE_7
26534 if (`PARGS.nas_check_on) begin
26535 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
26536 tid = 3
26537; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26538 end
26539`endif
26540
26541`endif
26542
26543`endif
26544
26545 end
26546 endtask
26547
26548
26549 task slam_NonZeroTsbConfig1_core7_thread4;
26550 input [63:0] value;
26551 reg [5:0] tid;
26552 integer junk;
26553
26554 begin
26555`ifdef AXIS_EMUL_COSIM
26556//Do Nothing
26557`else
26558`ifdef GATESIM
26559//Do Nothing
26560`else
26561`ifdef CORE_7
26562 if (`PARGS.nas_check_on) begin
26563 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
26564 tid = 4
26565; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26566 end
26567`endif
26568
26569`endif
26570
26571`endif
26572
26573 end
26574 endtask
26575
26576
26577 task slam_NonZeroTsbConfig1_core7_thread5;
26578 input [63:0] value;
26579 reg [5:0] tid;
26580 integer junk;
26581
26582 begin
26583`ifdef AXIS_EMUL_COSIM
26584//Do Nothing
26585`else
26586`ifdef GATESIM
26587//Do Nothing
26588`else
26589`ifdef CORE_7
26590 if (`PARGS.nas_check_on) begin
26591 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
26592 tid = 5
26593; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26594 end
26595`endif
26596
26597`endif
26598
26599`endif
26600
26601 end
26602 endtask
26603
26604
26605 task slam_NonZeroTsbConfig1_core7_thread6;
26606 input [63:0] value;
26607 reg [5:0] tid;
26608 integer junk;
26609
26610 begin
26611`ifdef AXIS_EMUL_COSIM
26612//Do Nothing
26613`else
26614`ifdef GATESIM
26615//Do Nothing
26616`else
26617`ifdef CORE_7
26618 if (`PARGS.nas_check_on) begin
26619 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
26620 tid = 6
26621; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26622 end
26623`endif
26624
26625`endif
26626
26627`endif
26628
26629 end
26630 endtask
26631
26632
26633 task slam_NonZeroTsbConfig1_core7_thread7;
26634 input [63:0] value;
26635 reg [5:0] tid;
26636 integer junk;
26637
26638 begin
26639`ifdef AXIS_EMUL_COSIM
26640//Do Nothing
26641`else
26642`ifdef GATESIM
26643//Do Nothing
26644`else
26645`ifdef CORE_7
26646 if (`PARGS.nas_check_on) begin
26647 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
26648 tid = 7
26649; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h38, value);
26650 end
26651`endif
26652
26653`endif
26654
26655`endif
26656
26657 end
26658 endtask
26659
26660
26661 task slam_NonZeroTsbConfig2_core0_thread0;
26662 input [63:0] value;
26663 reg [5:0] tid;
26664 integer junk;
26665
26666 begin
26667`ifdef AXIS_EMUL_COSIM
26668//Do Nothing
26669`else
26670`ifdef GATESIM
26671//Do Nothing
26672`else
26673`ifdef CORE_0
26674 if (`PARGS.nas_check_on) begin
26675 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
26676 tid = 0
26677; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26678 end
26679`endif
26680
26681`endif
26682
26683`endif
26684
26685 end
26686 endtask
26687
26688
26689 task slam_NonZeroTsbConfig2_core0_thread1;
26690 input [63:0] value;
26691 reg [5:0] tid;
26692 integer junk;
26693
26694 begin
26695`ifdef AXIS_EMUL_COSIM
26696//Do Nothing
26697`else
26698`ifdef GATESIM
26699//Do Nothing
26700`else
26701`ifdef CORE_0
26702 if (`PARGS.nas_check_on) begin
26703 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
26704 tid = 1
26705; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26706 end
26707`endif
26708
26709`endif
26710
26711`endif
26712
26713 end
26714 endtask
26715
26716
26717 task slam_NonZeroTsbConfig2_core0_thread2;
26718 input [63:0] value;
26719 reg [5:0] tid;
26720 integer junk;
26721
26722 begin
26723`ifdef AXIS_EMUL_COSIM
26724//Do Nothing
26725`else
26726`ifdef GATESIM
26727//Do Nothing
26728`else
26729`ifdef CORE_0
26730 if (`PARGS.nas_check_on) begin
26731 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
26732 tid = 2
26733; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26734 end
26735`endif
26736
26737`endif
26738
26739`endif
26740
26741 end
26742 endtask
26743
26744
26745 task slam_NonZeroTsbConfig2_core0_thread3;
26746 input [63:0] value;
26747 reg [5:0] tid;
26748 integer junk;
26749
26750 begin
26751`ifdef AXIS_EMUL_COSIM
26752//Do Nothing
26753`else
26754`ifdef GATESIM
26755//Do Nothing
26756`else
26757`ifdef CORE_0
26758 if (`PARGS.nas_check_on) begin
26759 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
26760 tid = 3
26761; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26762 end
26763`endif
26764
26765`endif
26766
26767`endif
26768
26769 end
26770 endtask
26771
26772
26773 task slam_NonZeroTsbConfig2_core0_thread4;
26774 input [63:0] value;
26775 reg [5:0] tid;
26776 integer junk;
26777
26778 begin
26779`ifdef AXIS_EMUL_COSIM
26780//Do Nothing
26781`else
26782`ifdef GATESIM
26783//Do Nothing
26784`else
26785`ifdef CORE_0
26786 if (`PARGS.nas_check_on) begin
26787 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
26788 tid = 4
26789; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26790 end
26791`endif
26792
26793`endif
26794
26795`endif
26796
26797 end
26798 endtask
26799
26800
26801 task slam_NonZeroTsbConfig2_core0_thread5;
26802 input [63:0] value;
26803 reg [5:0] tid;
26804 integer junk;
26805
26806 begin
26807`ifdef AXIS_EMUL_COSIM
26808//Do Nothing
26809`else
26810`ifdef GATESIM
26811//Do Nothing
26812`else
26813`ifdef CORE_0
26814 if (`PARGS.nas_check_on) begin
26815 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
26816 tid = 5
26817; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26818 end
26819`endif
26820
26821`endif
26822
26823`endif
26824
26825 end
26826 endtask
26827
26828
26829 task slam_NonZeroTsbConfig2_core0_thread6;
26830 input [63:0] value;
26831 reg [5:0] tid;
26832 integer junk;
26833
26834 begin
26835`ifdef AXIS_EMUL_COSIM
26836//Do Nothing
26837`else
26838`ifdef GATESIM
26839//Do Nothing
26840`else
26841`ifdef CORE_0
26842 if (`PARGS.nas_check_on) begin
26843 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
26844 tid = 6
26845; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26846 end
26847`endif
26848
26849`endif
26850
26851`endif
26852
26853 end
26854 endtask
26855
26856
26857 task slam_NonZeroTsbConfig2_core0_thread7;
26858 input [63:0] value;
26859 reg [5:0] tid;
26860 integer junk;
26861
26862 begin
26863`ifdef AXIS_EMUL_COSIM
26864//Do Nothing
26865`else
26866`ifdef GATESIM
26867//Do Nothing
26868`else
26869`ifdef CORE_0
26870 if (`PARGS.nas_check_on) begin
26871 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
26872 tid = 7
26873; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26874 end
26875`endif
26876
26877`endif
26878
26879`endif
26880
26881 end
26882 endtask
26883
26884
26885 task slam_NonZeroTsbConfig2_core1_thread0;
26886 input [63:0] value;
26887 reg [5:0] tid;
26888 integer junk;
26889
26890 begin
26891`ifdef AXIS_EMUL_COSIM
26892//Do Nothing
26893`else
26894`ifdef GATESIM
26895//Do Nothing
26896`else
26897`ifdef CORE_1
26898 if (`PARGS.nas_check_on) begin
26899 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
26900 tid = 0
26901; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26902 end
26903`endif
26904
26905`endif
26906
26907`endif
26908
26909 end
26910 endtask
26911
26912
26913 task slam_NonZeroTsbConfig2_core1_thread1;
26914 input [63:0] value;
26915 reg [5:0] tid;
26916 integer junk;
26917
26918 begin
26919`ifdef AXIS_EMUL_COSIM
26920//Do Nothing
26921`else
26922`ifdef GATESIM
26923//Do Nothing
26924`else
26925`ifdef CORE_1
26926 if (`PARGS.nas_check_on) begin
26927 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
26928 tid = 1
26929; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26930 end
26931`endif
26932
26933`endif
26934
26935`endif
26936
26937 end
26938 endtask
26939
26940
26941 task slam_NonZeroTsbConfig2_core1_thread2;
26942 input [63:0] value;
26943 reg [5:0] tid;
26944 integer junk;
26945
26946 begin
26947`ifdef AXIS_EMUL_COSIM
26948//Do Nothing
26949`else
26950`ifdef GATESIM
26951//Do Nothing
26952`else
26953`ifdef CORE_1
26954 if (`PARGS.nas_check_on) begin
26955 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
26956 tid = 2
26957; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26958 end
26959`endif
26960
26961`endif
26962
26963`endif
26964
26965 end
26966 endtask
26967
26968
26969 task slam_NonZeroTsbConfig2_core1_thread3;
26970 input [63:0] value;
26971 reg [5:0] tid;
26972 integer junk;
26973
26974 begin
26975`ifdef AXIS_EMUL_COSIM
26976//Do Nothing
26977`else
26978`ifdef GATESIM
26979//Do Nothing
26980`else
26981`ifdef CORE_1
26982 if (`PARGS.nas_check_on) begin
26983 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
26984 tid = 3
26985; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
26986 end
26987`endif
26988
26989`endif
26990
26991`endif
26992
26993 end
26994 endtask
26995
26996
26997 task slam_NonZeroTsbConfig2_core1_thread4;
26998 input [63:0] value;
26999 reg [5:0] tid;
27000 integer junk;
27001
27002 begin
27003`ifdef AXIS_EMUL_COSIM
27004//Do Nothing
27005`else
27006`ifdef GATESIM
27007//Do Nothing
27008`else
27009`ifdef CORE_1
27010 if (`PARGS.nas_check_on) begin
27011 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
27012 tid = 4
27013; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27014 end
27015`endif
27016
27017`endif
27018
27019`endif
27020
27021 end
27022 endtask
27023
27024
27025 task slam_NonZeroTsbConfig2_core1_thread5;
27026 input [63:0] value;
27027 reg [5:0] tid;
27028 integer junk;
27029
27030 begin
27031`ifdef AXIS_EMUL_COSIM
27032//Do Nothing
27033`else
27034`ifdef GATESIM
27035//Do Nothing
27036`else
27037`ifdef CORE_1
27038 if (`PARGS.nas_check_on) begin
27039 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
27040 tid = 5
27041; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27042 end
27043`endif
27044
27045`endif
27046
27047`endif
27048
27049 end
27050 endtask
27051
27052
27053 task slam_NonZeroTsbConfig2_core1_thread6;
27054 input [63:0] value;
27055 reg [5:0] tid;
27056 integer junk;
27057
27058 begin
27059`ifdef AXIS_EMUL_COSIM
27060//Do Nothing
27061`else
27062`ifdef GATESIM
27063//Do Nothing
27064`else
27065`ifdef CORE_1
27066 if (`PARGS.nas_check_on) begin
27067 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
27068 tid = 6
27069; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27070 end
27071`endif
27072
27073`endif
27074
27075`endif
27076
27077 end
27078 endtask
27079
27080
27081 task slam_NonZeroTsbConfig2_core1_thread7;
27082 input [63:0] value;
27083 reg [5:0] tid;
27084 integer junk;
27085
27086 begin
27087`ifdef AXIS_EMUL_COSIM
27088//Do Nothing
27089`else
27090`ifdef GATESIM
27091//Do Nothing
27092`else
27093`ifdef CORE_1
27094 if (`PARGS.nas_check_on) begin
27095 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
27096 tid = 7
27097; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27098 end
27099`endif
27100
27101`endif
27102
27103`endif
27104
27105 end
27106 endtask
27107
27108
27109 task slam_NonZeroTsbConfig2_core2_thread0;
27110 input [63:0] value;
27111 reg [5:0] tid;
27112 integer junk;
27113
27114 begin
27115`ifdef AXIS_EMUL_COSIM
27116//Do Nothing
27117`else
27118`ifdef GATESIM
27119//Do Nothing
27120`else
27121`ifdef CORE_2
27122 if (`PARGS.nas_check_on) begin
27123 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
27124 tid = 0
27125; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27126 end
27127`endif
27128
27129`endif
27130
27131`endif
27132
27133 end
27134 endtask
27135
27136
27137 task slam_NonZeroTsbConfig2_core2_thread1;
27138 input [63:0] value;
27139 reg [5:0] tid;
27140 integer junk;
27141
27142 begin
27143`ifdef AXIS_EMUL_COSIM
27144//Do Nothing
27145`else
27146`ifdef GATESIM
27147//Do Nothing
27148`else
27149`ifdef CORE_2
27150 if (`PARGS.nas_check_on) begin
27151 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
27152 tid = 1
27153; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27154 end
27155`endif
27156
27157`endif
27158
27159`endif
27160
27161 end
27162 endtask
27163
27164
27165 task slam_NonZeroTsbConfig2_core2_thread2;
27166 input [63:0] value;
27167 reg [5:0] tid;
27168 integer junk;
27169
27170 begin
27171`ifdef AXIS_EMUL_COSIM
27172//Do Nothing
27173`else
27174`ifdef GATESIM
27175//Do Nothing
27176`else
27177`ifdef CORE_2
27178 if (`PARGS.nas_check_on) begin
27179 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
27180 tid = 2
27181; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27182 end
27183`endif
27184
27185`endif
27186
27187`endif
27188
27189 end
27190 endtask
27191
27192
27193 task slam_NonZeroTsbConfig2_core2_thread3;
27194 input [63:0] value;
27195 reg [5:0] tid;
27196 integer junk;
27197
27198 begin
27199`ifdef AXIS_EMUL_COSIM
27200//Do Nothing
27201`else
27202`ifdef GATESIM
27203//Do Nothing
27204`else
27205`ifdef CORE_2
27206 if (`PARGS.nas_check_on) begin
27207 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
27208 tid = 3
27209; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27210 end
27211`endif
27212
27213`endif
27214
27215`endif
27216
27217 end
27218 endtask
27219
27220
27221 task slam_NonZeroTsbConfig2_core2_thread4;
27222 input [63:0] value;
27223 reg [5:0] tid;
27224 integer junk;
27225
27226 begin
27227`ifdef AXIS_EMUL_COSIM
27228//Do Nothing
27229`else
27230`ifdef GATESIM
27231//Do Nothing
27232`else
27233`ifdef CORE_2
27234 if (`PARGS.nas_check_on) begin
27235 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
27236 tid = 4
27237; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27238 end
27239`endif
27240
27241`endif
27242
27243`endif
27244
27245 end
27246 endtask
27247
27248
27249 task slam_NonZeroTsbConfig2_core2_thread5;
27250 input [63:0] value;
27251 reg [5:0] tid;
27252 integer junk;
27253
27254 begin
27255`ifdef AXIS_EMUL_COSIM
27256//Do Nothing
27257`else
27258`ifdef GATESIM
27259//Do Nothing
27260`else
27261`ifdef CORE_2
27262 if (`PARGS.nas_check_on) begin
27263 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
27264 tid = 5
27265; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27266 end
27267`endif
27268
27269`endif
27270
27271`endif
27272
27273 end
27274 endtask
27275
27276
27277 task slam_NonZeroTsbConfig2_core2_thread6;
27278 input [63:0] value;
27279 reg [5:0] tid;
27280 integer junk;
27281
27282 begin
27283`ifdef AXIS_EMUL_COSIM
27284//Do Nothing
27285`else
27286`ifdef GATESIM
27287//Do Nothing
27288`else
27289`ifdef CORE_2
27290 if (`PARGS.nas_check_on) begin
27291 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
27292 tid = 6
27293; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27294 end
27295`endif
27296
27297`endif
27298
27299`endif
27300
27301 end
27302 endtask
27303
27304
27305 task slam_NonZeroTsbConfig2_core2_thread7;
27306 input [63:0] value;
27307 reg [5:0] tid;
27308 integer junk;
27309
27310 begin
27311`ifdef AXIS_EMUL_COSIM
27312//Do Nothing
27313`else
27314`ifdef GATESIM
27315//Do Nothing
27316`else
27317`ifdef CORE_2
27318 if (`PARGS.nas_check_on) begin
27319 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
27320 tid = 7
27321; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27322 end
27323`endif
27324
27325`endif
27326
27327`endif
27328
27329 end
27330 endtask
27331
27332
27333 task slam_NonZeroTsbConfig2_core3_thread0;
27334 input [63:0] value;
27335 reg [5:0] tid;
27336 integer junk;
27337
27338 begin
27339`ifdef AXIS_EMUL_COSIM
27340//Do Nothing
27341`else
27342`ifdef GATESIM
27343//Do Nothing
27344`else
27345`ifdef CORE_3
27346 if (`PARGS.nas_check_on) begin
27347 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
27348 tid = 0
27349; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27350 end
27351`endif
27352
27353`endif
27354
27355`endif
27356
27357 end
27358 endtask
27359
27360
27361 task slam_NonZeroTsbConfig2_core3_thread1;
27362 input [63:0] value;
27363 reg [5:0] tid;
27364 integer junk;
27365
27366 begin
27367`ifdef AXIS_EMUL_COSIM
27368//Do Nothing
27369`else
27370`ifdef GATESIM
27371//Do Nothing
27372`else
27373`ifdef CORE_3
27374 if (`PARGS.nas_check_on) begin
27375 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
27376 tid = 1
27377; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27378 end
27379`endif
27380
27381`endif
27382
27383`endif
27384
27385 end
27386 endtask
27387
27388
27389 task slam_NonZeroTsbConfig2_core3_thread2;
27390 input [63:0] value;
27391 reg [5:0] tid;
27392 integer junk;
27393
27394 begin
27395`ifdef AXIS_EMUL_COSIM
27396//Do Nothing
27397`else
27398`ifdef GATESIM
27399//Do Nothing
27400`else
27401`ifdef CORE_3
27402 if (`PARGS.nas_check_on) begin
27403 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
27404 tid = 2
27405; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27406 end
27407`endif
27408
27409`endif
27410
27411`endif
27412
27413 end
27414 endtask
27415
27416
27417 task slam_NonZeroTsbConfig2_core3_thread3;
27418 input [63:0] value;
27419 reg [5:0] tid;
27420 integer junk;
27421
27422 begin
27423`ifdef AXIS_EMUL_COSIM
27424//Do Nothing
27425`else
27426`ifdef GATESIM
27427//Do Nothing
27428`else
27429`ifdef CORE_3
27430 if (`PARGS.nas_check_on) begin
27431 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
27432 tid = 3
27433; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27434 end
27435`endif
27436
27437`endif
27438
27439`endif
27440
27441 end
27442 endtask
27443
27444
27445 task slam_NonZeroTsbConfig2_core3_thread4;
27446 input [63:0] value;
27447 reg [5:0] tid;
27448 integer junk;
27449
27450 begin
27451`ifdef AXIS_EMUL_COSIM
27452//Do Nothing
27453`else
27454`ifdef GATESIM
27455//Do Nothing
27456`else
27457`ifdef CORE_3
27458 if (`PARGS.nas_check_on) begin
27459 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
27460 tid = 4
27461; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27462 end
27463`endif
27464
27465`endif
27466
27467`endif
27468
27469 end
27470 endtask
27471
27472
27473 task slam_NonZeroTsbConfig2_core3_thread5;
27474 input [63:0] value;
27475 reg [5:0] tid;
27476 integer junk;
27477
27478 begin
27479`ifdef AXIS_EMUL_COSIM
27480//Do Nothing
27481`else
27482`ifdef GATESIM
27483//Do Nothing
27484`else
27485`ifdef CORE_3
27486 if (`PARGS.nas_check_on) begin
27487 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
27488 tid = 5
27489; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27490 end
27491`endif
27492
27493`endif
27494
27495`endif
27496
27497 end
27498 endtask
27499
27500
27501 task slam_NonZeroTsbConfig2_core3_thread6;
27502 input [63:0] value;
27503 reg [5:0] tid;
27504 integer junk;
27505
27506 begin
27507`ifdef AXIS_EMUL_COSIM
27508//Do Nothing
27509`else
27510`ifdef GATESIM
27511//Do Nothing
27512`else
27513`ifdef CORE_3
27514 if (`PARGS.nas_check_on) begin
27515 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
27516 tid = 6
27517; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27518 end
27519`endif
27520
27521`endif
27522
27523`endif
27524
27525 end
27526 endtask
27527
27528
27529 task slam_NonZeroTsbConfig2_core3_thread7;
27530 input [63:0] value;
27531 reg [5:0] tid;
27532 integer junk;
27533
27534 begin
27535`ifdef AXIS_EMUL_COSIM
27536//Do Nothing
27537`else
27538`ifdef GATESIM
27539//Do Nothing
27540`else
27541`ifdef CORE_3
27542 if (`PARGS.nas_check_on) begin
27543 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
27544 tid = 7
27545; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27546 end
27547`endif
27548
27549`endif
27550
27551`endif
27552
27553 end
27554 endtask
27555
27556
27557 task slam_NonZeroTsbConfig2_core4_thread0;
27558 input [63:0] value;
27559 reg [5:0] tid;
27560 integer junk;
27561
27562 begin
27563`ifdef AXIS_EMUL_COSIM
27564//Do Nothing
27565`else
27566`ifdef GATESIM
27567//Do Nothing
27568`else
27569`ifdef CORE_4
27570 if (`PARGS.nas_check_on) begin
27571 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
27572 tid = 0
27573; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27574 end
27575`endif
27576
27577`endif
27578
27579`endif
27580
27581 end
27582 endtask
27583
27584
27585 task slam_NonZeroTsbConfig2_core4_thread1;
27586 input [63:0] value;
27587 reg [5:0] tid;
27588 integer junk;
27589
27590 begin
27591`ifdef AXIS_EMUL_COSIM
27592//Do Nothing
27593`else
27594`ifdef GATESIM
27595//Do Nothing
27596`else
27597`ifdef CORE_4
27598 if (`PARGS.nas_check_on) begin
27599 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
27600 tid = 1
27601; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27602 end
27603`endif
27604
27605`endif
27606
27607`endif
27608
27609 end
27610 endtask
27611
27612
27613 task slam_NonZeroTsbConfig2_core4_thread2;
27614 input [63:0] value;
27615 reg [5:0] tid;
27616 integer junk;
27617
27618 begin
27619`ifdef AXIS_EMUL_COSIM
27620//Do Nothing
27621`else
27622`ifdef GATESIM
27623//Do Nothing
27624`else
27625`ifdef CORE_4
27626 if (`PARGS.nas_check_on) begin
27627 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
27628 tid = 2
27629; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27630 end
27631`endif
27632
27633`endif
27634
27635`endif
27636
27637 end
27638 endtask
27639
27640
27641 task slam_NonZeroTsbConfig2_core4_thread3;
27642 input [63:0] value;
27643 reg [5:0] tid;
27644 integer junk;
27645
27646 begin
27647`ifdef AXIS_EMUL_COSIM
27648//Do Nothing
27649`else
27650`ifdef GATESIM
27651//Do Nothing
27652`else
27653`ifdef CORE_4
27654 if (`PARGS.nas_check_on) begin
27655 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
27656 tid = 3
27657; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27658 end
27659`endif
27660
27661`endif
27662
27663`endif
27664
27665 end
27666 endtask
27667
27668
27669 task slam_NonZeroTsbConfig2_core4_thread4;
27670 input [63:0] value;
27671 reg [5:0] tid;
27672 integer junk;
27673
27674 begin
27675`ifdef AXIS_EMUL_COSIM
27676//Do Nothing
27677`else
27678`ifdef GATESIM
27679//Do Nothing
27680`else
27681`ifdef CORE_4
27682 if (`PARGS.nas_check_on) begin
27683 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
27684 tid = 4
27685; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27686 end
27687`endif
27688
27689`endif
27690
27691`endif
27692
27693 end
27694 endtask
27695
27696
27697 task slam_NonZeroTsbConfig2_core4_thread5;
27698 input [63:0] value;
27699 reg [5:0] tid;
27700 integer junk;
27701
27702 begin
27703`ifdef AXIS_EMUL_COSIM
27704//Do Nothing
27705`else
27706`ifdef GATESIM
27707//Do Nothing
27708`else
27709`ifdef CORE_4
27710 if (`PARGS.nas_check_on) begin
27711 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
27712 tid = 5
27713; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27714 end
27715`endif
27716
27717`endif
27718
27719`endif
27720
27721 end
27722 endtask
27723
27724
27725 task slam_NonZeroTsbConfig2_core4_thread6;
27726 input [63:0] value;
27727 reg [5:0] tid;
27728 integer junk;
27729
27730 begin
27731`ifdef AXIS_EMUL_COSIM
27732//Do Nothing
27733`else
27734`ifdef GATESIM
27735//Do Nothing
27736`else
27737`ifdef CORE_4
27738 if (`PARGS.nas_check_on) begin
27739 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
27740 tid = 6
27741; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27742 end
27743`endif
27744
27745`endif
27746
27747`endif
27748
27749 end
27750 endtask
27751
27752
27753 task slam_NonZeroTsbConfig2_core4_thread7;
27754 input [63:0] value;
27755 reg [5:0] tid;
27756 integer junk;
27757
27758 begin
27759`ifdef AXIS_EMUL_COSIM
27760//Do Nothing
27761`else
27762`ifdef GATESIM
27763//Do Nothing
27764`else
27765`ifdef CORE_4
27766 if (`PARGS.nas_check_on) begin
27767 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
27768 tid = 7
27769; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27770 end
27771`endif
27772
27773`endif
27774
27775`endif
27776
27777 end
27778 endtask
27779
27780
27781 task slam_NonZeroTsbConfig2_core5_thread0;
27782 input [63:0] value;
27783 reg [5:0] tid;
27784 integer junk;
27785
27786 begin
27787`ifdef AXIS_EMUL_COSIM
27788//Do Nothing
27789`else
27790`ifdef GATESIM
27791//Do Nothing
27792`else
27793`ifdef CORE_5
27794 if (`PARGS.nas_check_on) begin
27795 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
27796 tid = 0
27797; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27798 end
27799`endif
27800
27801`endif
27802
27803`endif
27804
27805 end
27806 endtask
27807
27808
27809 task slam_NonZeroTsbConfig2_core5_thread1;
27810 input [63:0] value;
27811 reg [5:0] tid;
27812 integer junk;
27813
27814 begin
27815`ifdef AXIS_EMUL_COSIM
27816//Do Nothing
27817`else
27818`ifdef GATESIM
27819//Do Nothing
27820`else
27821`ifdef CORE_5
27822 if (`PARGS.nas_check_on) begin
27823 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
27824 tid = 1
27825; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27826 end
27827`endif
27828
27829`endif
27830
27831`endif
27832
27833 end
27834 endtask
27835
27836
27837 task slam_NonZeroTsbConfig2_core5_thread2;
27838 input [63:0] value;
27839 reg [5:0] tid;
27840 integer junk;
27841
27842 begin
27843`ifdef AXIS_EMUL_COSIM
27844//Do Nothing
27845`else
27846`ifdef GATESIM
27847//Do Nothing
27848`else
27849`ifdef CORE_5
27850 if (`PARGS.nas_check_on) begin
27851 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
27852 tid = 2
27853; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27854 end
27855`endif
27856
27857`endif
27858
27859`endif
27860
27861 end
27862 endtask
27863
27864
27865 task slam_NonZeroTsbConfig2_core5_thread3;
27866 input [63:0] value;
27867 reg [5:0] tid;
27868 integer junk;
27869
27870 begin
27871`ifdef AXIS_EMUL_COSIM
27872//Do Nothing
27873`else
27874`ifdef GATESIM
27875//Do Nothing
27876`else
27877`ifdef CORE_5
27878 if (`PARGS.nas_check_on) begin
27879 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
27880 tid = 3
27881; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27882 end
27883`endif
27884
27885`endif
27886
27887`endif
27888
27889 end
27890 endtask
27891
27892
27893 task slam_NonZeroTsbConfig2_core5_thread4;
27894 input [63:0] value;
27895 reg [5:0] tid;
27896 integer junk;
27897
27898 begin
27899`ifdef AXIS_EMUL_COSIM
27900//Do Nothing
27901`else
27902`ifdef GATESIM
27903//Do Nothing
27904`else
27905`ifdef CORE_5
27906 if (`PARGS.nas_check_on) begin
27907 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
27908 tid = 4
27909; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27910 end
27911`endif
27912
27913`endif
27914
27915`endif
27916
27917 end
27918 endtask
27919
27920
27921 task slam_NonZeroTsbConfig2_core5_thread5;
27922 input [63:0] value;
27923 reg [5:0] tid;
27924 integer junk;
27925
27926 begin
27927`ifdef AXIS_EMUL_COSIM
27928//Do Nothing
27929`else
27930`ifdef GATESIM
27931//Do Nothing
27932`else
27933`ifdef CORE_5
27934 if (`PARGS.nas_check_on) begin
27935 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
27936 tid = 5
27937; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27938 end
27939`endif
27940
27941`endif
27942
27943`endif
27944
27945 end
27946 endtask
27947
27948
27949 task slam_NonZeroTsbConfig2_core5_thread6;
27950 input [63:0] value;
27951 reg [5:0] tid;
27952 integer junk;
27953
27954 begin
27955`ifdef AXIS_EMUL_COSIM
27956//Do Nothing
27957`else
27958`ifdef GATESIM
27959//Do Nothing
27960`else
27961`ifdef CORE_5
27962 if (`PARGS.nas_check_on) begin
27963 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
27964 tid = 6
27965; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27966 end
27967`endif
27968
27969`endif
27970
27971`endif
27972
27973 end
27974 endtask
27975
27976
27977 task slam_NonZeroTsbConfig2_core5_thread7;
27978 input [63:0] value;
27979 reg [5:0] tid;
27980 integer junk;
27981
27982 begin
27983`ifdef AXIS_EMUL_COSIM
27984//Do Nothing
27985`else
27986`ifdef GATESIM
27987//Do Nothing
27988`else
27989`ifdef CORE_5
27990 if (`PARGS.nas_check_on) begin
27991 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
27992 tid = 7
27993; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
27994 end
27995`endif
27996
27997`endif
27998
27999`endif
28000
28001 end
28002 endtask
28003
28004
28005 task slam_NonZeroTsbConfig2_core6_thread0;
28006 input [63:0] value;
28007 reg [5:0] tid;
28008 integer junk;
28009
28010 begin
28011`ifdef AXIS_EMUL_COSIM
28012//Do Nothing
28013`else
28014`ifdef GATESIM
28015//Do Nothing
28016`else
28017`ifdef CORE_6
28018 if (`PARGS.nas_check_on) begin
28019 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
28020 tid = 0
28021; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28022 end
28023`endif
28024
28025`endif
28026
28027`endif
28028
28029 end
28030 endtask
28031
28032
28033 task slam_NonZeroTsbConfig2_core6_thread1;
28034 input [63:0] value;
28035 reg [5:0] tid;
28036 integer junk;
28037
28038 begin
28039`ifdef AXIS_EMUL_COSIM
28040//Do Nothing
28041`else
28042`ifdef GATESIM
28043//Do Nothing
28044`else
28045`ifdef CORE_6
28046 if (`PARGS.nas_check_on) begin
28047 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
28048 tid = 1
28049; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28050 end
28051`endif
28052
28053`endif
28054
28055`endif
28056
28057 end
28058 endtask
28059
28060
28061 task slam_NonZeroTsbConfig2_core6_thread2;
28062 input [63:0] value;
28063 reg [5:0] tid;
28064 integer junk;
28065
28066 begin
28067`ifdef AXIS_EMUL_COSIM
28068//Do Nothing
28069`else
28070`ifdef GATESIM
28071//Do Nothing
28072`else
28073`ifdef CORE_6
28074 if (`PARGS.nas_check_on) begin
28075 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
28076 tid = 2
28077; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28078 end
28079`endif
28080
28081`endif
28082
28083`endif
28084
28085 end
28086 endtask
28087
28088
28089 task slam_NonZeroTsbConfig2_core6_thread3;
28090 input [63:0] value;
28091 reg [5:0] tid;
28092 integer junk;
28093
28094 begin
28095`ifdef AXIS_EMUL_COSIM
28096//Do Nothing
28097`else
28098`ifdef GATESIM
28099//Do Nothing
28100`else
28101`ifdef CORE_6
28102 if (`PARGS.nas_check_on) begin
28103 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
28104 tid = 3
28105; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28106 end
28107`endif
28108
28109`endif
28110
28111`endif
28112
28113 end
28114 endtask
28115
28116
28117 task slam_NonZeroTsbConfig2_core6_thread4;
28118 input [63:0] value;
28119 reg [5:0] tid;
28120 integer junk;
28121
28122 begin
28123`ifdef AXIS_EMUL_COSIM
28124//Do Nothing
28125`else
28126`ifdef GATESIM
28127//Do Nothing
28128`else
28129`ifdef CORE_6
28130 if (`PARGS.nas_check_on) begin
28131 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
28132 tid = 4
28133; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28134 end
28135`endif
28136
28137`endif
28138
28139`endif
28140
28141 end
28142 endtask
28143
28144
28145 task slam_NonZeroTsbConfig2_core6_thread5;
28146 input [63:0] value;
28147 reg [5:0] tid;
28148 integer junk;
28149
28150 begin
28151`ifdef AXIS_EMUL_COSIM
28152//Do Nothing
28153`else
28154`ifdef GATESIM
28155//Do Nothing
28156`else
28157`ifdef CORE_6
28158 if (`PARGS.nas_check_on) begin
28159 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
28160 tid = 5
28161; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28162 end
28163`endif
28164
28165`endif
28166
28167`endif
28168
28169 end
28170 endtask
28171
28172
28173 task slam_NonZeroTsbConfig2_core6_thread6;
28174 input [63:0] value;
28175 reg [5:0] tid;
28176 integer junk;
28177
28178 begin
28179`ifdef AXIS_EMUL_COSIM
28180//Do Nothing
28181`else
28182`ifdef GATESIM
28183//Do Nothing
28184`else
28185`ifdef CORE_6
28186 if (`PARGS.nas_check_on) begin
28187 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
28188 tid = 6
28189; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28190 end
28191`endif
28192
28193`endif
28194
28195`endif
28196
28197 end
28198 endtask
28199
28200
28201 task slam_NonZeroTsbConfig2_core6_thread7;
28202 input [63:0] value;
28203 reg [5:0] tid;
28204 integer junk;
28205
28206 begin
28207`ifdef AXIS_EMUL_COSIM
28208//Do Nothing
28209`else
28210`ifdef GATESIM
28211//Do Nothing
28212`else
28213`ifdef CORE_6
28214 if (`PARGS.nas_check_on) begin
28215 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
28216 tid = 7
28217; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28218 end
28219`endif
28220
28221`endif
28222
28223`endif
28224
28225 end
28226 endtask
28227
28228
28229 task slam_NonZeroTsbConfig2_core7_thread0;
28230 input [63:0] value;
28231 reg [5:0] tid;
28232 integer junk;
28233
28234 begin
28235`ifdef AXIS_EMUL_COSIM
28236//Do Nothing
28237`else
28238`ifdef GATESIM
28239//Do Nothing
28240`else
28241`ifdef CORE_7
28242 if (`PARGS.nas_check_on) begin
28243 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
28244 tid = 0
28245; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28246 end
28247`endif
28248
28249`endif
28250
28251`endif
28252
28253 end
28254 endtask
28255
28256
28257 task slam_NonZeroTsbConfig2_core7_thread1;
28258 input [63:0] value;
28259 reg [5:0] tid;
28260 integer junk;
28261
28262 begin
28263`ifdef AXIS_EMUL_COSIM
28264//Do Nothing
28265`else
28266`ifdef GATESIM
28267//Do Nothing
28268`else
28269`ifdef CORE_7
28270 if (`PARGS.nas_check_on) begin
28271 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
28272 tid = 1
28273; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28274 end
28275`endif
28276
28277`endif
28278
28279`endif
28280
28281 end
28282 endtask
28283
28284
28285 task slam_NonZeroTsbConfig2_core7_thread2;
28286 input [63:0] value;
28287 reg [5:0] tid;
28288 integer junk;
28289
28290 begin
28291`ifdef AXIS_EMUL_COSIM
28292//Do Nothing
28293`else
28294`ifdef GATESIM
28295//Do Nothing
28296`else
28297`ifdef CORE_7
28298 if (`PARGS.nas_check_on) begin
28299 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
28300 tid = 2
28301; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28302 end
28303`endif
28304
28305`endif
28306
28307`endif
28308
28309 end
28310 endtask
28311
28312
28313 task slam_NonZeroTsbConfig2_core7_thread3;
28314 input [63:0] value;
28315 reg [5:0] tid;
28316 integer junk;
28317
28318 begin
28319`ifdef AXIS_EMUL_COSIM
28320//Do Nothing
28321`else
28322`ifdef GATESIM
28323//Do Nothing
28324`else
28325`ifdef CORE_7
28326 if (`PARGS.nas_check_on) begin
28327 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
28328 tid = 3
28329; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28330 end
28331`endif
28332
28333`endif
28334
28335`endif
28336
28337 end
28338 endtask
28339
28340
28341 task slam_NonZeroTsbConfig2_core7_thread4;
28342 input [63:0] value;
28343 reg [5:0] tid;
28344 integer junk;
28345
28346 begin
28347`ifdef AXIS_EMUL_COSIM
28348//Do Nothing
28349`else
28350`ifdef GATESIM
28351//Do Nothing
28352`else
28353`ifdef CORE_7
28354 if (`PARGS.nas_check_on) begin
28355 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
28356 tid = 4
28357; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28358 end
28359`endif
28360
28361`endif
28362
28363`endif
28364
28365 end
28366 endtask
28367
28368
28369 task slam_NonZeroTsbConfig2_core7_thread5;
28370 input [63:0] value;
28371 reg [5:0] tid;
28372 integer junk;
28373
28374 begin
28375`ifdef AXIS_EMUL_COSIM
28376//Do Nothing
28377`else
28378`ifdef GATESIM
28379//Do Nothing
28380`else
28381`ifdef CORE_7
28382 if (`PARGS.nas_check_on) begin
28383 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
28384 tid = 5
28385; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28386 end
28387`endif
28388
28389`endif
28390
28391`endif
28392
28393 end
28394 endtask
28395
28396
28397 task slam_NonZeroTsbConfig2_core7_thread6;
28398 input [63:0] value;
28399 reg [5:0] tid;
28400 integer junk;
28401
28402 begin
28403`ifdef AXIS_EMUL_COSIM
28404//Do Nothing
28405`else
28406`ifdef GATESIM
28407//Do Nothing
28408`else
28409`ifdef CORE_7
28410 if (`PARGS.nas_check_on) begin
28411 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
28412 tid = 6
28413; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28414 end
28415`endif
28416
28417`endif
28418
28419`endif
28420
28421 end
28422 endtask
28423
28424
28425 task slam_NonZeroTsbConfig2_core7_thread7;
28426 input [63:0] value;
28427 reg [5:0] tid;
28428 integer junk;
28429
28430 begin
28431`ifdef AXIS_EMUL_COSIM
28432//Do Nothing
28433`else
28434`ifdef GATESIM
28435//Do Nothing
28436`else
28437`ifdef CORE_7
28438 if (`PARGS.nas_check_on) begin
28439 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
28440 tid = 7
28441; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h40, value);
28442 end
28443`endif
28444
28445`endif
28446
28447`endif
28448
28449 end
28450 endtask
28451
28452
28453 task slam_NonZeroTsbConfig3_core0_thread0;
28454 input [63:0] value;
28455 reg [5:0] tid;
28456 integer junk;
28457
28458 begin
28459`ifdef AXIS_EMUL_COSIM
28460//Do Nothing
28461`else
28462`ifdef GATESIM
28463//Do Nothing
28464`else
28465`ifdef CORE_0
28466 if (`PARGS.nas_check_on) begin
28467 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 0, 54, value);
28468 tid = 0
28469; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28470 end
28471`endif
28472
28473`endif
28474
28475`endif
28476
28477 end
28478 endtask
28479
28480
28481 task slam_NonZeroTsbConfig3_core0_thread1;
28482 input [63:0] value;
28483 reg [5:0] tid;
28484 integer junk;
28485
28486 begin
28487`ifdef AXIS_EMUL_COSIM
28488//Do Nothing
28489`else
28490`ifdef GATESIM
28491//Do Nothing
28492`else
28493`ifdef CORE_0
28494 if (`PARGS.nas_check_on) begin
28495 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 1, 54, value);
28496 tid = 1
28497; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28498 end
28499`endif
28500
28501`endif
28502
28503`endif
28504
28505 end
28506 endtask
28507
28508
28509 task slam_NonZeroTsbConfig3_core0_thread2;
28510 input [63:0] value;
28511 reg [5:0] tid;
28512 integer junk;
28513
28514 begin
28515`ifdef AXIS_EMUL_COSIM
28516//Do Nothing
28517`else
28518`ifdef GATESIM
28519//Do Nothing
28520`else
28521`ifdef CORE_0
28522 if (`PARGS.nas_check_on) begin
28523 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 2, 54, value);
28524 tid = 2
28525; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28526 end
28527`endif
28528
28529`endif
28530
28531`endif
28532
28533 end
28534 endtask
28535
28536
28537 task slam_NonZeroTsbConfig3_core0_thread3;
28538 input [63:0] value;
28539 reg [5:0] tid;
28540 integer junk;
28541
28542 begin
28543`ifdef AXIS_EMUL_COSIM
28544//Do Nothing
28545`else
28546`ifdef GATESIM
28547//Do Nothing
28548`else
28549`ifdef CORE_0
28550 if (`PARGS.nas_check_on) begin
28551 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 3, 54, value);
28552 tid = 3
28553; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28554 end
28555`endif
28556
28557`endif
28558
28559`endif
28560
28561 end
28562 endtask
28563
28564
28565 task slam_NonZeroTsbConfig3_core0_thread4;
28566 input [63:0] value;
28567 reg [5:0] tid;
28568 integer junk;
28569
28570 begin
28571`ifdef AXIS_EMUL_COSIM
28572//Do Nothing
28573`else
28574`ifdef GATESIM
28575//Do Nothing
28576`else
28577`ifdef CORE_0
28578 if (`PARGS.nas_check_on) begin
28579 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 4, 54, value);
28580 tid = 4
28581; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28582 end
28583`endif
28584
28585`endif
28586
28587`endif
28588
28589 end
28590 endtask
28591
28592
28593 task slam_NonZeroTsbConfig3_core0_thread5;
28594 input [63:0] value;
28595 reg [5:0] tid;
28596 integer junk;
28597
28598 begin
28599`ifdef AXIS_EMUL_COSIM
28600//Do Nothing
28601`else
28602`ifdef GATESIM
28603//Do Nothing
28604`else
28605`ifdef CORE_0
28606 if (`PARGS.nas_check_on) begin
28607 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 5, 54, value);
28608 tid = 5
28609; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28610 end
28611`endif
28612
28613`endif
28614
28615`endif
28616
28617 end
28618 endtask
28619
28620
28621 task slam_NonZeroTsbConfig3_core0_thread6;
28622 input [63:0] value;
28623 reg [5:0] tid;
28624 integer junk;
28625
28626 begin
28627`ifdef AXIS_EMUL_COSIM
28628//Do Nothing
28629`else
28630`ifdef GATESIM
28631//Do Nothing
28632`else
28633`ifdef CORE_0
28634 if (`PARGS.nas_check_on) begin
28635 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 6, 54, value);
28636 tid = 6
28637; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28638 end
28639`endif
28640
28641`endif
28642
28643`endif
28644
28645 end
28646 endtask
28647
28648
28649 task slam_NonZeroTsbConfig3_core0_thread7;
28650 input [63:0] value;
28651 reg [5:0] tid;
28652 integer junk;
28653
28654 begin
28655`ifdef AXIS_EMUL_COSIM
28656//Do Nothing
28657`else
28658`ifdef GATESIM
28659//Do Nothing
28660`else
28661`ifdef CORE_0
28662 if (`PARGS.nas_check_on) begin
28663 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 0, 7, 54, value);
28664 tid = 7
28665; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28666 end
28667`endif
28668
28669`endif
28670
28671`endif
28672
28673 end
28674 endtask
28675
28676
28677 task slam_NonZeroTsbConfig3_core1_thread0;
28678 input [63:0] value;
28679 reg [5:0] tid;
28680 integer junk;
28681
28682 begin
28683`ifdef AXIS_EMUL_COSIM
28684//Do Nothing
28685`else
28686`ifdef GATESIM
28687//Do Nothing
28688`else
28689`ifdef CORE_1
28690 if (`PARGS.nas_check_on) begin
28691 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 0, 54, value);
28692 tid = 0
28693; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28694 end
28695`endif
28696
28697`endif
28698
28699`endif
28700
28701 end
28702 endtask
28703
28704
28705 task slam_NonZeroTsbConfig3_core1_thread1;
28706 input [63:0] value;
28707 reg [5:0] tid;
28708 integer junk;
28709
28710 begin
28711`ifdef AXIS_EMUL_COSIM
28712//Do Nothing
28713`else
28714`ifdef GATESIM
28715//Do Nothing
28716`else
28717`ifdef CORE_1
28718 if (`PARGS.nas_check_on) begin
28719 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 1, 54, value);
28720 tid = 1
28721; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28722 end
28723`endif
28724
28725`endif
28726
28727`endif
28728
28729 end
28730 endtask
28731
28732
28733 task slam_NonZeroTsbConfig3_core1_thread2;
28734 input [63:0] value;
28735 reg [5:0] tid;
28736 integer junk;
28737
28738 begin
28739`ifdef AXIS_EMUL_COSIM
28740//Do Nothing
28741`else
28742`ifdef GATESIM
28743//Do Nothing
28744`else
28745`ifdef CORE_1
28746 if (`PARGS.nas_check_on) begin
28747 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 2, 54, value);
28748 tid = 2
28749; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28750 end
28751`endif
28752
28753`endif
28754
28755`endif
28756
28757 end
28758 endtask
28759
28760
28761 task slam_NonZeroTsbConfig3_core1_thread3;
28762 input [63:0] value;
28763 reg [5:0] tid;
28764 integer junk;
28765
28766 begin
28767`ifdef AXIS_EMUL_COSIM
28768//Do Nothing
28769`else
28770`ifdef GATESIM
28771//Do Nothing
28772`else
28773`ifdef CORE_1
28774 if (`PARGS.nas_check_on) begin
28775 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 3, 54, value);
28776 tid = 3
28777; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28778 end
28779`endif
28780
28781`endif
28782
28783`endif
28784
28785 end
28786 endtask
28787
28788
28789 task slam_NonZeroTsbConfig3_core1_thread4;
28790 input [63:0] value;
28791 reg [5:0] tid;
28792 integer junk;
28793
28794 begin
28795`ifdef AXIS_EMUL_COSIM
28796//Do Nothing
28797`else
28798`ifdef GATESIM
28799//Do Nothing
28800`else
28801`ifdef CORE_1
28802 if (`PARGS.nas_check_on) begin
28803 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 4, 54, value);
28804 tid = 4
28805; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28806 end
28807`endif
28808
28809`endif
28810
28811`endif
28812
28813 end
28814 endtask
28815
28816
28817 task slam_NonZeroTsbConfig3_core1_thread5;
28818 input [63:0] value;
28819 reg [5:0] tid;
28820 integer junk;
28821
28822 begin
28823`ifdef AXIS_EMUL_COSIM
28824//Do Nothing
28825`else
28826`ifdef GATESIM
28827//Do Nothing
28828`else
28829`ifdef CORE_1
28830 if (`PARGS.nas_check_on) begin
28831 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 5, 54, value);
28832 tid = 5
28833; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28834 end
28835`endif
28836
28837`endif
28838
28839`endif
28840
28841 end
28842 endtask
28843
28844
28845 task slam_NonZeroTsbConfig3_core1_thread6;
28846 input [63:0] value;
28847 reg [5:0] tid;
28848 integer junk;
28849
28850 begin
28851`ifdef AXIS_EMUL_COSIM
28852//Do Nothing
28853`else
28854`ifdef GATESIM
28855//Do Nothing
28856`else
28857`ifdef CORE_1
28858 if (`PARGS.nas_check_on) begin
28859 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 6, 54, value);
28860 tid = 6
28861; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28862 end
28863`endif
28864
28865`endif
28866
28867`endif
28868
28869 end
28870 endtask
28871
28872
28873 task slam_NonZeroTsbConfig3_core1_thread7;
28874 input [63:0] value;
28875 reg [5:0] tid;
28876 integer junk;
28877
28878 begin
28879`ifdef AXIS_EMUL_COSIM
28880//Do Nothing
28881`else
28882`ifdef GATESIM
28883//Do Nothing
28884`else
28885`ifdef CORE_1
28886 if (`PARGS.nas_check_on) begin
28887 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 1, 7, 54, value);
28888 tid = 7
28889; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28890 end
28891`endif
28892
28893`endif
28894
28895`endif
28896
28897 end
28898 endtask
28899
28900
28901 task slam_NonZeroTsbConfig3_core2_thread0;
28902 input [63:0] value;
28903 reg [5:0] tid;
28904 integer junk;
28905
28906 begin
28907`ifdef AXIS_EMUL_COSIM
28908//Do Nothing
28909`else
28910`ifdef GATESIM
28911//Do Nothing
28912`else
28913`ifdef CORE_2
28914 if (`PARGS.nas_check_on) begin
28915 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 0, 54, value);
28916 tid = 0
28917; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28918 end
28919`endif
28920
28921`endif
28922
28923`endif
28924
28925 end
28926 endtask
28927
28928
28929 task slam_NonZeroTsbConfig3_core2_thread1;
28930 input [63:0] value;
28931 reg [5:0] tid;
28932 integer junk;
28933
28934 begin
28935`ifdef AXIS_EMUL_COSIM
28936//Do Nothing
28937`else
28938`ifdef GATESIM
28939//Do Nothing
28940`else
28941`ifdef CORE_2
28942 if (`PARGS.nas_check_on) begin
28943 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 1, 54, value);
28944 tid = 1
28945; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28946 end
28947`endif
28948
28949`endif
28950
28951`endif
28952
28953 end
28954 endtask
28955
28956
28957 task slam_NonZeroTsbConfig3_core2_thread2;
28958 input [63:0] value;
28959 reg [5:0] tid;
28960 integer junk;
28961
28962 begin
28963`ifdef AXIS_EMUL_COSIM
28964//Do Nothing
28965`else
28966`ifdef GATESIM
28967//Do Nothing
28968`else
28969`ifdef CORE_2
28970 if (`PARGS.nas_check_on) begin
28971 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 2, 54, value);
28972 tid = 2
28973; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
28974 end
28975`endif
28976
28977`endif
28978
28979`endif
28980
28981 end
28982 endtask
28983
28984
28985 task slam_NonZeroTsbConfig3_core2_thread3;
28986 input [63:0] value;
28987 reg [5:0] tid;
28988 integer junk;
28989
28990 begin
28991`ifdef AXIS_EMUL_COSIM
28992//Do Nothing
28993`else
28994`ifdef GATESIM
28995//Do Nothing
28996`else
28997`ifdef CORE_2
28998 if (`PARGS.nas_check_on) begin
28999 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 3, 54, value);
29000 tid = 3
29001; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29002 end
29003`endif
29004
29005`endif
29006
29007`endif
29008
29009 end
29010 endtask
29011
29012
29013 task slam_NonZeroTsbConfig3_core2_thread4;
29014 input [63:0] value;
29015 reg [5:0] tid;
29016 integer junk;
29017
29018 begin
29019`ifdef AXIS_EMUL_COSIM
29020//Do Nothing
29021`else
29022`ifdef GATESIM
29023//Do Nothing
29024`else
29025`ifdef CORE_2
29026 if (`PARGS.nas_check_on) begin
29027 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 4, 54, value);
29028 tid = 4
29029; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29030 end
29031`endif
29032
29033`endif
29034
29035`endif
29036
29037 end
29038 endtask
29039
29040
29041 task slam_NonZeroTsbConfig3_core2_thread5;
29042 input [63:0] value;
29043 reg [5:0] tid;
29044 integer junk;
29045
29046 begin
29047`ifdef AXIS_EMUL_COSIM
29048//Do Nothing
29049`else
29050`ifdef GATESIM
29051//Do Nothing
29052`else
29053`ifdef CORE_2
29054 if (`PARGS.nas_check_on) begin
29055 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 5, 54, value);
29056 tid = 5
29057; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29058 end
29059`endif
29060
29061`endif
29062
29063`endif
29064
29065 end
29066 endtask
29067
29068
29069 task slam_NonZeroTsbConfig3_core2_thread6;
29070 input [63:0] value;
29071 reg [5:0] tid;
29072 integer junk;
29073
29074 begin
29075`ifdef AXIS_EMUL_COSIM
29076//Do Nothing
29077`else
29078`ifdef GATESIM
29079//Do Nothing
29080`else
29081`ifdef CORE_2
29082 if (`PARGS.nas_check_on) begin
29083 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 6, 54, value);
29084 tid = 6
29085; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29086 end
29087`endif
29088
29089`endif
29090
29091`endif
29092
29093 end
29094 endtask
29095
29096
29097 task slam_NonZeroTsbConfig3_core2_thread7;
29098 input [63:0] value;
29099 reg [5:0] tid;
29100 integer junk;
29101
29102 begin
29103`ifdef AXIS_EMUL_COSIM
29104//Do Nothing
29105`else
29106`ifdef GATESIM
29107//Do Nothing
29108`else
29109`ifdef CORE_2
29110 if (`PARGS.nas_check_on) begin
29111 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 2, 7, 54, value);
29112 tid = 7
29113; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29114 end
29115`endif
29116
29117`endif
29118
29119`endif
29120
29121 end
29122 endtask
29123
29124
29125 task slam_NonZeroTsbConfig3_core3_thread0;
29126 input [63:0] value;
29127 reg [5:0] tid;
29128 integer junk;
29129
29130 begin
29131`ifdef AXIS_EMUL_COSIM
29132//Do Nothing
29133`else
29134`ifdef GATESIM
29135//Do Nothing
29136`else
29137`ifdef CORE_3
29138 if (`PARGS.nas_check_on) begin
29139 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 0, 54, value);
29140 tid = 0
29141; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29142 end
29143`endif
29144
29145`endif
29146
29147`endif
29148
29149 end
29150 endtask
29151
29152
29153 task slam_NonZeroTsbConfig3_core3_thread1;
29154 input [63:0] value;
29155 reg [5:0] tid;
29156 integer junk;
29157
29158 begin
29159`ifdef AXIS_EMUL_COSIM
29160//Do Nothing
29161`else
29162`ifdef GATESIM
29163//Do Nothing
29164`else
29165`ifdef CORE_3
29166 if (`PARGS.nas_check_on) begin
29167 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 1, 54, value);
29168 tid = 1
29169; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29170 end
29171`endif
29172
29173`endif
29174
29175`endif
29176
29177 end
29178 endtask
29179
29180
29181 task slam_NonZeroTsbConfig3_core3_thread2;
29182 input [63:0] value;
29183 reg [5:0] tid;
29184 integer junk;
29185
29186 begin
29187`ifdef AXIS_EMUL_COSIM
29188//Do Nothing
29189`else
29190`ifdef GATESIM
29191//Do Nothing
29192`else
29193`ifdef CORE_3
29194 if (`PARGS.nas_check_on) begin
29195 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 2, 54, value);
29196 tid = 2
29197; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29198 end
29199`endif
29200
29201`endif
29202
29203`endif
29204
29205 end
29206 endtask
29207
29208
29209 task slam_NonZeroTsbConfig3_core3_thread3;
29210 input [63:0] value;
29211 reg [5:0] tid;
29212 integer junk;
29213
29214 begin
29215`ifdef AXIS_EMUL_COSIM
29216//Do Nothing
29217`else
29218`ifdef GATESIM
29219//Do Nothing
29220`else
29221`ifdef CORE_3
29222 if (`PARGS.nas_check_on) begin
29223 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 3, 54, value);
29224 tid = 3
29225; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29226 end
29227`endif
29228
29229`endif
29230
29231`endif
29232
29233 end
29234 endtask
29235
29236
29237 task slam_NonZeroTsbConfig3_core3_thread4;
29238 input [63:0] value;
29239 reg [5:0] tid;
29240 integer junk;
29241
29242 begin
29243`ifdef AXIS_EMUL_COSIM
29244//Do Nothing
29245`else
29246`ifdef GATESIM
29247//Do Nothing
29248`else
29249`ifdef CORE_3
29250 if (`PARGS.nas_check_on) begin
29251 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 4, 54, value);
29252 tid = 4
29253; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29254 end
29255`endif
29256
29257`endif
29258
29259`endif
29260
29261 end
29262 endtask
29263
29264
29265 task slam_NonZeroTsbConfig3_core3_thread5;
29266 input [63:0] value;
29267 reg [5:0] tid;
29268 integer junk;
29269
29270 begin
29271`ifdef AXIS_EMUL_COSIM
29272//Do Nothing
29273`else
29274`ifdef GATESIM
29275//Do Nothing
29276`else
29277`ifdef CORE_3
29278 if (`PARGS.nas_check_on) begin
29279 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 5, 54, value);
29280 tid = 5
29281; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29282 end
29283`endif
29284
29285`endif
29286
29287`endif
29288
29289 end
29290 endtask
29291
29292
29293 task slam_NonZeroTsbConfig3_core3_thread6;
29294 input [63:0] value;
29295 reg [5:0] tid;
29296 integer junk;
29297
29298 begin
29299`ifdef AXIS_EMUL_COSIM
29300//Do Nothing
29301`else
29302`ifdef GATESIM
29303//Do Nothing
29304`else
29305`ifdef CORE_3
29306 if (`PARGS.nas_check_on) begin
29307 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 6, 54, value);
29308 tid = 6
29309; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29310 end
29311`endif
29312
29313`endif
29314
29315`endif
29316
29317 end
29318 endtask
29319
29320
29321 task slam_NonZeroTsbConfig3_core3_thread7;
29322 input [63:0] value;
29323 reg [5:0] tid;
29324 integer junk;
29325
29326 begin
29327`ifdef AXIS_EMUL_COSIM
29328//Do Nothing
29329`else
29330`ifdef GATESIM
29331//Do Nothing
29332`else
29333`ifdef CORE_3
29334 if (`PARGS.nas_check_on) begin
29335 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 3, 7, 54, value);
29336 tid = 7
29337; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29338 end
29339`endif
29340
29341`endif
29342
29343`endif
29344
29345 end
29346 endtask
29347
29348
29349 task slam_NonZeroTsbConfig3_core4_thread0;
29350 input [63:0] value;
29351 reg [5:0] tid;
29352 integer junk;
29353
29354 begin
29355`ifdef AXIS_EMUL_COSIM
29356//Do Nothing
29357`else
29358`ifdef GATESIM
29359//Do Nothing
29360`else
29361`ifdef CORE_4
29362 if (`PARGS.nas_check_on) begin
29363 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 0, 54, value);
29364 tid = 0
29365; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29366 end
29367`endif
29368
29369`endif
29370
29371`endif
29372
29373 end
29374 endtask
29375
29376
29377 task slam_NonZeroTsbConfig3_core4_thread1;
29378 input [63:0] value;
29379 reg [5:0] tid;
29380 integer junk;
29381
29382 begin
29383`ifdef AXIS_EMUL_COSIM
29384//Do Nothing
29385`else
29386`ifdef GATESIM
29387//Do Nothing
29388`else
29389`ifdef CORE_4
29390 if (`PARGS.nas_check_on) begin
29391 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 1, 54, value);
29392 tid = 1
29393; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29394 end
29395`endif
29396
29397`endif
29398
29399`endif
29400
29401 end
29402 endtask
29403
29404
29405 task slam_NonZeroTsbConfig3_core4_thread2;
29406 input [63:0] value;
29407 reg [5:0] tid;
29408 integer junk;
29409
29410 begin
29411`ifdef AXIS_EMUL_COSIM
29412//Do Nothing
29413`else
29414`ifdef GATESIM
29415//Do Nothing
29416`else
29417`ifdef CORE_4
29418 if (`PARGS.nas_check_on) begin
29419 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 2, 54, value);
29420 tid = 2
29421; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29422 end
29423`endif
29424
29425`endif
29426
29427`endif
29428
29429 end
29430 endtask
29431
29432
29433 task slam_NonZeroTsbConfig3_core4_thread3;
29434 input [63:0] value;
29435 reg [5:0] tid;
29436 integer junk;
29437
29438 begin
29439`ifdef AXIS_EMUL_COSIM
29440//Do Nothing
29441`else
29442`ifdef GATESIM
29443//Do Nothing
29444`else
29445`ifdef CORE_4
29446 if (`PARGS.nas_check_on) begin
29447 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 3, 54, value);
29448 tid = 3
29449; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29450 end
29451`endif
29452
29453`endif
29454
29455`endif
29456
29457 end
29458 endtask
29459
29460
29461 task slam_NonZeroTsbConfig3_core4_thread4;
29462 input [63:0] value;
29463 reg [5:0] tid;
29464 integer junk;
29465
29466 begin
29467`ifdef AXIS_EMUL_COSIM
29468//Do Nothing
29469`else
29470`ifdef GATESIM
29471//Do Nothing
29472`else
29473`ifdef CORE_4
29474 if (`PARGS.nas_check_on) begin
29475 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 4, 54, value);
29476 tid = 4
29477; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29478 end
29479`endif
29480
29481`endif
29482
29483`endif
29484
29485 end
29486 endtask
29487
29488
29489 task slam_NonZeroTsbConfig3_core4_thread5;
29490 input [63:0] value;
29491 reg [5:0] tid;
29492 integer junk;
29493
29494 begin
29495`ifdef AXIS_EMUL_COSIM
29496//Do Nothing
29497`else
29498`ifdef GATESIM
29499//Do Nothing
29500`else
29501`ifdef CORE_4
29502 if (`PARGS.nas_check_on) begin
29503 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 5, 54, value);
29504 tid = 5
29505; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29506 end
29507`endif
29508
29509`endif
29510
29511`endif
29512
29513 end
29514 endtask
29515
29516
29517 task slam_NonZeroTsbConfig3_core4_thread6;
29518 input [63:0] value;
29519 reg [5:0] tid;
29520 integer junk;
29521
29522 begin
29523`ifdef AXIS_EMUL_COSIM
29524//Do Nothing
29525`else
29526`ifdef GATESIM
29527//Do Nothing
29528`else
29529`ifdef CORE_4
29530 if (`PARGS.nas_check_on) begin
29531 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 6, 54, value);
29532 tid = 6
29533; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29534 end
29535`endif
29536
29537`endif
29538
29539`endif
29540
29541 end
29542 endtask
29543
29544
29545 task slam_NonZeroTsbConfig3_core4_thread7;
29546 input [63:0] value;
29547 reg [5:0] tid;
29548 integer junk;
29549
29550 begin
29551`ifdef AXIS_EMUL_COSIM
29552//Do Nothing
29553`else
29554`ifdef GATESIM
29555//Do Nothing
29556`else
29557`ifdef CORE_4
29558 if (`PARGS.nas_check_on) begin
29559 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 4, 7, 54, value);
29560 tid = 7
29561; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29562 end
29563`endif
29564
29565`endif
29566
29567`endif
29568
29569 end
29570 endtask
29571
29572
29573 task slam_NonZeroTsbConfig3_core5_thread0;
29574 input [63:0] value;
29575 reg [5:0] tid;
29576 integer junk;
29577
29578 begin
29579`ifdef AXIS_EMUL_COSIM
29580//Do Nothing
29581`else
29582`ifdef GATESIM
29583//Do Nothing
29584`else
29585`ifdef CORE_5
29586 if (`PARGS.nas_check_on) begin
29587 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 0, 54, value);
29588 tid = 0
29589; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29590 end
29591`endif
29592
29593`endif
29594
29595`endif
29596
29597 end
29598 endtask
29599
29600
29601 task slam_NonZeroTsbConfig3_core5_thread1;
29602 input [63:0] value;
29603 reg [5:0] tid;
29604 integer junk;
29605
29606 begin
29607`ifdef AXIS_EMUL_COSIM
29608//Do Nothing
29609`else
29610`ifdef GATESIM
29611//Do Nothing
29612`else
29613`ifdef CORE_5
29614 if (`PARGS.nas_check_on) begin
29615 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 1, 54, value);
29616 tid = 1
29617; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29618 end
29619`endif
29620
29621`endif
29622
29623`endif
29624
29625 end
29626 endtask
29627
29628
29629 task slam_NonZeroTsbConfig3_core5_thread2;
29630 input [63:0] value;
29631 reg [5:0] tid;
29632 integer junk;
29633
29634 begin
29635`ifdef AXIS_EMUL_COSIM
29636//Do Nothing
29637`else
29638`ifdef GATESIM
29639//Do Nothing
29640`else
29641`ifdef CORE_5
29642 if (`PARGS.nas_check_on) begin
29643 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 2, 54, value);
29644 tid = 2
29645; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29646 end
29647`endif
29648
29649`endif
29650
29651`endif
29652
29653 end
29654 endtask
29655
29656
29657 task slam_NonZeroTsbConfig3_core5_thread3;
29658 input [63:0] value;
29659 reg [5:0] tid;
29660 integer junk;
29661
29662 begin
29663`ifdef AXIS_EMUL_COSIM
29664//Do Nothing
29665`else
29666`ifdef GATESIM
29667//Do Nothing
29668`else
29669`ifdef CORE_5
29670 if (`PARGS.nas_check_on) begin
29671 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 3, 54, value);
29672 tid = 3
29673; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29674 end
29675`endif
29676
29677`endif
29678
29679`endif
29680
29681 end
29682 endtask
29683
29684
29685 task slam_NonZeroTsbConfig3_core5_thread4;
29686 input [63:0] value;
29687 reg [5:0] tid;
29688 integer junk;
29689
29690 begin
29691`ifdef AXIS_EMUL_COSIM
29692//Do Nothing
29693`else
29694`ifdef GATESIM
29695//Do Nothing
29696`else
29697`ifdef CORE_5
29698 if (`PARGS.nas_check_on) begin
29699 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 4, 54, value);
29700 tid = 4
29701; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29702 end
29703`endif
29704
29705`endif
29706
29707`endif
29708
29709 end
29710 endtask
29711
29712
29713 task slam_NonZeroTsbConfig3_core5_thread5;
29714 input [63:0] value;
29715 reg [5:0] tid;
29716 integer junk;
29717
29718 begin
29719`ifdef AXIS_EMUL_COSIM
29720//Do Nothing
29721`else
29722`ifdef GATESIM
29723//Do Nothing
29724`else
29725`ifdef CORE_5
29726 if (`PARGS.nas_check_on) begin
29727 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 5, 54, value);
29728 tid = 5
29729; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29730 end
29731`endif
29732
29733`endif
29734
29735`endif
29736
29737 end
29738 endtask
29739
29740
29741 task slam_NonZeroTsbConfig3_core5_thread6;
29742 input [63:0] value;
29743 reg [5:0] tid;
29744 integer junk;
29745
29746 begin
29747`ifdef AXIS_EMUL_COSIM
29748//Do Nothing
29749`else
29750`ifdef GATESIM
29751//Do Nothing
29752`else
29753`ifdef CORE_5
29754 if (`PARGS.nas_check_on) begin
29755 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 6, 54, value);
29756 tid = 6
29757; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29758 end
29759`endif
29760
29761`endif
29762
29763`endif
29764
29765 end
29766 endtask
29767
29768
29769 task slam_NonZeroTsbConfig3_core5_thread7;
29770 input [63:0] value;
29771 reg [5:0] tid;
29772 integer junk;
29773
29774 begin
29775`ifdef AXIS_EMUL_COSIM
29776//Do Nothing
29777`else
29778`ifdef GATESIM
29779//Do Nothing
29780`else
29781`ifdef CORE_5
29782 if (`PARGS.nas_check_on) begin
29783 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 5, 7, 54, value);
29784 tid = 7
29785; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29786 end
29787`endif
29788
29789`endif
29790
29791`endif
29792
29793 end
29794 endtask
29795
29796
29797 task slam_NonZeroTsbConfig3_core6_thread0;
29798 input [63:0] value;
29799 reg [5:0] tid;
29800 integer junk;
29801
29802 begin
29803`ifdef AXIS_EMUL_COSIM
29804//Do Nothing
29805`else
29806`ifdef GATESIM
29807//Do Nothing
29808`else
29809`ifdef CORE_6
29810 if (`PARGS.nas_check_on) begin
29811 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 0, 54, value);
29812 tid = 0
29813; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29814 end
29815`endif
29816
29817`endif
29818
29819`endif
29820
29821 end
29822 endtask
29823
29824
29825 task slam_NonZeroTsbConfig3_core6_thread1;
29826 input [63:0] value;
29827 reg [5:0] tid;
29828 integer junk;
29829
29830 begin
29831`ifdef AXIS_EMUL_COSIM
29832//Do Nothing
29833`else
29834`ifdef GATESIM
29835//Do Nothing
29836`else
29837`ifdef CORE_6
29838 if (`PARGS.nas_check_on) begin
29839 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 1, 54, value);
29840 tid = 1
29841; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29842 end
29843`endif
29844
29845`endif
29846
29847`endif
29848
29849 end
29850 endtask
29851
29852
29853 task slam_NonZeroTsbConfig3_core6_thread2;
29854 input [63:0] value;
29855 reg [5:0] tid;
29856 integer junk;
29857
29858 begin
29859`ifdef AXIS_EMUL_COSIM
29860//Do Nothing
29861`else
29862`ifdef GATESIM
29863//Do Nothing
29864`else
29865`ifdef CORE_6
29866 if (`PARGS.nas_check_on) begin
29867 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 2, 54, value);
29868 tid = 2
29869; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29870 end
29871`endif
29872
29873`endif
29874
29875`endif
29876
29877 end
29878 endtask
29879
29880
29881 task slam_NonZeroTsbConfig3_core6_thread3;
29882 input [63:0] value;
29883 reg [5:0] tid;
29884 integer junk;
29885
29886 begin
29887`ifdef AXIS_EMUL_COSIM
29888//Do Nothing
29889`else
29890`ifdef GATESIM
29891//Do Nothing
29892`else
29893`ifdef CORE_6
29894 if (`PARGS.nas_check_on) begin
29895 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 3, 54, value);
29896 tid = 3
29897; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29898 end
29899`endif
29900
29901`endif
29902
29903`endif
29904
29905 end
29906 endtask
29907
29908
29909 task slam_NonZeroTsbConfig3_core6_thread4;
29910 input [63:0] value;
29911 reg [5:0] tid;
29912 integer junk;
29913
29914 begin
29915`ifdef AXIS_EMUL_COSIM
29916//Do Nothing
29917`else
29918`ifdef GATESIM
29919//Do Nothing
29920`else
29921`ifdef CORE_6
29922 if (`PARGS.nas_check_on) begin
29923 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 4, 54, value);
29924 tid = 4
29925; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29926 end
29927`endif
29928
29929`endif
29930
29931`endif
29932
29933 end
29934 endtask
29935
29936
29937 task slam_NonZeroTsbConfig3_core6_thread5;
29938 input [63:0] value;
29939 reg [5:0] tid;
29940 integer junk;
29941
29942 begin
29943`ifdef AXIS_EMUL_COSIM
29944//Do Nothing
29945`else
29946`ifdef GATESIM
29947//Do Nothing
29948`else
29949`ifdef CORE_6
29950 if (`PARGS.nas_check_on) begin
29951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 5, 54, value);
29952 tid = 5
29953; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29954 end
29955`endif
29956
29957`endif
29958
29959`endif
29960
29961 end
29962 endtask
29963
29964
29965 task slam_NonZeroTsbConfig3_core6_thread6;
29966 input [63:0] value;
29967 reg [5:0] tid;
29968 integer junk;
29969
29970 begin
29971`ifdef AXIS_EMUL_COSIM
29972//Do Nothing
29973`else
29974`ifdef GATESIM
29975//Do Nothing
29976`else
29977`ifdef CORE_6
29978 if (`PARGS.nas_check_on) begin
29979 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 6, 54, value);
29980 tid = 6
29981; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
29982 end
29983`endif
29984
29985`endif
29986
29987`endif
29988
29989 end
29990 endtask
29991
29992
29993 task slam_NonZeroTsbConfig3_core6_thread7;
29994 input [63:0] value;
29995 reg [5:0] tid;
29996 integer junk;
29997
29998 begin
29999`ifdef AXIS_EMUL_COSIM
30000//Do Nothing
30001`else
30002`ifdef GATESIM
30003//Do Nothing
30004`else
30005`ifdef CORE_6
30006 if (`PARGS.nas_check_on) begin
30007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 6, 7, 54, value);
30008 tid = 7
30009; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30010 end
30011`endif
30012
30013`endif
30014
30015`endif
30016
30017 end
30018 endtask
30019
30020
30021 task slam_NonZeroTsbConfig3_core7_thread0;
30022 input [63:0] value;
30023 reg [5:0] tid;
30024 integer junk;
30025
30026 begin
30027`ifdef AXIS_EMUL_COSIM
30028//Do Nothing
30029`else
30030`ifdef GATESIM
30031//Do Nothing
30032`else
30033`ifdef CORE_7
30034 if (`PARGS.nas_check_on) begin
30035 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 0, 54, value);
30036 tid = 0
30037; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30038 end
30039`endif
30040
30041`endif
30042
30043`endif
30044
30045 end
30046 endtask
30047
30048
30049 task slam_NonZeroTsbConfig3_core7_thread1;
30050 input [63:0] value;
30051 reg [5:0] tid;
30052 integer junk;
30053
30054 begin
30055`ifdef AXIS_EMUL_COSIM
30056//Do Nothing
30057`else
30058`ifdef GATESIM
30059//Do Nothing
30060`else
30061`ifdef CORE_7
30062 if (`PARGS.nas_check_on) begin
30063 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 1, 54, value);
30064 tid = 1
30065; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30066 end
30067`endif
30068
30069`endif
30070
30071`endif
30072
30073 end
30074 endtask
30075
30076
30077 task slam_NonZeroTsbConfig3_core7_thread2;
30078 input [63:0] value;
30079 reg [5:0] tid;
30080 integer junk;
30081
30082 begin
30083`ifdef AXIS_EMUL_COSIM
30084//Do Nothing
30085`else
30086`ifdef GATESIM
30087//Do Nothing
30088`else
30089`ifdef CORE_7
30090 if (`PARGS.nas_check_on) begin
30091 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 2, 54, value);
30092 tid = 2
30093; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30094 end
30095`endif
30096
30097`endif
30098
30099`endif
30100
30101 end
30102 endtask
30103
30104
30105 task slam_NonZeroTsbConfig3_core7_thread3;
30106 input [63:0] value;
30107 reg [5:0] tid;
30108 integer junk;
30109
30110 begin
30111`ifdef AXIS_EMUL_COSIM
30112//Do Nothing
30113`else
30114`ifdef GATESIM
30115//Do Nothing
30116`else
30117`ifdef CORE_7
30118 if (`PARGS.nas_check_on) begin
30119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 3, 54, value);
30120 tid = 3
30121; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30122 end
30123`endif
30124
30125`endif
30126
30127`endif
30128
30129 end
30130 endtask
30131
30132
30133 task slam_NonZeroTsbConfig3_core7_thread4;
30134 input [63:0] value;
30135 reg [5:0] tid;
30136 integer junk;
30137
30138 begin
30139`ifdef AXIS_EMUL_COSIM
30140//Do Nothing
30141`else
30142`ifdef GATESIM
30143//Do Nothing
30144`else
30145`ifdef CORE_7
30146 if (`PARGS.nas_check_on) begin
30147 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 4, 54, value);
30148 tid = 4
30149; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30150 end
30151`endif
30152
30153`endif
30154
30155`endif
30156
30157 end
30158 endtask
30159
30160
30161 task slam_NonZeroTsbConfig3_core7_thread5;
30162 input [63:0] value;
30163 reg [5:0] tid;
30164 integer junk;
30165
30166 begin
30167`ifdef AXIS_EMUL_COSIM
30168//Do Nothing
30169`else
30170`ifdef GATESIM
30171//Do Nothing
30172`else
30173`ifdef CORE_7
30174 if (`PARGS.nas_check_on) begin
30175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 5, 54, value);
30176 tid = 5
30177; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30178 end
30179`endif
30180
30181`endif
30182
30183`endif
30184
30185 end
30186 endtask
30187
30188
30189 task slam_NonZeroTsbConfig3_core7_thread6;
30190 input [63:0] value;
30191 reg [5:0] tid;
30192 integer junk;
30193
30194 begin
30195`ifdef AXIS_EMUL_COSIM
30196//Do Nothing
30197`else
30198`ifdef GATESIM
30199//Do Nothing
30200`else
30201`ifdef CORE_7
30202 if (`PARGS.nas_check_on) begin
30203 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 6, 54, value);
30204 tid = 6
30205; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30206 end
30207`endif
30208
30209`endif
30210
30211`endif
30212
30213 end
30214 endtask
30215
30216
30217 task slam_NonZeroTsbConfig3_core7_thread7;
30218 input [63:0] value;
30219 reg [5:0] tid;
30220 integer junk;
30221
30222 begin
30223`ifdef AXIS_EMUL_COSIM
30224//Do Nothing
30225`else
30226`ifdef GATESIM
30227//Do Nothing
30228`else
30229`ifdef CORE_7
30230 if (`PARGS.nas_check_on) begin
30231 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x54 val=0x%h", 7, 7, 54, value);
30232 tid = 7
30233; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h54, 64'h48, value);
30234 end
30235`endif
30236
30237`endif
30238
30239`endif
30240
30241 end
30242 endtask
30243
30244
30245 task slam_RealRange0_core0_thread0;
30246 input [63:0] value;
30247 reg [5:0] tid;
30248 integer junk;
30249
30250 begin
30251`ifdef AXIS_EMUL_COSIM
30252//Do Nothing
30253`else
30254`ifdef GATESIM
30255//Do Nothing
30256`else
30257`ifdef CORE_0
30258 if (`PARGS.nas_check_on) begin
30259 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
30260 tid = 0
30261; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30262 end
30263`endif
30264
30265`endif
30266
30267`endif
30268
30269 end
30270 endtask
30271
30272
30273 task slam_RealRange0_core0_thread1;
30274 input [63:0] value;
30275 reg [5:0] tid;
30276 integer junk;
30277
30278 begin
30279`ifdef AXIS_EMUL_COSIM
30280//Do Nothing
30281`else
30282`ifdef GATESIM
30283//Do Nothing
30284`else
30285`ifdef CORE_0
30286 if (`PARGS.nas_check_on) begin
30287 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
30288 tid = 1
30289; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30290 end
30291`endif
30292
30293`endif
30294
30295`endif
30296
30297 end
30298 endtask
30299
30300
30301 task slam_RealRange0_core0_thread2;
30302 input [63:0] value;
30303 reg [5:0] tid;
30304 integer junk;
30305
30306 begin
30307`ifdef AXIS_EMUL_COSIM
30308//Do Nothing
30309`else
30310`ifdef GATESIM
30311//Do Nothing
30312`else
30313`ifdef CORE_0
30314 if (`PARGS.nas_check_on) begin
30315 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
30316 tid = 2
30317; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30318 end
30319`endif
30320
30321`endif
30322
30323`endif
30324
30325 end
30326 endtask
30327
30328
30329 task slam_RealRange0_core0_thread3;
30330 input [63:0] value;
30331 reg [5:0] tid;
30332 integer junk;
30333
30334 begin
30335`ifdef AXIS_EMUL_COSIM
30336//Do Nothing
30337`else
30338`ifdef GATESIM
30339//Do Nothing
30340`else
30341`ifdef CORE_0
30342 if (`PARGS.nas_check_on) begin
30343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
30344 tid = 3
30345; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30346 end
30347`endif
30348
30349`endif
30350
30351`endif
30352
30353 end
30354 endtask
30355
30356
30357 task slam_RealRange0_core0_thread4;
30358 input [63:0] value;
30359 reg [5:0] tid;
30360 integer junk;
30361
30362 begin
30363`ifdef AXIS_EMUL_COSIM
30364//Do Nothing
30365`else
30366`ifdef GATESIM
30367//Do Nothing
30368`else
30369`ifdef CORE_0
30370 if (`PARGS.nas_check_on) begin
30371 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
30372 tid = 4
30373; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30374 end
30375`endif
30376
30377`endif
30378
30379`endif
30380
30381 end
30382 endtask
30383
30384
30385 task slam_RealRange0_core0_thread5;
30386 input [63:0] value;
30387 reg [5:0] tid;
30388 integer junk;
30389
30390 begin
30391`ifdef AXIS_EMUL_COSIM
30392//Do Nothing
30393`else
30394`ifdef GATESIM
30395//Do Nothing
30396`else
30397`ifdef CORE_0
30398 if (`PARGS.nas_check_on) begin
30399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
30400 tid = 5
30401; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30402 end
30403`endif
30404
30405`endif
30406
30407`endif
30408
30409 end
30410 endtask
30411
30412
30413 task slam_RealRange0_core0_thread6;
30414 input [63:0] value;
30415 reg [5:0] tid;
30416 integer junk;
30417
30418 begin
30419`ifdef AXIS_EMUL_COSIM
30420//Do Nothing
30421`else
30422`ifdef GATESIM
30423//Do Nothing
30424`else
30425`ifdef CORE_0
30426 if (`PARGS.nas_check_on) begin
30427 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
30428 tid = 6
30429; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30430 end
30431`endif
30432
30433`endif
30434
30435`endif
30436
30437 end
30438 endtask
30439
30440
30441 task slam_RealRange0_core0_thread7;
30442 input [63:0] value;
30443 reg [5:0] tid;
30444 integer junk;
30445
30446 begin
30447`ifdef AXIS_EMUL_COSIM
30448//Do Nothing
30449`else
30450`ifdef GATESIM
30451//Do Nothing
30452`else
30453`ifdef CORE_0
30454 if (`PARGS.nas_check_on) begin
30455 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
30456 tid = 7
30457; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30458 end
30459`endif
30460
30461`endif
30462
30463`endif
30464
30465 end
30466 endtask
30467
30468
30469 task slam_RealRange0_core1_thread0;
30470 input [63:0] value;
30471 reg [5:0] tid;
30472 integer junk;
30473
30474 begin
30475`ifdef AXIS_EMUL_COSIM
30476//Do Nothing
30477`else
30478`ifdef GATESIM
30479//Do Nothing
30480`else
30481`ifdef CORE_1
30482 if (`PARGS.nas_check_on) begin
30483 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
30484 tid = 0
30485; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30486 end
30487`endif
30488
30489`endif
30490
30491`endif
30492
30493 end
30494 endtask
30495
30496
30497 task slam_RealRange0_core1_thread1;
30498 input [63:0] value;
30499 reg [5:0] tid;
30500 integer junk;
30501
30502 begin
30503`ifdef AXIS_EMUL_COSIM
30504//Do Nothing
30505`else
30506`ifdef GATESIM
30507//Do Nothing
30508`else
30509`ifdef CORE_1
30510 if (`PARGS.nas_check_on) begin
30511 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
30512 tid = 1
30513; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30514 end
30515`endif
30516
30517`endif
30518
30519`endif
30520
30521 end
30522 endtask
30523
30524
30525 task slam_RealRange0_core1_thread2;
30526 input [63:0] value;
30527 reg [5:0] tid;
30528 integer junk;
30529
30530 begin
30531`ifdef AXIS_EMUL_COSIM
30532//Do Nothing
30533`else
30534`ifdef GATESIM
30535//Do Nothing
30536`else
30537`ifdef CORE_1
30538 if (`PARGS.nas_check_on) begin
30539 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
30540 tid = 2
30541; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30542 end
30543`endif
30544
30545`endif
30546
30547`endif
30548
30549 end
30550 endtask
30551
30552
30553 task slam_RealRange0_core1_thread3;
30554 input [63:0] value;
30555 reg [5:0] tid;
30556 integer junk;
30557
30558 begin
30559`ifdef AXIS_EMUL_COSIM
30560//Do Nothing
30561`else
30562`ifdef GATESIM
30563//Do Nothing
30564`else
30565`ifdef CORE_1
30566 if (`PARGS.nas_check_on) begin
30567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
30568 tid = 3
30569; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30570 end
30571`endif
30572
30573`endif
30574
30575`endif
30576
30577 end
30578 endtask
30579
30580
30581 task slam_RealRange0_core1_thread4;
30582 input [63:0] value;
30583 reg [5:0] tid;
30584 integer junk;
30585
30586 begin
30587`ifdef AXIS_EMUL_COSIM
30588//Do Nothing
30589`else
30590`ifdef GATESIM
30591//Do Nothing
30592`else
30593`ifdef CORE_1
30594 if (`PARGS.nas_check_on) begin
30595 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
30596 tid = 4
30597; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30598 end
30599`endif
30600
30601`endif
30602
30603`endif
30604
30605 end
30606 endtask
30607
30608
30609 task slam_RealRange0_core1_thread5;
30610 input [63:0] value;
30611 reg [5:0] tid;
30612 integer junk;
30613
30614 begin
30615`ifdef AXIS_EMUL_COSIM
30616//Do Nothing
30617`else
30618`ifdef GATESIM
30619//Do Nothing
30620`else
30621`ifdef CORE_1
30622 if (`PARGS.nas_check_on) begin
30623 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
30624 tid = 5
30625; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30626 end
30627`endif
30628
30629`endif
30630
30631`endif
30632
30633 end
30634 endtask
30635
30636
30637 task slam_RealRange0_core1_thread6;
30638 input [63:0] value;
30639 reg [5:0] tid;
30640 integer junk;
30641
30642 begin
30643`ifdef AXIS_EMUL_COSIM
30644//Do Nothing
30645`else
30646`ifdef GATESIM
30647//Do Nothing
30648`else
30649`ifdef CORE_1
30650 if (`PARGS.nas_check_on) begin
30651 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
30652 tid = 6
30653; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30654 end
30655`endif
30656
30657`endif
30658
30659`endif
30660
30661 end
30662 endtask
30663
30664
30665 task slam_RealRange0_core1_thread7;
30666 input [63:0] value;
30667 reg [5:0] tid;
30668 integer junk;
30669
30670 begin
30671`ifdef AXIS_EMUL_COSIM
30672//Do Nothing
30673`else
30674`ifdef GATESIM
30675//Do Nothing
30676`else
30677`ifdef CORE_1
30678 if (`PARGS.nas_check_on) begin
30679 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
30680 tid = 7
30681; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30682 end
30683`endif
30684
30685`endif
30686
30687`endif
30688
30689 end
30690 endtask
30691
30692
30693 task slam_RealRange0_core2_thread0;
30694 input [63:0] value;
30695 reg [5:0] tid;
30696 integer junk;
30697
30698 begin
30699`ifdef AXIS_EMUL_COSIM
30700//Do Nothing
30701`else
30702`ifdef GATESIM
30703//Do Nothing
30704`else
30705`ifdef CORE_2
30706 if (`PARGS.nas_check_on) begin
30707 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
30708 tid = 0
30709; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30710 end
30711`endif
30712
30713`endif
30714
30715`endif
30716
30717 end
30718 endtask
30719
30720
30721 task slam_RealRange0_core2_thread1;
30722 input [63:0] value;
30723 reg [5:0] tid;
30724 integer junk;
30725
30726 begin
30727`ifdef AXIS_EMUL_COSIM
30728//Do Nothing
30729`else
30730`ifdef GATESIM
30731//Do Nothing
30732`else
30733`ifdef CORE_2
30734 if (`PARGS.nas_check_on) begin
30735 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
30736 tid = 1
30737; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30738 end
30739`endif
30740
30741`endif
30742
30743`endif
30744
30745 end
30746 endtask
30747
30748
30749 task slam_RealRange0_core2_thread2;
30750 input [63:0] value;
30751 reg [5:0] tid;
30752 integer junk;
30753
30754 begin
30755`ifdef AXIS_EMUL_COSIM
30756//Do Nothing
30757`else
30758`ifdef GATESIM
30759//Do Nothing
30760`else
30761`ifdef CORE_2
30762 if (`PARGS.nas_check_on) begin
30763 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
30764 tid = 2
30765; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30766 end
30767`endif
30768
30769`endif
30770
30771`endif
30772
30773 end
30774 endtask
30775
30776
30777 task slam_RealRange0_core2_thread3;
30778 input [63:0] value;
30779 reg [5:0] tid;
30780 integer junk;
30781
30782 begin
30783`ifdef AXIS_EMUL_COSIM
30784//Do Nothing
30785`else
30786`ifdef GATESIM
30787//Do Nothing
30788`else
30789`ifdef CORE_2
30790 if (`PARGS.nas_check_on) begin
30791 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
30792 tid = 3
30793; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30794 end
30795`endif
30796
30797`endif
30798
30799`endif
30800
30801 end
30802 endtask
30803
30804
30805 task slam_RealRange0_core2_thread4;
30806 input [63:0] value;
30807 reg [5:0] tid;
30808 integer junk;
30809
30810 begin
30811`ifdef AXIS_EMUL_COSIM
30812//Do Nothing
30813`else
30814`ifdef GATESIM
30815//Do Nothing
30816`else
30817`ifdef CORE_2
30818 if (`PARGS.nas_check_on) begin
30819 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
30820 tid = 4
30821; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30822 end
30823`endif
30824
30825`endif
30826
30827`endif
30828
30829 end
30830 endtask
30831
30832
30833 task slam_RealRange0_core2_thread5;
30834 input [63:0] value;
30835 reg [5:0] tid;
30836 integer junk;
30837
30838 begin
30839`ifdef AXIS_EMUL_COSIM
30840//Do Nothing
30841`else
30842`ifdef GATESIM
30843//Do Nothing
30844`else
30845`ifdef CORE_2
30846 if (`PARGS.nas_check_on) begin
30847 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
30848 tid = 5
30849; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30850 end
30851`endif
30852
30853`endif
30854
30855`endif
30856
30857 end
30858 endtask
30859
30860
30861 task slam_RealRange0_core2_thread6;
30862 input [63:0] value;
30863 reg [5:0] tid;
30864 integer junk;
30865
30866 begin
30867`ifdef AXIS_EMUL_COSIM
30868//Do Nothing
30869`else
30870`ifdef GATESIM
30871//Do Nothing
30872`else
30873`ifdef CORE_2
30874 if (`PARGS.nas_check_on) begin
30875 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
30876 tid = 6
30877; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30878 end
30879`endif
30880
30881`endif
30882
30883`endif
30884
30885 end
30886 endtask
30887
30888
30889 task slam_RealRange0_core2_thread7;
30890 input [63:0] value;
30891 reg [5:0] tid;
30892 integer junk;
30893
30894 begin
30895`ifdef AXIS_EMUL_COSIM
30896//Do Nothing
30897`else
30898`ifdef GATESIM
30899//Do Nothing
30900`else
30901`ifdef CORE_2
30902 if (`PARGS.nas_check_on) begin
30903 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
30904 tid = 7
30905; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30906 end
30907`endif
30908
30909`endif
30910
30911`endif
30912
30913 end
30914 endtask
30915
30916
30917 task slam_RealRange0_core3_thread0;
30918 input [63:0] value;
30919 reg [5:0] tid;
30920 integer junk;
30921
30922 begin
30923`ifdef AXIS_EMUL_COSIM
30924//Do Nothing
30925`else
30926`ifdef GATESIM
30927//Do Nothing
30928`else
30929`ifdef CORE_3
30930 if (`PARGS.nas_check_on) begin
30931 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
30932 tid = 0
30933; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30934 end
30935`endif
30936
30937`endif
30938
30939`endif
30940
30941 end
30942 endtask
30943
30944
30945 task slam_RealRange0_core3_thread1;
30946 input [63:0] value;
30947 reg [5:0] tid;
30948 integer junk;
30949
30950 begin
30951`ifdef AXIS_EMUL_COSIM
30952//Do Nothing
30953`else
30954`ifdef GATESIM
30955//Do Nothing
30956`else
30957`ifdef CORE_3
30958 if (`PARGS.nas_check_on) begin
30959 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
30960 tid = 1
30961; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30962 end
30963`endif
30964
30965`endif
30966
30967`endif
30968
30969 end
30970 endtask
30971
30972
30973 task slam_RealRange0_core3_thread2;
30974 input [63:0] value;
30975 reg [5:0] tid;
30976 integer junk;
30977
30978 begin
30979`ifdef AXIS_EMUL_COSIM
30980//Do Nothing
30981`else
30982`ifdef GATESIM
30983//Do Nothing
30984`else
30985`ifdef CORE_3
30986 if (`PARGS.nas_check_on) begin
30987 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
30988 tid = 2
30989; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
30990 end
30991`endif
30992
30993`endif
30994
30995`endif
30996
30997 end
30998 endtask
30999
31000
31001 task slam_RealRange0_core3_thread3;
31002 input [63:0] value;
31003 reg [5:0] tid;
31004 integer junk;
31005
31006 begin
31007`ifdef AXIS_EMUL_COSIM
31008//Do Nothing
31009`else
31010`ifdef GATESIM
31011//Do Nothing
31012`else
31013`ifdef CORE_3
31014 if (`PARGS.nas_check_on) begin
31015 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
31016 tid = 3
31017; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31018 end
31019`endif
31020
31021`endif
31022
31023`endif
31024
31025 end
31026 endtask
31027
31028
31029 task slam_RealRange0_core3_thread4;
31030 input [63:0] value;
31031 reg [5:0] tid;
31032 integer junk;
31033
31034 begin
31035`ifdef AXIS_EMUL_COSIM
31036//Do Nothing
31037`else
31038`ifdef GATESIM
31039//Do Nothing
31040`else
31041`ifdef CORE_3
31042 if (`PARGS.nas_check_on) begin
31043 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
31044 tid = 4
31045; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31046 end
31047`endif
31048
31049`endif
31050
31051`endif
31052
31053 end
31054 endtask
31055
31056
31057 task slam_RealRange0_core3_thread5;
31058 input [63:0] value;
31059 reg [5:0] tid;
31060 integer junk;
31061
31062 begin
31063`ifdef AXIS_EMUL_COSIM
31064//Do Nothing
31065`else
31066`ifdef GATESIM
31067//Do Nothing
31068`else
31069`ifdef CORE_3
31070 if (`PARGS.nas_check_on) begin
31071 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
31072 tid = 5
31073; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31074 end
31075`endif
31076
31077`endif
31078
31079`endif
31080
31081 end
31082 endtask
31083
31084
31085 task slam_RealRange0_core3_thread6;
31086 input [63:0] value;
31087 reg [5:0] tid;
31088 integer junk;
31089
31090 begin
31091`ifdef AXIS_EMUL_COSIM
31092//Do Nothing
31093`else
31094`ifdef GATESIM
31095//Do Nothing
31096`else
31097`ifdef CORE_3
31098 if (`PARGS.nas_check_on) begin
31099 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
31100 tid = 6
31101; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31102 end
31103`endif
31104
31105`endif
31106
31107`endif
31108
31109 end
31110 endtask
31111
31112
31113 task slam_RealRange0_core3_thread7;
31114 input [63:0] value;
31115 reg [5:0] tid;
31116 integer junk;
31117
31118 begin
31119`ifdef AXIS_EMUL_COSIM
31120//Do Nothing
31121`else
31122`ifdef GATESIM
31123//Do Nothing
31124`else
31125`ifdef CORE_3
31126 if (`PARGS.nas_check_on) begin
31127 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
31128 tid = 7
31129; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31130 end
31131`endif
31132
31133`endif
31134
31135`endif
31136
31137 end
31138 endtask
31139
31140
31141 task slam_RealRange0_core4_thread0;
31142 input [63:0] value;
31143 reg [5:0] tid;
31144 integer junk;
31145
31146 begin
31147`ifdef AXIS_EMUL_COSIM
31148//Do Nothing
31149`else
31150`ifdef GATESIM
31151//Do Nothing
31152`else
31153`ifdef CORE_4
31154 if (`PARGS.nas_check_on) begin
31155 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
31156 tid = 0
31157; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31158 end
31159`endif
31160
31161`endif
31162
31163`endif
31164
31165 end
31166 endtask
31167
31168
31169 task slam_RealRange0_core4_thread1;
31170 input [63:0] value;
31171 reg [5:0] tid;
31172 integer junk;
31173
31174 begin
31175`ifdef AXIS_EMUL_COSIM
31176//Do Nothing
31177`else
31178`ifdef GATESIM
31179//Do Nothing
31180`else
31181`ifdef CORE_4
31182 if (`PARGS.nas_check_on) begin
31183 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
31184 tid = 1
31185; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31186 end
31187`endif
31188
31189`endif
31190
31191`endif
31192
31193 end
31194 endtask
31195
31196
31197 task slam_RealRange0_core4_thread2;
31198 input [63:0] value;
31199 reg [5:0] tid;
31200 integer junk;
31201
31202 begin
31203`ifdef AXIS_EMUL_COSIM
31204//Do Nothing
31205`else
31206`ifdef GATESIM
31207//Do Nothing
31208`else
31209`ifdef CORE_4
31210 if (`PARGS.nas_check_on) begin
31211 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
31212 tid = 2
31213; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31214 end
31215`endif
31216
31217`endif
31218
31219`endif
31220
31221 end
31222 endtask
31223
31224
31225 task slam_RealRange0_core4_thread3;
31226 input [63:0] value;
31227 reg [5:0] tid;
31228 integer junk;
31229
31230 begin
31231`ifdef AXIS_EMUL_COSIM
31232//Do Nothing
31233`else
31234`ifdef GATESIM
31235//Do Nothing
31236`else
31237`ifdef CORE_4
31238 if (`PARGS.nas_check_on) begin
31239 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
31240 tid = 3
31241; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31242 end
31243`endif
31244
31245`endif
31246
31247`endif
31248
31249 end
31250 endtask
31251
31252
31253 task slam_RealRange0_core4_thread4;
31254 input [63:0] value;
31255 reg [5:0] tid;
31256 integer junk;
31257
31258 begin
31259`ifdef AXIS_EMUL_COSIM
31260//Do Nothing
31261`else
31262`ifdef GATESIM
31263//Do Nothing
31264`else
31265`ifdef CORE_4
31266 if (`PARGS.nas_check_on) begin
31267 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
31268 tid = 4
31269; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31270 end
31271`endif
31272
31273`endif
31274
31275`endif
31276
31277 end
31278 endtask
31279
31280
31281 task slam_RealRange0_core4_thread5;
31282 input [63:0] value;
31283 reg [5:0] tid;
31284 integer junk;
31285
31286 begin
31287`ifdef AXIS_EMUL_COSIM
31288//Do Nothing
31289`else
31290`ifdef GATESIM
31291//Do Nothing
31292`else
31293`ifdef CORE_4
31294 if (`PARGS.nas_check_on) begin
31295 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
31296 tid = 5
31297; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31298 end
31299`endif
31300
31301`endif
31302
31303`endif
31304
31305 end
31306 endtask
31307
31308
31309 task slam_RealRange0_core4_thread6;
31310 input [63:0] value;
31311 reg [5:0] tid;
31312 integer junk;
31313
31314 begin
31315`ifdef AXIS_EMUL_COSIM
31316//Do Nothing
31317`else
31318`ifdef GATESIM
31319//Do Nothing
31320`else
31321`ifdef CORE_4
31322 if (`PARGS.nas_check_on) begin
31323 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
31324 tid = 6
31325; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31326 end
31327`endif
31328
31329`endif
31330
31331`endif
31332
31333 end
31334 endtask
31335
31336
31337 task slam_RealRange0_core4_thread7;
31338 input [63:0] value;
31339 reg [5:0] tid;
31340 integer junk;
31341
31342 begin
31343`ifdef AXIS_EMUL_COSIM
31344//Do Nothing
31345`else
31346`ifdef GATESIM
31347//Do Nothing
31348`else
31349`ifdef CORE_4
31350 if (`PARGS.nas_check_on) begin
31351 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
31352 tid = 7
31353; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31354 end
31355`endif
31356
31357`endif
31358
31359`endif
31360
31361 end
31362 endtask
31363
31364
31365 task slam_RealRange0_core5_thread0;
31366 input [63:0] value;
31367 reg [5:0] tid;
31368 integer junk;
31369
31370 begin
31371`ifdef AXIS_EMUL_COSIM
31372//Do Nothing
31373`else
31374`ifdef GATESIM
31375//Do Nothing
31376`else
31377`ifdef CORE_5
31378 if (`PARGS.nas_check_on) begin
31379 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
31380 tid = 0
31381; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31382 end
31383`endif
31384
31385`endif
31386
31387`endif
31388
31389 end
31390 endtask
31391
31392
31393 task slam_RealRange0_core5_thread1;
31394 input [63:0] value;
31395 reg [5:0] tid;
31396 integer junk;
31397
31398 begin
31399`ifdef AXIS_EMUL_COSIM
31400//Do Nothing
31401`else
31402`ifdef GATESIM
31403//Do Nothing
31404`else
31405`ifdef CORE_5
31406 if (`PARGS.nas_check_on) begin
31407 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
31408 tid = 1
31409; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31410 end
31411`endif
31412
31413`endif
31414
31415`endif
31416
31417 end
31418 endtask
31419
31420
31421 task slam_RealRange0_core5_thread2;
31422 input [63:0] value;
31423 reg [5:0] tid;
31424 integer junk;
31425
31426 begin
31427`ifdef AXIS_EMUL_COSIM
31428//Do Nothing
31429`else
31430`ifdef GATESIM
31431//Do Nothing
31432`else
31433`ifdef CORE_5
31434 if (`PARGS.nas_check_on) begin
31435 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
31436 tid = 2
31437; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31438 end
31439`endif
31440
31441`endif
31442
31443`endif
31444
31445 end
31446 endtask
31447
31448
31449 task slam_RealRange0_core5_thread3;
31450 input [63:0] value;
31451 reg [5:0] tid;
31452 integer junk;
31453
31454 begin
31455`ifdef AXIS_EMUL_COSIM
31456//Do Nothing
31457`else
31458`ifdef GATESIM
31459//Do Nothing
31460`else
31461`ifdef CORE_5
31462 if (`PARGS.nas_check_on) begin
31463 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
31464 tid = 3
31465; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31466 end
31467`endif
31468
31469`endif
31470
31471`endif
31472
31473 end
31474 endtask
31475
31476
31477 task slam_RealRange0_core5_thread4;
31478 input [63:0] value;
31479 reg [5:0] tid;
31480 integer junk;
31481
31482 begin
31483`ifdef AXIS_EMUL_COSIM
31484//Do Nothing
31485`else
31486`ifdef GATESIM
31487//Do Nothing
31488`else
31489`ifdef CORE_5
31490 if (`PARGS.nas_check_on) begin
31491 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
31492 tid = 4
31493; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31494 end
31495`endif
31496
31497`endif
31498
31499`endif
31500
31501 end
31502 endtask
31503
31504
31505 task slam_RealRange0_core5_thread5;
31506 input [63:0] value;
31507 reg [5:0] tid;
31508 integer junk;
31509
31510 begin
31511`ifdef AXIS_EMUL_COSIM
31512//Do Nothing
31513`else
31514`ifdef GATESIM
31515//Do Nothing
31516`else
31517`ifdef CORE_5
31518 if (`PARGS.nas_check_on) begin
31519 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
31520 tid = 5
31521; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31522 end
31523`endif
31524
31525`endif
31526
31527`endif
31528
31529 end
31530 endtask
31531
31532
31533 task slam_RealRange0_core5_thread6;
31534 input [63:0] value;
31535 reg [5:0] tid;
31536 integer junk;
31537
31538 begin
31539`ifdef AXIS_EMUL_COSIM
31540//Do Nothing
31541`else
31542`ifdef GATESIM
31543//Do Nothing
31544`else
31545`ifdef CORE_5
31546 if (`PARGS.nas_check_on) begin
31547 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
31548 tid = 6
31549; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31550 end
31551`endif
31552
31553`endif
31554
31555`endif
31556
31557 end
31558 endtask
31559
31560
31561 task slam_RealRange0_core5_thread7;
31562 input [63:0] value;
31563 reg [5:0] tid;
31564 integer junk;
31565
31566 begin
31567`ifdef AXIS_EMUL_COSIM
31568//Do Nothing
31569`else
31570`ifdef GATESIM
31571//Do Nothing
31572`else
31573`ifdef CORE_5
31574 if (`PARGS.nas_check_on) begin
31575 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
31576 tid = 7
31577; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31578 end
31579`endif
31580
31581`endif
31582
31583`endif
31584
31585 end
31586 endtask
31587
31588
31589 task slam_RealRange0_core6_thread0;
31590 input [63:0] value;
31591 reg [5:0] tid;
31592 integer junk;
31593
31594 begin
31595`ifdef AXIS_EMUL_COSIM
31596//Do Nothing
31597`else
31598`ifdef GATESIM
31599//Do Nothing
31600`else
31601`ifdef CORE_6
31602 if (`PARGS.nas_check_on) begin
31603 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
31604 tid = 0
31605; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31606 end
31607`endif
31608
31609`endif
31610
31611`endif
31612
31613 end
31614 endtask
31615
31616
31617 task slam_RealRange0_core6_thread1;
31618 input [63:0] value;
31619 reg [5:0] tid;
31620 integer junk;
31621
31622 begin
31623`ifdef AXIS_EMUL_COSIM
31624//Do Nothing
31625`else
31626`ifdef GATESIM
31627//Do Nothing
31628`else
31629`ifdef CORE_6
31630 if (`PARGS.nas_check_on) begin
31631 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
31632 tid = 1
31633; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31634 end
31635`endif
31636
31637`endif
31638
31639`endif
31640
31641 end
31642 endtask
31643
31644
31645 task slam_RealRange0_core6_thread2;
31646 input [63:0] value;
31647 reg [5:0] tid;
31648 integer junk;
31649
31650 begin
31651`ifdef AXIS_EMUL_COSIM
31652//Do Nothing
31653`else
31654`ifdef GATESIM
31655//Do Nothing
31656`else
31657`ifdef CORE_6
31658 if (`PARGS.nas_check_on) begin
31659 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
31660 tid = 2
31661; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31662 end
31663`endif
31664
31665`endif
31666
31667`endif
31668
31669 end
31670 endtask
31671
31672
31673 task slam_RealRange0_core6_thread3;
31674 input [63:0] value;
31675 reg [5:0] tid;
31676 integer junk;
31677
31678 begin
31679`ifdef AXIS_EMUL_COSIM
31680//Do Nothing
31681`else
31682`ifdef GATESIM
31683//Do Nothing
31684`else
31685`ifdef CORE_6
31686 if (`PARGS.nas_check_on) begin
31687 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
31688 tid = 3
31689; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31690 end
31691`endif
31692
31693`endif
31694
31695`endif
31696
31697 end
31698 endtask
31699
31700
31701 task slam_RealRange0_core6_thread4;
31702 input [63:0] value;
31703 reg [5:0] tid;
31704 integer junk;
31705
31706 begin
31707`ifdef AXIS_EMUL_COSIM
31708//Do Nothing
31709`else
31710`ifdef GATESIM
31711//Do Nothing
31712`else
31713`ifdef CORE_6
31714 if (`PARGS.nas_check_on) begin
31715 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
31716 tid = 4
31717; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31718 end
31719`endif
31720
31721`endif
31722
31723`endif
31724
31725 end
31726 endtask
31727
31728
31729 task slam_RealRange0_core6_thread5;
31730 input [63:0] value;
31731 reg [5:0] tid;
31732 integer junk;
31733
31734 begin
31735`ifdef AXIS_EMUL_COSIM
31736//Do Nothing
31737`else
31738`ifdef GATESIM
31739//Do Nothing
31740`else
31741`ifdef CORE_6
31742 if (`PARGS.nas_check_on) begin
31743 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
31744 tid = 5
31745; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31746 end
31747`endif
31748
31749`endif
31750
31751`endif
31752
31753 end
31754 endtask
31755
31756
31757 task slam_RealRange0_core6_thread6;
31758 input [63:0] value;
31759 reg [5:0] tid;
31760 integer junk;
31761
31762 begin
31763`ifdef AXIS_EMUL_COSIM
31764//Do Nothing
31765`else
31766`ifdef GATESIM
31767//Do Nothing
31768`else
31769`ifdef CORE_6
31770 if (`PARGS.nas_check_on) begin
31771 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
31772 tid = 6
31773; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31774 end
31775`endif
31776
31777`endif
31778
31779`endif
31780
31781 end
31782 endtask
31783
31784
31785 task slam_RealRange0_core6_thread7;
31786 input [63:0] value;
31787 reg [5:0] tid;
31788 integer junk;
31789
31790 begin
31791`ifdef AXIS_EMUL_COSIM
31792//Do Nothing
31793`else
31794`ifdef GATESIM
31795//Do Nothing
31796`else
31797`ifdef CORE_6
31798 if (`PARGS.nas_check_on) begin
31799 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
31800 tid = 7
31801; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31802 end
31803`endif
31804
31805`endif
31806
31807`endif
31808
31809 end
31810 endtask
31811
31812
31813 task slam_RealRange0_core7_thread0;
31814 input [63:0] value;
31815 reg [5:0] tid;
31816 integer junk;
31817
31818 begin
31819`ifdef AXIS_EMUL_COSIM
31820//Do Nothing
31821`else
31822`ifdef GATESIM
31823//Do Nothing
31824`else
31825`ifdef CORE_7
31826 if (`PARGS.nas_check_on) begin
31827 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
31828 tid = 0
31829; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31830 end
31831`endif
31832
31833`endif
31834
31835`endif
31836
31837 end
31838 endtask
31839
31840
31841 task slam_RealRange0_core7_thread1;
31842 input [63:0] value;
31843 reg [5:0] tid;
31844 integer junk;
31845
31846 begin
31847`ifdef AXIS_EMUL_COSIM
31848//Do Nothing
31849`else
31850`ifdef GATESIM
31851//Do Nothing
31852`else
31853`ifdef CORE_7
31854 if (`PARGS.nas_check_on) begin
31855 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
31856 tid = 1
31857; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31858 end
31859`endif
31860
31861`endif
31862
31863`endif
31864
31865 end
31866 endtask
31867
31868
31869 task slam_RealRange0_core7_thread2;
31870 input [63:0] value;
31871 reg [5:0] tid;
31872 integer junk;
31873
31874 begin
31875`ifdef AXIS_EMUL_COSIM
31876//Do Nothing
31877`else
31878`ifdef GATESIM
31879//Do Nothing
31880`else
31881`ifdef CORE_7
31882 if (`PARGS.nas_check_on) begin
31883 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
31884 tid = 2
31885; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31886 end
31887`endif
31888
31889`endif
31890
31891`endif
31892
31893 end
31894 endtask
31895
31896
31897 task slam_RealRange0_core7_thread3;
31898 input [63:0] value;
31899 reg [5:0] tid;
31900 integer junk;
31901
31902 begin
31903`ifdef AXIS_EMUL_COSIM
31904//Do Nothing
31905`else
31906`ifdef GATESIM
31907//Do Nothing
31908`else
31909`ifdef CORE_7
31910 if (`PARGS.nas_check_on) begin
31911 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
31912 tid = 3
31913; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31914 end
31915`endif
31916
31917`endif
31918
31919`endif
31920
31921 end
31922 endtask
31923
31924
31925 task slam_RealRange0_core7_thread4;
31926 input [63:0] value;
31927 reg [5:0] tid;
31928 integer junk;
31929
31930 begin
31931`ifdef AXIS_EMUL_COSIM
31932//Do Nothing
31933`else
31934`ifdef GATESIM
31935//Do Nothing
31936`else
31937`ifdef CORE_7
31938 if (`PARGS.nas_check_on) begin
31939 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
31940 tid = 4
31941; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31942 end
31943`endif
31944
31945`endif
31946
31947`endif
31948
31949 end
31950 endtask
31951
31952
31953 task slam_RealRange0_core7_thread5;
31954 input [63:0] value;
31955 reg [5:0] tid;
31956 integer junk;
31957
31958 begin
31959`ifdef AXIS_EMUL_COSIM
31960//Do Nothing
31961`else
31962`ifdef GATESIM
31963//Do Nothing
31964`else
31965`ifdef CORE_7
31966 if (`PARGS.nas_check_on) begin
31967 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
31968 tid = 5
31969; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31970 end
31971`endif
31972
31973`endif
31974
31975`endif
31976
31977 end
31978 endtask
31979
31980
31981 task slam_RealRange0_core7_thread6;
31982 input [63:0] value;
31983 reg [5:0] tid;
31984 integer junk;
31985
31986 begin
31987`ifdef AXIS_EMUL_COSIM
31988//Do Nothing
31989`else
31990`ifdef GATESIM
31991//Do Nothing
31992`else
31993`ifdef CORE_7
31994 if (`PARGS.nas_check_on) begin
31995 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
31996 tid = 6
31997; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
31998 end
31999`endif
32000
32001`endif
32002
32003`endif
32004
32005 end
32006 endtask
32007
32008
32009 task slam_RealRange0_core7_thread7;
32010 input [63:0] value;
32011 reg [5:0] tid;
32012 integer junk;
32013
32014 begin
32015`ifdef AXIS_EMUL_COSIM
32016//Do Nothing
32017`else
32018`ifdef GATESIM
32019//Do Nothing
32020`else
32021`ifdef CORE_7
32022 if (`PARGS.nas_check_on) begin
32023 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
32024 tid = 7
32025; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h108, value);
32026 end
32027`endif
32028
32029`endif
32030
32031`endif
32032
32033 end
32034 endtask
32035
32036
32037 task slam_RealRange1_core0_thread0;
32038 input [63:0] value;
32039 reg [5:0] tid;
32040 integer junk;
32041
32042 begin
32043`ifdef AXIS_EMUL_COSIM
32044//Do Nothing
32045`else
32046`ifdef GATESIM
32047//Do Nothing
32048`else
32049`ifdef CORE_0
32050 if (`PARGS.nas_check_on) begin
32051 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
32052 tid = 0
32053; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32054 end
32055`endif
32056
32057`endif
32058
32059`endif
32060
32061 end
32062 endtask
32063
32064
32065 task slam_RealRange1_core0_thread1;
32066 input [63:0] value;
32067 reg [5:0] tid;
32068 integer junk;
32069
32070 begin
32071`ifdef AXIS_EMUL_COSIM
32072//Do Nothing
32073`else
32074`ifdef GATESIM
32075//Do Nothing
32076`else
32077`ifdef CORE_0
32078 if (`PARGS.nas_check_on) begin
32079 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
32080 tid = 1
32081; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32082 end
32083`endif
32084
32085`endif
32086
32087`endif
32088
32089 end
32090 endtask
32091
32092
32093 task slam_RealRange1_core0_thread2;
32094 input [63:0] value;
32095 reg [5:0] tid;
32096 integer junk;
32097
32098 begin
32099`ifdef AXIS_EMUL_COSIM
32100//Do Nothing
32101`else
32102`ifdef GATESIM
32103//Do Nothing
32104`else
32105`ifdef CORE_0
32106 if (`PARGS.nas_check_on) begin
32107 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
32108 tid = 2
32109; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32110 end
32111`endif
32112
32113`endif
32114
32115`endif
32116
32117 end
32118 endtask
32119
32120
32121 task slam_RealRange1_core0_thread3;
32122 input [63:0] value;
32123 reg [5:0] tid;
32124 integer junk;
32125
32126 begin
32127`ifdef AXIS_EMUL_COSIM
32128//Do Nothing
32129`else
32130`ifdef GATESIM
32131//Do Nothing
32132`else
32133`ifdef CORE_0
32134 if (`PARGS.nas_check_on) begin
32135 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
32136 tid = 3
32137; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32138 end
32139`endif
32140
32141`endif
32142
32143`endif
32144
32145 end
32146 endtask
32147
32148
32149 task slam_RealRange1_core0_thread4;
32150 input [63:0] value;
32151 reg [5:0] tid;
32152 integer junk;
32153
32154 begin
32155`ifdef AXIS_EMUL_COSIM
32156//Do Nothing
32157`else
32158`ifdef GATESIM
32159//Do Nothing
32160`else
32161`ifdef CORE_0
32162 if (`PARGS.nas_check_on) begin
32163 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
32164 tid = 4
32165; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32166 end
32167`endif
32168
32169`endif
32170
32171`endif
32172
32173 end
32174 endtask
32175
32176
32177 task slam_RealRange1_core0_thread5;
32178 input [63:0] value;
32179 reg [5:0] tid;
32180 integer junk;
32181
32182 begin
32183`ifdef AXIS_EMUL_COSIM
32184//Do Nothing
32185`else
32186`ifdef GATESIM
32187//Do Nothing
32188`else
32189`ifdef CORE_0
32190 if (`PARGS.nas_check_on) begin
32191 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
32192 tid = 5
32193; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32194 end
32195`endif
32196
32197`endif
32198
32199`endif
32200
32201 end
32202 endtask
32203
32204
32205 task slam_RealRange1_core0_thread6;
32206 input [63:0] value;
32207 reg [5:0] tid;
32208 integer junk;
32209
32210 begin
32211`ifdef AXIS_EMUL_COSIM
32212//Do Nothing
32213`else
32214`ifdef GATESIM
32215//Do Nothing
32216`else
32217`ifdef CORE_0
32218 if (`PARGS.nas_check_on) begin
32219 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
32220 tid = 6
32221; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32222 end
32223`endif
32224
32225`endif
32226
32227`endif
32228
32229 end
32230 endtask
32231
32232
32233 task slam_RealRange1_core0_thread7;
32234 input [63:0] value;
32235 reg [5:0] tid;
32236 integer junk;
32237
32238 begin
32239`ifdef AXIS_EMUL_COSIM
32240//Do Nothing
32241`else
32242`ifdef GATESIM
32243//Do Nothing
32244`else
32245`ifdef CORE_0
32246 if (`PARGS.nas_check_on) begin
32247 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
32248 tid = 7
32249; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32250 end
32251`endif
32252
32253`endif
32254
32255`endif
32256
32257 end
32258 endtask
32259
32260
32261 task slam_RealRange1_core1_thread0;
32262 input [63:0] value;
32263 reg [5:0] tid;
32264 integer junk;
32265
32266 begin
32267`ifdef AXIS_EMUL_COSIM
32268//Do Nothing
32269`else
32270`ifdef GATESIM
32271//Do Nothing
32272`else
32273`ifdef CORE_1
32274 if (`PARGS.nas_check_on) begin
32275 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
32276 tid = 0
32277; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32278 end
32279`endif
32280
32281`endif
32282
32283`endif
32284
32285 end
32286 endtask
32287
32288
32289 task slam_RealRange1_core1_thread1;
32290 input [63:0] value;
32291 reg [5:0] tid;
32292 integer junk;
32293
32294 begin
32295`ifdef AXIS_EMUL_COSIM
32296//Do Nothing
32297`else
32298`ifdef GATESIM
32299//Do Nothing
32300`else
32301`ifdef CORE_1
32302 if (`PARGS.nas_check_on) begin
32303 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
32304 tid = 1
32305; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32306 end
32307`endif
32308
32309`endif
32310
32311`endif
32312
32313 end
32314 endtask
32315
32316
32317 task slam_RealRange1_core1_thread2;
32318 input [63:0] value;
32319 reg [5:0] tid;
32320 integer junk;
32321
32322 begin
32323`ifdef AXIS_EMUL_COSIM
32324//Do Nothing
32325`else
32326`ifdef GATESIM
32327//Do Nothing
32328`else
32329`ifdef CORE_1
32330 if (`PARGS.nas_check_on) begin
32331 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
32332 tid = 2
32333; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32334 end
32335`endif
32336
32337`endif
32338
32339`endif
32340
32341 end
32342 endtask
32343
32344
32345 task slam_RealRange1_core1_thread3;
32346 input [63:0] value;
32347 reg [5:0] tid;
32348 integer junk;
32349
32350 begin
32351`ifdef AXIS_EMUL_COSIM
32352//Do Nothing
32353`else
32354`ifdef GATESIM
32355//Do Nothing
32356`else
32357`ifdef CORE_1
32358 if (`PARGS.nas_check_on) begin
32359 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
32360 tid = 3
32361; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32362 end
32363`endif
32364
32365`endif
32366
32367`endif
32368
32369 end
32370 endtask
32371
32372
32373 task slam_RealRange1_core1_thread4;
32374 input [63:0] value;
32375 reg [5:0] tid;
32376 integer junk;
32377
32378 begin
32379`ifdef AXIS_EMUL_COSIM
32380//Do Nothing
32381`else
32382`ifdef GATESIM
32383//Do Nothing
32384`else
32385`ifdef CORE_1
32386 if (`PARGS.nas_check_on) begin
32387 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
32388 tid = 4
32389; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32390 end
32391`endif
32392
32393`endif
32394
32395`endif
32396
32397 end
32398 endtask
32399
32400
32401 task slam_RealRange1_core1_thread5;
32402 input [63:0] value;
32403 reg [5:0] tid;
32404 integer junk;
32405
32406 begin
32407`ifdef AXIS_EMUL_COSIM
32408//Do Nothing
32409`else
32410`ifdef GATESIM
32411//Do Nothing
32412`else
32413`ifdef CORE_1
32414 if (`PARGS.nas_check_on) begin
32415 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
32416 tid = 5
32417; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32418 end
32419`endif
32420
32421`endif
32422
32423`endif
32424
32425 end
32426 endtask
32427
32428
32429 task slam_RealRange1_core1_thread6;
32430 input [63:0] value;
32431 reg [5:0] tid;
32432 integer junk;
32433
32434 begin
32435`ifdef AXIS_EMUL_COSIM
32436//Do Nothing
32437`else
32438`ifdef GATESIM
32439//Do Nothing
32440`else
32441`ifdef CORE_1
32442 if (`PARGS.nas_check_on) begin
32443 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
32444 tid = 6
32445; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32446 end
32447`endif
32448
32449`endif
32450
32451`endif
32452
32453 end
32454 endtask
32455
32456
32457 task slam_RealRange1_core1_thread7;
32458 input [63:0] value;
32459 reg [5:0] tid;
32460 integer junk;
32461
32462 begin
32463`ifdef AXIS_EMUL_COSIM
32464//Do Nothing
32465`else
32466`ifdef GATESIM
32467//Do Nothing
32468`else
32469`ifdef CORE_1
32470 if (`PARGS.nas_check_on) begin
32471 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
32472 tid = 7
32473; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32474 end
32475`endif
32476
32477`endif
32478
32479`endif
32480
32481 end
32482 endtask
32483
32484
32485 task slam_RealRange1_core2_thread0;
32486 input [63:0] value;
32487 reg [5:0] tid;
32488 integer junk;
32489
32490 begin
32491`ifdef AXIS_EMUL_COSIM
32492//Do Nothing
32493`else
32494`ifdef GATESIM
32495//Do Nothing
32496`else
32497`ifdef CORE_2
32498 if (`PARGS.nas_check_on) begin
32499 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
32500 tid = 0
32501; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32502 end
32503`endif
32504
32505`endif
32506
32507`endif
32508
32509 end
32510 endtask
32511
32512
32513 task slam_RealRange1_core2_thread1;
32514 input [63:0] value;
32515 reg [5:0] tid;
32516 integer junk;
32517
32518 begin
32519`ifdef AXIS_EMUL_COSIM
32520//Do Nothing
32521`else
32522`ifdef GATESIM
32523//Do Nothing
32524`else
32525`ifdef CORE_2
32526 if (`PARGS.nas_check_on) begin
32527 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
32528 tid = 1
32529; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32530 end
32531`endif
32532
32533`endif
32534
32535`endif
32536
32537 end
32538 endtask
32539
32540
32541 task slam_RealRange1_core2_thread2;
32542 input [63:0] value;
32543 reg [5:0] tid;
32544 integer junk;
32545
32546 begin
32547`ifdef AXIS_EMUL_COSIM
32548//Do Nothing
32549`else
32550`ifdef GATESIM
32551//Do Nothing
32552`else
32553`ifdef CORE_2
32554 if (`PARGS.nas_check_on) begin
32555 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
32556 tid = 2
32557; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32558 end
32559`endif
32560
32561`endif
32562
32563`endif
32564
32565 end
32566 endtask
32567
32568
32569 task slam_RealRange1_core2_thread3;
32570 input [63:0] value;
32571 reg [5:0] tid;
32572 integer junk;
32573
32574 begin
32575`ifdef AXIS_EMUL_COSIM
32576//Do Nothing
32577`else
32578`ifdef GATESIM
32579//Do Nothing
32580`else
32581`ifdef CORE_2
32582 if (`PARGS.nas_check_on) begin
32583 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
32584 tid = 3
32585; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32586 end
32587`endif
32588
32589`endif
32590
32591`endif
32592
32593 end
32594 endtask
32595
32596
32597 task slam_RealRange1_core2_thread4;
32598 input [63:0] value;
32599 reg [5:0] tid;
32600 integer junk;
32601
32602 begin
32603`ifdef AXIS_EMUL_COSIM
32604//Do Nothing
32605`else
32606`ifdef GATESIM
32607//Do Nothing
32608`else
32609`ifdef CORE_2
32610 if (`PARGS.nas_check_on) begin
32611 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
32612 tid = 4
32613; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32614 end
32615`endif
32616
32617`endif
32618
32619`endif
32620
32621 end
32622 endtask
32623
32624
32625 task slam_RealRange1_core2_thread5;
32626 input [63:0] value;
32627 reg [5:0] tid;
32628 integer junk;
32629
32630 begin
32631`ifdef AXIS_EMUL_COSIM
32632//Do Nothing
32633`else
32634`ifdef GATESIM
32635//Do Nothing
32636`else
32637`ifdef CORE_2
32638 if (`PARGS.nas_check_on) begin
32639 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
32640 tid = 5
32641; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32642 end
32643`endif
32644
32645`endif
32646
32647`endif
32648
32649 end
32650 endtask
32651
32652
32653 task slam_RealRange1_core2_thread6;
32654 input [63:0] value;
32655 reg [5:0] tid;
32656 integer junk;
32657
32658 begin
32659`ifdef AXIS_EMUL_COSIM
32660//Do Nothing
32661`else
32662`ifdef GATESIM
32663//Do Nothing
32664`else
32665`ifdef CORE_2
32666 if (`PARGS.nas_check_on) begin
32667 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
32668 tid = 6
32669; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32670 end
32671`endif
32672
32673`endif
32674
32675`endif
32676
32677 end
32678 endtask
32679
32680
32681 task slam_RealRange1_core2_thread7;
32682 input [63:0] value;
32683 reg [5:0] tid;
32684 integer junk;
32685
32686 begin
32687`ifdef AXIS_EMUL_COSIM
32688//Do Nothing
32689`else
32690`ifdef GATESIM
32691//Do Nothing
32692`else
32693`ifdef CORE_2
32694 if (`PARGS.nas_check_on) begin
32695 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
32696 tid = 7
32697; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32698 end
32699`endif
32700
32701`endif
32702
32703`endif
32704
32705 end
32706 endtask
32707
32708
32709 task slam_RealRange1_core3_thread0;
32710 input [63:0] value;
32711 reg [5:0] tid;
32712 integer junk;
32713
32714 begin
32715`ifdef AXIS_EMUL_COSIM
32716//Do Nothing
32717`else
32718`ifdef GATESIM
32719//Do Nothing
32720`else
32721`ifdef CORE_3
32722 if (`PARGS.nas_check_on) begin
32723 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
32724 tid = 0
32725; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32726 end
32727`endif
32728
32729`endif
32730
32731`endif
32732
32733 end
32734 endtask
32735
32736
32737 task slam_RealRange1_core3_thread1;
32738 input [63:0] value;
32739 reg [5:0] tid;
32740 integer junk;
32741
32742 begin
32743`ifdef AXIS_EMUL_COSIM
32744//Do Nothing
32745`else
32746`ifdef GATESIM
32747//Do Nothing
32748`else
32749`ifdef CORE_3
32750 if (`PARGS.nas_check_on) begin
32751 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
32752 tid = 1
32753; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32754 end
32755`endif
32756
32757`endif
32758
32759`endif
32760
32761 end
32762 endtask
32763
32764
32765 task slam_RealRange1_core3_thread2;
32766 input [63:0] value;
32767 reg [5:0] tid;
32768 integer junk;
32769
32770 begin
32771`ifdef AXIS_EMUL_COSIM
32772//Do Nothing
32773`else
32774`ifdef GATESIM
32775//Do Nothing
32776`else
32777`ifdef CORE_3
32778 if (`PARGS.nas_check_on) begin
32779 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
32780 tid = 2
32781; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32782 end
32783`endif
32784
32785`endif
32786
32787`endif
32788
32789 end
32790 endtask
32791
32792
32793 task slam_RealRange1_core3_thread3;
32794 input [63:0] value;
32795 reg [5:0] tid;
32796 integer junk;
32797
32798 begin
32799`ifdef AXIS_EMUL_COSIM
32800//Do Nothing
32801`else
32802`ifdef GATESIM
32803//Do Nothing
32804`else
32805`ifdef CORE_3
32806 if (`PARGS.nas_check_on) begin
32807 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
32808 tid = 3
32809; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32810 end
32811`endif
32812
32813`endif
32814
32815`endif
32816
32817 end
32818 endtask
32819
32820
32821 task slam_RealRange1_core3_thread4;
32822 input [63:0] value;
32823 reg [5:0] tid;
32824 integer junk;
32825
32826 begin
32827`ifdef AXIS_EMUL_COSIM
32828//Do Nothing
32829`else
32830`ifdef GATESIM
32831//Do Nothing
32832`else
32833`ifdef CORE_3
32834 if (`PARGS.nas_check_on) begin
32835 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
32836 tid = 4
32837; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32838 end
32839`endif
32840
32841`endif
32842
32843`endif
32844
32845 end
32846 endtask
32847
32848
32849 task slam_RealRange1_core3_thread5;
32850 input [63:0] value;
32851 reg [5:0] tid;
32852 integer junk;
32853
32854 begin
32855`ifdef AXIS_EMUL_COSIM
32856//Do Nothing
32857`else
32858`ifdef GATESIM
32859//Do Nothing
32860`else
32861`ifdef CORE_3
32862 if (`PARGS.nas_check_on) begin
32863 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
32864 tid = 5
32865; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32866 end
32867`endif
32868
32869`endif
32870
32871`endif
32872
32873 end
32874 endtask
32875
32876
32877 task slam_RealRange1_core3_thread6;
32878 input [63:0] value;
32879 reg [5:0] tid;
32880 integer junk;
32881
32882 begin
32883`ifdef AXIS_EMUL_COSIM
32884//Do Nothing
32885`else
32886`ifdef GATESIM
32887//Do Nothing
32888`else
32889`ifdef CORE_3
32890 if (`PARGS.nas_check_on) begin
32891 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
32892 tid = 6
32893; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32894 end
32895`endif
32896
32897`endif
32898
32899`endif
32900
32901 end
32902 endtask
32903
32904
32905 task slam_RealRange1_core3_thread7;
32906 input [63:0] value;
32907 reg [5:0] tid;
32908 integer junk;
32909
32910 begin
32911`ifdef AXIS_EMUL_COSIM
32912//Do Nothing
32913`else
32914`ifdef GATESIM
32915//Do Nothing
32916`else
32917`ifdef CORE_3
32918 if (`PARGS.nas_check_on) begin
32919 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
32920 tid = 7
32921; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32922 end
32923`endif
32924
32925`endif
32926
32927`endif
32928
32929 end
32930 endtask
32931
32932
32933 task slam_RealRange1_core4_thread0;
32934 input [63:0] value;
32935 reg [5:0] tid;
32936 integer junk;
32937
32938 begin
32939`ifdef AXIS_EMUL_COSIM
32940//Do Nothing
32941`else
32942`ifdef GATESIM
32943//Do Nothing
32944`else
32945`ifdef CORE_4
32946 if (`PARGS.nas_check_on) begin
32947 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
32948 tid = 0
32949; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32950 end
32951`endif
32952
32953`endif
32954
32955`endif
32956
32957 end
32958 endtask
32959
32960
32961 task slam_RealRange1_core4_thread1;
32962 input [63:0] value;
32963 reg [5:0] tid;
32964 integer junk;
32965
32966 begin
32967`ifdef AXIS_EMUL_COSIM
32968//Do Nothing
32969`else
32970`ifdef GATESIM
32971//Do Nothing
32972`else
32973`ifdef CORE_4
32974 if (`PARGS.nas_check_on) begin
32975 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
32976 tid = 1
32977; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
32978 end
32979`endif
32980
32981`endif
32982
32983`endif
32984
32985 end
32986 endtask
32987
32988
32989 task slam_RealRange1_core4_thread2;
32990 input [63:0] value;
32991 reg [5:0] tid;
32992 integer junk;
32993
32994 begin
32995`ifdef AXIS_EMUL_COSIM
32996//Do Nothing
32997`else
32998`ifdef GATESIM
32999//Do Nothing
33000`else
33001`ifdef CORE_4
33002 if (`PARGS.nas_check_on) begin
33003 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
33004 tid = 2
33005; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33006 end
33007`endif
33008
33009`endif
33010
33011`endif
33012
33013 end
33014 endtask
33015
33016
33017 task slam_RealRange1_core4_thread3;
33018 input [63:0] value;
33019 reg [5:0] tid;
33020 integer junk;
33021
33022 begin
33023`ifdef AXIS_EMUL_COSIM
33024//Do Nothing
33025`else
33026`ifdef GATESIM
33027//Do Nothing
33028`else
33029`ifdef CORE_4
33030 if (`PARGS.nas_check_on) begin
33031 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
33032 tid = 3
33033; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33034 end
33035`endif
33036
33037`endif
33038
33039`endif
33040
33041 end
33042 endtask
33043
33044
33045 task slam_RealRange1_core4_thread4;
33046 input [63:0] value;
33047 reg [5:0] tid;
33048 integer junk;
33049
33050 begin
33051`ifdef AXIS_EMUL_COSIM
33052//Do Nothing
33053`else
33054`ifdef GATESIM
33055//Do Nothing
33056`else
33057`ifdef CORE_4
33058 if (`PARGS.nas_check_on) begin
33059 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
33060 tid = 4
33061; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33062 end
33063`endif
33064
33065`endif
33066
33067`endif
33068
33069 end
33070 endtask
33071
33072
33073 task slam_RealRange1_core4_thread5;
33074 input [63:0] value;
33075 reg [5:0] tid;
33076 integer junk;
33077
33078 begin
33079`ifdef AXIS_EMUL_COSIM
33080//Do Nothing
33081`else
33082`ifdef GATESIM
33083//Do Nothing
33084`else
33085`ifdef CORE_4
33086 if (`PARGS.nas_check_on) begin
33087 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
33088 tid = 5
33089; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33090 end
33091`endif
33092
33093`endif
33094
33095`endif
33096
33097 end
33098 endtask
33099
33100
33101 task slam_RealRange1_core4_thread6;
33102 input [63:0] value;
33103 reg [5:0] tid;
33104 integer junk;
33105
33106 begin
33107`ifdef AXIS_EMUL_COSIM
33108//Do Nothing
33109`else
33110`ifdef GATESIM
33111//Do Nothing
33112`else
33113`ifdef CORE_4
33114 if (`PARGS.nas_check_on) begin
33115 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
33116 tid = 6
33117; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33118 end
33119`endif
33120
33121`endif
33122
33123`endif
33124
33125 end
33126 endtask
33127
33128
33129 task slam_RealRange1_core4_thread7;
33130 input [63:0] value;
33131 reg [5:0] tid;
33132 integer junk;
33133
33134 begin
33135`ifdef AXIS_EMUL_COSIM
33136//Do Nothing
33137`else
33138`ifdef GATESIM
33139//Do Nothing
33140`else
33141`ifdef CORE_4
33142 if (`PARGS.nas_check_on) begin
33143 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
33144 tid = 7
33145; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33146 end
33147`endif
33148
33149`endif
33150
33151`endif
33152
33153 end
33154 endtask
33155
33156
33157 task slam_RealRange1_core5_thread0;
33158 input [63:0] value;
33159 reg [5:0] tid;
33160 integer junk;
33161
33162 begin
33163`ifdef AXIS_EMUL_COSIM
33164//Do Nothing
33165`else
33166`ifdef GATESIM
33167//Do Nothing
33168`else
33169`ifdef CORE_5
33170 if (`PARGS.nas_check_on) begin
33171 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
33172 tid = 0
33173; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33174 end
33175`endif
33176
33177`endif
33178
33179`endif
33180
33181 end
33182 endtask
33183
33184
33185 task slam_RealRange1_core5_thread1;
33186 input [63:0] value;
33187 reg [5:0] tid;
33188 integer junk;
33189
33190 begin
33191`ifdef AXIS_EMUL_COSIM
33192//Do Nothing
33193`else
33194`ifdef GATESIM
33195//Do Nothing
33196`else
33197`ifdef CORE_5
33198 if (`PARGS.nas_check_on) begin
33199 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
33200 tid = 1
33201; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33202 end
33203`endif
33204
33205`endif
33206
33207`endif
33208
33209 end
33210 endtask
33211
33212
33213 task slam_RealRange1_core5_thread2;
33214 input [63:0] value;
33215 reg [5:0] tid;
33216 integer junk;
33217
33218 begin
33219`ifdef AXIS_EMUL_COSIM
33220//Do Nothing
33221`else
33222`ifdef GATESIM
33223//Do Nothing
33224`else
33225`ifdef CORE_5
33226 if (`PARGS.nas_check_on) begin
33227 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
33228 tid = 2
33229; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33230 end
33231`endif
33232
33233`endif
33234
33235`endif
33236
33237 end
33238 endtask
33239
33240
33241 task slam_RealRange1_core5_thread3;
33242 input [63:0] value;
33243 reg [5:0] tid;
33244 integer junk;
33245
33246 begin
33247`ifdef AXIS_EMUL_COSIM
33248//Do Nothing
33249`else
33250`ifdef GATESIM
33251//Do Nothing
33252`else
33253`ifdef CORE_5
33254 if (`PARGS.nas_check_on) begin
33255 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
33256 tid = 3
33257; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33258 end
33259`endif
33260
33261`endif
33262
33263`endif
33264
33265 end
33266 endtask
33267
33268
33269 task slam_RealRange1_core5_thread4;
33270 input [63:0] value;
33271 reg [5:0] tid;
33272 integer junk;
33273
33274 begin
33275`ifdef AXIS_EMUL_COSIM
33276//Do Nothing
33277`else
33278`ifdef GATESIM
33279//Do Nothing
33280`else
33281`ifdef CORE_5
33282 if (`PARGS.nas_check_on) begin
33283 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
33284 tid = 4
33285; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33286 end
33287`endif
33288
33289`endif
33290
33291`endif
33292
33293 end
33294 endtask
33295
33296
33297 task slam_RealRange1_core5_thread5;
33298 input [63:0] value;
33299 reg [5:0] tid;
33300 integer junk;
33301
33302 begin
33303`ifdef AXIS_EMUL_COSIM
33304//Do Nothing
33305`else
33306`ifdef GATESIM
33307//Do Nothing
33308`else
33309`ifdef CORE_5
33310 if (`PARGS.nas_check_on) begin
33311 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
33312 tid = 5
33313; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33314 end
33315`endif
33316
33317`endif
33318
33319`endif
33320
33321 end
33322 endtask
33323
33324
33325 task slam_RealRange1_core5_thread6;
33326 input [63:0] value;
33327 reg [5:0] tid;
33328 integer junk;
33329
33330 begin
33331`ifdef AXIS_EMUL_COSIM
33332//Do Nothing
33333`else
33334`ifdef GATESIM
33335//Do Nothing
33336`else
33337`ifdef CORE_5
33338 if (`PARGS.nas_check_on) begin
33339 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
33340 tid = 6
33341; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33342 end
33343`endif
33344
33345`endif
33346
33347`endif
33348
33349 end
33350 endtask
33351
33352
33353 task slam_RealRange1_core5_thread7;
33354 input [63:0] value;
33355 reg [5:0] tid;
33356 integer junk;
33357
33358 begin
33359`ifdef AXIS_EMUL_COSIM
33360//Do Nothing
33361`else
33362`ifdef GATESIM
33363//Do Nothing
33364`else
33365`ifdef CORE_5
33366 if (`PARGS.nas_check_on) begin
33367 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
33368 tid = 7
33369; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33370 end
33371`endif
33372
33373`endif
33374
33375`endif
33376
33377 end
33378 endtask
33379
33380
33381 task slam_RealRange1_core6_thread0;
33382 input [63:0] value;
33383 reg [5:0] tid;
33384 integer junk;
33385
33386 begin
33387`ifdef AXIS_EMUL_COSIM
33388//Do Nothing
33389`else
33390`ifdef GATESIM
33391//Do Nothing
33392`else
33393`ifdef CORE_6
33394 if (`PARGS.nas_check_on) begin
33395 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
33396 tid = 0
33397; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33398 end
33399`endif
33400
33401`endif
33402
33403`endif
33404
33405 end
33406 endtask
33407
33408
33409 task slam_RealRange1_core6_thread1;
33410 input [63:0] value;
33411 reg [5:0] tid;
33412 integer junk;
33413
33414 begin
33415`ifdef AXIS_EMUL_COSIM
33416//Do Nothing
33417`else
33418`ifdef GATESIM
33419//Do Nothing
33420`else
33421`ifdef CORE_6
33422 if (`PARGS.nas_check_on) begin
33423 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
33424 tid = 1
33425; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33426 end
33427`endif
33428
33429`endif
33430
33431`endif
33432
33433 end
33434 endtask
33435
33436
33437 task slam_RealRange1_core6_thread2;
33438 input [63:0] value;
33439 reg [5:0] tid;
33440 integer junk;
33441
33442 begin
33443`ifdef AXIS_EMUL_COSIM
33444//Do Nothing
33445`else
33446`ifdef GATESIM
33447//Do Nothing
33448`else
33449`ifdef CORE_6
33450 if (`PARGS.nas_check_on) begin
33451 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
33452 tid = 2
33453; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33454 end
33455`endif
33456
33457`endif
33458
33459`endif
33460
33461 end
33462 endtask
33463
33464
33465 task slam_RealRange1_core6_thread3;
33466 input [63:0] value;
33467 reg [5:0] tid;
33468 integer junk;
33469
33470 begin
33471`ifdef AXIS_EMUL_COSIM
33472//Do Nothing
33473`else
33474`ifdef GATESIM
33475//Do Nothing
33476`else
33477`ifdef CORE_6
33478 if (`PARGS.nas_check_on) begin
33479 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
33480 tid = 3
33481; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33482 end
33483`endif
33484
33485`endif
33486
33487`endif
33488
33489 end
33490 endtask
33491
33492
33493 task slam_RealRange1_core6_thread4;
33494 input [63:0] value;
33495 reg [5:0] tid;
33496 integer junk;
33497
33498 begin
33499`ifdef AXIS_EMUL_COSIM
33500//Do Nothing
33501`else
33502`ifdef GATESIM
33503//Do Nothing
33504`else
33505`ifdef CORE_6
33506 if (`PARGS.nas_check_on) begin
33507 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
33508 tid = 4
33509; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33510 end
33511`endif
33512
33513`endif
33514
33515`endif
33516
33517 end
33518 endtask
33519
33520
33521 task slam_RealRange1_core6_thread5;
33522 input [63:0] value;
33523 reg [5:0] tid;
33524 integer junk;
33525
33526 begin
33527`ifdef AXIS_EMUL_COSIM
33528//Do Nothing
33529`else
33530`ifdef GATESIM
33531//Do Nothing
33532`else
33533`ifdef CORE_6
33534 if (`PARGS.nas_check_on) begin
33535 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
33536 tid = 5
33537; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33538 end
33539`endif
33540
33541`endif
33542
33543`endif
33544
33545 end
33546 endtask
33547
33548
33549 task slam_RealRange1_core6_thread6;
33550 input [63:0] value;
33551 reg [5:0] tid;
33552 integer junk;
33553
33554 begin
33555`ifdef AXIS_EMUL_COSIM
33556//Do Nothing
33557`else
33558`ifdef GATESIM
33559//Do Nothing
33560`else
33561`ifdef CORE_6
33562 if (`PARGS.nas_check_on) begin
33563 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
33564 tid = 6
33565; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33566 end
33567`endif
33568
33569`endif
33570
33571`endif
33572
33573 end
33574 endtask
33575
33576
33577 task slam_RealRange1_core6_thread7;
33578 input [63:0] value;
33579 reg [5:0] tid;
33580 integer junk;
33581
33582 begin
33583`ifdef AXIS_EMUL_COSIM
33584//Do Nothing
33585`else
33586`ifdef GATESIM
33587//Do Nothing
33588`else
33589`ifdef CORE_6
33590 if (`PARGS.nas_check_on) begin
33591 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
33592 tid = 7
33593; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33594 end
33595`endif
33596
33597`endif
33598
33599`endif
33600
33601 end
33602 endtask
33603
33604
33605 task slam_RealRange1_core7_thread0;
33606 input [63:0] value;
33607 reg [5:0] tid;
33608 integer junk;
33609
33610 begin
33611`ifdef AXIS_EMUL_COSIM
33612//Do Nothing
33613`else
33614`ifdef GATESIM
33615//Do Nothing
33616`else
33617`ifdef CORE_7
33618 if (`PARGS.nas_check_on) begin
33619 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
33620 tid = 0
33621; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33622 end
33623`endif
33624
33625`endif
33626
33627`endif
33628
33629 end
33630 endtask
33631
33632
33633 task slam_RealRange1_core7_thread1;
33634 input [63:0] value;
33635 reg [5:0] tid;
33636 integer junk;
33637
33638 begin
33639`ifdef AXIS_EMUL_COSIM
33640//Do Nothing
33641`else
33642`ifdef GATESIM
33643//Do Nothing
33644`else
33645`ifdef CORE_7
33646 if (`PARGS.nas_check_on) begin
33647 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
33648 tid = 1
33649; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33650 end
33651`endif
33652
33653`endif
33654
33655`endif
33656
33657 end
33658 endtask
33659
33660
33661 task slam_RealRange1_core7_thread2;
33662 input [63:0] value;
33663 reg [5:0] tid;
33664 integer junk;
33665
33666 begin
33667`ifdef AXIS_EMUL_COSIM
33668//Do Nothing
33669`else
33670`ifdef GATESIM
33671//Do Nothing
33672`else
33673`ifdef CORE_7
33674 if (`PARGS.nas_check_on) begin
33675 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
33676 tid = 2
33677; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33678 end
33679`endif
33680
33681`endif
33682
33683`endif
33684
33685 end
33686 endtask
33687
33688
33689 task slam_RealRange1_core7_thread3;
33690 input [63:0] value;
33691 reg [5:0] tid;
33692 integer junk;
33693
33694 begin
33695`ifdef AXIS_EMUL_COSIM
33696//Do Nothing
33697`else
33698`ifdef GATESIM
33699//Do Nothing
33700`else
33701`ifdef CORE_7
33702 if (`PARGS.nas_check_on) begin
33703 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
33704 tid = 3
33705; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33706 end
33707`endif
33708
33709`endif
33710
33711`endif
33712
33713 end
33714 endtask
33715
33716
33717 task slam_RealRange1_core7_thread4;
33718 input [63:0] value;
33719 reg [5:0] tid;
33720 integer junk;
33721
33722 begin
33723`ifdef AXIS_EMUL_COSIM
33724//Do Nothing
33725`else
33726`ifdef GATESIM
33727//Do Nothing
33728`else
33729`ifdef CORE_7
33730 if (`PARGS.nas_check_on) begin
33731 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
33732 tid = 4
33733; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33734 end
33735`endif
33736
33737`endif
33738
33739`endif
33740
33741 end
33742 endtask
33743
33744
33745 task slam_RealRange1_core7_thread5;
33746 input [63:0] value;
33747 reg [5:0] tid;
33748 integer junk;
33749
33750 begin
33751`ifdef AXIS_EMUL_COSIM
33752//Do Nothing
33753`else
33754`ifdef GATESIM
33755//Do Nothing
33756`else
33757`ifdef CORE_7
33758 if (`PARGS.nas_check_on) begin
33759 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
33760 tid = 5
33761; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33762 end
33763`endif
33764
33765`endif
33766
33767`endif
33768
33769 end
33770 endtask
33771
33772
33773 task slam_RealRange1_core7_thread6;
33774 input [63:0] value;
33775 reg [5:0] tid;
33776 integer junk;
33777
33778 begin
33779`ifdef AXIS_EMUL_COSIM
33780//Do Nothing
33781`else
33782`ifdef GATESIM
33783//Do Nothing
33784`else
33785`ifdef CORE_7
33786 if (`PARGS.nas_check_on) begin
33787 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
33788 tid = 6
33789; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33790 end
33791`endif
33792
33793`endif
33794
33795`endif
33796
33797 end
33798 endtask
33799
33800
33801 task slam_RealRange1_core7_thread7;
33802 input [63:0] value;
33803 reg [5:0] tid;
33804 integer junk;
33805
33806 begin
33807`ifdef AXIS_EMUL_COSIM
33808//Do Nothing
33809`else
33810`ifdef GATESIM
33811//Do Nothing
33812`else
33813`ifdef CORE_7
33814 if (`PARGS.nas_check_on) begin
33815 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
33816 tid = 7
33817; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h110, value);
33818 end
33819`endif
33820
33821`endif
33822
33823`endif
33824
33825 end
33826 endtask
33827
33828
33829 task slam_RealRange2_core0_thread0;
33830 input [63:0] value;
33831 reg [5:0] tid;
33832 integer junk;
33833
33834 begin
33835`ifdef AXIS_EMUL_COSIM
33836//Do Nothing
33837`else
33838`ifdef GATESIM
33839//Do Nothing
33840`else
33841`ifdef CORE_0
33842 if (`PARGS.nas_check_on) begin
33843 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
33844 tid = 0
33845; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33846 end
33847`endif
33848
33849`endif
33850
33851`endif
33852
33853 end
33854 endtask
33855
33856
33857 task slam_RealRange2_core0_thread1;
33858 input [63:0] value;
33859 reg [5:0] tid;
33860 integer junk;
33861
33862 begin
33863`ifdef AXIS_EMUL_COSIM
33864//Do Nothing
33865`else
33866`ifdef GATESIM
33867//Do Nothing
33868`else
33869`ifdef CORE_0
33870 if (`PARGS.nas_check_on) begin
33871 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
33872 tid = 1
33873; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33874 end
33875`endif
33876
33877`endif
33878
33879`endif
33880
33881 end
33882 endtask
33883
33884
33885 task slam_RealRange2_core0_thread2;
33886 input [63:0] value;
33887 reg [5:0] tid;
33888 integer junk;
33889
33890 begin
33891`ifdef AXIS_EMUL_COSIM
33892//Do Nothing
33893`else
33894`ifdef GATESIM
33895//Do Nothing
33896`else
33897`ifdef CORE_0
33898 if (`PARGS.nas_check_on) begin
33899 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
33900 tid = 2
33901; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33902 end
33903`endif
33904
33905`endif
33906
33907`endif
33908
33909 end
33910 endtask
33911
33912
33913 task slam_RealRange2_core0_thread3;
33914 input [63:0] value;
33915 reg [5:0] tid;
33916 integer junk;
33917
33918 begin
33919`ifdef AXIS_EMUL_COSIM
33920//Do Nothing
33921`else
33922`ifdef GATESIM
33923//Do Nothing
33924`else
33925`ifdef CORE_0
33926 if (`PARGS.nas_check_on) begin
33927 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
33928 tid = 3
33929; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33930 end
33931`endif
33932
33933`endif
33934
33935`endif
33936
33937 end
33938 endtask
33939
33940
33941 task slam_RealRange2_core0_thread4;
33942 input [63:0] value;
33943 reg [5:0] tid;
33944 integer junk;
33945
33946 begin
33947`ifdef AXIS_EMUL_COSIM
33948//Do Nothing
33949`else
33950`ifdef GATESIM
33951//Do Nothing
33952`else
33953`ifdef CORE_0
33954 if (`PARGS.nas_check_on) begin
33955 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
33956 tid = 4
33957; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33958 end
33959`endif
33960
33961`endif
33962
33963`endif
33964
33965 end
33966 endtask
33967
33968
33969 task slam_RealRange2_core0_thread5;
33970 input [63:0] value;
33971 reg [5:0] tid;
33972 integer junk;
33973
33974 begin
33975`ifdef AXIS_EMUL_COSIM
33976//Do Nothing
33977`else
33978`ifdef GATESIM
33979//Do Nothing
33980`else
33981`ifdef CORE_0
33982 if (`PARGS.nas_check_on) begin
33983 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
33984 tid = 5
33985; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
33986 end
33987`endif
33988
33989`endif
33990
33991`endif
33992
33993 end
33994 endtask
33995
33996
33997 task slam_RealRange2_core0_thread6;
33998 input [63:0] value;
33999 reg [5:0] tid;
34000 integer junk;
34001
34002 begin
34003`ifdef AXIS_EMUL_COSIM
34004//Do Nothing
34005`else
34006`ifdef GATESIM
34007//Do Nothing
34008`else
34009`ifdef CORE_0
34010 if (`PARGS.nas_check_on) begin
34011 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
34012 tid = 6
34013; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34014 end
34015`endif
34016
34017`endif
34018
34019`endif
34020
34021 end
34022 endtask
34023
34024
34025 task slam_RealRange2_core0_thread7;
34026 input [63:0] value;
34027 reg [5:0] tid;
34028 integer junk;
34029
34030 begin
34031`ifdef AXIS_EMUL_COSIM
34032//Do Nothing
34033`else
34034`ifdef GATESIM
34035//Do Nothing
34036`else
34037`ifdef CORE_0
34038 if (`PARGS.nas_check_on) begin
34039 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
34040 tid = 7
34041; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34042 end
34043`endif
34044
34045`endif
34046
34047`endif
34048
34049 end
34050 endtask
34051
34052
34053 task slam_RealRange2_core1_thread0;
34054 input [63:0] value;
34055 reg [5:0] tid;
34056 integer junk;
34057
34058 begin
34059`ifdef AXIS_EMUL_COSIM
34060//Do Nothing
34061`else
34062`ifdef GATESIM
34063//Do Nothing
34064`else
34065`ifdef CORE_1
34066 if (`PARGS.nas_check_on) begin
34067 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
34068 tid = 0
34069; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34070 end
34071`endif
34072
34073`endif
34074
34075`endif
34076
34077 end
34078 endtask
34079
34080
34081 task slam_RealRange2_core1_thread1;
34082 input [63:0] value;
34083 reg [5:0] tid;
34084 integer junk;
34085
34086 begin
34087`ifdef AXIS_EMUL_COSIM
34088//Do Nothing
34089`else
34090`ifdef GATESIM
34091//Do Nothing
34092`else
34093`ifdef CORE_1
34094 if (`PARGS.nas_check_on) begin
34095 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
34096 tid = 1
34097; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34098 end
34099`endif
34100
34101`endif
34102
34103`endif
34104
34105 end
34106 endtask
34107
34108
34109 task slam_RealRange2_core1_thread2;
34110 input [63:0] value;
34111 reg [5:0] tid;
34112 integer junk;
34113
34114 begin
34115`ifdef AXIS_EMUL_COSIM
34116//Do Nothing
34117`else
34118`ifdef GATESIM
34119//Do Nothing
34120`else
34121`ifdef CORE_1
34122 if (`PARGS.nas_check_on) begin
34123 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
34124 tid = 2
34125; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34126 end
34127`endif
34128
34129`endif
34130
34131`endif
34132
34133 end
34134 endtask
34135
34136
34137 task slam_RealRange2_core1_thread3;
34138 input [63:0] value;
34139 reg [5:0] tid;
34140 integer junk;
34141
34142 begin
34143`ifdef AXIS_EMUL_COSIM
34144//Do Nothing
34145`else
34146`ifdef GATESIM
34147//Do Nothing
34148`else
34149`ifdef CORE_1
34150 if (`PARGS.nas_check_on) begin
34151 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
34152 tid = 3
34153; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34154 end
34155`endif
34156
34157`endif
34158
34159`endif
34160
34161 end
34162 endtask
34163
34164
34165 task slam_RealRange2_core1_thread4;
34166 input [63:0] value;
34167 reg [5:0] tid;
34168 integer junk;
34169
34170 begin
34171`ifdef AXIS_EMUL_COSIM
34172//Do Nothing
34173`else
34174`ifdef GATESIM
34175//Do Nothing
34176`else
34177`ifdef CORE_1
34178 if (`PARGS.nas_check_on) begin
34179 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
34180 tid = 4
34181; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34182 end
34183`endif
34184
34185`endif
34186
34187`endif
34188
34189 end
34190 endtask
34191
34192
34193 task slam_RealRange2_core1_thread5;
34194 input [63:0] value;
34195 reg [5:0] tid;
34196 integer junk;
34197
34198 begin
34199`ifdef AXIS_EMUL_COSIM
34200//Do Nothing
34201`else
34202`ifdef GATESIM
34203//Do Nothing
34204`else
34205`ifdef CORE_1
34206 if (`PARGS.nas_check_on) begin
34207 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
34208 tid = 5
34209; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34210 end
34211`endif
34212
34213`endif
34214
34215`endif
34216
34217 end
34218 endtask
34219
34220
34221 task slam_RealRange2_core1_thread6;
34222 input [63:0] value;
34223 reg [5:0] tid;
34224 integer junk;
34225
34226 begin
34227`ifdef AXIS_EMUL_COSIM
34228//Do Nothing
34229`else
34230`ifdef GATESIM
34231//Do Nothing
34232`else
34233`ifdef CORE_1
34234 if (`PARGS.nas_check_on) begin
34235 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
34236 tid = 6
34237; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34238 end
34239`endif
34240
34241`endif
34242
34243`endif
34244
34245 end
34246 endtask
34247
34248
34249 task slam_RealRange2_core1_thread7;
34250 input [63:0] value;
34251 reg [5:0] tid;
34252 integer junk;
34253
34254 begin
34255`ifdef AXIS_EMUL_COSIM
34256//Do Nothing
34257`else
34258`ifdef GATESIM
34259//Do Nothing
34260`else
34261`ifdef CORE_1
34262 if (`PARGS.nas_check_on) begin
34263 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
34264 tid = 7
34265; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34266 end
34267`endif
34268
34269`endif
34270
34271`endif
34272
34273 end
34274 endtask
34275
34276
34277 task slam_RealRange2_core2_thread0;
34278 input [63:0] value;
34279 reg [5:0] tid;
34280 integer junk;
34281
34282 begin
34283`ifdef AXIS_EMUL_COSIM
34284//Do Nothing
34285`else
34286`ifdef GATESIM
34287//Do Nothing
34288`else
34289`ifdef CORE_2
34290 if (`PARGS.nas_check_on) begin
34291 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
34292 tid = 0
34293; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34294 end
34295`endif
34296
34297`endif
34298
34299`endif
34300
34301 end
34302 endtask
34303
34304
34305 task slam_RealRange2_core2_thread1;
34306 input [63:0] value;
34307 reg [5:0] tid;
34308 integer junk;
34309
34310 begin
34311`ifdef AXIS_EMUL_COSIM
34312//Do Nothing
34313`else
34314`ifdef GATESIM
34315//Do Nothing
34316`else
34317`ifdef CORE_2
34318 if (`PARGS.nas_check_on) begin
34319 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
34320 tid = 1
34321; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34322 end
34323`endif
34324
34325`endif
34326
34327`endif
34328
34329 end
34330 endtask
34331
34332
34333 task slam_RealRange2_core2_thread2;
34334 input [63:0] value;
34335 reg [5:0] tid;
34336 integer junk;
34337
34338 begin
34339`ifdef AXIS_EMUL_COSIM
34340//Do Nothing
34341`else
34342`ifdef GATESIM
34343//Do Nothing
34344`else
34345`ifdef CORE_2
34346 if (`PARGS.nas_check_on) begin
34347 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
34348 tid = 2
34349; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34350 end
34351`endif
34352
34353`endif
34354
34355`endif
34356
34357 end
34358 endtask
34359
34360
34361 task slam_RealRange2_core2_thread3;
34362 input [63:0] value;
34363 reg [5:0] tid;
34364 integer junk;
34365
34366 begin
34367`ifdef AXIS_EMUL_COSIM
34368//Do Nothing
34369`else
34370`ifdef GATESIM
34371//Do Nothing
34372`else
34373`ifdef CORE_2
34374 if (`PARGS.nas_check_on) begin
34375 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
34376 tid = 3
34377; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34378 end
34379`endif
34380
34381`endif
34382
34383`endif
34384
34385 end
34386 endtask
34387
34388
34389 task slam_RealRange2_core2_thread4;
34390 input [63:0] value;
34391 reg [5:0] tid;
34392 integer junk;
34393
34394 begin
34395`ifdef AXIS_EMUL_COSIM
34396//Do Nothing
34397`else
34398`ifdef GATESIM
34399//Do Nothing
34400`else
34401`ifdef CORE_2
34402 if (`PARGS.nas_check_on) begin
34403 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
34404 tid = 4
34405; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34406 end
34407`endif
34408
34409`endif
34410
34411`endif
34412
34413 end
34414 endtask
34415
34416
34417 task slam_RealRange2_core2_thread5;
34418 input [63:0] value;
34419 reg [5:0] tid;
34420 integer junk;
34421
34422 begin
34423`ifdef AXIS_EMUL_COSIM
34424//Do Nothing
34425`else
34426`ifdef GATESIM
34427//Do Nothing
34428`else
34429`ifdef CORE_2
34430 if (`PARGS.nas_check_on) begin
34431 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
34432 tid = 5
34433; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34434 end
34435`endif
34436
34437`endif
34438
34439`endif
34440
34441 end
34442 endtask
34443
34444
34445 task slam_RealRange2_core2_thread6;
34446 input [63:0] value;
34447 reg [5:0] tid;
34448 integer junk;
34449
34450 begin
34451`ifdef AXIS_EMUL_COSIM
34452//Do Nothing
34453`else
34454`ifdef GATESIM
34455//Do Nothing
34456`else
34457`ifdef CORE_2
34458 if (`PARGS.nas_check_on) begin
34459 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
34460 tid = 6
34461; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34462 end
34463`endif
34464
34465`endif
34466
34467`endif
34468
34469 end
34470 endtask
34471
34472
34473 task slam_RealRange2_core2_thread7;
34474 input [63:0] value;
34475 reg [5:0] tid;
34476 integer junk;
34477
34478 begin
34479`ifdef AXIS_EMUL_COSIM
34480//Do Nothing
34481`else
34482`ifdef GATESIM
34483//Do Nothing
34484`else
34485`ifdef CORE_2
34486 if (`PARGS.nas_check_on) begin
34487 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
34488 tid = 7
34489; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34490 end
34491`endif
34492
34493`endif
34494
34495`endif
34496
34497 end
34498 endtask
34499
34500
34501 task slam_RealRange2_core3_thread0;
34502 input [63:0] value;
34503 reg [5:0] tid;
34504 integer junk;
34505
34506 begin
34507`ifdef AXIS_EMUL_COSIM
34508//Do Nothing
34509`else
34510`ifdef GATESIM
34511//Do Nothing
34512`else
34513`ifdef CORE_3
34514 if (`PARGS.nas_check_on) begin
34515 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
34516 tid = 0
34517; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34518 end
34519`endif
34520
34521`endif
34522
34523`endif
34524
34525 end
34526 endtask
34527
34528
34529 task slam_RealRange2_core3_thread1;
34530 input [63:0] value;
34531 reg [5:0] tid;
34532 integer junk;
34533
34534 begin
34535`ifdef AXIS_EMUL_COSIM
34536//Do Nothing
34537`else
34538`ifdef GATESIM
34539//Do Nothing
34540`else
34541`ifdef CORE_3
34542 if (`PARGS.nas_check_on) begin
34543 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
34544 tid = 1
34545; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34546 end
34547`endif
34548
34549`endif
34550
34551`endif
34552
34553 end
34554 endtask
34555
34556
34557 task slam_RealRange2_core3_thread2;
34558 input [63:0] value;
34559 reg [5:0] tid;
34560 integer junk;
34561
34562 begin
34563`ifdef AXIS_EMUL_COSIM
34564//Do Nothing
34565`else
34566`ifdef GATESIM
34567//Do Nothing
34568`else
34569`ifdef CORE_3
34570 if (`PARGS.nas_check_on) begin
34571 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
34572 tid = 2
34573; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34574 end
34575`endif
34576
34577`endif
34578
34579`endif
34580
34581 end
34582 endtask
34583
34584
34585 task slam_RealRange2_core3_thread3;
34586 input [63:0] value;
34587 reg [5:0] tid;
34588 integer junk;
34589
34590 begin
34591`ifdef AXIS_EMUL_COSIM
34592//Do Nothing
34593`else
34594`ifdef GATESIM
34595//Do Nothing
34596`else
34597`ifdef CORE_3
34598 if (`PARGS.nas_check_on) begin
34599 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
34600 tid = 3
34601; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34602 end
34603`endif
34604
34605`endif
34606
34607`endif
34608
34609 end
34610 endtask
34611
34612
34613 task slam_RealRange2_core3_thread4;
34614 input [63:0] value;
34615 reg [5:0] tid;
34616 integer junk;
34617
34618 begin
34619`ifdef AXIS_EMUL_COSIM
34620//Do Nothing
34621`else
34622`ifdef GATESIM
34623//Do Nothing
34624`else
34625`ifdef CORE_3
34626 if (`PARGS.nas_check_on) begin
34627 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
34628 tid = 4
34629; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34630 end
34631`endif
34632
34633`endif
34634
34635`endif
34636
34637 end
34638 endtask
34639
34640
34641 task slam_RealRange2_core3_thread5;
34642 input [63:0] value;
34643 reg [5:0] tid;
34644 integer junk;
34645
34646 begin
34647`ifdef AXIS_EMUL_COSIM
34648//Do Nothing
34649`else
34650`ifdef GATESIM
34651//Do Nothing
34652`else
34653`ifdef CORE_3
34654 if (`PARGS.nas_check_on) begin
34655 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
34656 tid = 5
34657; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34658 end
34659`endif
34660
34661`endif
34662
34663`endif
34664
34665 end
34666 endtask
34667
34668
34669 task slam_RealRange2_core3_thread6;
34670 input [63:0] value;
34671 reg [5:0] tid;
34672 integer junk;
34673
34674 begin
34675`ifdef AXIS_EMUL_COSIM
34676//Do Nothing
34677`else
34678`ifdef GATESIM
34679//Do Nothing
34680`else
34681`ifdef CORE_3
34682 if (`PARGS.nas_check_on) begin
34683 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
34684 tid = 6
34685; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34686 end
34687`endif
34688
34689`endif
34690
34691`endif
34692
34693 end
34694 endtask
34695
34696
34697 task slam_RealRange2_core3_thread7;
34698 input [63:0] value;
34699 reg [5:0] tid;
34700 integer junk;
34701
34702 begin
34703`ifdef AXIS_EMUL_COSIM
34704//Do Nothing
34705`else
34706`ifdef GATESIM
34707//Do Nothing
34708`else
34709`ifdef CORE_3
34710 if (`PARGS.nas_check_on) begin
34711 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
34712 tid = 7
34713; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34714 end
34715`endif
34716
34717`endif
34718
34719`endif
34720
34721 end
34722 endtask
34723
34724
34725 task slam_RealRange2_core4_thread0;
34726 input [63:0] value;
34727 reg [5:0] tid;
34728 integer junk;
34729
34730 begin
34731`ifdef AXIS_EMUL_COSIM
34732//Do Nothing
34733`else
34734`ifdef GATESIM
34735//Do Nothing
34736`else
34737`ifdef CORE_4
34738 if (`PARGS.nas_check_on) begin
34739 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
34740 tid = 0
34741; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34742 end
34743`endif
34744
34745`endif
34746
34747`endif
34748
34749 end
34750 endtask
34751
34752
34753 task slam_RealRange2_core4_thread1;
34754 input [63:0] value;
34755 reg [5:0] tid;
34756 integer junk;
34757
34758 begin
34759`ifdef AXIS_EMUL_COSIM
34760//Do Nothing
34761`else
34762`ifdef GATESIM
34763//Do Nothing
34764`else
34765`ifdef CORE_4
34766 if (`PARGS.nas_check_on) begin
34767 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
34768 tid = 1
34769; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34770 end
34771`endif
34772
34773`endif
34774
34775`endif
34776
34777 end
34778 endtask
34779
34780
34781 task slam_RealRange2_core4_thread2;
34782 input [63:0] value;
34783 reg [5:0] tid;
34784 integer junk;
34785
34786 begin
34787`ifdef AXIS_EMUL_COSIM
34788//Do Nothing
34789`else
34790`ifdef GATESIM
34791//Do Nothing
34792`else
34793`ifdef CORE_4
34794 if (`PARGS.nas_check_on) begin
34795 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
34796 tid = 2
34797; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34798 end
34799`endif
34800
34801`endif
34802
34803`endif
34804
34805 end
34806 endtask
34807
34808
34809 task slam_RealRange2_core4_thread3;
34810 input [63:0] value;
34811 reg [5:0] tid;
34812 integer junk;
34813
34814 begin
34815`ifdef AXIS_EMUL_COSIM
34816//Do Nothing
34817`else
34818`ifdef GATESIM
34819//Do Nothing
34820`else
34821`ifdef CORE_4
34822 if (`PARGS.nas_check_on) begin
34823 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
34824 tid = 3
34825; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34826 end
34827`endif
34828
34829`endif
34830
34831`endif
34832
34833 end
34834 endtask
34835
34836
34837 task slam_RealRange2_core4_thread4;
34838 input [63:0] value;
34839 reg [5:0] tid;
34840 integer junk;
34841
34842 begin
34843`ifdef AXIS_EMUL_COSIM
34844//Do Nothing
34845`else
34846`ifdef GATESIM
34847//Do Nothing
34848`else
34849`ifdef CORE_4
34850 if (`PARGS.nas_check_on) begin
34851 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
34852 tid = 4
34853; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34854 end
34855`endif
34856
34857`endif
34858
34859`endif
34860
34861 end
34862 endtask
34863
34864
34865 task slam_RealRange2_core4_thread5;
34866 input [63:0] value;
34867 reg [5:0] tid;
34868 integer junk;
34869
34870 begin
34871`ifdef AXIS_EMUL_COSIM
34872//Do Nothing
34873`else
34874`ifdef GATESIM
34875//Do Nothing
34876`else
34877`ifdef CORE_4
34878 if (`PARGS.nas_check_on) begin
34879 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
34880 tid = 5
34881; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34882 end
34883`endif
34884
34885`endif
34886
34887`endif
34888
34889 end
34890 endtask
34891
34892
34893 task slam_RealRange2_core4_thread6;
34894 input [63:0] value;
34895 reg [5:0] tid;
34896 integer junk;
34897
34898 begin
34899`ifdef AXIS_EMUL_COSIM
34900//Do Nothing
34901`else
34902`ifdef GATESIM
34903//Do Nothing
34904`else
34905`ifdef CORE_4
34906 if (`PARGS.nas_check_on) begin
34907 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
34908 tid = 6
34909; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34910 end
34911`endif
34912
34913`endif
34914
34915`endif
34916
34917 end
34918 endtask
34919
34920
34921 task slam_RealRange2_core4_thread7;
34922 input [63:0] value;
34923 reg [5:0] tid;
34924 integer junk;
34925
34926 begin
34927`ifdef AXIS_EMUL_COSIM
34928//Do Nothing
34929`else
34930`ifdef GATESIM
34931//Do Nothing
34932`else
34933`ifdef CORE_4
34934 if (`PARGS.nas_check_on) begin
34935 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
34936 tid = 7
34937; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34938 end
34939`endif
34940
34941`endif
34942
34943`endif
34944
34945 end
34946 endtask
34947
34948
34949 task slam_RealRange2_core5_thread0;
34950 input [63:0] value;
34951 reg [5:0] tid;
34952 integer junk;
34953
34954 begin
34955`ifdef AXIS_EMUL_COSIM
34956//Do Nothing
34957`else
34958`ifdef GATESIM
34959//Do Nothing
34960`else
34961`ifdef CORE_5
34962 if (`PARGS.nas_check_on) begin
34963 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
34964 tid = 0
34965; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34966 end
34967`endif
34968
34969`endif
34970
34971`endif
34972
34973 end
34974 endtask
34975
34976
34977 task slam_RealRange2_core5_thread1;
34978 input [63:0] value;
34979 reg [5:0] tid;
34980 integer junk;
34981
34982 begin
34983`ifdef AXIS_EMUL_COSIM
34984//Do Nothing
34985`else
34986`ifdef GATESIM
34987//Do Nothing
34988`else
34989`ifdef CORE_5
34990 if (`PARGS.nas_check_on) begin
34991 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
34992 tid = 1
34993; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
34994 end
34995`endif
34996
34997`endif
34998
34999`endif
35000
35001 end
35002 endtask
35003
35004
35005 task slam_RealRange2_core5_thread2;
35006 input [63:0] value;
35007 reg [5:0] tid;
35008 integer junk;
35009
35010 begin
35011`ifdef AXIS_EMUL_COSIM
35012//Do Nothing
35013`else
35014`ifdef GATESIM
35015//Do Nothing
35016`else
35017`ifdef CORE_5
35018 if (`PARGS.nas_check_on) begin
35019 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
35020 tid = 2
35021; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35022 end
35023`endif
35024
35025`endif
35026
35027`endif
35028
35029 end
35030 endtask
35031
35032
35033 task slam_RealRange2_core5_thread3;
35034 input [63:0] value;
35035 reg [5:0] tid;
35036 integer junk;
35037
35038 begin
35039`ifdef AXIS_EMUL_COSIM
35040//Do Nothing
35041`else
35042`ifdef GATESIM
35043//Do Nothing
35044`else
35045`ifdef CORE_5
35046 if (`PARGS.nas_check_on) begin
35047 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
35048 tid = 3
35049; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35050 end
35051`endif
35052
35053`endif
35054
35055`endif
35056
35057 end
35058 endtask
35059
35060
35061 task slam_RealRange2_core5_thread4;
35062 input [63:0] value;
35063 reg [5:0] tid;
35064 integer junk;
35065
35066 begin
35067`ifdef AXIS_EMUL_COSIM
35068//Do Nothing
35069`else
35070`ifdef GATESIM
35071//Do Nothing
35072`else
35073`ifdef CORE_5
35074 if (`PARGS.nas_check_on) begin
35075 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
35076 tid = 4
35077; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35078 end
35079`endif
35080
35081`endif
35082
35083`endif
35084
35085 end
35086 endtask
35087
35088
35089 task slam_RealRange2_core5_thread5;
35090 input [63:0] value;
35091 reg [5:0] tid;
35092 integer junk;
35093
35094 begin
35095`ifdef AXIS_EMUL_COSIM
35096//Do Nothing
35097`else
35098`ifdef GATESIM
35099//Do Nothing
35100`else
35101`ifdef CORE_5
35102 if (`PARGS.nas_check_on) begin
35103 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
35104 tid = 5
35105; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35106 end
35107`endif
35108
35109`endif
35110
35111`endif
35112
35113 end
35114 endtask
35115
35116
35117 task slam_RealRange2_core5_thread6;
35118 input [63:0] value;
35119 reg [5:0] tid;
35120 integer junk;
35121
35122 begin
35123`ifdef AXIS_EMUL_COSIM
35124//Do Nothing
35125`else
35126`ifdef GATESIM
35127//Do Nothing
35128`else
35129`ifdef CORE_5
35130 if (`PARGS.nas_check_on) begin
35131 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
35132 tid = 6
35133; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35134 end
35135`endif
35136
35137`endif
35138
35139`endif
35140
35141 end
35142 endtask
35143
35144
35145 task slam_RealRange2_core5_thread7;
35146 input [63:0] value;
35147 reg [5:0] tid;
35148 integer junk;
35149
35150 begin
35151`ifdef AXIS_EMUL_COSIM
35152//Do Nothing
35153`else
35154`ifdef GATESIM
35155//Do Nothing
35156`else
35157`ifdef CORE_5
35158 if (`PARGS.nas_check_on) begin
35159 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
35160 tid = 7
35161; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35162 end
35163`endif
35164
35165`endif
35166
35167`endif
35168
35169 end
35170 endtask
35171
35172
35173 task slam_RealRange2_core6_thread0;
35174 input [63:0] value;
35175 reg [5:0] tid;
35176 integer junk;
35177
35178 begin
35179`ifdef AXIS_EMUL_COSIM
35180//Do Nothing
35181`else
35182`ifdef GATESIM
35183//Do Nothing
35184`else
35185`ifdef CORE_6
35186 if (`PARGS.nas_check_on) begin
35187 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
35188 tid = 0
35189; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35190 end
35191`endif
35192
35193`endif
35194
35195`endif
35196
35197 end
35198 endtask
35199
35200
35201 task slam_RealRange2_core6_thread1;
35202 input [63:0] value;
35203 reg [5:0] tid;
35204 integer junk;
35205
35206 begin
35207`ifdef AXIS_EMUL_COSIM
35208//Do Nothing
35209`else
35210`ifdef GATESIM
35211//Do Nothing
35212`else
35213`ifdef CORE_6
35214 if (`PARGS.nas_check_on) begin
35215 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
35216 tid = 1
35217; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35218 end
35219`endif
35220
35221`endif
35222
35223`endif
35224
35225 end
35226 endtask
35227
35228
35229 task slam_RealRange2_core6_thread2;
35230 input [63:0] value;
35231 reg [5:0] tid;
35232 integer junk;
35233
35234 begin
35235`ifdef AXIS_EMUL_COSIM
35236//Do Nothing
35237`else
35238`ifdef GATESIM
35239//Do Nothing
35240`else
35241`ifdef CORE_6
35242 if (`PARGS.nas_check_on) begin
35243 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
35244 tid = 2
35245; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35246 end
35247`endif
35248
35249`endif
35250
35251`endif
35252
35253 end
35254 endtask
35255
35256
35257 task slam_RealRange2_core6_thread3;
35258 input [63:0] value;
35259 reg [5:0] tid;
35260 integer junk;
35261
35262 begin
35263`ifdef AXIS_EMUL_COSIM
35264//Do Nothing
35265`else
35266`ifdef GATESIM
35267//Do Nothing
35268`else
35269`ifdef CORE_6
35270 if (`PARGS.nas_check_on) begin
35271 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
35272 tid = 3
35273; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35274 end
35275`endif
35276
35277`endif
35278
35279`endif
35280
35281 end
35282 endtask
35283
35284
35285 task slam_RealRange2_core6_thread4;
35286 input [63:0] value;
35287 reg [5:0] tid;
35288 integer junk;
35289
35290 begin
35291`ifdef AXIS_EMUL_COSIM
35292//Do Nothing
35293`else
35294`ifdef GATESIM
35295//Do Nothing
35296`else
35297`ifdef CORE_6
35298 if (`PARGS.nas_check_on) begin
35299 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
35300 tid = 4
35301; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35302 end
35303`endif
35304
35305`endif
35306
35307`endif
35308
35309 end
35310 endtask
35311
35312
35313 task slam_RealRange2_core6_thread5;
35314 input [63:0] value;
35315 reg [5:0] tid;
35316 integer junk;
35317
35318 begin
35319`ifdef AXIS_EMUL_COSIM
35320//Do Nothing
35321`else
35322`ifdef GATESIM
35323//Do Nothing
35324`else
35325`ifdef CORE_6
35326 if (`PARGS.nas_check_on) begin
35327 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
35328 tid = 5
35329; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35330 end
35331`endif
35332
35333`endif
35334
35335`endif
35336
35337 end
35338 endtask
35339
35340
35341 task slam_RealRange2_core6_thread6;
35342 input [63:0] value;
35343 reg [5:0] tid;
35344 integer junk;
35345
35346 begin
35347`ifdef AXIS_EMUL_COSIM
35348//Do Nothing
35349`else
35350`ifdef GATESIM
35351//Do Nothing
35352`else
35353`ifdef CORE_6
35354 if (`PARGS.nas_check_on) begin
35355 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
35356 tid = 6
35357; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35358 end
35359`endif
35360
35361`endif
35362
35363`endif
35364
35365 end
35366 endtask
35367
35368
35369 task slam_RealRange2_core6_thread7;
35370 input [63:0] value;
35371 reg [5:0] tid;
35372 integer junk;
35373
35374 begin
35375`ifdef AXIS_EMUL_COSIM
35376//Do Nothing
35377`else
35378`ifdef GATESIM
35379//Do Nothing
35380`else
35381`ifdef CORE_6
35382 if (`PARGS.nas_check_on) begin
35383 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
35384 tid = 7
35385; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35386 end
35387`endif
35388
35389`endif
35390
35391`endif
35392
35393 end
35394 endtask
35395
35396
35397 task slam_RealRange2_core7_thread0;
35398 input [63:0] value;
35399 reg [5:0] tid;
35400 integer junk;
35401
35402 begin
35403`ifdef AXIS_EMUL_COSIM
35404//Do Nothing
35405`else
35406`ifdef GATESIM
35407//Do Nothing
35408`else
35409`ifdef CORE_7
35410 if (`PARGS.nas_check_on) begin
35411 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
35412 tid = 0
35413; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35414 end
35415`endif
35416
35417`endif
35418
35419`endif
35420
35421 end
35422 endtask
35423
35424
35425 task slam_RealRange2_core7_thread1;
35426 input [63:0] value;
35427 reg [5:0] tid;
35428 integer junk;
35429
35430 begin
35431`ifdef AXIS_EMUL_COSIM
35432//Do Nothing
35433`else
35434`ifdef GATESIM
35435//Do Nothing
35436`else
35437`ifdef CORE_7
35438 if (`PARGS.nas_check_on) begin
35439 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
35440 tid = 1
35441; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35442 end
35443`endif
35444
35445`endif
35446
35447`endif
35448
35449 end
35450 endtask
35451
35452
35453 task slam_RealRange2_core7_thread2;
35454 input [63:0] value;
35455 reg [5:0] tid;
35456 integer junk;
35457
35458 begin
35459`ifdef AXIS_EMUL_COSIM
35460//Do Nothing
35461`else
35462`ifdef GATESIM
35463//Do Nothing
35464`else
35465`ifdef CORE_7
35466 if (`PARGS.nas_check_on) begin
35467 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
35468 tid = 2
35469; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35470 end
35471`endif
35472
35473`endif
35474
35475`endif
35476
35477 end
35478 endtask
35479
35480
35481 task slam_RealRange2_core7_thread3;
35482 input [63:0] value;
35483 reg [5:0] tid;
35484 integer junk;
35485
35486 begin
35487`ifdef AXIS_EMUL_COSIM
35488//Do Nothing
35489`else
35490`ifdef GATESIM
35491//Do Nothing
35492`else
35493`ifdef CORE_7
35494 if (`PARGS.nas_check_on) begin
35495 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
35496 tid = 3
35497; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35498 end
35499`endif
35500
35501`endif
35502
35503`endif
35504
35505 end
35506 endtask
35507
35508
35509 task slam_RealRange2_core7_thread4;
35510 input [63:0] value;
35511 reg [5:0] tid;
35512 integer junk;
35513
35514 begin
35515`ifdef AXIS_EMUL_COSIM
35516//Do Nothing
35517`else
35518`ifdef GATESIM
35519//Do Nothing
35520`else
35521`ifdef CORE_7
35522 if (`PARGS.nas_check_on) begin
35523 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
35524 tid = 4
35525; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35526 end
35527`endif
35528
35529`endif
35530
35531`endif
35532
35533 end
35534 endtask
35535
35536
35537 task slam_RealRange2_core7_thread5;
35538 input [63:0] value;
35539 reg [5:0] tid;
35540 integer junk;
35541
35542 begin
35543`ifdef AXIS_EMUL_COSIM
35544//Do Nothing
35545`else
35546`ifdef GATESIM
35547//Do Nothing
35548`else
35549`ifdef CORE_7
35550 if (`PARGS.nas_check_on) begin
35551 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
35552 tid = 5
35553; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35554 end
35555`endif
35556
35557`endif
35558
35559`endif
35560
35561 end
35562 endtask
35563
35564
35565 task slam_RealRange2_core7_thread6;
35566 input [63:0] value;
35567 reg [5:0] tid;
35568 integer junk;
35569
35570 begin
35571`ifdef AXIS_EMUL_COSIM
35572//Do Nothing
35573`else
35574`ifdef GATESIM
35575//Do Nothing
35576`else
35577`ifdef CORE_7
35578 if (`PARGS.nas_check_on) begin
35579 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
35580 tid = 6
35581; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35582 end
35583`endif
35584
35585`endif
35586
35587`endif
35588
35589 end
35590 endtask
35591
35592
35593 task slam_RealRange2_core7_thread7;
35594 input [63:0] value;
35595 reg [5:0] tid;
35596 integer junk;
35597
35598 begin
35599`ifdef AXIS_EMUL_COSIM
35600//Do Nothing
35601`else
35602`ifdef GATESIM
35603//Do Nothing
35604`else
35605`ifdef CORE_7
35606 if (`PARGS.nas_check_on) begin
35607 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
35608 tid = 7
35609; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h118, value);
35610 end
35611`endif
35612
35613`endif
35614
35615`endif
35616
35617 end
35618 endtask
35619
35620
35621 task slam_RealRange3_core0_thread0;
35622 input [63:0] value;
35623 reg [5:0] tid;
35624 integer junk;
35625
35626 begin
35627`ifdef AXIS_EMUL_COSIM
35628//Do Nothing
35629`else
35630`ifdef GATESIM
35631//Do Nothing
35632`else
35633`ifdef CORE_0
35634 if (`PARGS.nas_check_on) begin
35635 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
35636 tid = 0
35637; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35638 end
35639`endif
35640
35641`endif
35642
35643`endif
35644
35645 end
35646 endtask
35647
35648
35649 task slam_RealRange3_core0_thread1;
35650 input [63:0] value;
35651 reg [5:0] tid;
35652 integer junk;
35653
35654 begin
35655`ifdef AXIS_EMUL_COSIM
35656//Do Nothing
35657`else
35658`ifdef GATESIM
35659//Do Nothing
35660`else
35661`ifdef CORE_0
35662 if (`PARGS.nas_check_on) begin
35663 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
35664 tid = 1
35665; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35666 end
35667`endif
35668
35669`endif
35670
35671`endif
35672
35673 end
35674 endtask
35675
35676
35677 task slam_RealRange3_core0_thread2;
35678 input [63:0] value;
35679 reg [5:0] tid;
35680 integer junk;
35681
35682 begin
35683`ifdef AXIS_EMUL_COSIM
35684//Do Nothing
35685`else
35686`ifdef GATESIM
35687//Do Nothing
35688`else
35689`ifdef CORE_0
35690 if (`PARGS.nas_check_on) begin
35691 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
35692 tid = 2
35693; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35694 end
35695`endif
35696
35697`endif
35698
35699`endif
35700
35701 end
35702 endtask
35703
35704
35705 task slam_RealRange3_core0_thread3;
35706 input [63:0] value;
35707 reg [5:0] tid;
35708 integer junk;
35709
35710 begin
35711`ifdef AXIS_EMUL_COSIM
35712//Do Nothing
35713`else
35714`ifdef GATESIM
35715//Do Nothing
35716`else
35717`ifdef CORE_0
35718 if (`PARGS.nas_check_on) begin
35719 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
35720 tid = 3
35721; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35722 end
35723`endif
35724
35725`endif
35726
35727`endif
35728
35729 end
35730 endtask
35731
35732
35733 task slam_RealRange3_core0_thread4;
35734 input [63:0] value;
35735 reg [5:0] tid;
35736 integer junk;
35737
35738 begin
35739`ifdef AXIS_EMUL_COSIM
35740//Do Nothing
35741`else
35742`ifdef GATESIM
35743//Do Nothing
35744`else
35745`ifdef CORE_0
35746 if (`PARGS.nas_check_on) begin
35747 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
35748 tid = 4
35749; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35750 end
35751`endif
35752
35753`endif
35754
35755`endif
35756
35757 end
35758 endtask
35759
35760
35761 task slam_RealRange3_core0_thread5;
35762 input [63:0] value;
35763 reg [5:0] tid;
35764 integer junk;
35765
35766 begin
35767`ifdef AXIS_EMUL_COSIM
35768//Do Nothing
35769`else
35770`ifdef GATESIM
35771//Do Nothing
35772`else
35773`ifdef CORE_0
35774 if (`PARGS.nas_check_on) begin
35775 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
35776 tid = 5
35777; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35778 end
35779`endif
35780
35781`endif
35782
35783`endif
35784
35785 end
35786 endtask
35787
35788
35789 task slam_RealRange3_core0_thread6;
35790 input [63:0] value;
35791 reg [5:0] tid;
35792 integer junk;
35793
35794 begin
35795`ifdef AXIS_EMUL_COSIM
35796//Do Nothing
35797`else
35798`ifdef GATESIM
35799//Do Nothing
35800`else
35801`ifdef CORE_0
35802 if (`PARGS.nas_check_on) begin
35803 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
35804 tid = 6
35805; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35806 end
35807`endif
35808
35809`endif
35810
35811`endif
35812
35813 end
35814 endtask
35815
35816
35817 task slam_RealRange3_core0_thread7;
35818 input [63:0] value;
35819 reg [5:0] tid;
35820 integer junk;
35821
35822 begin
35823`ifdef AXIS_EMUL_COSIM
35824//Do Nothing
35825`else
35826`ifdef GATESIM
35827//Do Nothing
35828`else
35829`ifdef CORE_0
35830 if (`PARGS.nas_check_on) begin
35831 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
35832 tid = 7
35833; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35834 end
35835`endif
35836
35837`endif
35838
35839`endif
35840
35841 end
35842 endtask
35843
35844
35845 task slam_RealRange3_core1_thread0;
35846 input [63:0] value;
35847 reg [5:0] tid;
35848 integer junk;
35849
35850 begin
35851`ifdef AXIS_EMUL_COSIM
35852//Do Nothing
35853`else
35854`ifdef GATESIM
35855//Do Nothing
35856`else
35857`ifdef CORE_1
35858 if (`PARGS.nas_check_on) begin
35859 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
35860 tid = 0
35861; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35862 end
35863`endif
35864
35865`endif
35866
35867`endif
35868
35869 end
35870 endtask
35871
35872
35873 task slam_RealRange3_core1_thread1;
35874 input [63:0] value;
35875 reg [5:0] tid;
35876 integer junk;
35877
35878 begin
35879`ifdef AXIS_EMUL_COSIM
35880//Do Nothing
35881`else
35882`ifdef GATESIM
35883//Do Nothing
35884`else
35885`ifdef CORE_1
35886 if (`PARGS.nas_check_on) begin
35887 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
35888 tid = 1
35889; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35890 end
35891`endif
35892
35893`endif
35894
35895`endif
35896
35897 end
35898 endtask
35899
35900
35901 task slam_RealRange3_core1_thread2;
35902 input [63:0] value;
35903 reg [5:0] tid;
35904 integer junk;
35905
35906 begin
35907`ifdef AXIS_EMUL_COSIM
35908//Do Nothing
35909`else
35910`ifdef GATESIM
35911//Do Nothing
35912`else
35913`ifdef CORE_1
35914 if (`PARGS.nas_check_on) begin
35915 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
35916 tid = 2
35917; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35918 end
35919`endif
35920
35921`endif
35922
35923`endif
35924
35925 end
35926 endtask
35927
35928
35929 task slam_RealRange3_core1_thread3;
35930 input [63:0] value;
35931 reg [5:0] tid;
35932 integer junk;
35933
35934 begin
35935`ifdef AXIS_EMUL_COSIM
35936//Do Nothing
35937`else
35938`ifdef GATESIM
35939//Do Nothing
35940`else
35941`ifdef CORE_1
35942 if (`PARGS.nas_check_on) begin
35943 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
35944 tid = 3
35945; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35946 end
35947`endif
35948
35949`endif
35950
35951`endif
35952
35953 end
35954 endtask
35955
35956
35957 task slam_RealRange3_core1_thread4;
35958 input [63:0] value;
35959 reg [5:0] tid;
35960 integer junk;
35961
35962 begin
35963`ifdef AXIS_EMUL_COSIM
35964//Do Nothing
35965`else
35966`ifdef GATESIM
35967//Do Nothing
35968`else
35969`ifdef CORE_1
35970 if (`PARGS.nas_check_on) begin
35971 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
35972 tid = 4
35973; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
35974 end
35975`endif
35976
35977`endif
35978
35979`endif
35980
35981 end
35982 endtask
35983
35984
35985 task slam_RealRange3_core1_thread5;
35986 input [63:0] value;
35987 reg [5:0] tid;
35988 integer junk;
35989
35990 begin
35991`ifdef AXIS_EMUL_COSIM
35992//Do Nothing
35993`else
35994`ifdef GATESIM
35995//Do Nothing
35996`else
35997`ifdef CORE_1
35998 if (`PARGS.nas_check_on) begin
35999 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
36000 tid = 5
36001; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36002 end
36003`endif
36004
36005`endif
36006
36007`endif
36008
36009 end
36010 endtask
36011
36012
36013 task slam_RealRange3_core1_thread6;
36014 input [63:0] value;
36015 reg [5:0] tid;
36016 integer junk;
36017
36018 begin
36019`ifdef AXIS_EMUL_COSIM
36020//Do Nothing
36021`else
36022`ifdef GATESIM
36023//Do Nothing
36024`else
36025`ifdef CORE_1
36026 if (`PARGS.nas_check_on) begin
36027 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
36028 tid = 6
36029; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36030 end
36031`endif
36032
36033`endif
36034
36035`endif
36036
36037 end
36038 endtask
36039
36040
36041 task slam_RealRange3_core1_thread7;
36042 input [63:0] value;
36043 reg [5:0] tid;
36044 integer junk;
36045
36046 begin
36047`ifdef AXIS_EMUL_COSIM
36048//Do Nothing
36049`else
36050`ifdef GATESIM
36051//Do Nothing
36052`else
36053`ifdef CORE_1
36054 if (`PARGS.nas_check_on) begin
36055 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
36056 tid = 7
36057; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36058 end
36059`endif
36060
36061`endif
36062
36063`endif
36064
36065 end
36066 endtask
36067
36068
36069 task slam_RealRange3_core2_thread0;
36070 input [63:0] value;
36071 reg [5:0] tid;
36072 integer junk;
36073
36074 begin
36075`ifdef AXIS_EMUL_COSIM
36076//Do Nothing
36077`else
36078`ifdef GATESIM
36079//Do Nothing
36080`else
36081`ifdef CORE_2
36082 if (`PARGS.nas_check_on) begin
36083 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
36084 tid = 0
36085; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36086 end
36087`endif
36088
36089`endif
36090
36091`endif
36092
36093 end
36094 endtask
36095
36096
36097 task slam_RealRange3_core2_thread1;
36098 input [63:0] value;
36099 reg [5:0] tid;
36100 integer junk;
36101
36102 begin
36103`ifdef AXIS_EMUL_COSIM
36104//Do Nothing
36105`else
36106`ifdef GATESIM
36107//Do Nothing
36108`else
36109`ifdef CORE_2
36110 if (`PARGS.nas_check_on) begin
36111 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
36112 tid = 1
36113; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36114 end
36115`endif
36116
36117`endif
36118
36119`endif
36120
36121 end
36122 endtask
36123
36124
36125 task slam_RealRange3_core2_thread2;
36126 input [63:0] value;
36127 reg [5:0] tid;
36128 integer junk;
36129
36130 begin
36131`ifdef AXIS_EMUL_COSIM
36132//Do Nothing
36133`else
36134`ifdef GATESIM
36135//Do Nothing
36136`else
36137`ifdef CORE_2
36138 if (`PARGS.nas_check_on) begin
36139 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
36140 tid = 2
36141; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36142 end
36143`endif
36144
36145`endif
36146
36147`endif
36148
36149 end
36150 endtask
36151
36152
36153 task slam_RealRange3_core2_thread3;
36154 input [63:0] value;
36155 reg [5:0] tid;
36156 integer junk;
36157
36158 begin
36159`ifdef AXIS_EMUL_COSIM
36160//Do Nothing
36161`else
36162`ifdef GATESIM
36163//Do Nothing
36164`else
36165`ifdef CORE_2
36166 if (`PARGS.nas_check_on) begin
36167 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
36168 tid = 3
36169; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36170 end
36171`endif
36172
36173`endif
36174
36175`endif
36176
36177 end
36178 endtask
36179
36180
36181 task slam_RealRange3_core2_thread4;
36182 input [63:0] value;
36183 reg [5:0] tid;
36184 integer junk;
36185
36186 begin
36187`ifdef AXIS_EMUL_COSIM
36188//Do Nothing
36189`else
36190`ifdef GATESIM
36191//Do Nothing
36192`else
36193`ifdef CORE_2
36194 if (`PARGS.nas_check_on) begin
36195 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
36196 tid = 4
36197; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36198 end
36199`endif
36200
36201`endif
36202
36203`endif
36204
36205 end
36206 endtask
36207
36208
36209 task slam_RealRange3_core2_thread5;
36210 input [63:0] value;
36211 reg [5:0] tid;
36212 integer junk;
36213
36214 begin
36215`ifdef AXIS_EMUL_COSIM
36216//Do Nothing
36217`else
36218`ifdef GATESIM
36219//Do Nothing
36220`else
36221`ifdef CORE_2
36222 if (`PARGS.nas_check_on) begin
36223 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
36224 tid = 5
36225; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36226 end
36227`endif
36228
36229`endif
36230
36231`endif
36232
36233 end
36234 endtask
36235
36236
36237 task slam_RealRange3_core2_thread6;
36238 input [63:0] value;
36239 reg [5:0] tid;
36240 integer junk;
36241
36242 begin
36243`ifdef AXIS_EMUL_COSIM
36244//Do Nothing
36245`else
36246`ifdef GATESIM
36247//Do Nothing
36248`else
36249`ifdef CORE_2
36250 if (`PARGS.nas_check_on) begin
36251 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
36252 tid = 6
36253; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36254 end
36255`endif
36256
36257`endif
36258
36259`endif
36260
36261 end
36262 endtask
36263
36264
36265 task slam_RealRange3_core2_thread7;
36266 input [63:0] value;
36267 reg [5:0] tid;
36268 integer junk;
36269
36270 begin
36271`ifdef AXIS_EMUL_COSIM
36272//Do Nothing
36273`else
36274`ifdef GATESIM
36275//Do Nothing
36276`else
36277`ifdef CORE_2
36278 if (`PARGS.nas_check_on) begin
36279 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
36280 tid = 7
36281; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36282 end
36283`endif
36284
36285`endif
36286
36287`endif
36288
36289 end
36290 endtask
36291
36292
36293 task slam_RealRange3_core3_thread0;
36294 input [63:0] value;
36295 reg [5:0] tid;
36296 integer junk;
36297
36298 begin
36299`ifdef AXIS_EMUL_COSIM
36300//Do Nothing
36301`else
36302`ifdef GATESIM
36303//Do Nothing
36304`else
36305`ifdef CORE_3
36306 if (`PARGS.nas_check_on) begin
36307 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
36308 tid = 0
36309; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36310 end
36311`endif
36312
36313`endif
36314
36315`endif
36316
36317 end
36318 endtask
36319
36320
36321 task slam_RealRange3_core3_thread1;
36322 input [63:0] value;
36323 reg [5:0] tid;
36324 integer junk;
36325
36326 begin
36327`ifdef AXIS_EMUL_COSIM
36328//Do Nothing
36329`else
36330`ifdef GATESIM
36331//Do Nothing
36332`else
36333`ifdef CORE_3
36334 if (`PARGS.nas_check_on) begin
36335 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
36336 tid = 1
36337; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36338 end
36339`endif
36340
36341`endif
36342
36343`endif
36344
36345 end
36346 endtask
36347
36348
36349 task slam_RealRange3_core3_thread2;
36350 input [63:0] value;
36351 reg [5:0] tid;
36352 integer junk;
36353
36354 begin
36355`ifdef AXIS_EMUL_COSIM
36356//Do Nothing
36357`else
36358`ifdef GATESIM
36359//Do Nothing
36360`else
36361`ifdef CORE_3
36362 if (`PARGS.nas_check_on) begin
36363 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
36364 tid = 2
36365; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36366 end
36367`endif
36368
36369`endif
36370
36371`endif
36372
36373 end
36374 endtask
36375
36376
36377 task slam_RealRange3_core3_thread3;
36378 input [63:0] value;
36379 reg [5:0] tid;
36380 integer junk;
36381
36382 begin
36383`ifdef AXIS_EMUL_COSIM
36384//Do Nothing
36385`else
36386`ifdef GATESIM
36387//Do Nothing
36388`else
36389`ifdef CORE_3
36390 if (`PARGS.nas_check_on) begin
36391 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
36392 tid = 3
36393; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36394 end
36395`endif
36396
36397`endif
36398
36399`endif
36400
36401 end
36402 endtask
36403
36404
36405 task slam_RealRange3_core3_thread4;
36406 input [63:0] value;
36407 reg [5:0] tid;
36408 integer junk;
36409
36410 begin
36411`ifdef AXIS_EMUL_COSIM
36412//Do Nothing
36413`else
36414`ifdef GATESIM
36415//Do Nothing
36416`else
36417`ifdef CORE_3
36418 if (`PARGS.nas_check_on) begin
36419 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
36420 tid = 4
36421; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36422 end
36423`endif
36424
36425`endif
36426
36427`endif
36428
36429 end
36430 endtask
36431
36432
36433 task slam_RealRange3_core3_thread5;
36434 input [63:0] value;
36435 reg [5:0] tid;
36436 integer junk;
36437
36438 begin
36439`ifdef AXIS_EMUL_COSIM
36440//Do Nothing
36441`else
36442`ifdef GATESIM
36443//Do Nothing
36444`else
36445`ifdef CORE_3
36446 if (`PARGS.nas_check_on) begin
36447 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
36448 tid = 5
36449; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36450 end
36451`endif
36452
36453`endif
36454
36455`endif
36456
36457 end
36458 endtask
36459
36460
36461 task slam_RealRange3_core3_thread6;
36462 input [63:0] value;
36463 reg [5:0] tid;
36464 integer junk;
36465
36466 begin
36467`ifdef AXIS_EMUL_COSIM
36468//Do Nothing
36469`else
36470`ifdef GATESIM
36471//Do Nothing
36472`else
36473`ifdef CORE_3
36474 if (`PARGS.nas_check_on) begin
36475 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
36476 tid = 6
36477; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36478 end
36479`endif
36480
36481`endif
36482
36483`endif
36484
36485 end
36486 endtask
36487
36488
36489 task slam_RealRange3_core3_thread7;
36490 input [63:0] value;
36491 reg [5:0] tid;
36492 integer junk;
36493
36494 begin
36495`ifdef AXIS_EMUL_COSIM
36496//Do Nothing
36497`else
36498`ifdef GATESIM
36499//Do Nothing
36500`else
36501`ifdef CORE_3
36502 if (`PARGS.nas_check_on) begin
36503 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
36504 tid = 7
36505; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36506 end
36507`endif
36508
36509`endif
36510
36511`endif
36512
36513 end
36514 endtask
36515
36516
36517 task slam_RealRange3_core4_thread0;
36518 input [63:0] value;
36519 reg [5:0] tid;
36520 integer junk;
36521
36522 begin
36523`ifdef AXIS_EMUL_COSIM
36524//Do Nothing
36525`else
36526`ifdef GATESIM
36527//Do Nothing
36528`else
36529`ifdef CORE_4
36530 if (`PARGS.nas_check_on) begin
36531 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
36532 tid = 0
36533; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36534 end
36535`endif
36536
36537`endif
36538
36539`endif
36540
36541 end
36542 endtask
36543
36544
36545 task slam_RealRange3_core4_thread1;
36546 input [63:0] value;
36547 reg [5:0] tid;
36548 integer junk;
36549
36550 begin
36551`ifdef AXIS_EMUL_COSIM
36552//Do Nothing
36553`else
36554`ifdef GATESIM
36555//Do Nothing
36556`else
36557`ifdef CORE_4
36558 if (`PARGS.nas_check_on) begin
36559 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
36560 tid = 1
36561; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36562 end
36563`endif
36564
36565`endif
36566
36567`endif
36568
36569 end
36570 endtask
36571
36572
36573 task slam_RealRange3_core4_thread2;
36574 input [63:0] value;
36575 reg [5:0] tid;
36576 integer junk;
36577
36578 begin
36579`ifdef AXIS_EMUL_COSIM
36580//Do Nothing
36581`else
36582`ifdef GATESIM
36583//Do Nothing
36584`else
36585`ifdef CORE_4
36586 if (`PARGS.nas_check_on) begin
36587 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
36588 tid = 2
36589; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36590 end
36591`endif
36592
36593`endif
36594
36595`endif
36596
36597 end
36598 endtask
36599
36600
36601 task slam_RealRange3_core4_thread3;
36602 input [63:0] value;
36603 reg [5:0] tid;
36604 integer junk;
36605
36606 begin
36607`ifdef AXIS_EMUL_COSIM
36608//Do Nothing
36609`else
36610`ifdef GATESIM
36611//Do Nothing
36612`else
36613`ifdef CORE_4
36614 if (`PARGS.nas_check_on) begin
36615 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
36616 tid = 3
36617; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36618 end
36619`endif
36620
36621`endif
36622
36623`endif
36624
36625 end
36626 endtask
36627
36628
36629 task slam_RealRange3_core4_thread4;
36630 input [63:0] value;
36631 reg [5:0] tid;
36632 integer junk;
36633
36634 begin
36635`ifdef AXIS_EMUL_COSIM
36636//Do Nothing
36637`else
36638`ifdef GATESIM
36639//Do Nothing
36640`else
36641`ifdef CORE_4
36642 if (`PARGS.nas_check_on) begin
36643 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
36644 tid = 4
36645; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36646 end
36647`endif
36648
36649`endif
36650
36651`endif
36652
36653 end
36654 endtask
36655
36656
36657 task slam_RealRange3_core4_thread5;
36658 input [63:0] value;
36659 reg [5:0] tid;
36660 integer junk;
36661
36662 begin
36663`ifdef AXIS_EMUL_COSIM
36664//Do Nothing
36665`else
36666`ifdef GATESIM
36667//Do Nothing
36668`else
36669`ifdef CORE_4
36670 if (`PARGS.nas_check_on) begin
36671 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
36672 tid = 5
36673; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36674 end
36675`endif
36676
36677`endif
36678
36679`endif
36680
36681 end
36682 endtask
36683
36684
36685 task slam_RealRange3_core4_thread6;
36686 input [63:0] value;
36687 reg [5:0] tid;
36688 integer junk;
36689
36690 begin
36691`ifdef AXIS_EMUL_COSIM
36692//Do Nothing
36693`else
36694`ifdef GATESIM
36695//Do Nothing
36696`else
36697`ifdef CORE_4
36698 if (`PARGS.nas_check_on) begin
36699 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
36700 tid = 6
36701; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36702 end
36703`endif
36704
36705`endif
36706
36707`endif
36708
36709 end
36710 endtask
36711
36712
36713 task slam_RealRange3_core4_thread7;
36714 input [63:0] value;
36715 reg [5:0] tid;
36716 integer junk;
36717
36718 begin
36719`ifdef AXIS_EMUL_COSIM
36720//Do Nothing
36721`else
36722`ifdef GATESIM
36723//Do Nothing
36724`else
36725`ifdef CORE_4
36726 if (`PARGS.nas_check_on) begin
36727 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
36728 tid = 7
36729; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36730 end
36731`endif
36732
36733`endif
36734
36735`endif
36736
36737 end
36738 endtask
36739
36740
36741 task slam_RealRange3_core5_thread0;
36742 input [63:0] value;
36743 reg [5:0] tid;
36744 integer junk;
36745
36746 begin
36747`ifdef AXIS_EMUL_COSIM
36748//Do Nothing
36749`else
36750`ifdef GATESIM
36751//Do Nothing
36752`else
36753`ifdef CORE_5
36754 if (`PARGS.nas_check_on) begin
36755 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
36756 tid = 0
36757; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36758 end
36759`endif
36760
36761`endif
36762
36763`endif
36764
36765 end
36766 endtask
36767
36768
36769 task slam_RealRange3_core5_thread1;
36770 input [63:0] value;
36771 reg [5:0] tid;
36772 integer junk;
36773
36774 begin
36775`ifdef AXIS_EMUL_COSIM
36776//Do Nothing
36777`else
36778`ifdef GATESIM
36779//Do Nothing
36780`else
36781`ifdef CORE_5
36782 if (`PARGS.nas_check_on) begin
36783 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
36784 tid = 1
36785; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36786 end
36787`endif
36788
36789`endif
36790
36791`endif
36792
36793 end
36794 endtask
36795
36796
36797 task slam_RealRange3_core5_thread2;
36798 input [63:0] value;
36799 reg [5:0] tid;
36800 integer junk;
36801
36802 begin
36803`ifdef AXIS_EMUL_COSIM
36804//Do Nothing
36805`else
36806`ifdef GATESIM
36807//Do Nothing
36808`else
36809`ifdef CORE_5
36810 if (`PARGS.nas_check_on) begin
36811 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
36812 tid = 2
36813; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36814 end
36815`endif
36816
36817`endif
36818
36819`endif
36820
36821 end
36822 endtask
36823
36824
36825 task slam_RealRange3_core5_thread3;
36826 input [63:0] value;
36827 reg [5:0] tid;
36828 integer junk;
36829
36830 begin
36831`ifdef AXIS_EMUL_COSIM
36832//Do Nothing
36833`else
36834`ifdef GATESIM
36835//Do Nothing
36836`else
36837`ifdef CORE_5
36838 if (`PARGS.nas_check_on) begin
36839 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
36840 tid = 3
36841; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36842 end
36843`endif
36844
36845`endif
36846
36847`endif
36848
36849 end
36850 endtask
36851
36852
36853 task slam_RealRange3_core5_thread4;
36854 input [63:0] value;
36855 reg [5:0] tid;
36856 integer junk;
36857
36858 begin
36859`ifdef AXIS_EMUL_COSIM
36860//Do Nothing
36861`else
36862`ifdef GATESIM
36863//Do Nothing
36864`else
36865`ifdef CORE_5
36866 if (`PARGS.nas_check_on) begin
36867 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
36868 tid = 4
36869; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36870 end
36871`endif
36872
36873`endif
36874
36875`endif
36876
36877 end
36878 endtask
36879
36880
36881 task slam_RealRange3_core5_thread5;
36882 input [63:0] value;
36883 reg [5:0] tid;
36884 integer junk;
36885
36886 begin
36887`ifdef AXIS_EMUL_COSIM
36888//Do Nothing
36889`else
36890`ifdef GATESIM
36891//Do Nothing
36892`else
36893`ifdef CORE_5
36894 if (`PARGS.nas_check_on) begin
36895 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
36896 tid = 5
36897; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36898 end
36899`endif
36900
36901`endif
36902
36903`endif
36904
36905 end
36906 endtask
36907
36908
36909 task slam_RealRange3_core5_thread6;
36910 input [63:0] value;
36911 reg [5:0] tid;
36912 integer junk;
36913
36914 begin
36915`ifdef AXIS_EMUL_COSIM
36916//Do Nothing
36917`else
36918`ifdef GATESIM
36919//Do Nothing
36920`else
36921`ifdef CORE_5
36922 if (`PARGS.nas_check_on) begin
36923 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
36924 tid = 6
36925; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36926 end
36927`endif
36928
36929`endif
36930
36931`endif
36932
36933 end
36934 endtask
36935
36936
36937 task slam_RealRange3_core5_thread7;
36938 input [63:0] value;
36939 reg [5:0] tid;
36940 integer junk;
36941
36942 begin
36943`ifdef AXIS_EMUL_COSIM
36944//Do Nothing
36945`else
36946`ifdef GATESIM
36947//Do Nothing
36948`else
36949`ifdef CORE_5
36950 if (`PARGS.nas_check_on) begin
36951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
36952 tid = 7
36953; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36954 end
36955`endif
36956
36957`endif
36958
36959`endif
36960
36961 end
36962 endtask
36963
36964
36965 task slam_RealRange3_core6_thread0;
36966 input [63:0] value;
36967 reg [5:0] tid;
36968 integer junk;
36969
36970 begin
36971`ifdef AXIS_EMUL_COSIM
36972//Do Nothing
36973`else
36974`ifdef GATESIM
36975//Do Nothing
36976`else
36977`ifdef CORE_6
36978 if (`PARGS.nas_check_on) begin
36979 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
36980 tid = 0
36981; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
36982 end
36983`endif
36984
36985`endif
36986
36987`endif
36988
36989 end
36990 endtask
36991
36992
36993 task slam_RealRange3_core6_thread1;
36994 input [63:0] value;
36995 reg [5:0] tid;
36996 integer junk;
36997
36998 begin
36999`ifdef AXIS_EMUL_COSIM
37000//Do Nothing
37001`else
37002`ifdef GATESIM
37003//Do Nothing
37004`else
37005`ifdef CORE_6
37006 if (`PARGS.nas_check_on) begin
37007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
37008 tid = 1
37009; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37010 end
37011`endif
37012
37013`endif
37014
37015`endif
37016
37017 end
37018 endtask
37019
37020
37021 task slam_RealRange3_core6_thread2;
37022 input [63:0] value;
37023 reg [5:0] tid;
37024 integer junk;
37025
37026 begin
37027`ifdef AXIS_EMUL_COSIM
37028//Do Nothing
37029`else
37030`ifdef GATESIM
37031//Do Nothing
37032`else
37033`ifdef CORE_6
37034 if (`PARGS.nas_check_on) begin
37035 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
37036 tid = 2
37037; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37038 end
37039`endif
37040
37041`endif
37042
37043`endif
37044
37045 end
37046 endtask
37047
37048
37049 task slam_RealRange3_core6_thread3;
37050 input [63:0] value;
37051 reg [5:0] tid;
37052 integer junk;
37053
37054 begin
37055`ifdef AXIS_EMUL_COSIM
37056//Do Nothing
37057`else
37058`ifdef GATESIM
37059//Do Nothing
37060`else
37061`ifdef CORE_6
37062 if (`PARGS.nas_check_on) begin
37063 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
37064 tid = 3
37065; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37066 end
37067`endif
37068
37069`endif
37070
37071`endif
37072
37073 end
37074 endtask
37075
37076
37077 task slam_RealRange3_core6_thread4;
37078 input [63:0] value;
37079 reg [5:0] tid;
37080 integer junk;
37081
37082 begin
37083`ifdef AXIS_EMUL_COSIM
37084//Do Nothing
37085`else
37086`ifdef GATESIM
37087//Do Nothing
37088`else
37089`ifdef CORE_6
37090 if (`PARGS.nas_check_on) begin
37091 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
37092 tid = 4
37093; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37094 end
37095`endif
37096
37097`endif
37098
37099`endif
37100
37101 end
37102 endtask
37103
37104
37105 task slam_RealRange3_core6_thread5;
37106 input [63:0] value;
37107 reg [5:0] tid;
37108 integer junk;
37109
37110 begin
37111`ifdef AXIS_EMUL_COSIM
37112//Do Nothing
37113`else
37114`ifdef GATESIM
37115//Do Nothing
37116`else
37117`ifdef CORE_6
37118 if (`PARGS.nas_check_on) begin
37119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
37120 tid = 5
37121; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37122 end
37123`endif
37124
37125`endif
37126
37127`endif
37128
37129 end
37130 endtask
37131
37132
37133 task slam_RealRange3_core6_thread6;
37134 input [63:0] value;
37135 reg [5:0] tid;
37136 integer junk;
37137
37138 begin
37139`ifdef AXIS_EMUL_COSIM
37140//Do Nothing
37141`else
37142`ifdef GATESIM
37143//Do Nothing
37144`else
37145`ifdef CORE_6
37146 if (`PARGS.nas_check_on) begin
37147 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
37148 tid = 6
37149; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37150 end
37151`endif
37152
37153`endif
37154
37155`endif
37156
37157 end
37158 endtask
37159
37160
37161 task slam_RealRange3_core6_thread7;
37162 input [63:0] value;
37163 reg [5:0] tid;
37164 integer junk;
37165
37166 begin
37167`ifdef AXIS_EMUL_COSIM
37168//Do Nothing
37169`else
37170`ifdef GATESIM
37171//Do Nothing
37172`else
37173`ifdef CORE_6
37174 if (`PARGS.nas_check_on) begin
37175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
37176 tid = 7
37177; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37178 end
37179`endif
37180
37181`endif
37182
37183`endif
37184
37185 end
37186 endtask
37187
37188
37189 task slam_RealRange3_core7_thread0;
37190 input [63:0] value;
37191 reg [5:0] tid;
37192 integer junk;
37193
37194 begin
37195`ifdef AXIS_EMUL_COSIM
37196//Do Nothing
37197`else
37198`ifdef GATESIM
37199//Do Nothing
37200`else
37201`ifdef CORE_7
37202 if (`PARGS.nas_check_on) begin
37203 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
37204 tid = 0
37205; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37206 end
37207`endif
37208
37209`endif
37210
37211`endif
37212
37213 end
37214 endtask
37215
37216
37217 task slam_RealRange3_core7_thread1;
37218 input [63:0] value;
37219 reg [5:0] tid;
37220 integer junk;
37221
37222 begin
37223`ifdef AXIS_EMUL_COSIM
37224//Do Nothing
37225`else
37226`ifdef GATESIM
37227//Do Nothing
37228`else
37229`ifdef CORE_7
37230 if (`PARGS.nas_check_on) begin
37231 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
37232 tid = 1
37233; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37234 end
37235`endif
37236
37237`endif
37238
37239`endif
37240
37241 end
37242 endtask
37243
37244
37245 task slam_RealRange3_core7_thread2;
37246 input [63:0] value;
37247 reg [5:0] tid;
37248 integer junk;
37249
37250 begin
37251`ifdef AXIS_EMUL_COSIM
37252//Do Nothing
37253`else
37254`ifdef GATESIM
37255//Do Nothing
37256`else
37257`ifdef CORE_7
37258 if (`PARGS.nas_check_on) begin
37259 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
37260 tid = 2
37261; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37262 end
37263`endif
37264
37265`endif
37266
37267`endif
37268
37269 end
37270 endtask
37271
37272
37273 task slam_RealRange3_core7_thread3;
37274 input [63:0] value;
37275 reg [5:0] tid;
37276 integer junk;
37277
37278 begin
37279`ifdef AXIS_EMUL_COSIM
37280//Do Nothing
37281`else
37282`ifdef GATESIM
37283//Do Nothing
37284`else
37285`ifdef CORE_7
37286 if (`PARGS.nas_check_on) begin
37287 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
37288 tid = 3
37289; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37290 end
37291`endif
37292
37293`endif
37294
37295`endif
37296
37297 end
37298 endtask
37299
37300
37301 task slam_RealRange3_core7_thread4;
37302 input [63:0] value;
37303 reg [5:0] tid;
37304 integer junk;
37305
37306 begin
37307`ifdef AXIS_EMUL_COSIM
37308//Do Nothing
37309`else
37310`ifdef GATESIM
37311//Do Nothing
37312`else
37313`ifdef CORE_7
37314 if (`PARGS.nas_check_on) begin
37315 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
37316 tid = 4
37317; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37318 end
37319`endif
37320
37321`endif
37322
37323`endif
37324
37325 end
37326 endtask
37327
37328
37329 task slam_RealRange3_core7_thread5;
37330 input [63:0] value;
37331 reg [5:0] tid;
37332 integer junk;
37333
37334 begin
37335`ifdef AXIS_EMUL_COSIM
37336//Do Nothing
37337`else
37338`ifdef GATESIM
37339//Do Nothing
37340`else
37341`ifdef CORE_7
37342 if (`PARGS.nas_check_on) begin
37343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
37344 tid = 5
37345; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37346 end
37347`endif
37348
37349`endif
37350
37351`endif
37352
37353 end
37354 endtask
37355
37356
37357 task slam_RealRange3_core7_thread6;
37358 input [63:0] value;
37359 reg [5:0] tid;
37360 integer junk;
37361
37362 begin
37363`ifdef AXIS_EMUL_COSIM
37364//Do Nothing
37365`else
37366`ifdef GATESIM
37367//Do Nothing
37368`else
37369`ifdef CORE_7
37370 if (`PARGS.nas_check_on) begin
37371 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
37372 tid = 6
37373; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37374 end
37375`endif
37376
37377`endif
37378
37379`endif
37380
37381 end
37382 endtask
37383
37384
37385 task slam_RealRange3_core7_thread7;
37386 input [63:0] value;
37387 reg [5:0] tid;
37388 integer junk;
37389
37390 begin
37391`ifdef AXIS_EMUL_COSIM
37392//Do Nothing
37393`else
37394`ifdef GATESIM
37395//Do Nothing
37396`else
37397`ifdef CORE_7
37398 if (`PARGS.nas_check_on) begin
37399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
37400 tid = 7
37401; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h120, value);
37402 end
37403`endif
37404
37405`endif
37406
37407`endif
37408
37409 end
37410 endtask
37411
37412
37413 task slam_PhysicalOffset0_core0_thread0;
37414 input [63:0] value;
37415 reg [5:0] tid;
37416 integer junk;
37417
37418 begin
37419`ifdef AXIS_EMUL_COSIM
37420//Do Nothing
37421`else
37422`ifdef GATESIM
37423//Do Nothing
37424`else
37425`ifdef CORE_0
37426 if (`PARGS.nas_check_on) begin
37427 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
37428 tid = 0
37429; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37430 end
37431`endif
37432
37433`endif
37434
37435`endif
37436
37437 end
37438 endtask
37439
37440
37441 task slam_PhysicalOffset0_core0_thread1;
37442 input [63:0] value;
37443 reg [5:0] tid;
37444 integer junk;
37445
37446 begin
37447`ifdef AXIS_EMUL_COSIM
37448//Do Nothing
37449`else
37450`ifdef GATESIM
37451//Do Nothing
37452`else
37453`ifdef CORE_0
37454 if (`PARGS.nas_check_on) begin
37455 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
37456 tid = 1
37457; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37458 end
37459`endif
37460
37461`endif
37462
37463`endif
37464
37465 end
37466 endtask
37467
37468
37469 task slam_PhysicalOffset0_core0_thread2;
37470 input [63:0] value;
37471 reg [5:0] tid;
37472 integer junk;
37473
37474 begin
37475`ifdef AXIS_EMUL_COSIM
37476//Do Nothing
37477`else
37478`ifdef GATESIM
37479//Do Nothing
37480`else
37481`ifdef CORE_0
37482 if (`PARGS.nas_check_on) begin
37483 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
37484 tid = 2
37485; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37486 end
37487`endif
37488
37489`endif
37490
37491`endif
37492
37493 end
37494 endtask
37495
37496
37497 task slam_PhysicalOffset0_core0_thread3;
37498 input [63:0] value;
37499 reg [5:0] tid;
37500 integer junk;
37501
37502 begin
37503`ifdef AXIS_EMUL_COSIM
37504//Do Nothing
37505`else
37506`ifdef GATESIM
37507//Do Nothing
37508`else
37509`ifdef CORE_0
37510 if (`PARGS.nas_check_on) begin
37511 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
37512 tid = 3
37513; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37514 end
37515`endif
37516
37517`endif
37518
37519`endif
37520
37521 end
37522 endtask
37523
37524
37525 task slam_PhysicalOffset0_core0_thread4;
37526 input [63:0] value;
37527 reg [5:0] tid;
37528 integer junk;
37529
37530 begin
37531`ifdef AXIS_EMUL_COSIM
37532//Do Nothing
37533`else
37534`ifdef GATESIM
37535//Do Nothing
37536`else
37537`ifdef CORE_0
37538 if (`PARGS.nas_check_on) begin
37539 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
37540 tid = 4
37541; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37542 end
37543`endif
37544
37545`endif
37546
37547`endif
37548
37549 end
37550 endtask
37551
37552
37553 task slam_PhysicalOffset0_core0_thread5;
37554 input [63:0] value;
37555 reg [5:0] tid;
37556 integer junk;
37557
37558 begin
37559`ifdef AXIS_EMUL_COSIM
37560//Do Nothing
37561`else
37562`ifdef GATESIM
37563//Do Nothing
37564`else
37565`ifdef CORE_0
37566 if (`PARGS.nas_check_on) begin
37567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
37568 tid = 5
37569; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37570 end
37571`endif
37572
37573`endif
37574
37575`endif
37576
37577 end
37578 endtask
37579
37580
37581 task slam_PhysicalOffset0_core0_thread6;
37582 input [63:0] value;
37583 reg [5:0] tid;
37584 integer junk;
37585
37586 begin
37587`ifdef AXIS_EMUL_COSIM
37588//Do Nothing
37589`else
37590`ifdef GATESIM
37591//Do Nothing
37592`else
37593`ifdef CORE_0
37594 if (`PARGS.nas_check_on) begin
37595 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
37596 tid = 6
37597; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37598 end
37599`endif
37600
37601`endif
37602
37603`endif
37604
37605 end
37606 endtask
37607
37608
37609 task slam_PhysicalOffset0_core0_thread7;
37610 input [63:0] value;
37611 reg [5:0] tid;
37612 integer junk;
37613
37614 begin
37615`ifdef AXIS_EMUL_COSIM
37616//Do Nothing
37617`else
37618`ifdef GATESIM
37619//Do Nothing
37620`else
37621`ifdef CORE_0
37622 if (`PARGS.nas_check_on) begin
37623 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
37624 tid = 7
37625; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37626 end
37627`endif
37628
37629`endif
37630
37631`endif
37632
37633 end
37634 endtask
37635
37636
37637 task slam_PhysicalOffset0_core1_thread0;
37638 input [63:0] value;
37639 reg [5:0] tid;
37640 integer junk;
37641
37642 begin
37643`ifdef AXIS_EMUL_COSIM
37644//Do Nothing
37645`else
37646`ifdef GATESIM
37647//Do Nothing
37648`else
37649`ifdef CORE_1
37650 if (`PARGS.nas_check_on) begin
37651 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
37652 tid = 0
37653; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37654 end
37655`endif
37656
37657`endif
37658
37659`endif
37660
37661 end
37662 endtask
37663
37664
37665 task slam_PhysicalOffset0_core1_thread1;
37666 input [63:0] value;
37667 reg [5:0] tid;
37668 integer junk;
37669
37670 begin
37671`ifdef AXIS_EMUL_COSIM
37672//Do Nothing
37673`else
37674`ifdef GATESIM
37675//Do Nothing
37676`else
37677`ifdef CORE_1
37678 if (`PARGS.nas_check_on) begin
37679 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
37680 tid = 1
37681; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37682 end
37683`endif
37684
37685`endif
37686
37687`endif
37688
37689 end
37690 endtask
37691
37692
37693 task slam_PhysicalOffset0_core1_thread2;
37694 input [63:0] value;
37695 reg [5:0] tid;
37696 integer junk;
37697
37698 begin
37699`ifdef AXIS_EMUL_COSIM
37700//Do Nothing
37701`else
37702`ifdef GATESIM
37703//Do Nothing
37704`else
37705`ifdef CORE_1
37706 if (`PARGS.nas_check_on) begin
37707 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
37708 tid = 2
37709; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37710 end
37711`endif
37712
37713`endif
37714
37715`endif
37716
37717 end
37718 endtask
37719
37720
37721 task slam_PhysicalOffset0_core1_thread3;
37722 input [63:0] value;
37723 reg [5:0] tid;
37724 integer junk;
37725
37726 begin
37727`ifdef AXIS_EMUL_COSIM
37728//Do Nothing
37729`else
37730`ifdef GATESIM
37731//Do Nothing
37732`else
37733`ifdef CORE_1
37734 if (`PARGS.nas_check_on) begin
37735 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
37736 tid = 3
37737; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37738 end
37739`endif
37740
37741`endif
37742
37743`endif
37744
37745 end
37746 endtask
37747
37748
37749 task slam_PhysicalOffset0_core1_thread4;
37750 input [63:0] value;
37751 reg [5:0] tid;
37752 integer junk;
37753
37754 begin
37755`ifdef AXIS_EMUL_COSIM
37756//Do Nothing
37757`else
37758`ifdef GATESIM
37759//Do Nothing
37760`else
37761`ifdef CORE_1
37762 if (`PARGS.nas_check_on) begin
37763 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
37764 tid = 4
37765; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37766 end
37767`endif
37768
37769`endif
37770
37771`endif
37772
37773 end
37774 endtask
37775
37776
37777 task slam_PhysicalOffset0_core1_thread5;
37778 input [63:0] value;
37779 reg [5:0] tid;
37780 integer junk;
37781
37782 begin
37783`ifdef AXIS_EMUL_COSIM
37784//Do Nothing
37785`else
37786`ifdef GATESIM
37787//Do Nothing
37788`else
37789`ifdef CORE_1
37790 if (`PARGS.nas_check_on) begin
37791 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
37792 tid = 5
37793; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37794 end
37795`endif
37796
37797`endif
37798
37799`endif
37800
37801 end
37802 endtask
37803
37804
37805 task slam_PhysicalOffset0_core1_thread6;
37806 input [63:0] value;
37807 reg [5:0] tid;
37808 integer junk;
37809
37810 begin
37811`ifdef AXIS_EMUL_COSIM
37812//Do Nothing
37813`else
37814`ifdef GATESIM
37815//Do Nothing
37816`else
37817`ifdef CORE_1
37818 if (`PARGS.nas_check_on) begin
37819 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
37820 tid = 6
37821; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37822 end
37823`endif
37824
37825`endif
37826
37827`endif
37828
37829 end
37830 endtask
37831
37832
37833 task slam_PhysicalOffset0_core1_thread7;
37834 input [63:0] value;
37835 reg [5:0] tid;
37836 integer junk;
37837
37838 begin
37839`ifdef AXIS_EMUL_COSIM
37840//Do Nothing
37841`else
37842`ifdef GATESIM
37843//Do Nothing
37844`else
37845`ifdef CORE_1
37846 if (`PARGS.nas_check_on) begin
37847 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
37848 tid = 7
37849; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37850 end
37851`endif
37852
37853`endif
37854
37855`endif
37856
37857 end
37858 endtask
37859
37860
37861 task slam_PhysicalOffset0_core2_thread0;
37862 input [63:0] value;
37863 reg [5:0] tid;
37864 integer junk;
37865
37866 begin
37867`ifdef AXIS_EMUL_COSIM
37868//Do Nothing
37869`else
37870`ifdef GATESIM
37871//Do Nothing
37872`else
37873`ifdef CORE_2
37874 if (`PARGS.nas_check_on) begin
37875 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
37876 tid = 0
37877; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37878 end
37879`endif
37880
37881`endif
37882
37883`endif
37884
37885 end
37886 endtask
37887
37888
37889 task slam_PhysicalOffset0_core2_thread1;
37890 input [63:0] value;
37891 reg [5:0] tid;
37892 integer junk;
37893
37894 begin
37895`ifdef AXIS_EMUL_COSIM
37896//Do Nothing
37897`else
37898`ifdef GATESIM
37899//Do Nothing
37900`else
37901`ifdef CORE_2
37902 if (`PARGS.nas_check_on) begin
37903 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
37904 tid = 1
37905; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37906 end
37907`endif
37908
37909`endif
37910
37911`endif
37912
37913 end
37914 endtask
37915
37916
37917 task slam_PhysicalOffset0_core2_thread2;
37918 input [63:0] value;
37919 reg [5:0] tid;
37920 integer junk;
37921
37922 begin
37923`ifdef AXIS_EMUL_COSIM
37924//Do Nothing
37925`else
37926`ifdef GATESIM
37927//Do Nothing
37928`else
37929`ifdef CORE_2
37930 if (`PARGS.nas_check_on) begin
37931 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
37932 tid = 2
37933; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37934 end
37935`endif
37936
37937`endif
37938
37939`endif
37940
37941 end
37942 endtask
37943
37944
37945 task slam_PhysicalOffset0_core2_thread3;
37946 input [63:0] value;
37947 reg [5:0] tid;
37948 integer junk;
37949
37950 begin
37951`ifdef AXIS_EMUL_COSIM
37952//Do Nothing
37953`else
37954`ifdef GATESIM
37955//Do Nothing
37956`else
37957`ifdef CORE_2
37958 if (`PARGS.nas_check_on) begin
37959 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
37960 tid = 3
37961; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37962 end
37963`endif
37964
37965`endif
37966
37967`endif
37968
37969 end
37970 endtask
37971
37972
37973 task slam_PhysicalOffset0_core2_thread4;
37974 input [63:0] value;
37975 reg [5:0] tid;
37976 integer junk;
37977
37978 begin
37979`ifdef AXIS_EMUL_COSIM
37980//Do Nothing
37981`else
37982`ifdef GATESIM
37983//Do Nothing
37984`else
37985`ifdef CORE_2
37986 if (`PARGS.nas_check_on) begin
37987 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
37988 tid = 4
37989; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
37990 end
37991`endif
37992
37993`endif
37994
37995`endif
37996
37997 end
37998 endtask
37999
38000
38001 task slam_PhysicalOffset0_core2_thread5;
38002 input [63:0] value;
38003 reg [5:0] tid;
38004 integer junk;
38005
38006 begin
38007`ifdef AXIS_EMUL_COSIM
38008//Do Nothing
38009`else
38010`ifdef GATESIM
38011//Do Nothing
38012`else
38013`ifdef CORE_2
38014 if (`PARGS.nas_check_on) begin
38015 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
38016 tid = 5
38017; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38018 end
38019`endif
38020
38021`endif
38022
38023`endif
38024
38025 end
38026 endtask
38027
38028
38029 task slam_PhysicalOffset0_core2_thread6;
38030 input [63:0] value;
38031 reg [5:0] tid;
38032 integer junk;
38033
38034 begin
38035`ifdef AXIS_EMUL_COSIM
38036//Do Nothing
38037`else
38038`ifdef GATESIM
38039//Do Nothing
38040`else
38041`ifdef CORE_2
38042 if (`PARGS.nas_check_on) begin
38043 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
38044 tid = 6
38045; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38046 end
38047`endif
38048
38049`endif
38050
38051`endif
38052
38053 end
38054 endtask
38055
38056
38057 task slam_PhysicalOffset0_core2_thread7;
38058 input [63:0] value;
38059 reg [5:0] tid;
38060 integer junk;
38061
38062 begin
38063`ifdef AXIS_EMUL_COSIM
38064//Do Nothing
38065`else
38066`ifdef GATESIM
38067//Do Nothing
38068`else
38069`ifdef CORE_2
38070 if (`PARGS.nas_check_on) begin
38071 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
38072 tid = 7
38073; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38074 end
38075`endif
38076
38077`endif
38078
38079`endif
38080
38081 end
38082 endtask
38083
38084
38085 task slam_PhysicalOffset0_core3_thread0;
38086 input [63:0] value;
38087 reg [5:0] tid;
38088 integer junk;
38089
38090 begin
38091`ifdef AXIS_EMUL_COSIM
38092//Do Nothing
38093`else
38094`ifdef GATESIM
38095//Do Nothing
38096`else
38097`ifdef CORE_3
38098 if (`PARGS.nas_check_on) begin
38099 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
38100 tid = 0
38101; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38102 end
38103`endif
38104
38105`endif
38106
38107`endif
38108
38109 end
38110 endtask
38111
38112
38113 task slam_PhysicalOffset0_core3_thread1;
38114 input [63:0] value;
38115 reg [5:0] tid;
38116 integer junk;
38117
38118 begin
38119`ifdef AXIS_EMUL_COSIM
38120//Do Nothing
38121`else
38122`ifdef GATESIM
38123//Do Nothing
38124`else
38125`ifdef CORE_3
38126 if (`PARGS.nas_check_on) begin
38127 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
38128 tid = 1
38129; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38130 end
38131`endif
38132
38133`endif
38134
38135`endif
38136
38137 end
38138 endtask
38139
38140
38141 task slam_PhysicalOffset0_core3_thread2;
38142 input [63:0] value;
38143 reg [5:0] tid;
38144 integer junk;
38145
38146 begin
38147`ifdef AXIS_EMUL_COSIM
38148//Do Nothing
38149`else
38150`ifdef GATESIM
38151//Do Nothing
38152`else
38153`ifdef CORE_3
38154 if (`PARGS.nas_check_on) begin
38155 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
38156 tid = 2
38157; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38158 end
38159`endif
38160
38161`endif
38162
38163`endif
38164
38165 end
38166 endtask
38167
38168
38169 task slam_PhysicalOffset0_core3_thread3;
38170 input [63:0] value;
38171 reg [5:0] tid;
38172 integer junk;
38173
38174 begin
38175`ifdef AXIS_EMUL_COSIM
38176//Do Nothing
38177`else
38178`ifdef GATESIM
38179//Do Nothing
38180`else
38181`ifdef CORE_3
38182 if (`PARGS.nas_check_on) begin
38183 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
38184 tid = 3
38185; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38186 end
38187`endif
38188
38189`endif
38190
38191`endif
38192
38193 end
38194 endtask
38195
38196
38197 task slam_PhysicalOffset0_core3_thread4;
38198 input [63:0] value;
38199 reg [5:0] tid;
38200 integer junk;
38201
38202 begin
38203`ifdef AXIS_EMUL_COSIM
38204//Do Nothing
38205`else
38206`ifdef GATESIM
38207//Do Nothing
38208`else
38209`ifdef CORE_3
38210 if (`PARGS.nas_check_on) begin
38211 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
38212 tid = 4
38213; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38214 end
38215`endif
38216
38217`endif
38218
38219`endif
38220
38221 end
38222 endtask
38223
38224
38225 task slam_PhysicalOffset0_core3_thread5;
38226 input [63:0] value;
38227 reg [5:0] tid;
38228 integer junk;
38229
38230 begin
38231`ifdef AXIS_EMUL_COSIM
38232//Do Nothing
38233`else
38234`ifdef GATESIM
38235//Do Nothing
38236`else
38237`ifdef CORE_3
38238 if (`PARGS.nas_check_on) begin
38239 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
38240 tid = 5
38241; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38242 end
38243`endif
38244
38245`endif
38246
38247`endif
38248
38249 end
38250 endtask
38251
38252
38253 task slam_PhysicalOffset0_core3_thread6;
38254 input [63:0] value;
38255 reg [5:0] tid;
38256 integer junk;
38257
38258 begin
38259`ifdef AXIS_EMUL_COSIM
38260//Do Nothing
38261`else
38262`ifdef GATESIM
38263//Do Nothing
38264`else
38265`ifdef CORE_3
38266 if (`PARGS.nas_check_on) begin
38267 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
38268 tid = 6
38269; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38270 end
38271`endif
38272
38273`endif
38274
38275`endif
38276
38277 end
38278 endtask
38279
38280
38281 task slam_PhysicalOffset0_core3_thread7;
38282 input [63:0] value;
38283 reg [5:0] tid;
38284 integer junk;
38285
38286 begin
38287`ifdef AXIS_EMUL_COSIM
38288//Do Nothing
38289`else
38290`ifdef GATESIM
38291//Do Nothing
38292`else
38293`ifdef CORE_3
38294 if (`PARGS.nas_check_on) begin
38295 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
38296 tid = 7
38297; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38298 end
38299`endif
38300
38301`endif
38302
38303`endif
38304
38305 end
38306 endtask
38307
38308
38309 task slam_PhysicalOffset0_core4_thread0;
38310 input [63:0] value;
38311 reg [5:0] tid;
38312 integer junk;
38313
38314 begin
38315`ifdef AXIS_EMUL_COSIM
38316//Do Nothing
38317`else
38318`ifdef GATESIM
38319//Do Nothing
38320`else
38321`ifdef CORE_4
38322 if (`PARGS.nas_check_on) begin
38323 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
38324 tid = 0
38325; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38326 end
38327`endif
38328
38329`endif
38330
38331`endif
38332
38333 end
38334 endtask
38335
38336
38337 task slam_PhysicalOffset0_core4_thread1;
38338 input [63:0] value;
38339 reg [5:0] tid;
38340 integer junk;
38341
38342 begin
38343`ifdef AXIS_EMUL_COSIM
38344//Do Nothing
38345`else
38346`ifdef GATESIM
38347//Do Nothing
38348`else
38349`ifdef CORE_4
38350 if (`PARGS.nas_check_on) begin
38351 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
38352 tid = 1
38353; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38354 end
38355`endif
38356
38357`endif
38358
38359`endif
38360
38361 end
38362 endtask
38363
38364
38365 task slam_PhysicalOffset0_core4_thread2;
38366 input [63:0] value;
38367 reg [5:0] tid;
38368 integer junk;
38369
38370 begin
38371`ifdef AXIS_EMUL_COSIM
38372//Do Nothing
38373`else
38374`ifdef GATESIM
38375//Do Nothing
38376`else
38377`ifdef CORE_4
38378 if (`PARGS.nas_check_on) begin
38379 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
38380 tid = 2
38381; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38382 end
38383`endif
38384
38385`endif
38386
38387`endif
38388
38389 end
38390 endtask
38391
38392
38393 task slam_PhysicalOffset0_core4_thread3;
38394 input [63:0] value;
38395 reg [5:0] tid;
38396 integer junk;
38397
38398 begin
38399`ifdef AXIS_EMUL_COSIM
38400//Do Nothing
38401`else
38402`ifdef GATESIM
38403//Do Nothing
38404`else
38405`ifdef CORE_4
38406 if (`PARGS.nas_check_on) begin
38407 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
38408 tid = 3
38409; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38410 end
38411`endif
38412
38413`endif
38414
38415`endif
38416
38417 end
38418 endtask
38419
38420
38421 task slam_PhysicalOffset0_core4_thread4;
38422 input [63:0] value;
38423 reg [5:0] tid;
38424 integer junk;
38425
38426 begin
38427`ifdef AXIS_EMUL_COSIM
38428//Do Nothing
38429`else
38430`ifdef GATESIM
38431//Do Nothing
38432`else
38433`ifdef CORE_4
38434 if (`PARGS.nas_check_on) begin
38435 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
38436 tid = 4
38437; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38438 end
38439`endif
38440
38441`endif
38442
38443`endif
38444
38445 end
38446 endtask
38447
38448
38449 task slam_PhysicalOffset0_core4_thread5;
38450 input [63:0] value;
38451 reg [5:0] tid;
38452 integer junk;
38453
38454 begin
38455`ifdef AXIS_EMUL_COSIM
38456//Do Nothing
38457`else
38458`ifdef GATESIM
38459//Do Nothing
38460`else
38461`ifdef CORE_4
38462 if (`PARGS.nas_check_on) begin
38463 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
38464 tid = 5
38465; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38466 end
38467`endif
38468
38469`endif
38470
38471`endif
38472
38473 end
38474 endtask
38475
38476
38477 task slam_PhysicalOffset0_core4_thread6;
38478 input [63:0] value;
38479 reg [5:0] tid;
38480 integer junk;
38481
38482 begin
38483`ifdef AXIS_EMUL_COSIM
38484//Do Nothing
38485`else
38486`ifdef GATESIM
38487//Do Nothing
38488`else
38489`ifdef CORE_4
38490 if (`PARGS.nas_check_on) begin
38491 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
38492 tid = 6
38493; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38494 end
38495`endif
38496
38497`endif
38498
38499`endif
38500
38501 end
38502 endtask
38503
38504
38505 task slam_PhysicalOffset0_core4_thread7;
38506 input [63:0] value;
38507 reg [5:0] tid;
38508 integer junk;
38509
38510 begin
38511`ifdef AXIS_EMUL_COSIM
38512//Do Nothing
38513`else
38514`ifdef GATESIM
38515//Do Nothing
38516`else
38517`ifdef CORE_4
38518 if (`PARGS.nas_check_on) begin
38519 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
38520 tid = 7
38521; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38522 end
38523`endif
38524
38525`endif
38526
38527`endif
38528
38529 end
38530 endtask
38531
38532
38533 task slam_PhysicalOffset0_core5_thread0;
38534 input [63:0] value;
38535 reg [5:0] tid;
38536 integer junk;
38537
38538 begin
38539`ifdef AXIS_EMUL_COSIM
38540//Do Nothing
38541`else
38542`ifdef GATESIM
38543//Do Nothing
38544`else
38545`ifdef CORE_5
38546 if (`PARGS.nas_check_on) begin
38547 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
38548 tid = 0
38549; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38550 end
38551`endif
38552
38553`endif
38554
38555`endif
38556
38557 end
38558 endtask
38559
38560
38561 task slam_PhysicalOffset0_core5_thread1;
38562 input [63:0] value;
38563 reg [5:0] tid;
38564 integer junk;
38565
38566 begin
38567`ifdef AXIS_EMUL_COSIM
38568//Do Nothing
38569`else
38570`ifdef GATESIM
38571//Do Nothing
38572`else
38573`ifdef CORE_5
38574 if (`PARGS.nas_check_on) begin
38575 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
38576 tid = 1
38577; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38578 end
38579`endif
38580
38581`endif
38582
38583`endif
38584
38585 end
38586 endtask
38587
38588
38589 task slam_PhysicalOffset0_core5_thread2;
38590 input [63:0] value;
38591 reg [5:0] tid;
38592 integer junk;
38593
38594 begin
38595`ifdef AXIS_EMUL_COSIM
38596//Do Nothing
38597`else
38598`ifdef GATESIM
38599//Do Nothing
38600`else
38601`ifdef CORE_5
38602 if (`PARGS.nas_check_on) begin
38603 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
38604 tid = 2
38605; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38606 end
38607`endif
38608
38609`endif
38610
38611`endif
38612
38613 end
38614 endtask
38615
38616
38617 task slam_PhysicalOffset0_core5_thread3;
38618 input [63:0] value;
38619 reg [5:0] tid;
38620 integer junk;
38621
38622 begin
38623`ifdef AXIS_EMUL_COSIM
38624//Do Nothing
38625`else
38626`ifdef GATESIM
38627//Do Nothing
38628`else
38629`ifdef CORE_5
38630 if (`PARGS.nas_check_on) begin
38631 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
38632 tid = 3
38633; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38634 end
38635`endif
38636
38637`endif
38638
38639`endif
38640
38641 end
38642 endtask
38643
38644
38645 task slam_PhysicalOffset0_core5_thread4;
38646 input [63:0] value;
38647 reg [5:0] tid;
38648 integer junk;
38649
38650 begin
38651`ifdef AXIS_EMUL_COSIM
38652//Do Nothing
38653`else
38654`ifdef GATESIM
38655//Do Nothing
38656`else
38657`ifdef CORE_5
38658 if (`PARGS.nas_check_on) begin
38659 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
38660 tid = 4
38661; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38662 end
38663`endif
38664
38665`endif
38666
38667`endif
38668
38669 end
38670 endtask
38671
38672
38673 task slam_PhysicalOffset0_core5_thread5;
38674 input [63:0] value;
38675 reg [5:0] tid;
38676 integer junk;
38677
38678 begin
38679`ifdef AXIS_EMUL_COSIM
38680//Do Nothing
38681`else
38682`ifdef GATESIM
38683//Do Nothing
38684`else
38685`ifdef CORE_5
38686 if (`PARGS.nas_check_on) begin
38687 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
38688 tid = 5
38689; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38690 end
38691`endif
38692
38693`endif
38694
38695`endif
38696
38697 end
38698 endtask
38699
38700
38701 task slam_PhysicalOffset0_core5_thread6;
38702 input [63:0] value;
38703 reg [5:0] tid;
38704 integer junk;
38705
38706 begin
38707`ifdef AXIS_EMUL_COSIM
38708//Do Nothing
38709`else
38710`ifdef GATESIM
38711//Do Nothing
38712`else
38713`ifdef CORE_5
38714 if (`PARGS.nas_check_on) begin
38715 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
38716 tid = 6
38717; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38718 end
38719`endif
38720
38721`endif
38722
38723`endif
38724
38725 end
38726 endtask
38727
38728
38729 task slam_PhysicalOffset0_core5_thread7;
38730 input [63:0] value;
38731 reg [5:0] tid;
38732 integer junk;
38733
38734 begin
38735`ifdef AXIS_EMUL_COSIM
38736//Do Nothing
38737`else
38738`ifdef GATESIM
38739//Do Nothing
38740`else
38741`ifdef CORE_5
38742 if (`PARGS.nas_check_on) begin
38743 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
38744 tid = 7
38745; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38746 end
38747`endif
38748
38749`endif
38750
38751`endif
38752
38753 end
38754 endtask
38755
38756
38757 task slam_PhysicalOffset0_core6_thread0;
38758 input [63:0] value;
38759 reg [5:0] tid;
38760 integer junk;
38761
38762 begin
38763`ifdef AXIS_EMUL_COSIM
38764//Do Nothing
38765`else
38766`ifdef GATESIM
38767//Do Nothing
38768`else
38769`ifdef CORE_6
38770 if (`PARGS.nas_check_on) begin
38771 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
38772 tid = 0
38773; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38774 end
38775`endif
38776
38777`endif
38778
38779`endif
38780
38781 end
38782 endtask
38783
38784
38785 task slam_PhysicalOffset0_core6_thread1;
38786 input [63:0] value;
38787 reg [5:0] tid;
38788 integer junk;
38789
38790 begin
38791`ifdef AXIS_EMUL_COSIM
38792//Do Nothing
38793`else
38794`ifdef GATESIM
38795//Do Nothing
38796`else
38797`ifdef CORE_6
38798 if (`PARGS.nas_check_on) begin
38799 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
38800 tid = 1
38801; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38802 end
38803`endif
38804
38805`endif
38806
38807`endif
38808
38809 end
38810 endtask
38811
38812
38813 task slam_PhysicalOffset0_core6_thread2;
38814 input [63:0] value;
38815 reg [5:0] tid;
38816 integer junk;
38817
38818 begin
38819`ifdef AXIS_EMUL_COSIM
38820//Do Nothing
38821`else
38822`ifdef GATESIM
38823//Do Nothing
38824`else
38825`ifdef CORE_6
38826 if (`PARGS.nas_check_on) begin
38827 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
38828 tid = 2
38829; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38830 end
38831`endif
38832
38833`endif
38834
38835`endif
38836
38837 end
38838 endtask
38839
38840
38841 task slam_PhysicalOffset0_core6_thread3;
38842 input [63:0] value;
38843 reg [5:0] tid;
38844 integer junk;
38845
38846 begin
38847`ifdef AXIS_EMUL_COSIM
38848//Do Nothing
38849`else
38850`ifdef GATESIM
38851//Do Nothing
38852`else
38853`ifdef CORE_6
38854 if (`PARGS.nas_check_on) begin
38855 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
38856 tid = 3
38857; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38858 end
38859`endif
38860
38861`endif
38862
38863`endif
38864
38865 end
38866 endtask
38867
38868
38869 task slam_PhysicalOffset0_core6_thread4;
38870 input [63:0] value;
38871 reg [5:0] tid;
38872 integer junk;
38873
38874 begin
38875`ifdef AXIS_EMUL_COSIM
38876//Do Nothing
38877`else
38878`ifdef GATESIM
38879//Do Nothing
38880`else
38881`ifdef CORE_6
38882 if (`PARGS.nas_check_on) begin
38883 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
38884 tid = 4
38885; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38886 end
38887`endif
38888
38889`endif
38890
38891`endif
38892
38893 end
38894 endtask
38895
38896
38897 task slam_PhysicalOffset0_core6_thread5;
38898 input [63:0] value;
38899 reg [5:0] tid;
38900 integer junk;
38901
38902 begin
38903`ifdef AXIS_EMUL_COSIM
38904//Do Nothing
38905`else
38906`ifdef GATESIM
38907//Do Nothing
38908`else
38909`ifdef CORE_6
38910 if (`PARGS.nas_check_on) begin
38911 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
38912 tid = 5
38913; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38914 end
38915`endif
38916
38917`endif
38918
38919`endif
38920
38921 end
38922 endtask
38923
38924
38925 task slam_PhysicalOffset0_core6_thread6;
38926 input [63:0] value;
38927 reg [5:0] tid;
38928 integer junk;
38929
38930 begin
38931`ifdef AXIS_EMUL_COSIM
38932//Do Nothing
38933`else
38934`ifdef GATESIM
38935//Do Nothing
38936`else
38937`ifdef CORE_6
38938 if (`PARGS.nas_check_on) begin
38939 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
38940 tid = 6
38941; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38942 end
38943`endif
38944
38945`endif
38946
38947`endif
38948
38949 end
38950 endtask
38951
38952
38953 task slam_PhysicalOffset0_core6_thread7;
38954 input [63:0] value;
38955 reg [5:0] tid;
38956 integer junk;
38957
38958 begin
38959`ifdef AXIS_EMUL_COSIM
38960//Do Nothing
38961`else
38962`ifdef GATESIM
38963//Do Nothing
38964`else
38965`ifdef CORE_6
38966 if (`PARGS.nas_check_on) begin
38967 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
38968 tid = 7
38969; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38970 end
38971`endif
38972
38973`endif
38974
38975`endif
38976
38977 end
38978 endtask
38979
38980
38981 task slam_PhysicalOffset0_core7_thread0;
38982 input [63:0] value;
38983 reg [5:0] tid;
38984 integer junk;
38985
38986 begin
38987`ifdef AXIS_EMUL_COSIM
38988//Do Nothing
38989`else
38990`ifdef GATESIM
38991//Do Nothing
38992`else
38993`ifdef CORE_7
38994 if (`PARGS.nas_check_on) begin
38995 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
38996 tid = 0
38997; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
38998 end
38999`endif
39000
39001`endif
39002
39003`endif
39004
39005 end
39006 endtask
39007
39008
39009 task slam_PhysicalOffset0_core7_thread1;
39010 input [63:0] value;
39011 reg [5:0] tid;
39012 integer junk;
39013
39014 begin
39015`ifdef AXIS_EMUL_COSIM
39016//Do Nothing
39017`else
39018`ifdef GATESIM
39019//Do Nothing
39020`else
39021`ifdef CORE_7
39022 if (`PARGS.nas_check_on) begin
39023 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
39024 tid = 1
39025; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39026 end
39027`endif
39028
39029`endif
39030
39031`endif
39032
39033 end
39034 endtask
39035
39036
39037 task slam_PhysicalOffset0_core7_thread2;
39038 input [63:0] value;
39039 reg [5:0] tid;
39040 integer junk;
39041
39042 begin
39043`ifdef AXIS_EMUL_COSIM
39044//Do Nothing
39045`else
39046`ifdef GATESIM
39047//Do Nothing
39048`else
39049`ifdef CORE_7
39050 if (`PARGS.nas_check_on) begin
39051 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
39052 tid = 2
39053; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39054 end
39055`endif
39056
39057`endif
39058
39059`endif
39060
39061 end
39062 endtask
39063
39064
39065 task slam_PhysicalOffset0_core7_thread3;
39066 input [63:0] value;
39067 reg [5:0] tid;
39068 integer junk;
39069
39070 begin
39071`ifdef AXIS_EMUL_COSIM
39072//Do Nothing
39073`else
39074`ifdef GATESIM
39075//Do Nothing
39076`else
39077`ifdef CORE_7
39078 if (`PARGS.nas_check_on) begin
39079 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
39080 tid = 3
39081; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39082 end
39083`endif
39084
39085`endif
39086
39087`endif
39088
39089 end
39090 endtask
39091
39092
39093 task slam_PhysicalOffset0_core7_thread4;
39094 input [63:0] value;
39095 reg [5:0] tid;
39096 integer junk;
39097
39098 begin
39099`ifdef AXIS_EMUL_COSIM
39100//Do Nothing
39101`else
39102`ifdef GATESIM
39103//Do Nothing
39104`else
39105`ifdef CORE_7
39106 if (`PARGS.nas_check_on) begin
39107 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
39108 tid = 4
39109; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39110 end
39111`endif
39112
39113`endif
39114
39115`endif
39116
39117 end
39118 endtask
39119
39120
39121 task slam_PhysicalOffset0_core7_thread5;
39122 input [63:0] value;
39123 reg [5:0] tid;
39124 integer junk;
39125
39126 begin
39127`ifdef AXIS_EMUL_COSIM
39128//Do Nothing
39129`else
39130`ifdef GATESIM
39131//Do Nothing
39132`else
39133`ifdef CORE_7
39134 if (`PARGS.nas_check_on) begin
39135 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
39136 tid = 5
39137; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39138 end
39139`endif
39140
39141`endif
39142
39143`endif
39144
39145 end
39146 endtask
39147
39148
39149 task slam_PhysicalOffset0_core7_thread6;
39150 input [63:0] value;
39151 reg [5:0] tid;
39152 integer junk;
39153
39154 begin
39155`ifdef AXIS_EMUL_COSIM
39156//Do Nothing
39157`else
39158`ifdef GATESIM
39159//Do Nothing
39160`else
39161`ifdef CORE_7
39162 if (`PARGS.nas_check_on) begin
39163 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
39164 tid = 6
39165; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39166 end
39167`endif
39168
39169`endif
39170
39171`endif
39172
39173 end
39174 endtask
39175
39176
39177 task slam_PhysicalOffset0_core7_thread7;
39178 input [63:0] value;
39179 reg [5:0] tid;
39180 integer junk;
39181
39182 begin
39183`ifdef AXIS_EMUL_COSIM
39184//Do Nothing
39185`else
39186`ifdef GATESIM
39187//Do Nothing
39188`else
39189`ifdef CORE_7
39190 if (`PARGS.nas_check_on) begin
39191 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
39192 tid = 7
39193; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h208, value);
39194 end
39195`endif
39196
39197`endif
39198
39199`endif
39200
39201 end
39202 endtask
39203
39204
39205 task slam_PhysicalOffset1_core0_thread0;
39206 input [63:0] value;
39207 reg [5:0] tid;
39208 integer junk;
39209
39210 begin
39211`ifdef AXIS_EMUL_COSIM
39212//Do Nothing
39213`else
39214`ifdef GATESIM
39215//Do Nothing
39216`else
39217`ifdef CORE_0
39218 if (`PARGS.nas_check_on) begin
39219 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
39220 tid = 0
39221; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39222 end
39223`endif
39224
39225`endif
39226
39227`endif
39228
39229 end
39230 endtask
39231
39232
39233 task slam_PhysicalOffset1_core0_thread1;
39234 input [63:0] value;
39235 reg [5:0] tid;
39236 integer junk;
39237
39238 begin
39239`ifdef AXIS_EMUL_COSIM
39240//Do Nothing
39241`else
39242`ifdef GATESIM
39243//Do Nothing
39244`else
39245`ifdef CORE_0
39246 if (`PARGS.nas_check_on) begin
39247 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
39248 tid = 1
39249; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39250 end
39251`endif
39252
39253`endif
39254
39255`endif
39256
39257 end
39258 endtask
39259
39260
39261 task slam_PhysicalOffset1_core0_thread2;
39262 input [63:0] value;
39263 reg [5:0] tid;
39264 integer junk;
39265
39266 begin
39267`ifdef AXIS_EMUL_COSIM
39268//Do Nothing
39269`else
39270`ifdef GATESIM
39271//Do Nothing
39272`else
39273`ifdef CORE_0
39274 if (`PARGS.nas_check_on) begin
39275 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
39276 tid = 2
39277; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39278 end
39279`endif
39280
39281`endif
39282
39283`endif
39284
39285 end
39286 endtask
39287
39288
39289 task slam_PhysicalOffset1_core0_thread3;
39290 input [63:0] value;
39291 reg [5:0] tid;
39292 integer junk;
39293
39294 begin
39295`ifdef AXIS_EMUL_COSIM
39296//Do Nothing
39297`else
39298`ifdef GATESIM
39299//Do Nothing
39300`else
39301`ifdef CORE_0
39302 if (`PARGS.nas_check_on) begin
39303 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
39304 tid = 3
39305; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39306 end
39307`endif
39308
39309`endif
39310
39311`endif
39312
39313 end
39314 endtask
39315
39316
39317 task slam_PhysicalOffset1_core0_thread4;
39318 input [63:0] value;
39319 reg [5:0] tid;
39320 integer junk;
39321
39322 begin
39323`ifdef AXIS_EMUL_COSIM
39324//Do Nothing
39325`else
39326`ifdef GATESIM
39327//Do Nothing
39328`else
39329`ifdef CORE_0
39330 if (`PARGS.nas_check_on) begin
39331 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
39332 tid = 4
39333; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39334 end
39335`endif
39336
39337`endif
39338
39339`endif
39340
39341 end
39342 endtask
39343
39344
39345 task slam_PhysicalOffset1_core0_thread5;
39346 input [63:0] value;
39347 reg [5:0] tid;
39348 integer junk;
39349
39350 begin
39351`ifdef AXIS_EMUL_COSIM
39352//Do Nothing
39353`else
39354`ifdef GATESIM
39355//Do Nothing
39356`else
39357`ifdef CORE_0
39358 if (`PARGS.nas_check_on) begin
39359 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
39360 tid = 5
39361; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39362 end
39363`endif
39364
39365`endif
39366
39367`endif
39368
39369 end
39370 endtask
39371
39372
39373 task slam_PhysicalOffset1_core0_thread6;
39374 input [63:0] value;
39375 reg [5:0] tid;
39376 integer junk;
39377
39378 begin
39379`ifdef AXIS_EMUL_COSIM
39380//Do Nothing
39381`else
39382`ifdef GATESIM
39383//Do Nothing
39384`else
39385`ifdef CORE_0
39386 if (`PARGS.nas_check_on) begin
39387 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
39388 tid = 6
39389; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39390 end
39391`endif
39392
39393`endif
39394
39395`endif
39396
39397 end
39398 endtask
39399
39400
39401 task slam_PhysicalOffset1_core0_thread7;
39402 input [63:0] value;
39403 reg [5:0] tid;
39404 integer junk;
39405
39406 begin
39407`ifdef AXIS_EMUL_COSIM
39408//Do Nothing
39409`else
39410`ifdef GATESIM
39411//Do Nothing
39412`else
39413`ifdef CORE_0
39414 if (`PARGS.nas_check_on) begin
39415 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
39416 tid = 7
39417; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39418 end
39419`endif
39420
39421`endif
39422
39423`endif
39424
39425 end
39426 endtask
39427
39428
39429 task slam_PhysicalOffset1_core1_thread0;
39430 input [63:0] value;
39431 reg [5:0] tid;
39432 integer junk;
39433
39434 begin
39435`ifdef AXIS_EMUL_COSIM
39436//Do Nothing
39437`else
39438`ifdef GATESIM
39439//Do Nothing
39440`else
39441`ifdef CORE_1
39442 if (`PARGS.nas_check_on) begin
39443 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
39444 tid = 0
39445; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39446 end
39447`endif
39448
39449`endif
39450
39451`endif
39452
39453 end
39454 endtask
39455
39456
39457 task slam_PhysicalOffset1_core1_thread1;
39458 input [63:0] value;
39459 reg [5:0] tid;
39460 integer junk;
39461
39462 begin
39463`ifdef AXIS_EMUL_COSIM
39464//Do Nothing
39465`else
39466`ifdef GATESIM
39467//Do Nothing
39468`else
39469`ifdef CORE_1
39470 if (`PARGS.nas_check_on) begin
39471 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
39472 tid = 1
39473; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39474 end
39475`endif
39476
39477`endif
39478
39479`endif
39480
39481 end
39482 endtask
39483
39484
39485 task slam_PhysicalOffset1_core1_thread2;
39486 input [63:0] value;
39487 reg [5:0] tid;
39488 integer junk;
39489
39490 begin
39491`ifdef AXIS_EMUL_COSIM
39492//Do Nothing
39493`else
39494`ifdef GATESIM
39495//Do Nothing
39496`else
39497`ifdef CORE_1
39498 if (`PARGS.nas_check_on) begin
39499 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
39500 tid = 2
39501; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39502 end
39503`endif
39504
39505`endif
39506
39507`endif
39508
39509 end
39510 endtask
39511
39512
39513 task slam_PhysicalOffset1_core1_thread3;
39514 input [63:0] value;
39515 reg [5:0] tid;
39516 integer junk;
39517
39518 begin
39519`ifdef AXIS_EMUL_COSIM
39520//Do Nothing
39521`else
39522`ifdef GATESIM
39523//Do Nothing
39524`else
39525`ifdef CORE_1
39526 if (`PARGS.nas_check_on) begin
39527 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
39528 tid = 3
39529; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39530 end
39531`endif
39532
39533`endif
39534
39535`endif
39536
39537 end
39538 endtask
39539
39540
39541 task slam_PhysicalOffset1_core1_thread4;
39542 input [63:0] value;
39543 reg [5:0] tid;
39544 integer junk;
39545
39546 begin
39547`ifdef AXIS_EMUL_COSIM
39548//Do Nothing
39549`else
39550`ifdef GATESIM
39551//Do Nothing
39552`else
39553`ifdef CORE_1
39554 if (`PARGS.nas_check_on) begin
39555 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
39556 tid = 4
39557; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39558 end
39559`endif
39560
39561`endif
39562
39563`endif
39564
39565 end
39566 endtask
39567
39568
39569 task slam_PhysicalOffset1_core1_thread5;
39570 input [63:0] value;
39571 reg [5:0] tid;
39572 integer junk;
39573
39574 begin
39575`ifdef AXIS_EMUL_COSIM
39576//Do Nothing
39577`else
39578`ifdef GATESIM
39579//Do Nothing
39580`else
39581`ifdef CORE_1
39582 if (`PARGS.nas_check_on) begin
39583 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
39584 tid = 5
39585; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39586 end
39587`endif
39588
39589`endif
39590
39591`endif
39592
39593 end
39594 endtask
39595
39596
39597 task slam_PhysicalOffset1_core1_thread6;
39598 input [63:0] value;
39599 reg [5:0] tid;
39600 integer junk;
39601
39602 begin
39603`ifdef AXIS_EMUL_COSIM
39604//Do Nothing
39605`else
39606`ifdef GATESIM
39607//Do Nothing
39608`else
39609`ifdef CORE_1
39610 if (`PARGS.nas_check_on) begin
39611 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
39612 tid = 6
39613; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39614 end
39615`endif
39616
39617`endif
39618
39619`endif
39620
39621 end
39622 endtask
39623
39624
39625 task slam_PhysicalOffset1_core1_thread7;
39626 input [63:0] value;
39627 reg [5:0] tid;
39628 integer junk;
39629
39630 begin
39631`ifdef AXIS_EMUL_COSIM
39632//Do Nothing
39633`else
39634`ifdef GATESIM
39635//Do Nothing
39636`else
39637`ifdef CORE_1
39638 if (`PARGS.nas_check_on) begin
39639 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
39640 tid = 7
39641; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39642 end
39643`endif
39644
39645`endif
39646
39647`endif
39648
39649 end
39650 endtask
39651
39652
39653 task slam_PhysicalOffset1_core2_thread0;
39654 input [63:0] value;
39655 reg [5:0] tid;
39656 integer junk;
39657
39658 begin
39659`ifdef AXIS_EMUL_COSIM
39660//Do Nothing
39661`else
39662`ifdef GATESIM
39663//Do Nothing
39664`else
39665`ifdef CORE_2
39666 if (`PARGS.nas_check_on) begin
39667 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
39668 tid = 0
39669; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39670 end
39671`endif
39672
39673`endif
39674
39675`endif
39676
39677 end
39678 endtask
39679
39680
39681 task slam_PhysicalOffset1_core2_thread1;
39682 input [63:0] value;
39683 reg [5:0] tid;
39684 integer junk;
39685
39686 begin
39687`ifdef AXIS_EMUL_COSIM
39688//Do Nothing
39689`else
39690`ifdef GATESIM
39691//Do Nothing
39692`else
39693`ifdef CORE_2
39694 if (`PARGS.nas_check_on) begin
39695 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
39696 tid = 1
39697; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39698 end
39699`endif
39700
39701`endif
39702
39703`endif
39704
39705 end
39706 endtask
39707
39708
39709 task slam_PhysicalOffset1_core2_thread2;
39710 input [63:0] value;
39711 reg [5:0] tid;
39712 integer junk;
39713
39714 begin
39715`ifdef AXIS_EMUL_COSIM
39716//Do Nothing
39717`else
39718`ifdef GATESIM
39719//Do Nothing
39720`else
39721`ifdef CORE_2
39722 if (`PARGS.nas_check_on) begin
39723 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
39724 tid = 2
39725; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39726 end
39727`endif
39728
39729`endif
39730
39731`endif
39732
39733 end
39734 endtask
39735
39736
39737 task slam_PhysicalOffset1_core2_thread3;
39738 input [63:0] value;
39739 reg [5:0] tid;
39740 integer junk;
39741
39742 begin
39743`ifdef AXIS_EMUL_COSIM
39744//Do Nothing
39745`else
39746`ifdef GATESIM
39747//Do Nothing
39748`else
39749`ifdef CORE_2
39750 if (`PARGS.nas_check_on) begin
39751 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
39752 tid = 3
39753; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39754 end
39755`endif
39756
39757`endif
39758
39759`endif
39760
39761 end
39762 endtask
39763
39764
39765 task slam_PhysicalOffset1_core2_thread4;
39766 input [63:0] value;
39767 reg [5:0] tid;
39768 integer junk;
39769
39770 begin
39771`ifdef AXIS_EMUL_COSIM
39772//Do Nothing
39773`else
39774`ifdef GATESIM
39775//Do Nothing
39776`else
39777`ifdef CORE_2
39778 if (`PARGS.nas_check_on) begin
39779 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
39780 tid = 4
39781; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39782 end
39783`endif
39784
39785`endif
39786
39787`endif
39788
39789 end
39790 endtask
39791
39792
39793 task slam_PhysicalOffset1_core2_thread5;
39794 input [63:0] value;
39795 reg [5:0] tid;
39796 integer junk;
39797
39798 begin
39799`ifdef AXIS_EMUL_COSIM
39800//Do Nothing
39801`else
39802`ifdef GATESIM
39803//Do Nothing
39804`else
39805`ifdef CORE_2
39806 if (`PARGS.nas_check_on) begin
39807 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
39808 tid = 5
39809; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39810 end
39811`endif
39812
39813`endif
39814
39815`endif
39816
39817 end
39818 endtask
39819
39820
39821 task slam_PhysicalOffset1_core2_thread6;
39822 input [63:0] value;
39823 reg [5:0] tid;
39824 integer junk;
39825
39826 begin
39827`ifdef AXIS_EMUL_COSIM
39828//Do Nothing
39829`else
39830`ifdef GATESIM
39831//Do Nothing
39832`else
39833`ifdef CORE_2
39834 if (`PARGS.nas_check_on) begin
39835 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
39836 tid = 6
39837; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39838 end
39839`endif
39840
39841`endif
39842
39843`endif
39844
39845 end
39846 endtask
39847
39848
39849 task slam_PhysicalOffset1_core2_thread7;
39850 input [63:0] value;
39851 reg [5:0] tid;
39852 integer junk;
39853
39854 begin
39855`ifdef AXIS_EMUL_COSIM
39856//Do Nothing
39857`else
39858`ifdef GATESIM
39859//Do Nothing
39860`else
39861`ifdef CORE_2
39862 if (`PARGS.nas_check_on) begin
39863 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
39864 tid = 7
39865; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39866 end
39867`endif
39868
39869`endif
39870
39871`endif
39872
39873 end
39874 endtask
39875
39876
39877 task slam_PhysicalOffset1_core3_thread0;
39878 input [63:0] value;
39879 reg [5:0] tid;
39880 integer junk;
39881
39882 begin
39883`ifdef AXIS_EMUL_COSIM
39884//Do Nothing
39885`else
39886`ifdef GATESIM
39887//Do Nothing
39888`else
39889`ifdef CORE_3
39890 if (`PARGS.nas_check_on) begin
39891 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
39892 tid = 0
39893; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39894 end
39895`endif
39896
39897`endif
39898
39899`endif
39900
39901 end
39902 endtask
39903
39904
39905 task slam_PhysicalOffset1_core3_thread1;
39906 input [63:0] value;
39907 reg [5:0] tid;
39908 integer junk;
39909
39910 begin
39911`ifdef AXIS_EMUL_COSIM
39912//Do Nothing
39913`else
39914`ifdef GATESIM
39915//Do Nothing
39916`else
39917`ifdef CORE_3
39918 if (`PARGS.nas_check_on) begin
39919 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
39920 tid = 1
39921; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39922 end
39923`endif
39924
39925`endif
39926
39927`endif
39928
39929 end
39930 endtask
39931
39932
39933 task slam_PhysicalOffset1_core3_thread2;
39934 input [63:0] value;
39935 reg [5:0] tid;
39936 integer junk;
39937
39938 begin
39939`ifdef AXIS_EMUL_COSIM
39940//Do Nothing
39941`else
39942`ifdef GATESIM
39943//Do Nothing
39944`else
39945`ifdef CORE_3
39946 if (`PARGS.nas_check_on) begin
39947 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
39948 tid = 2
39949; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39950 end
39951`endif
39952
39953`endif
39954
39955`endif
39956
39957 end
39958 endtask
39959
39960
39961 task slam_PhysicalOffset1_core3_thread3;
39962 input [63:0] value;
39963 reg [5:0] tid;
39964 integer junk;
39965
39966 begin
39967`ifdef AXIS_EMUL_COSIM
39968//Do Nothing
39969`else
39970`ifdef GATESIM
39971//Do Nothing
39972`else
39973`ifdef CORE_3
39974 if (`PARGS.nas_check_on) begin
39975 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
39976 tid = 3
39977; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
39978 end
39979`endif
39980
39981`endif
39982
39983`endif
39984
39985 end
39986 endtask
39987
39988
39989 task slam_PhysicalOffset1_core3_thread4;
39990 input [63:0] value;
39991 reg [5:0] tid;
39992 integer junk;
39993
39994 begin
39995`ifdef AXIS_EMUL_COSIM
39996//Do Nothing
39997`else
39998`ifdef GATESIM
39999//Do Nothing
40000`else
40001`ifdef CORE_3
40002 if (`PARGS.nas_check_on) begin
40003 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
40004 tid = 4
40005; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40006 end
40007`endif
40008
40009`endif
40010
40011`endif
40012
40013 end
40014 endtask
40015
40016
40017 task slam_PhysicalOffset1_core3_thread5;
40018 input [63:0] value;
40019 reg [5:0] tid;
40020 integer junk;
40021
40022 begin
40023`ifdef AXIS_EMUL_COSIM
40024//Do Nothing
40025`else
40026`ifdef GATESIM
40027//Do Nothing
40028`else
40029`ifdef CORE_3
40030 if (`PARGS.nas_check_on) begin
40031 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
40032 tid = 5
40033; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40034 end
40035`endif
40036
40037`endif
40038
40039`endif
40040
40041 end
40042 endtask
40043
40044
40045 task slam_PhysicalOffset1_core3_thread6;
40046 input [63:0] value;
40047 reg [5:0] tid;
40048 integer junk;
40049
40050 begin
40051`ifdef AXIS_EMUL_COSIM
40052//Do Nothing
40053`else
40054`ifdef GATESIM
40055//Do Nothing
40056`else
40057`ifdef CORE_3
40058 if (`PARGS.nas_check_on) begin
40059 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
40060 tid = 6
40061; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40062 end
40063`endif
40064
40065`endif
40066
40067`endif
40068
40069 end
40070 endtask
40071
40072
40073 task slam_PhysicalOffset1_core3_thread7;
40074 input [63:0] value;
40075 reg [5:0] tid;
40076 integer junk;
40077
40078 begin
40079`ifdef AXIS_EMUL_COSIM
40080//Do Nothing
40081`else
40082`ifdef GATESIM
40083//Do Nothing
40084`else
40085`ifdef CORE_3
40086 if (`PARGS.nas_check_on) begin
40087 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
40088 tid = 7
40089; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40090 end
40091`endif
40092
40093`endif
40094
40095`endif
40096
40097 end
40098 endtask
40099
40100
40101 task slam_PhysicalOffset1_core4_thread0;
40102 input [63:0] value;
40103 reg [5:0] tid;
40104 integer junk;
40105
40106 begin
40107`ifdef AXIS_EMUL_COSIM
40108//Do Nothing
40109`else
40110`ifdef GATESIM
40111//Do Nothing
40112`else
40113`ifdef CORE_4
40114 if (`PARGS.nas_check_on) begin
40115 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
40116 tid = 0
40117; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40118 end
40119`endif
40120
40121`endif
40122
40123`endif
40124
40125 end
40126 endtask
40127
40128
40129 task slam_PhysicalOffset1_core4_thread1;
40130 input [63:0] value;
40131 reg [5:0] tid;
40132 integer junk;
40133
40134 begin
40135`ifdef AXIS_EMUL_COSIM
40136//Do Nothing
40137`else
40138`ifdef GATESIM
40139//Do Nothing
40140`else
40141`ifdef CORE_4
40142 if (`PARGS.nas_check_on) begin
40143 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
40144 tid = 1
40145; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40146 end
40147`endif
40148
40149`endif
40150
40151`endif
40152
40153 end
40154 endtask
40155
40156
40157 task slam_PhysicalOffset1_core4_thread2;
40158 input [63:0] value;
40159 reg [5:0] tid;
40160 integer junk;
40161
40162 begin
40163`ifdef AXIS_EMUL_COSIM
40164//Do Nothing
40165`else
40166`ifdef GATESIM
40167//Do Nothing
40168`else
40169`ifdef CORE_4
40170 if (`PARGS.nas_check_on) begin
40171 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
40172 tid = 2
40173; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40174 end
40175`endif
40176
40177`endif
40178
40179`endif
40180
40181 end
40182 endtask
40183
40184
40185 task slam_PhysicalOffset1_core4_thread3;
40186 input [63:0] value;
40187 reg [5:0] tid;
40188 integer junk;
40189
40190 begin
40191`ifdef AXIS_EMUL_COSIM
40192//Do Nothing
40193`else
40194`ifdef GATESIM
40195//Do Nothing
40196`else
40197`ifdef CORE_4
40198 if (`PARGS.nas_check_on) begin
40199 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
40200 tid = 3
40201; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40202 end
40203`endif
40204
40205`endif
40206
40207`endif
40208
40209 end
40210 endtask
40211
40212
40213 task slam_PhysicalOffset1_core4_thread4;
40214 input [63:0] value;
40215 reg [5:0] tid;
40216 integer junk;
40217
40218 begin
40219`ifdef AXIS_EMUL_COSIM
40220//Do Nothing
40221`else
40222`ifdef GATESIM
40223//Do Nothing
40224`else
40225`ifdef CORE_4
40226 if (`PARGS.nas_check_on) begin
40227 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
40228 tid = 4
40229; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40230 end
40231`endif
40232
40233`endif
40234
40235`endif
40236
40237 end
40238 endtask
40239
40240
40241 task slam_PhysicalOffset1_core4_thread5;
40242 input [63:0] value;
40243 reg [5:0] tid;
40244 integer junk;
40245
40246 begin
40247`ifdef AXIS_EMUL_COSIM
40248//Do Nothing
40249`else
40250`ifdef GATESIM
40251//Do Nothing
40252`else
40253`ifdef CORE_4
40254 if (`PARGS.nas_check_on) begin
40255 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
40256 tid = 5
40257; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40258 end
40259`endif
40260
40261`endif
40262
40263`endif
40264
40265 end
40266 endtask
40267
40268
40269 task slam_PhysicalOffset1_core4_thread6;
40270 input [63:0] value;
40271 reg [5:0] tid;
40272 integer junk;
40273
40274 begin
40275`ifdef AXIS_EMUL_COSIM
40276//Do Nothing
40277`else
40278`ifdef GATESIM
40279//Do Nothing
40280`else
40281`ifdef CORE_4
40282 if (`PARGS.nas_check_on) begin
40283 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
40284 tid = 6
40285; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40286 end
40287`endif
40288
40289`endif
40290
40291`endif
40292
40293 end
40294 endtask
40295
40296
40297 task slam_PhysicalOffset1_core4_thread7;
40298 input [63:0] value;
40299 reg [5:0] tid;
40300 integer junk;
40301
40302 begin
40303`ifdef AXIS_EMUL_COSIM
40304//Do Nothing
40305`else
40306`ifdef GATESIM
40307//Do Nothing
40308`else
40309`ifdef CORE_4
40310 if (`PARGS.nas_check_on) begin
40311 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
40312 tid = 7
40313; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40314 end
40315`endif
40316
40317`endif
40318
40319`endif
40320
40321 end
40322 endtask
40323
40324
40325 task slam_PhysicalOffset1_core5_thread0;
40326 input [63:0] value;
40327 reg [5:0] tid;
40328 integer junk;
40329
40330 begin
40331`ifdef AXIS_EMUL_COSIM
40332//Do Nothing
40333`else
40334`ifdef GATESIM
40335//Do Nothing
40336`else
40337`ifdef CORE_5
40338 if (`PARGS.nas_check_on) begin
40339 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
40340 tid = 0
40341; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40342 end
40343`endif
40344
40345`endif
40346
40347`endif
40348
40349 end
40350 endtask
40351
40352
40353 task slam_PhysicalOffset1_core5_thread1;
40354 input [63:0] value;
40355 reg [5:0] tid;
40356 integer junk;
40357
40358 begin
40359`ifdef AXIS_EMUL_COSIM
40360//Do Nothing
40361`else
40362`ifdef GATESIM
40363//Do Nothing
40364`else
40365`ifdef CORE_5
40366 if (`PARGS.nas_check_on) begin
40367 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
40368 tid = 1
40369; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40370 end
40371`endif
40372
40373`endif
40374
40375`endif
40376
40377 end
40378 endtask
40379
40380
40381 task slam_PhysicalOffset1_core5_thread2;
40382 input [63:0] value;
40383 reg [5:0] tid;
40384 integer junk;
40385
40386 begin
40387`ifdef AXIS_EMUL_COSIM
40388//Do Nothing
40389`else
40390`ifdef GATESIM
40391//Do Nothing
40392`else
40393`ifdef CORE_5
40394 if (`PARGS.nas_check_on) begin
40395 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
40396 tid = 2
40397; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40398 end
40399`endif
40400
40401`endif
40402
40403`endif
40404
40405 end
40406 endtask
40407
40408
40409 task slam_PhysicalOffset1_core5_thread3;
40410 input [63:0] value;
40411 reg [5:0] tid;
40412 integer junk;
40413
40414 begin
40415`ifdef AXIS_EMUL_COSIM
40416//Do Nothing
40417`else
40418`ifdef GATESIM
40419//Do Nothing
40420`else
40421`ifdef CORE_5
40422 if (`PARGS.nas_check_on) begin
40423 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
40424 tid = 3
40425; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40426 end
40427`endif
40428
40429`endif
40430
40431`endif
40432
40433 end
40434 endtask
40435
40436
40437 task slam_PhysicalOffset1_core5_thread4;
40438 input [63:0] value;
40439 reg [5:0] tid;
40440 integer junk;
40441
40442 begin
40443`ifdef AXIS_EMUL_COSIM
40444//Do Nothing
40445`else
40446`ifdef GATESIM
40447//Do Nothing
40448`else
40449`ifdef CORE_5
40450 if (`PARGS.nas_check_on) begin
40451 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
40452 tid = 4
40453; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40454 end
40455`endif
40456
40457`endif
40458
40459`endif
40460
40461 end
40462 endtask
40463
40464
40465 task slam_PhysicalOffset1_core5_thread5;
40466 input [63:0] value;
40467 reg [5:0] tid;
40468 integer junk;
40469
40470 begin
40471`ifdef AXIS_EMUL_COSIM
40472//Do Nothing
40473`else
40474`ifdef GATESIM
40475//Do Nothing
40476`else
40477`ifdef CORE_5
40478 if (`PARGS.nas_check_on) begin
40479 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
40480 tid = 5
40481; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40482 end
40483`endif
40484
40485`endif
40486
40487`endif
40488
40489 end
40490 endtask
40491
40492
40493 task slam_PhysicalOffset1_core5_thread6;
40494 input [63:0] value;
40495 reg [5:0] tid;
40496 integer junk;
40497
40498 begin
40499`ifdef AXIS_EMUL_COSIM
40500//Do Nothing
40501`else
40502`ifdef GATESIM
40503//Do Nothing
40504`else
40505`ifdef CORE_5
40506 if (`PARGS.nas_check_on) begin
40507 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
40508 tid = 6
40509; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40510 end
40511`endif
40512
40513`endif
40514
40515`endif
40516
40517 end
40518 endtask
40519
40520
40521 task slam_PhysicalOffset1_core5_thread7;
40522 input [63:0] value;
40523 reg [5:0] tid;
40524 integer junk;
40525
40526 begin
40527`ifdef AXIS_EMUL_COSIM
40528//Do Nothing
40529`else
40530`ifdef GATESIM
40531//Do Nothing
40532`else
40533`ifdef CORE_5
40534 if (`PARGS.nas_check_on) begin
40535 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
40536 tid = 7
40537; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40538 end
40539`endif
40540
40541`endif
40542
40543`endif
40544
40545 end
40546 endtask
40547
40548
40549 task slam_PhysicalOffset1_core6_thread0;
40550 input [63:0] value;
40551 reg [5:0] tid;
40552 integer junk;
40553
40554 begin
40555`ifdef AXIS_EMUL_COSIM
40556//Do Nothing
40557`else
40558`ifdef GATESIM
40559//Do Nothing
40560`else
40561`ifdef CORE_6
40562 if (`PARGS.nas_check_on) begin
40563 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
40564 tid = 0
40565; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40566 end
40567`endif
40568
40569`endif
40570
40571`endif
40572
40573 end
40574 endtask
40575
40576
40577 task slam_PhysicalOffset1_core6_thread1;
40578 input [63:0] value;
40579 reg [5:0] tid;
40580 integer junk;
40581
40582 begin
40583`ifdef AXIS_EMUL_COSIM
40584//Do Nothing
40585`else
40586`ifdef GATESIM
40587//Do Nothing
40588`else
40589`ifdef CORE_6
40590 if (`PARGS.nas_check_on) begin
40591 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
40592 tid = 1
40593; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40594 end
40595`endif
40596
40597`endif
40598
40599`endif
40600
40601 end
40602 endtask
40603
40604
40605 task slam_PhysicalOffset1_core6_thread2;
40606 input [63:0] value;
40607 reg [5:0] tid;
40608 integer junk;
40609
40610 begin
40611`ifdef AXIS_EMUL_COSIM
40612//Do Nothing
40613`else
40614`ifdef GATESIM
40615//Do Nothing
40616`else
40617`ifdef CORE_6
40618 if (`PARGS.nas_check_on) begin
40619 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
40620 tid = 2
40621; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40622 end
40623`endif
40624
40625`endif
40626
40627`endif
40628
40629 end
40630 endtask
40631
40632
40633 task slam_PhysicalOffset1_core6_thread3;
40634 input [63:0] value;
40635 reg [5:0] tid;
40636 integer junk;
40637
40638 begin
40639`ifdef AXIS_EMUL_COSIM
40640//Do Nothing
40641`else
40642`ifdef GATESIM
40643//Do Nothing
40644`else
40645`ifdef CORE_6
40646 if (`PARGS.nas_check_on) begin
40647 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
40648 tid = 3
40649; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40650 end
40651`endif
40652
40653`endif
40654
40655`endif
40656
40657 end
40658 endtask
40659
40660
40661 task slam_PhysicalOffset1_core6_thread4;
40662 input [63:0] value;
40663 reg [5:0] tid;
40664 integer junk;
40665
40666 begin
40667`ifdef AXIS_EMUL_COSIM
40668//Do Nothing
40669`else
40670`ifdef GATESIM
40671//Do Nothing
40672`else
40673`ifdef CORE_6
40674 if (`PARGS.nas_check_on) begin
40675 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
40676 tid = 4
40677; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40678 end
40679`endif
40680
40681`endif
40682
40683`endif
40684
40685 end
40686 endtask
40687
40688
40689 task slam_PhysicalOffset1_core6_thread5;
40690 input [63:0] value;
40691 reg [5:0] tid;
40692 integer junk;
40693
40694 begin
40695`ifdef AXIS_EMUL_COSIM
40696//Do Nothing
40697`else
40698`ifdef GATESIM
40699//Do Nothing
40700`else
40701`ifdef CORE_6
40702 if (`PARGS.nas_check_on) begin
40703 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
40704 tid = 5
40705; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40706 end
40707`endif
40708
40709`endif
40710
40711`endif
40712
40713 end
40714 endtask
40715
40716
40717 task slam_PhysicalOffset1_core6_thread6;
40718 input [63:0] value;
40719 reg [5:0] tid;
40720 integer junk;
40721
40722 begin
40723`ifdef AXIS_EMUL_COSIM
40724//Do Nothing
40725`else
40726`ifdef GATESIM
40727//Do Nothing
40728`else
40729`ifdef CORE_6
40730 if (`PARGS.nas_check_on) begin
40731 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
40732 tid = 6
40733; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40734 end
40735`endif
40736
40737`endif
40738
40739`endif
40740
40741 end
40742 endtask
40743
40744
40745 task slam_PhysicalOffset1_core6_thread7;
40746 input [63:0] value;
40747 reg [5:0] tid;
40748 integer junk;
40749
40750 begin
40751`ifdef AXIS_EMUL_COSIM
40752//Do Nothing
40753`else
40754`ifdef GATESIM
40755//Do Nothing
40756`else
40757`ifdef CORE_6
40758 if (`PARGS.nas_check_on) begin
40759 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
40760 tid = 7
40761; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40762 end
40763`endif
40764
40765`endif
40766
40767`endif
40768
40769 end
40770 endtask
40771
40772
40773 task slam_PhysicalOffset1_core7_thread0;
40774 input [63:0] value;
40775 reg [5:0] tid;
40776 integer junk;
40777
40778 begin
40779`ifdef AXIS_EMUL_COSIM
40780//Do Nothing
40781`else
40782`ifdef GATESIM
40783//Do Nothing
40784`else
40785`ifdef CORE_7
40786 if (`PARGS.nas_check_on) begin
40787 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
40788 tid = 0
40789; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40790 end
40791`endif
40792
40793`endif
40794
40795`endif
40796
40797 end
40798 endtask
40799
40800
40801 task slam_PhysicalOffset1_core7_thread1;
40802 input [63:0] value;
40803 reg [5:0] tid;
40804 integer junk;
40805
40806 begin
40807`ifdef AXIS_EMUL_COSIM
40808//Do Nothing
40809`else
40810`ifdef GATESIM
40811//Do Nothing
40812`else
40813`ifdef CORE_7
40814 if (`PARGS.nas_check_on) begin
40815 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
40816 tid = 1
40817; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40818 end
40819`endif
40820
40821`endif
40822
40823`endif
40824
40825 end
40826 endtask
40827
40828
40829 task slam_PhysicalOffset1_core7_thread2;
40830 input [63:0] value;
40831 reg [5:0] tid;
40832 integer junk;
40833
40834 begin
40835`ifdef AXIS_EMUL_COSIM
40836//Do Nothing
40837`else
40838`ifdef GATESIM
40839//Do Nothing
40840`else
40841`ifdef CORE_7
40842 if (`PARGS.nas_check_on) begin
40843 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
40844 tid = 2
40845; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40846 end
40847`endif
40848
40849`endif
40850
40851`endif
40852
40853 end
40854 endtask
40855
40856
40857 task slam_PhysicalOffset1_core7_thread3;
40858 input [63:0] value;
40859 reg [5:0] tid;
40860 integer junk;
40861
40862 begin
40863`ifdef AXIS_EMUL_COSIM
40864//Do Nothing
40865`else
40866`ifdef GATESIM
40867//Do Nothing
40868`else
40869`ifdef CORE_7
40870 if (`PARGS.nas_check_on) begin
40871 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
40872 tid = 3
40873; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40874 end
40875`endif
40876
40877`endif
40878
40879`endif
40880
40881 end
40882 endtask
40883
40884
40885 task slam_PhysicalOffset1_core7_thread4;
40886 input [63:0] value;
40887 reg [5:0] tid;
40888 integer junk;
40889
40890 begin
40891`ifdef AXIS_EMUL_COSIM
40892//Do Nothing
40893`else
40894`ifdef GATESIM
40895//Do Nothing
40896`else
40897`ifdef CORE_7
40898 if (`PARGS.nas_check_on) begin
40899 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
40900 tid = 4
40901; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40902 end
40903`endif
40904
40905`endif
40906
40907`endif
40908
40909 end
40910 endtask
40911
40912
40913 task slam_PhysicalOffset1_core7_thread5;
40914 input [63:0] value;
40915 reg [5:0] tid;
40916 integer junk;
40917
40918 begin
40919`ifdef AXIS_EMUL_COSIM
40920//Do Nothing
40921`else
40922`ifdef GATESIM
40923//Do Nothing
40924`else
40925`ifdef CORE_7
40926 if (`PARGS.nas_check_on) begin
40927 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
40928 tid = 5
40929; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40930 end
40931`endif
40932
40933`endif
40934
40935`endif
40936
40937 end
40938 endtask
40939
40940
40941 task slam_PhysicalOffset1_core7_thread6;
40942 input [63:0] value;
40943 reg [5:0] tid;
40944 integer junk;
40945
40946 begin
40947`ifdef AXIS_EMUL_COSIM
40948//Do Nothing
40949`else
40950`ifdef GATESIM
40951//Do Nothing
40952`else
40953`ifdef CORE_7
40954 if (`PARGS.nas_check_on) begin
40955 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
40956 tid = 6
40957; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40958 end
40959`endif
40960
40961`endif
40962
40963`endif
40964
40965 end
40966 endtask
40967
40968
40969 task slam_PhysicalOffset1_core7_thread7;
40970 input [63:0] value;
40971 reg [5:0] tid;
40972 integer junk;
40973
40974 begin
40975`ifdef AXIS_EMUL_COSIM
40976//Do Nothing
40977`else
40978`ifdef GATESIM
40979//Do Nothing
40980`else
40981`ifdef CORE_7
40982 if (`PARGS.nas_check_on) begin
40983 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
40984 tid = 7
40985; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h210, value);
40986 end
40987`endif
40988
40989`endif
40990
40991`endif
40992
40993 end
40994 endtask
40995
40996
40997 task slam_PhysicalOffset2_core0_thread0;
40998 input [63:0] value;
40999 reg [5:0] tid;
41000 integer junk;
41001
41002 begin
41003`ifdef AXIS_EMUL_COSIM
41004//Do Nothing
41005`else
41006`ifdef GATESIM
41007//Do Nothing
41008`else
41009`ifdef CORE_0
41010 if (`PARGS.nas_check_on) begin
41011 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
41012 tid = 0
41013; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41014 end
41015`endif
41016
41017`endif
41018
41019`endif
41020
41021 end
41022 endtask
41023
41024
41025 task slam_PhysicalOffset2_core0_thread1;
41026 input [63:0] value;
41027 reg [5:0] tid;
41028 integer junk;
41029
41030 begin
41031`ifdef AXIS_EMUL_COSIM
41032//Do Nothing
41033`else
41034`ifdef GATESIM
41035//Do Nothing
41036`else
41037`ifdef CORE_0
41038 if (`PARGS.nas_check_on) begin
41039 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
41040 tid = 1
41041; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41042 end
41043`endif
41044
41045`endif
41046
41047`endif
41048
41049 end
41050 endtask
41051
41052
41053 task slam_PhysicalOffset2_core0_thread2;
41054 input [63:0] value;
41055 reg [5:0] tid;
41056 integer junk;
41057
41058 begin
41059`ifdef AXIS_EMUL_COSIM
41060//Do Nothing
41061`else
41062`ifdef GATESIM
41063//Do Nothing
41064`else
41065`ifdef CORE_0
41066 if (`PARGS.nas_check_on) begin
41067 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
41068 tid = 2
41069; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41070 end
41071`endif
41072
41073`endif
41074
41075`endif
41076
41077 end
41078 endtask
41079
41080
41081 task slam_PhysicalOffset2_core0_thread3;
41082 input [63:0] value;
41083 reg [5:0] tid;
41084 integer junk;
41085
41086 begin
41087`ifdef AXIS_EMUL_COSIM
41088//Do Nothing
41089`else
41090`ifdef GATESIM
41091//Do Nothing
41092`else
41093`ifdef CORE_0
41094 if (`PARGS.nas_check_on) begin
41095 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
41096 tid = 3
41097; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41098 end
41099`endif
41100
41101`endif
41102
41103`endif
41104
41105 end
41106 endtask
41107
41108
41109 task slam_PhysicalOffset2_core0_thread4;
41110 input [63:0] value;
41111 reg [5:0] tid;
41112 integer junk;
41113
41114 begin
41115`ifdef AXIS_EMUL_COSIM
41116//Do Nothing
41117`else
41118`ifdef GATESIM
41119//Do Nothing
41120`else
41121`ifdef CORE_0
41122 if (`PARGS.nas_check_on) begin
41123 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
41124 tid = 4
41125; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41126 end
41127`endif
41128
41129`endif
41130
41131`endif
41132
41133 end
41134 endtask
41135
41136
41137 task slam_PhysicalOffset2_core0_thread5;
41138 input [63:0] value;
41139 reg [5:0] tid;
41140 integer junk;
41141
41142 begin
41143`ifdef AXIS_EMUL_COSIM
41144//Do Nothing
41145`else
41146`ifdef GATESIM
41147//Do Nothing
41148`else
41149`ifdef CORE_0
41150 if (`PARGS.nas_check_on) begin
41151 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
41152 tid = 5
41153; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41154 end
41155`endif
41156
41157`endif
41158
41159`endif
41160
41161 end
41162 endtask
41163
41164
41165 task slam_PhysicalOffset2_core0_thread6;
41166 input [63:0] value;
41167 reg [5:0] tid;
41168 integer junk;
41169
41170 begin
41171`ifdef AXIS_EMUL_COSIM
41172//Do Nothing
41173`else
41174`ifdef GATESIM
41175//Do Nothing
41176`else
41177`ifdef CORE_0
41178 if (`PARGS.nas_check_on) begin
41179 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
41180 tid = 6
41181; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41182 end
41183`endif
41184
41185`endif
41186
41187`endif
41188
41189 end
41190 endtask
41191
41192
41193 task slam_PhysicalOffset2_core0_thread7;
41194 input [63:0] value;
41195 reg [5:0] tid;
41196 integer junk;
41197
41198 begin
41199`ifdef AXIS_EMUL_COSIM
41200//Do Nothing
41201`else
41202`ifdef GATESIM
41203//Do Nothing
41204`else
41205`ifdef CORE_0
41206 if (`PARGS.nas_check_on) begin
41207 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
41208 tid = 7
41209; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41210 end
41211`endif
41212
41213`endif
41214
41215`endif
41216
41217 end
41218 endtask
41219
41220
41221 task slam_PhysicalOffset2_core1_thread0;
41222 input [63:0] value;
41223 reg [5:0] tid;
41224 integer junk;
41225
41226 begin
41227`ifdef AXIS_EMUL_COSIM
41228//Do Nothing
41229`else
41230`ifdef GATESIM
41231//Do Nothing
41232`else
41233`ifdef CORE_1
41234 if (`PARGS.nas_check_on) begin
41235 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
41236 tid = 0
41237; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41238 end
41239`endif
41240
41241`endif
41242
41243`endif
41244
41245 end
41246 endtask
41247
41248
41249 task slam_PhysicalOffset2_core1_thread1;
41250 input [63:0] value;
41251 reg [5:0] tid;
41252 integer junk;
41253
41254 begin
41255`ifdef AXIS_EMUL_COSIM
41256//Do Nothing
41257`else
41258`ifdef GATESIM
41259//Do Nothing
41260`else
41261`ifdef CORE_1
41262 if (`PARGS.nas_check_on) begin
41263 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
41264 tid = 1
41265; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41266 end
41267`endif
41268
41269`endif
41270
41271`endif
41272
41273 end
41274 endtask
41275
41276
41277 task slam_PhysicalOffset2_core1_thread2;
41278 input [63:0] value;
41279 reg [5:0] tid;
41280 integer junk;
41281
41282 begin
41283`ifdef AXIS_EMUL_COSIM
41284//Do Nothing
41285`else
41286`ifdef GATESIM
41287//Do Nothing
41288`else
41289`ifdef CORE_1
41290 if (`PARGS.nas_check_on) begin
41291 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
41292 tid = 2
41293; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41294 end
41295`endif
41296
41297`endif
41298
41299`endif
41300
41301 end
41302 endtask
41303
41304
41305 task slam_PhysicalOffset2_core1_thread3;
41306 input [63:0] value;
41307 reg [5:0] tid;
41308 integer junk;
41309
41310 begin
41311`ifdef AXIS_EMUL_COSIM
41312//Do Nothing
41313`else
41314`ifdef GATESIM
41315//Do Nothing
41316`else
41317`ifdef CORE_1
41318 if (`PARGS.nas_check_on) begin
41319 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
41320 tid = 3
41321; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41322 end
41323`endif
41324
41325`endif
41326
41327`endif
41328
41329 end
41330 endtask
41331
41332
41333 task slam_PhysicalOffset2_core1_thread4;
41334 input [63:0] value;
41335 reg [5:0] tid;
41336 integer junk;
41337
41338 begin
41339`ifdef AXIS_EMUL_COSIM
41340//Do Nothing
41341`else
41342`ifdef GATESIM
41343//Do Nothing
41344`else
41345`ifdef CORE_1
41346 if (`PARGS.nas_check_on) begin
41347 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
41348 tid = 4
41349; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41350 end
41351`endif
41352
41353`endif
41354
41355`endif
41356
41357 end
41358 endtask
41359
41360
41361 task slam_PhysicalOffset2_core1_thread5;
41362 input [63:0] value;
41363 reg [5:0] tid;
41364 integer junk;
41365
41366 begin
41367`ifdef AXIS_EMUL_COSIM
41368//Do Nothing
41369`else
41370`ifdef GATESIM
41371//Do Nothing
41372`else
41373`ifdef CORE_1
41374 if (`PARGS.nas_check_on) begin
41375 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
41376 tid = 5
41377; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41378 end
41379`endif
41380
41381`endif
41382
41383`endif
41384
41385 end
41386 endtask
41387
41388
41389 task slam_PhysicalOffset2_core1_thread6;
41390 input [63:0] value;
41391 reg [5:0] tid;
41392 integer junk;
41393
41394 begin
41395`ifdef AXIS_EMUL_COSIM
41396//Do Nothing
41397`else
41398`ifdef GATESIM
41399//Do Nothing
41400`else
41401`ifdef CORE_1
41402 if (`PARGS.nas_check_on) begin
41403 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
41404 tid = 6
41405; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41406 end
41407`endif
41408
41409`endif
41410
41411`endif
41412
41413 end
41414 endtask
41415
41416
41417 task slam_PhysicalOffset2_core1_thread7;
41418 input [63:0] value;
41419 reg [5:0] tid;
41420 integer junk;
41421
41422 begin
41423`ifdef AXIS_EMUL_COSIM
41424//Do Nothing
41425`else
41426`ifdef GATESIM
41427//Do Nothing
41428`else
41429`ifdef CORE_1
41430 if (`PARGS.nas_check_on) begin
41431 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
41432 tid = 7
41433; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41434 end
41435`endif
41436
41437`endif
41438
41439`endif
41440
41441 end
41442 endtask
41443
41444
41445 task slam_PhysicalOffset2_core2_thread0;
41446 input [63:0] value;
41447 reg [5:0] tid;
41448 integer junk;
41449
41450 begin
41451`ifdef AXIS_EMUL_COSIM
41452//Do Nothing
41453`else
41454`ifdef GATESIM
41455//Do Nothing
41456`else
41457`ifdef CORE_2
41458 if (`PARGS.nas_check_on) begin
41459 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
41460 tid = 0
41461; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41462 end
41463`endif
41464
41465`endif
41466
41467`endif
41468
41469 end
41470 endtask
41471
41472
41473 task slam_PhysicalOffset2_core2_thread1;
41474 input [63:0] value;
41475 reg [5:0] tid;
41476 integer junk;
41477
41478 begin
41479`ifdef AXIS_EMUL_COSIM
41480//Do Nothing
41481`else
41482`ifdef GATESIM
41483//Do Nothing
41484`else
41485`ifdef CORE_2
41486 if (`PARGS.nas_check_on) begin
41487 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
41488 tid = 1
41489; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41490 end
41491`endif
41492
41493`endif
41494
41495`endif
41496
41497 end
41498 endtask
41499
41500
41501 task slam_PhysicalOffset2_core2_thread2;
41502 input [63:0] value;
41503 reg [5:0] tid;
41504 integer junk;
41505
41506 begin
41507`ifdef AXIS_EMUL_COSIM
41508//Do Nothing
41509`else
41510`ifdef GATESIM
41511//Do Nothing
41512`else
41513`ifdef CORE_2
41514 if (`PARGS.nas_check_on) begin
41515 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
41516 tid = 2
41517; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41518 end
41519`endif
41520
41521`endif
41522
41523`endif
41524
41525 end
41526 endtask
41527
41528
41529 task slam_PhysicalOffset2_core2_thread3;
41530 input [63:0] value;
41531 reg [5:0] tid;
41532 integer junk;
41533
41534 begin
41535`ifdef AXIS_EMUL_COSIM
41536//Do Nothing
41537`else
41538`ifdef GATESIM
41539//Do Nothing
41540`else
41541`ifdef CORE_2
41542 if (`PARGS.nas_check_on) begin
41543 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
41544 tid = 3
41545; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41546 end
41547`endif
41548
41549`endif
41550
41551`endif
41552
41553 end
41554 endtask
41555
41556
41557 task slam_PhysicalOffset2_core2_thread4;
41558 input [63:0] value;
41559 reg [5:0] tid;
41560 integer junk;
41561
41562 begin
41563`ifdef AXIS_EMUL_COSIM
41564//Do Nothing
41565`else
41566`ifdef GATESIM
41567//Do Nothing
41568`else
41569`ifdef CORE_2
41570 if (`PARGS.nas_check_on) begin
41571 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
41572 tid = 4
41573; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41574 end
41575`endif
41576
41577`endif
41578
41579`endif
41580
41581 end
41582 endtask
41583
41584
41585 task slam_PhysicalOffset2_core2_thread5;
41586 input [63:0] value;
41587 reg [5:0] tid;
41588 integer junk;
41589
41590 begin
41591`ifdef AXIS_EMUL_COSIM
41592//Do Nothing
41593`else
41594`ifdef GATESIM
41595//Do Nothing
41596`else
41597`ifdef CORE_2
41598 if (`PARGS.nas_check_on) begin
41599 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
41600 tid = 5
41601; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41602 end
41603`endif
41604
41605`endif
41606
41607`endif
41608
41609 end
41610 endtask
41611
41612
41613 task slam_PhysicalOffset2_core2_thread6;
41614 input [63:0] value;
41615 reg [5:0] tid;
41616 integer junk;
41617
41618 begin
41619`ifdef AXIS_EMUL_COSIM
41620//Do Nothing
41621`else
41622`ifdef GATESIM
41623//Do Nothing
41624`else
41625`ifdef CORE_2
41626 if (`PARGS.nas_check_on) begin
41627 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
41628 tid = 6
41629; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41630 end
41631`endif
41632
41633`endif
41634
41635`endif
41636
41637 end
41638 endtask
41639
41640
41641 task slam_PhysicalOffset2_core2_thread7;
41642 input [63:0] value;
41643 reg [5:0] tid;
41644 integer junk;
41645
41646 begin
41647`ifdef AXIS_EMUL_COSIM
41648//Do Nothing
41649`else
41650`ifdef GATESIM
41651//Do Nothing
41652`else
41653`ifdef CORE_2
41654 if (`PARGS.nas_check_on) begin
41655 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
41656 tid = 7
41657; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41658 end
41659`endif
41660
41661`endif
41662
41663`endif
41664
41665 end
41666 endtask
41667
41668
41669 task slam_PhysicalOffset2_core3_thread0;
41670 input [63:0] value;
41671 reg [5:0] tid;
41672 integer junk;
41673
41674 begin
41675`ifdef AXIS_EMUL_COSIM
41676//Do Nothing
41677`else
41678`ifdef GATESIM
41679//Do Nothing
41680`else
41681`ifdef CORE_3
41682 if (`PARGS.nas_check_on) begin
41683 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
41684 tid = 0
41685; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41686 end
41687`endif
41688
41689`endif
41690
41691`endif
41692
41693 end
41694 endtask
41695
41696
41697 task slam_PhysicalOffset2_core3_thread1;
41698 input [63:0] value;
41699 reg [5:0] tid;
41700 integer junk;
41701
41702 begin
41703`ifdef AXIS_EMUL_COSIM
41704//Do Nothing
41705`else
41706`ifdef GATESIM
41707//Do Nothing
41708`else
41709`ifdef CORE_3
41710 if (`PARGS.nas_check_on) begin
41711 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
41712 tid = 1
41713; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41714 end
41715`endif
41716
41717`endif
41718
41719`endif
41720
41721 end
41722 endtask
41723
41724
41725 task slam_PhysicalOffset2_core3_thread2;
41726 input [63:0] value;
41727 reg [5:0] tid;
41728 integer junk;
41729
41730 begin
41731`ifdef AXIS_EMUL_COSIM
41732//Do Nothing
41733`else
41734`ifdef GATESIM
41735//Do Nothing
41736`else
41737`ifdef CORE_3
41738 if (`PARGS.nas_check_on) begin
41739 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
41740 tid = 2
41741; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41742 end
41743`endif
41744
41745`endif
41746
41747`endif
41748
41749 end
41750 endtask
41751
41752
41753 task slam_PhysicalOffset2_core3_thread3;
41754 input [63:0] value;
41755 reg [5:0] tid;
41756 integer junk;
41757
41758 begin
41759`ifdef AXIS_EMUL_COSIM
41760//Do Nothing
41761`else
41762`ifdef GATESIM
41763//Do Nothing
41764`else
41765`ifdef CORE_3
41766 if (`PARGS.nas_check_on) begin
41767 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
41768 tid = 3
41769; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41770 end
41771`endif
41772
41773`endif
41774
41775`endif
41776
41777 end
41778 endtask
41779
41780
41781 task slam_PhysicalOffset2_core3_thread4;
41782 input [63:0] value;
41783 reg [5:0] tid;
41784 integer junk;
41785
41786 begin
41787`ifdef AXIS_EMUL_COSIM
41788//Do Nothing
41789`else
41790`ifdef GATESIM
41791//Do Nothing
41792`else
41793`ifdef CORE_3
41794 if (`PARGS.nas_check_on) begin
41795 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
41796 tid = 4
41797; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41798 end
41799`endif
41800
41801`endif
41802
41803`endif
41804
41805 end
41806 endtask
41807
41808
41809 task slam_PhysicalOffset2_core3_thread5;
41810 input [63:0] value;
41811 reg [5:0] tid;
41812 integer junk;
41813
41814 begin
41815`ifdef AXIS_EMUL_COSIM
41816//Do Nothing
41817`else
41818`ifdef GATESIM
41819//Do Nothing
41820`else
41821`ifdef CORE_3
41822 if (`PARGS.nas_check_on) begin
41823 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
41824 tid = 5
41825; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41826 end
41827`endif
41828
41829`endif
41830
41831`endif
41832
41833 end
41834 endtask
41835
41836
41837 task slam_PhysicalOffset2_core3_thread6;
41838 input [63:0] value;
41839 reg [5:0] tid;
41840 integer junk;
41841
41842 begin
41843`ifdef AXIS_EMUL_COSIM
41844//Do Nothing
41845`else
41846`ifdef GATESIM
41847//Do Nothing
41848`else
41849`ifdef CORE_3
41850 if (`PARGS.nas_check_on) begin
41851 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
41852 tid = 6
41853; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41854 end
41855`endif
41856
41857`endif
41858
41859`endif
41860
41861 end
41862 endtask
41863
41864
41865 task slam_PhysicalOffset2_core3_thread7;
41866 input [63:0] value;
41867 reg [5:0] tid;
41868 integer junk;
41869
41870 begin
41871`ifdef AXIS_EMUL_COSIM
41872//Do Nothing
41873`else
41874`ifdef GATESIM
41875//Do Nothing
41876`else
41877`ifdef CORE_3
41878 if (`PARGS.nas_check_on) begin
41879 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
41880 tid = 7
41881; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41882 end
41883`endif
41884
41885`endif
41886
41887`endif
41888
41889 end
41890 endtask
41891
41892
41893 task slam_PhysicalOffset2_core4_thread0;
41894 input [63:0] value;
41895 reg [5:0] tid;
41896 integer junk;
41897
41898 begin
41899`ifdef AXIS_EMUL_COSIM
41900//Do Nothing
41901`else
41902`ifdef GATESIM
41903//Do Nothing
41904`else
41905`ifdef CORE_4
41906 if (`PARGS.nas_check_on) begin
41907 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
41908 tid = 0
41909; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41910 end
41911`endif
41912
41913`endif
41914
41915`endif
41916
41917 end
41918 endtask
41919
41920
41921 task slam_PhysicalOffset2_core4_thread1;
41922 input [63:0] value;
41923 reg [5:0] tid;
41924 integer junk;
41925
41926 begin
41927`ifdef AXIS_EMUL_COSIM
41928//Do Nothing
41929`else
41930`ifdef GATESIM
41931//Do Nothing
41932`else
41933`ifdef CORE_4
41934 if (`PARGS.nas_check_on) begin
41935 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
41936 tid = 1
41937; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41938 end
41939`endif
41940
41941`endif
41942
41943`endif
41944
41945 end
41946 endtask
41947
41948
41949 task slam_PhysicalOffset2_core4_thread2;
41950 input [63:0] value;
41951 reg [5:0] tid;
41952 integer junk;
41953
41954 begin
41955`ifdef AXIS_EMUL_COSIM
41956//Do Nothing
41957`else
41958`ifdef GATESIM
41959//Do Nothing
41960`else
41961`ifdef CORE_4
41962 if (`PARGS.nas_check_on) begin
41963 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
41964 tid = 2
41965; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41966 end
41967`endif
41968
41969`endif
41970
41971`endif
41972
41973 end
41974 endtask
41975
41976
41977 task slam_PhysicalOffset2_core4_thread3;
41978 input [63:0] value;
41979 reg [5:0] tid;
41980 integer junk;
41981
41982 begin
41983`ifdef AXIS_EMUL_COSIM
41984//Do Nothing
41985`else
41986`ifdef GATESIM
41987//Do Nothing
41988`else
41989`ifdef CORE_4
41990 if (`PARGS.nas_check_on) begin
41991 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
41992 tid = 3
41993; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
41994 end
41995`endif
41996
41997`endif
41998
41999`endif
42000
42001 end
42002 endtask
42003
42004
42005 task slam_PhysicalOffset2_core4_thread4;
42006 input [63:0] value;
42007 reg [5:0] tid;
42008 integer junk;
42009
42010 begin
42011`ifdef AXIS_EMUL_COSIM
42012//Do Nothing
42013`else
42014`ifdef GATESIM
42015//Do Nothing
42016`else
42017`ifdef CORE_4
42018 if (`PARGS.nas_check_on) begin
42019 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
42020 tid = 4
42021; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42022 end
42023`endif
42024
42025`endif
42026
42027`endif
42028
42029 end
42030 endtask
42031
42032
42033 task slam_PhysicalOffset2_core4_thread5;
42034 input [63:0] value;
42035 reg [5:0] tid;
42036 integer junk;
42037
42038 begin
42039`ifdef AXIS_EMUL_COSIM
42040//Do Nothing
42041`else
42042`ifdef GATESIM
42043//Do Nothing
42044`else
42045`ifdef CORE_4
42046 if (`PARGS.nas_check_on) begin
42047 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
42048 tid = 5
42049; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42050 end
42051`endif
42052
42053`endif
42054
42055`endif
42056
42057 end
42058 endtask
42059
42060
42061 task slam_PhysicalOffset2_core4_thread6;
42062 input [63:0] value;
42063 reg [5:0] tid;
42064 integer junk;
42065
42066 begin
42067`ifdef AXIS_EMUL_COSIM
42068//Do Nothing
42069`else
42070`ifdef GATESIM
42071//Do Nothing
42072`else
42073`ifdef CORE_4
42074 if (`PARGS.nas_check_on) begin
42075 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
42076 tid = 6
42077; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42078 end
42079`endif
42080
42081`endif
42082
42083`endif
42084
42085 end
42086 endtask
42087
42088
42089 task slam_PhysicalOffset2_core4_thread7;
42090 input [63:0] value;
42091 reg [5:0] tid;
42092 integer junk;
42093
42094 begin
42095`ifdef AXIS_EMUL_COSIM
42096//Do Nothing
42097`else
42098`ifdef GATESIM
42099//Do Nothing
42100`else
42101`ifdef CORE_4
42102 if (`PARGS.nas_check_on) begin
42103 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
42104 tid = 7
42105; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42106 end
42107`endif
42108
42109`endif
42110
42111`endif
42112
42113 end
42114 endtask
42115
42116
42117 task slam_PhysicalOffset2_core5_thread0;
42118 input [63:0] value;
42119 reg [5:0] tid;
42120 integer junk;
42121
42122 begin
42123`ifdef AXIS_EMUL_COSIM
42124//Do Nothing
42125`else
42126`ifdef GATESIM
42127//Do Nothing
42128`else
42129`ifdef CORE_5
42130 if (`PARGS.nas_check_on) begin
42131 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
42132 tid = 0
42133; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42134 end
42135`endif
42136
42137`endif
42138
42139`endif
42140
42141 end
42142 endtask
42143
42144
42145 task slam_PhysicalOffset2_core5_thread1;
42146 input [63:0] value;
42147 reg [5:0] tid;
42148 integer junk;
42149
42150 begin
42151`ifdef AXIS_EMUL_COSIM
42152//Do Nothing
42153`else
42154`ifdef GATESIM
42155//Do Nothing
42156`else
42157`ifdef CORE_5
42158 if (`PARGS.nas_check_on) begin
42159 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
42160 tid = 1
42161; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42162 end
42163`endif
42164
42165`endif
42166
42167`endif
42168
42169 end
42170 endtask
42171
42172
42173 task slam_PhysicalOffset2_core5_thread2;
42174 input [63:0] value;
42175 reg [5:0] tid;
42176 integer junk;
42177
42178 begin
42179`ifdef AXIS_EMUL_COSIM
42180//Do Nothing
42181`else
42182`ifdef GATESIM
42183//Do Nothing
42184`else
42185`ifdef CORE_5
42186 if (`PARGS.nas_check_on) begin
42187 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
42188 tid = 2
42189; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42190 end
42191`endif
42192
42193`endif
42194
42195`endif
42196
42197 end
42198 endtask
42199
42200
42201 task slam_PhysicalOffset2_core5_thread3;
42202 input [63:0] value;
42203 reg [5:0] tid;
42204 integer junk;
42205
42206 begin
42207`ifdef AXIS_EMUL_COSIM
42208//Do Nothing
42209`else
42210`ifdef GATESIM
42211//Do Nothing
42212`else
42213`ifdef CORE_5
42214 if (`PARGS.nas_check_on) begin
42215 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
42216 tid = 3
42217; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42218 end
42219`endif
42220
42221`endif
42222
42223`endif
42224
42225 end
42226 endtask
42227
42228
42229 task slam_PhysicalOffset2_core5_thread4;
42230 input [63:0] value;
42231 reg [5:0] tid;
42232 integer junk;
42233
42234 begin
42235`ifdef AXIS_EMUL_COSIM
42236//Do Nothing
42237`else
42238`ifdef GATESIM
42239//Do Nothing
42240`else
42241`ifdef CORE_5
42242 if (`PARGS.nas_check_on) begin
42243 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
42244 tid = 4
42245; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42246 end
42247`endif
42248
42249`endif
42250
42251`endif
42252
42253 end
42254 endtask
42255
42256
42257 task slam_PhysicalOffset2_core5_thread5;
42258 input [63:0] value;
42259 reg [5:0] tid;
42260 integer junk;
42261
42262 begin
42263`ifdef AXIS_EMUL_COSIM
42264//Do Nothing
42265`else
42266`ifdef GATESIM
42267//Do Nothing
42268`else
42269`ifdef CORE_5
42270 if (`PARGS.nas_check_on) begin
42271 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
42272 tid = 5
42273; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42274 end
42275`endif
42276
42277`endif
42278
42279`endif
42280
42281 end
42282 endtask
42283
42284
42285 task slam_PhysicalOffset2_core5_thread6;
42286 input [63:0] value;
42287 reg [5:0] tid;
42288 integer junk;
42289
42290 begin
42291`ifdef AXIS_EMUL_COSIM
42292//Do Nothing
42293`else
42294`ifdef GATESIM
42295//Do Nothing
42296`else
42297`ifdef CORE_5
42298 if (`PARGS.nas_check_on) begin
42299 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
42300 tid = 6
42301; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42302 end
42303`endif
42304
42305`endif
42306
42307`endif
42308
42309 end
42310 endtask
42311
42312
42313 task slam_PhysicalOffset2_core5_thread7;
42314 input [63:0] value;
42315 reg [5:0] tid;
42316 integer junk;
42317
42318 begin
42319`ifdef AXIS_EMUL_COSIM
42320//Do Nothing
42321`else
42322`ifdef GATESIM
42323//Do Nothing
42324`else
42325`ifdef CORE_5
42326 if (`PARGS.nas_check_on) begin
42327 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
42328 tid = 7
42329; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42330 end
42331`endif
42332
42333`endif
42334
42335`endif
42336
42337 end
42338 endtask
42339
42340
42341 task slam_PhysicalOffset2_core6_thread0;
42342 input [63:0] value;
42343 reg [5:0] tid;
42344 integer junk;
42345
42346 begin
42347`ifdef AXIS_EMUL_COSIM
42348//Do Nothing
42349`else
42350`ifdef GATESIM
42351//Do Nothing
42352`else
42353`ifdef CORE_6
42354 if (`PARGS.nas_check_on) begin
42355 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
42356 tid = 0
42357; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42358 end
42359`endif
42360
42361`endif
42362
42363`endif
42364
42365 end
42366 endtask
42367
42368
42369 task slam_PhysicalOffset2_core6_thread1;
42370 input [63:0] value;
42371 reg [5:0] tid;
42372 integer junk;
42373
42374 begin
42375`ifdef AXIS_EMUL_COSIM
42376//Do Nothing
42377`else
42378`ifdef GATESIM
42379//Do Nothing
42380`else
42381`ifdef CORE_6
42382 if (`PARGS.nas_check_on) begin
42383 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
42384 tid = 1
42385; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42386 end
42387`endif
42388
42389`endif
42390
42391`endif
42392
42393 end
42394 endtask
42395
42396
42397 task slam_PhysicalOffset2_core6_thread2;
42398 input [63:0] value;
42399 reg [5:0] tid;
42400 integer junk;
42401
42402 begin
42403`ifdef AXIS_EMUL_COSIM
42404//Do Nothing
42405`else
42406`ifdef GATESIM
42407//Do Nothing
42408`else
42409`ifdef CORE_6
42410 if (`PARGS.nas_check_on) begin
42411 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
42412 tid = 2
42413; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42414 end
42415`endif
42416
42417`endif
42418
42419`endif
42420
42421 end
42422 endtask
42423
42424
42425 task slam_PhysicalOffset2_core6_thread3;
42426 input [63:0] value;
42427 reg [5:0] tid;
42428 integer junk;
42429
42430 begin
42431`ifdef AXIS_EMUL_COSIM
42432//Do Nothing
42433`else
42434`ifdef GATESIM
42435//Do Nothing
42436`else
42437`ifdef CORE_6
42438 if (`PARGS.nas_check_on) begin
42439 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
42440 tid = 3
42441; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42442 end
42443`endif
42444
42445`endif
42446
42447`endif
42448
42449 end
42450 endtask
42451
42452
42453 task slam_PhysicalOffset2_core6_thread4;
42454 input [63:0] value;
42455 reg [5:0] tid;
42456 integer junk;
42457
42458 begin
42459`ifdef AXIS_EMUL_COSIM
42460//Do Nothing
42461`else
42462`ifdef GATESIM
42463//Do Nothing
42464`else
42465`ifdef CORE_6
42466 if (`PARGS.nas_check_on) begin
42467 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
42468 tid = 4
42469; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42470 end
42471`endif
42472
42473`endif
42474
42475`endif
42476
42477 end
42478 endtask
42479
42480
42481 task slam_PhysicalOffset2_core6_thread5;
42482 input [63:0] value;
42483 reg [5:0] tid;
42484 integer junk;
42485
42486 begin
42487`ifdef AXIS_EMUL_COSIM
42488//Do Nothing
42489`else
42490`ifdef GATESIM
42491//Do Nothing
42492`else
42493`ifdef CORE_6
42494 if (`PARGS.nas_check_on) begin
42495 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
42496 tid = 5
42497; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42498 end
42499`endif
42500
42501`endif
42502
42503`endif
42504
42505 end
42506 endtask
42507
42508
42509 task slam_PhysicalOffset2_core6_thread6;
42510 input [63:0] value;
42511 reg [5:0] tid;
42512 integer junk;
42513
42514 begin
42515`ifdef AXIS_EMUL_COSIM
42516//Do Nothing
42517`else
42518`ifdef GATESIM
42519//Do Nothing
42520`else
42521`ifdef CORE_6
42522 if (`PARGS.nas_check_on) begin
42523 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
42524 tid = 6
42525; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42526 end
42527`endif
42528
42529`endif
42530
42531`endif
42532
42533 end
42534 endtask
42535
42536
42537 task slam_PhysicalOffset2_core6_thread7;
42538 input [63:0] value;
42539 reg [5:0] tid;
42540 integer junk;
42541
42542 begin
42543`ifdef AXIS_EMUL_COSIM
42544//Do Nothing
42545`else
42546`ifdef GATESIM
42547//Do Nothing
42548`else
42549`ifdef CORE_6
42550 if (`PARGS.nas_check_on) begin
42551 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
42552 tid = 7
42553; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42554 end
42555`endif
42556
42557`endif
42558
42559`endif
42560
42561 end
42562 endtask
42563
42564
42565 task slam_PhysicalOffset2_core7_thread0;
42566 input [63:0] value;
42567 reg [5:0] tid;
42568 integer junk;
42569
42570 begin
42571`ifdef AXIS_EMUL_COSIM
42572//Do Nothing
42573`else
42574`ifdef GATESIM
42575//Do Nothing
42576`else
42577`ifdef CORE_7
42578 if (`PARGS.nas_check_on) begin
42579 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
42580 tid = 0
42581; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42582 end
42583`endif
42584
42585`endif
42586
42587`endif
42588
42589 end
42590 endtask
42591
42592
42593 task slam_PhysicalOffset2_core7_thread1;
42594 input [63:0] value;
42595 reg [5:0] tid;
42596 integer junk;
42597
42598 begin
42599`ifdef AXIS_EMUL_COSIM
42600//Do Nothing
42601`else
42602`ifdef GATESIM
42603//Do Nothing
42604`else
42605`ifdef CORE_7
42606 if (`PARGS.nas_check_on) begin
42607 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
42608 tid = 1
42609; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42610 end
42611`endif
42612
42613`endif
42614
42615`endif
42616
42617 end
42618 endtask
42619
42620
42621 task slam_PhysicalOffset2_core7_thread2;
42622 input [63:0] value;
42623 reg [5:0] tid;
42624 integer junk;
42625
42626 begin
42627`ifdef AXIS_EMUL_COSIM
42628//Do Nothing
42629`else
42630`ifdef GATESIM
42631//Do Nothing
42632`else
42633`ifdef CORE_7
42634 if (`PARGS.nas_check_on) begin
42635 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
42636 tid = 2
42637; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42638 end
42639`endif
42640
42641`endif
42642
42643`endif
42644
42645 end
42646 endtask
42647
42648
42649 task slam_PhysicalOffset2_core7_thread3;
42650 input [63:0] value;
42651 reg [5:0] tid;
42652 integer junk;
42653
42654 begin
42655`ifdef AXIS_EMUL_COSIM
42656//Do Nothing
42657`else
42658`ifdef GATESIM
42659//Do Nothing
42660`else
42661`ifdef CORE_7
42662 if (`PARGS.nas_check_on) begin
42663 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
42664 tid = 3
42665; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42666 end
42667`endif
42668
42669`endif
42670
42671`endif
42672
42673 end
42674 endtask
42675
42676
42677 task slam_PhysicalOffset2_core7_thread4;
42678 input [63:0] value;
42679 reg [5:0] tid;
42680 integer junk;
42681
42682 begin
42683`ifdef AXIS_EMUL_COSIM
42684//Do Nothing
42685`else
42686`ifdef GATESIM
42687//Do Nothing
42688`else
42689`ifdef CORE_7
42690 if (`PARGS.nas_check_on) begin
42691 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
42692 tid = 4
42693; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42694 end
42695`endif
42696
42697`endif
42698
42699`endif
42700
42701 end
42702 endtask
42703
42704
42705 task slam_PhysicalOffset2_core7_thread5;
42706 input [63:0] value;
42707 reg [5:0] tid;
42708 integer junk;
42709
42710 begin
42711`ifdef AXIS_EMUL_COSIM
42712//Do Nothing
42713`else
42714`ifdef GATESIM
42715//Do Nothing
42716`else
42717`ifdef CORE_7
42718 if (`PARGS.nas_check_on) begin
42719 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
42720 tid = 5
42721; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42722 end
42723`endif
42724
42725`endif
42726
42727`endif
42728
42729 end
42730 endtask
42731
42732
42733 task slam_PhysicalOffset2_core7_thread6;
42734 input [63:0] value;
42735 reg [5:0] tid;
42736 integer junk;
42737
42738 begin
42739`ifdef AXIS_EMUL_COSIM
42740//Do Nothing
42741`else
42742`ifdef GATESIM
42743//Do Nothing
42744`else
42745`ifdef CORE_7
42746 if (`PARGS.nas_check_on) begin
42747 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
42748 tid = 6
42749; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42750 end
42751`endif
42752
42753`endif
42754
42755`endif
42756
42757 end
42758 endtask
42759
42760
42761 task slam_PhysicalOffset2_core7_thread7;
42762 input [63:0] value;
42763 reg [5:0] tid;
42764 integer junk;
42765
42766 begin
42767`ifdef AXIS_EMUL_COSIM
42768//Do Nothing
42769`else
42770`ifdef GATESIM
42771//Do Nothing
42772`else
42773`ifdef CORE_7
42774 if (`PARGS.nas_check_on) begin
42775 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
42776 tid = 7
42777; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h218, value);
42778 end
42779`endif
42780
42781`endif
42782
42783`endif
42784
42785 end
42786 endtask
42787
42788
42789 task slam_PhysicalOffset3_core0_thread0;
42790 input [63:0] value;
42791 reg [5:0] tid;
42792 integer junk;
42793
42794 begin
42795`ifdef AXIS_EMUL_COSIM
42796//Do Nothing
42797`else
42798`ifdef GATESIM
42799//Do Nothing
42800`else
42801`ifdef CORE_0
42802 if (`PARGS.nas_check_on) begin
42803 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 0, 52, value);
42804 tid = 0
42805; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42806 end
42807`endif
42808
42809`endif
42810
42811`endif
42812
42813 end
42814 endtask
42815
42816
42817 task slam_PhysicalOffset3_core0_thread1;
42818 input [63:0] value;
42819 reg [5:0] tid;
42820 integer junk;
42821
42822 begin
42823`ifdef AXIS_EMUL_COSIM
42824//Do Nothing
42825`else
42826`ifdef GATESIM
42827//Do Nothing
42828`else
42829`ifdef CORE_0
42830 if (`PARGS.nas_check_on) begin
42831 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 1, 52, value);
42832 tid = 1
42833; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42834 end
42835`endif
42836
42837`endif
42838
42839`endif
42840
42841 end
42842 endtask
42843
42844
42845 task slam_PhysicalOffset3_core0_thread2;
42846 input [63:0] value;
42847 reg [5:0] tid;
42848 integer junk;
42849
42850 begin
42851`ifdef AXIS_EMUL_COSIM
42852//Do Nothing
42853`else
42854`ifdef GATESIM
42855//Do Nothing
42856`else
42857`ifdef CORE_0
42858 if (`PARGS.nas_check_on) begin
42859 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 2, 52, value);
42860 tid = 2
42861; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42862 end
42863`endif
42864
42865`endif
42866
42867`endif
42868
42869 end
42870 endtask
42871
42872
42873 task slam_PhysicalOffset3_core0_thread3;
42874 input [63:0] value;
42875 reg [5:0] tid;
42876 integer junk;
42877
42878 begin
42879`ifdef AXIS_EMUL_COSIM
42880//Do Nothing
42881`else
42882`ifdef GATESIM
42883//Do Nothing
42884`else
42885`ifdef CORE_0
42886 if (`PARGS.nas_check_on) begin
42887 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 3, 52, value);
42888 tid = 3
42889; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42890 end
42891`endif
42892
42893`endif
42894
42895`endif
42896
42897 end
42898 endtask
42899
42900
42901 task slam_PhysicalOffset3_core0_thread4;
42902 input [63:0] value;
42903 reg [5:0] tid;
42904 integer junk;
42905
42906 begin
42907`ifdef AXIS_EMUL_COSIM
42908//Do Nothing
42909`else
42910`ifdef GATESIM
42911//Do Nothing
42912`else
42913`ifdef CORE_0
42914 if (`PARGS.nas_check_on) begin
42915 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 4, 52, value);
42916 tid = 4
42917; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42918 end
42919`endif
42920
42921`endif
42922
42923`endif
42924
42925 end
42926 endtask
42927
42928
42929 task slam_PhysicalOffset3_core0_thread5;
42930 input [63:0] value;
42931 reg [5:0] tid;
42932 integer junk;
42933
42934 begin
42935`ifdef AXIS_EMUL_COSIM
42936//Do Nothing
42937`else
42938`ifdef GATESIM
42939//Do Nothing
42940`else
42941`ifdef CORE_0
42942 if (`PARGS.nas_check_on) begin
42943 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 5, 52, value);
42944 tid = 5
42945; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42946 end
42947`endif
42948
42949`endif
42950
42951`endif
42952
42953 end
42954 endtask
42955
42956
42957 task slam_PhysicalOffset3_core0_thread6;
42958 input [63:0] value;
42959 reg [5:0] tid;
42960 integer junk;
42961
42962 begin
42963`ifdef AXIS_EMUL_COSIM
42964//Do Nothing
42965`else
42966`ifdef GATESIM
42967//Do Nothing
42968`else
42969`ifdef CORE_0
42970 if (`PARGS.nas_check_on) begin
42971 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 6, 52, value);
42972 tid = 6
42973; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
42974 end
42975`endif
42976
42977`endif
42978
42979`endif
42980
42981 end
42982 endtask
42983
42984
42985 task slam_PhysicalOffset3_core0_thread7;
42986 input [63:0] value;
42987 reg [5:0] tid;
42988 integer junk;
42989
42990 begin
42991`ifdef AXIS_EMUL_COSIM
42992//Do Nothing
42993`else
42994`ifdef GATESIM
42995//Do Nothing
42996`else
42997`ifdef CORE_0
42998 if (`PARGS.nas_check_on) begin
42999 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 0, 7, 52, value);
43000 tid = 7
43001; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43002 end
43003`endif
43004
43005`endif
43006
43007`endif
43008
43009 end
43010 endtask
43011
43012
43013 task slam_PhysicalOffset3_core1_thread0;
43014 input [63:0] value;
43015 reg [5:0] tid;
43016 integer junk;
43017
43018 begin
43019`ifdef AXIS_EMUL_COSIM
43020//Do Nothing
43021`else
43022`ifdef GATESIM
43023//Do Nothing
43024`else
43025`ifdef CORE_1
43026 if (`PARGS.nas_check_on) begin
43027 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 0, 52, value);
43028 tid = 0
43029; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43030 end
43031`endif
43032
43033`endif
43034
43035`endif
43036
43037 end
43038 endtask
43039
43040
43041 task slam_PhysicalOffset3_core1_thread1;
43042 input [63:0] value;
43043 reg [5:0] tid;
43044 integer junk;
43045
43046 begin
43047`ifdef AXIS_EMUL_COSIM
43048//Do Nothing
43049`else
43050`ifdef GATESIM
43051//Do Nothing
43052`else
43053`ifdef CORE_1
43054 if (`PARGS.nas_check_on) begin
43055 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 1, 52, value);
43056 tid = 1
43057; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43058 end
43059`endif
43060
43061`endif
43062
43063`endif
43064
43065 end
43066 endtask
43067
43068
43069 task slam_PhysicalOffset3_core1_thread2;
43070 input [63:0] value;
43071 reg [5:0] tid;
43072 integer junk;
43073
43074 begin
43075`ifdef AXIS_EMUL_COSIM
43076//Do Nothing
43077`else
43078`ifdef GATESIM
43079//Do Nothing
43080`else
43081`ifdef CORE_1
43082 if (`PARGS.nas_check_on) begin
43083 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 2, 52, value);
43084 tid = 2
43085; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43086 end
43087`endif
43088
43089`endif
43090
43091`endif
43092
43093 end
43094 endtask
43095
43096
43097 task slam_PhysicalOffset3_core1_thread3;
43098 input [63:0] value;
43099 reg [5:0] tid;
43100 integer junk;
43101
43102 begin
43103`ifdef AXIS_EMUL_COSIM
43104//Do Nothing
43105`else
43106`ifdef GATESIM
43107//Do Nothing
43108`else
43109`ifdef CORE_1
43110 if (`PARGS.nas_check_on) begin
43111 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 3, 52, value);
43112 tid = 3
43113; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43114 end
43115`endif
43116
43117`endif
43118
43119`endif
43120
43121 end
43122 endtask
43123
43124
43125 task slam_PhysicalOffset3_core1_thread4;
43126 input [63:0] value;
43127 reg [5:0] tid;
43128 integer junk;
43129
43130 begin
43131`ifdef AXIS_EMUL_COSIM
43132//Do Nothing
43133`else
43134`ifdef GATESIM
43135//Do Nothing
43136`else
43137`ifdef CORE_1
43138 if (`PARGS.nas_check_on) begin
43139 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 4, 52, value);
43140 tid = 4
43141; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43142 end
43143`endif
43144
43145`endif
43146
43147`endif
43148
43149 end
43150 endtask
43151
43152
43153 task slam_PhysicalOffset3_core1_thread5;
43154 input [63:0] value;
43155 reg [5:0] tid;
43156 integer junk;
43157
43158 begin
43159`ifdef AXIS_EMUL_COSIM
43160//Do Nothing
43161`else
43162`ifdef GATESIM
43163//Do Nothing
43164`else
43165`ifdef CORE_1
43166 if (`PARGS.nas_check_on) begin
43167 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 5, 52, value);
43168 tid = 5
43169; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43170 end
43171`endif
43172
43173`endif
43174
43175`endif
43176
43177 end
43178 endtask
43179
43180
43181 task slam_PhysicalOffset3_core1_thread6;
43182 input [63:0] value;
43183 reg [5:0] tid;
43184 integer junk;
43185
43186 begin
43187`ifdef AXIS_EMUL_COSIM
43188//Do Nothing
43189`else
43190`ifdef GATESIM
43191//Do Nothing
43192`else
43193`ifdef CORE_1
43194 if (`PARGS.nas_check_on) begin
43195 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 6, 52, value);
43196 tid = 6
43197; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43198 end
43199`endif
43200
43201`endif
43202
43203`endif
43204
43205 end
43206 endtask
43207
43208
43209 task slam_PhysicalOffset3_core1_thread7;
43210 input [63:0] value;
43211 reg [5:0] tid;
43212 integer junk;
43213
43214 begin
43215`ifdef AXIS_EMUL_COSIM
43216//Do Nothing
43217`else
43218`ifdef GATESIM
43219//Do Nothing
43220`else
43221`ifdef CORE_1
43222 if (`PARGS.nas_check_on) begin
43223 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 1, 7, 52, value);
43224 tid = 7
43225; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43226 end
43227`endif
43228
43229`endif
43230
43231`endif
43232
43233 end
43234 endtask
43235
43236
43237 task slam_PhysicalOffset3_core2_thread0;
43238 input [63:0] value;
43239 reg [5:0] tid;
43240 integer junk;
43241
43242 begin
43243`ifdef AXIS_EMUL_COSIM
43244//Do Nothing
43245`else
43246`ifdef GATESIM
43247//Do Nothing
43248`else
43249`ifdef CORE_2
43250 if (`PARGS.nas_check_on) begin
43251 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 0, 52, value);
43252 tid = 0
43253; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43254 end
43255`endif
43256
43257`endif
43258
43259`endif
43260
43261 end
43262 endtask
43263
43264
43265 task slam_PhysicalOffset3_core2_thread1;
43266 input [63:0] value;
43267 reg [5:0] tid;
43268 integer junk;
43269
43270 begin
43271`ifdef AXIS_EMUL_COSIM
43272//Do Nothing
43273`else
43274`ifdef GATESIM
43275//Do Nothing
43276`else
43277`ifdef CORE_2
43278 if (`PARGS.nas_check_on) begin
43279 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 1, 52, value);
43280 tid = 1
43281; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43282 end
43283`endif
43284
43285`endif
43286
43287`endif
43288
43289 end
43290 endtask
43291
43292
43293 task slam_PhysicalOffset3_core2_thread2;
43294 input [63:0] value;
43295 reg [5:0] tid;
43296 integer junk;
43297
43298 begin
43299`ifdef AXIS_EMUL_COSIM
43300//Do Nothing
43301`else
43302`ifdef GATESIM
43303//Do Nothing
43304`else
43305`ifdef CORE_2
43306 if (`PARGS.nas_check_on) begin
43307 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 2, 52, value);
43308 tid = 2
43309; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43310 end
43311`endif
43312
43313`endif
43314
43315`endif
43316
43317 end
43318 endtask
43319
43320
43321 task slam_PhysicalOffset3_core2_thread3;
43322 input [63:0] value;
43323 reg [5:0] tid;
43324 integer junk;
43325
43326 begin
43327`ifdef AXIS_EMUL_COSIM
43328//Do Nothing
43329`else
43330`ifdef GATESIM
43331//Do Nothing
43332`else
43333`ifdef CORE_2
43334 if (`PARGS.nas_check_on) begin
43335 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 3, 52, value);
43336 tid = 3
43337; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43338 end
43339`endif
43340
43341`endif
43342
43343`endif
43344
43345 end
43346 endtask
43347
43348
43349 task slam_PhysicalOffset3_core2_thread4;
43350 input [63:0] value;
43351 reg [5:0] tid;
43352 integer junk;
43353
43354 begin
43355`ifdef AXIS_EMUL_COSIM
43356//Do Nothing
43357`else
43358`ifdef GATESIM
43359//Do Nothing
43360`else
43361`ifdef CORE_2
43362 if (`PARGS.nas_check_on) begin
43363 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 4, 52, value);
43364 tid = 4
43365; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43366 end
43367`endif
43368
43369`endif
43370
43371`endif
43372
43373 end
43374 endtask
43375
43376
43377 task slam_PhysicalOffset3_core2_thread5;
43378 input [63:0] value;
43379 reg [5:0] tid;
43380 integer junk;
43381
43382 begin
43383`ifdef AXIS_EMUL_COSIM
43384//Do Nothing
43385`else
43386`ifdef GATESIM
43387//Do Nothing
43388`else
43389`ifdef CORE_2
43390 if (`PARGS.nas_check_on) begin
43391 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 5, 52, value);
43392 tid = 5
43393; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43394 end
43395`endif
43396
43397`endif
43398
43399`endif
43400
43401 end
43402 endtask
43403
43404
43405 task slam_PhysicalOffset3_core2_thread6;
43406 input [63:0] value;
43407 reg [5:0] tid;
43408 integer junk;
43409
43410 begin
43411`ifdef AXIS_EMUL_COSIM
43412//Do Nothing
43413`else
43414`ifdef GATESIM
43415//Do Nothing
43416`else
43417`ifdef CORE_2
43418 if (`PARGS.nas_check_on) begin
43419 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 6, 52, value);
43420 tid = 6
43421; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43422 end
43423`endif
43424
43425`endif
43426
43427`endif
43428
43429 end
43430 endtask
43431
43432
43433 task slam_PhysicalOffset3_core2_thread7;
43434 input [63:0] value;
43435 reg [5:0] tid;
43436 integer junk;
43437
43438 begin
43439`ifdef AXIS_EMUL_COSIM
43440//Do Nothing
43441`else
43442`ifdef GATESIM
43443//Do Nothing
43444`else
43445`ifdef CORE_2
43446 if (`PARGS.nas_check_on) begin
43447 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 2, 7, 52, value);
43448 tid = 7
43449; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43450 end
43451`endif
43452
43453`endif
43454
43455`endif
43456
43457 end
43458 endtask
43459
43460
43461 task slam_PhysicalOffset3_core3_thread0;
43462 input [63:0] value;
43463 reg [5:0] tid;
43464 integer junk;
43465
43466 begin
43467`ifdef AXIS_EMUL_COSIM
43468//Do Nothing
43469`else
43470`ifdef GATESIM
43471//Do Nothing
43472`else
43473`ifdef CORE_3
43474 if (`PARGS.nas_check_on) begin
43475 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 0, 52, value);
43476 tid = 0
43477; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43478 end
43479`endif
43480
43481`endif
43482
43483`endif
43484
43485 end
43486 endtask
43487
43488
43489 task slam_PhysicalOffset3_core3_thread1;
43490 input [63:0] value;
43491 reg [5:0] tid;
43492 integer junk;
43493
43494 begin
43495`ifdef AXIS_EMUL_COSIM
43496//Do Nothing
43497`else
43498`ifdef GATESIM
43499//Do Nothing
43500`else
43501`ifdef CORE_3
43502 if (`PARGS.nas_check_on) begin
43503 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 1, 52, value);
43504 tid = 1
43505; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43506 end
43507`endif
43508
43509`endif
43510
43511`endif
43512
43513 end
43514 endtask
43515
43516
43517 task slam_PhysicalOffset3_core3_thread2;
43518 input [63:0] value;
43519 reg [5:0] tid;
43520 integer junk;
43521
43522 begin
43523`ifdef AXIS_EMUL_COSIM
43524//Do Nothing
43525`else
43526`ifdef GATESIM
43527//Do Nothing
43528`else
43529`ifdef CORE_3
43530 if (`PARGS.nas_check_on) begin
43531 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 2, 52, value);
43532 tid = 2
43533; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43534 end
43535`endif
43536
43537`endif
43538
43539`endif
43540
43541 end
43542 endtask
43543
43544
43545 task slam_PhysicalOffset3_core3_thread3;
43546 input [63:0] value;
43547 reg [5:0] tid;
43548 integer junk;
43549
43550 begin
43551`ifdef AXIS_EMUL_COSIM
43552//Do Nothing
43553`else
43554`ifdef GATESIM
43555//Do Nothing
43556`else
43557`ifdef CORE_3
43558 if (`PARGS.nas_check_on) begin
43559 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 3, 52, value);
43560 tid = 3
43561; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43562 end
43563`endif
43564
43565`endif
43566
43567`endif
43568
43569 end
43570 endtask
43571
43572
43573 task slam_PhysicalOffset3_core3_thread4;
43574 input [63:0] value;
43575 reg [5:0] tid;
43576 integer junk;
43577
43578 begin
43579`ifdef AXIS_EMUL_COSIM
43580//Do Nothing
43581`else
43582`ifdef GATESIM
43583//Do Nothing
43584`else
43585`ifdef CORE_3
43586 if (`PARGS.nas_check_on) begin
43587 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 4, 52, value);
43588 tid = 4
43589; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43590 end
43591`endif
43592
43593`endif
43594
43595`endif
43596
43597 end
43598 endtask
43599
43600
43601 task slam_PhysicalOffset3_core3_thread5;
43602 input [63:0] value;
43603 reg [5:0] tid;
43604 integer junk;
43605
43606 begin
43607`ifdef AXIS_EMUL_COSIM
43608//Do Nothing
43609`else
43610`ifdef GATESIM
43611//Do Nothing
43612`else
43613`ifdef CORE_3
43614 if (`PARGS.nas_check_on) begin
43615 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 5, 52, value);
43616 tid = 5
43617; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43618 end
43619`endif
43620
43621`endif
43622
43623`endif
43624
43625 end
43626 endtask
43627
43628
43629 task slam_PhysicalOffset3_core3_thread6;
43630 input [63:0] value;
43631 reg [5:0] tid;
43632 integer junk;
43633
43634 begin
43635`ifdef AXIS_EMUL_COSIM
43636//Do Nothing
43637`else
43638`ifdef GATESIM
43639//Do Nothing
43640`else
43641`ifdef CORE_3
43642 if (`PARGS.nas_check_on) begin
43643 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 6, 52, value);
43644 tid = 6
43645; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43646 end
43647`endif
43648
43649`endif
43650
43651`endif
43652
43653 end
43654 endtask
43655
43656
43657 task slam_PhysicalOffset3_core3_thread7;
43658 input [63:0] value;
43659 reg [5:0] tid;
43660 integer junk;
43661
43662 begin
43663`ifdef AXIS_EMUL_COSIM
43664//Do Nothing
43665`else
43666`ifdef GATESIM
43667//Do Nothing
43668`else
43669`ifdef CORE_3
43670 if (`PARGS.nas_check_on) begin
43671 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 3, 7, 52, value);
43672 tid = 7
43673; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43674 end
43675`endif
43676
43677`endif
43678
43679`endif
43680
43681 end
43682 endtask
43683
43684
43685 task slam_PhysicalOffset3_core4_thread0;
43686 input [63:0] value;
43687 reg [5:0] tid;
43688 integer junk;
43689
43690 begin
43691`ifdef AXIS_EMUL_COSIM
43692//Do Nothing
43693`else
43694`ifdef GATESIM
43695//Do Nothing
43696`else
43697`ifdef CORE_4
43698 if (`PARGS.nas_check_on) begin
43699 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 0, 52, value);
43700 tid = 0
43701; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43702 end
43703`endif
43704
43705`endif
43706
43707`endif
43708
43709 end
43710 endtask
43711
43712
43713 task slam_PhysicalOffset3_core4_thread1;
43714 input [63:0] value;
43715 reg [5:0] tid;
43716 integer junk;
43717
43718 begin
43719`ifdef AXIS_EMUL_COSIM
43720//Do Nothing
43721`else
43722`ifdef GATESIM
43723//Do Nothing
43724`else
43725`ifdef CORE_4
43726 if (`PARGS.nas_check_on) begin
43727 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 1, 52, value);
43728 tid = 1
43729; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43730 end
43731`endif
43732
43733`endif
43734
43735`endif
43736
43737 end
43738 endtask
43739
43740
43741 task slam_PhysicalOffset3_core4_thread2;
43742 input [63:0] value;
43743 reg [5:0] tid;
43744 integer junk;
43745
43746 begin
43747`ifdef AXIS_EMUL_COSIM
43748//Do Nothing
43749`else
43750`ifdef GATESIM
43751//Do Nothing
43752`else
43753`ifdef CORE_4
43754 if (`PARGS.nas_check_on) begin
43755 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 2, 52, value);
43756 tid = 2
43757; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43758 end
43759`endif
43760
43761`endif
43762
43763`endif
43764
43765 end
43766 endtask
43767
43768
43769 task slam_PhysicalOffset3_core4_thread3;
43770 input [63:0] value;
43771 reg [5:0] tid;
43772 integer junk;
43773
43774 begin
43775`ifdef AXIS_EMUL_COSIM
43776//Do Nothing
43777`else
43778`ifdef GATESIM
43779//Do Nothing
43780`else
43781`ifdef CORE_4
43782 if (`PARGS.nas_check_on) begin
43783 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 3, 52, value);
43784 tid = 3
43785; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43786 end
43787`endif
43788
43789`endif
43790
43791`endif
43792
43793 end
43794 endtask
43795
43796
43797 task slam_PhysicalOffset3_core4_thread4;
43798 input [63:0] value;
43799 reg [5:0] tid;
43800 integer junk;
43801
43802 begin
43803`ifdef AXIS_EMUL_COSIM
43804//Do Nothing
43805`else
43806`ifdef GATESIM
43807//Do Nothing
43808`else
43809`ifdef CORE_4
43810 if (`PARGS.nas_check_on) begin
43811 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 4, 52, value);
43812 tid = 4
43813; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43814 end
43815`endif
43816
43817`endif
43818
43819`endif
43820
43821 end
43822 endtask
43823
43824
43825 task slam_PhysicalOffset3_core4_thread5;
43826 input [63:0] value;
43827 reg [5:0] tid;
43828 integer junk;
43829
43830 begin
43831`ifdef AXIS_EMUL_COSIM
43832//Do Nothing
43833`else
43834`ifdef GATESIM
43835//Do Nothing
43836`else
43837`ifdef CORE_4
43838 if (`PARGS.nas_check_on) begin
43839 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 5, 52, value);
43840 tid = 5
43841; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43842 end
43843`endif
43844
43845`endif
43846
43847`endif
43848
43849 end
43850 endtask
43851
43852
43853 task slam_PhysicalOffset3_core4_thread6;
43854 input [63:0] value;
43855 reg [5:0] tid;
43856 integer junk;
43857
43858 begin
43859`ifdef AXIS_EMUL_COSIM
43860//Do Nothing
43861`else
43862`ifdef GATESIM
43863//Do Nothing
43864`else
43865`ifdef CORE_4
43866 if (`PARGS.nas_check_on) begin
43867 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 6, 52, value);
43868 tid = 6
43869; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43870 end
43871`endif
43872
43873`endif
43874
43875`endif
43876
43877 end
43878 endtask
43879
43880
43881 task slam_PhysicalOffset3_core4_thread7;
43882 input [63:0] value;
43883 reg [5:0] tid;
43884 integer junk;
43885
43886 begin
43887`ifdef AXIS_EMUL_COSIM
43888//Do Nothing
43889`else
43890`ifdef GATESIM
43891//Do Nothing
43892`else
43893`ifdef CORE_4
43894 if (`PARGS.nas_check_on) begin
43895 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 4, 7, 52, value);
43896 tid = 7
43897; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43898 end
43899`endif
43900
43901`endif
43902
43903`endif
43904
43905 end
43906 endtask
43907
43908
43909 task slam_PhysicalOffset3_core5_thread0;
43910 input [63:0] value;
43911 reg [5:0] tid;
43912 integer junk;
43913
43914 begin
43915`ifdef AXIS_EMUL_COSIM
43916//Do Nothing
43917`else
43918`ifdef GATESIM
43919//Do Nothing
43920`else
43921`ifdef CORE_5
43922 if (`PARGS.nas_check_on) begin
43923 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 0, 52, value);
43924 tid = 0
43925; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43926 end
43927`endif
43928
43929`endif
43930
43931`endif
43932
43933 end
43934 endtask
43935
43936
43937 task slam_PhysicalOffset3_core5_thread1;
43938 input [63:0] value;
43939 reg [5:0] tid;
43940 integer junk;
43941
43942 begin
43943`ifdef AXIS_EMUL_COSIM
43944//Do Nothing
43945`else
43946`ifdef GATESIM
43947//Do Nothing
43948`else
43949`ifdef CORE_5
43950 if (`PARGS.nas_check_on) begin
43951 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 1, 52, value);
43952 tid = 1
43953; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43954 end
43955`endif
43956
43957`endif
43958
43959`endif
43960
43961 end
43962 endtask
43963
43964
43965 task slam_PhysicalOffset3_core5_thread2;
43966 input [63:0] value;
43967 reg [5:0] tid;
43968 integer junk;
43969
43970 begin
43971`ifdef AXIS_EMUL_COSIM
43972//Do Nothing
43973`else
43974`ifdef GATESIM
43975//Do Nothing
43976`else
43977`ifdef CORE_5
43978 if (`PARGS.nas_check_on) begin
43979 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 2, 52, value);
43980 tid = 2
43981; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
43982 end
43983`endif
43984
43985`endif
43986
43987`endif
43988
43989 end
43990 endtask
43991
43992
43993 task slam_PhysicalOffset3_core5_thread3;
43994 input [63:0] value;
43995 reg [5:0] tid;
43996 integer junk;
43997
43998 begin
43999`ifdef AXIS_EMUL_COSIM
44000//Do Nothing
44001`else
44002`ifdef GATESIM
44003//Do Nothing
44004`else
44005`ifdef CORE_5
44006 if (`PARGS.nas_check_on) begin
44007 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 3, 52, value);
44008 tid = 3
44009; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44010 end
44011`endif
44012
44013`endif
44014
44015`endif
44016
44017 end
44018 endtask
44019
44020
44021 task slam_PhysicalOffset3_core5_thread4;
44022 input [63:0] value;
44023 reg [5:0] tid;
44024 integer junk;
44025
44026 begin
44027`ifdef AXIS_EMUL_COSIM
44028//Do Nothing
44029`else
44030`ifdef GATESIM
44031//Do Nothing
44032`else
44033`ifdef CORE_5
44034 if (`PARGS.nas_check_on) begin
44035 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 4, 52, value);
44036 tid = 4
44037; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44038 end
44039`endif
44040
44041`endif
44042
44043`endif
44044
44045 end
44046 endtask
44047
44048
44049 task slam_PhysicalOffset3_core5_thread5;
44050 input [63:0] value;
44051 reg [5:0] tid;
44052 integer junk;
44053
44054 begin
44055`ifdef AXIS_EMUL_COSIM
44056//Do Nothing
44057`else
44058`ifdef GATESIM
44059//Do Nothing
44060`else
44061`ifdef CORE_5
44062 if (`PARGS.nas_check_on) begin
44063 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 5, 52, value);
44064 tid = 5
44065; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44066 end
44067`endif
44068
44069`endif
44070
44071`endif
44072
44073 end
44074 endtask
44075
44076
44077 task slam_PhysicalOffset3_core5_thread6;
44078 input [63:0] value;
44079 reg [5:0] tid;
44080 integer junk;
44081
44082 begin
44083`ifdef AXIS_EMUL_COSIM
44084//Do Nothing
44085`else
44086`ifdef GATESIM
44087//Do Nothing
44088`else
44089`ifdef CORE_5
44090 if (`PARGS.nas_check_on) begin
44091 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 6, 52, value);
44092 tid = 6
44093; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44094 end
44095`endif
44096
44097`endif
44098
44099`endif
44100
44101 end
44102 endtask
44103
44104
44105 task slam_PhysicalOffset3_core5_thread7;
44106 input [63:0] value;
44107 reg [5:0] tid;
44108 integer junk;
44109
44110 begin
44111`ifdef AXIS_EMUL_COSIM
44112//Do Nothing
44113`else
44114`ifdef GATESIM
44115//Do Nothing
44116`else
44117`ifdef CORE_5
44118 if (`PARGS.nas_check_on) begin
44119 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 5, 7, 52, value);
44120 tid = 7
44121; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44122 end
44123`endif
44124
44125`endif
44126
44127`endif
44128
44129 end
44130 endtask
44131
44132
44133 task slam_PhysicalOffset3_core6_thread0;
44134 input [63:0] value;
44135 reg [5:0] tid;
44136 integer junk;
44137
44138 begin
44139`ifdef AXIS_EMUL_COSIM
44140//Do Nothing
44141`else
44142`ifdef GATESIM
44143//Do Nothing
44144`else
44145`ifdef CORE_6
44146 if (`PARGS.nas_check_on) begin
44147 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 0, 52, value);
44148 tid = 0
44149; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44150 end
44151`endif
44152
44153`endif
44154
44155`endif
44156
44157 end
44158 endtask
44159
44160
44161 task slam_PhysicalOffset3_core6_thread1;
44162 input [63:0] value;
44163 reg [5:0] tid;
44164 integer junk;
44165
44166 begin
44167`ifdef AXIS_EMUL_COSIM
44168//Do Nothing
44169`else
44170`ifdef GATESIM
44171//Do Nothing
44172`else
44173`ifdef CORE_6
44174 if (`PARGS.nas_check_on) begin
44175 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 1, 52, value);
44176 tid = 1
44177; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44178 end
44179`endif
44180
44181`endif
44182
44183`endif
44184
44185 end
44186 endtask
44187
44188
44189 task slam_PhysicalOffset3_core6_thread2;
44190 input [63:0] value;
44191 reg [5:0] tid;
44192 integer junk;
44193
44194 begin
44195`ifdef AXIS_EMUL_COSIM
44196//Do Nothing
44197`else
44198`ifdef GATESIM
44199//Do Nothing
44200`else
44201`ifdef CORE_6
44202 if (`PARGS.nas_check_on) begin
44203 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 2, 52, value);
44204 tid = 2
44205; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44206 end
44207`endif
44208
44209`endif
44210
44211`endif
44212
44213 end
44214 endtask
44215
44216
44217 task slam_PhysicalOffset3_core6_thread3;
44218 input [63:0] value;
44219 reg [5:0] tid;
44220 integer junk;
44221
44222 begin
44223`ifdef AXIS_EMUL_COSIM
44224//Do Nothing
44225`else
44226`ifdef GATESIM
44227//Do Nothing
44228`else
44229`ifdef CORE_6
44230 if (`PARGS.nas_check_on) begin
44231 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 3, 52, value);
44232 tid = 3
44233; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44234 end
44235`endif
44236
44237`endif
44238
44239`endif
44240
44241 end
44242 endtask
44243
44244
44245 task slam_PhysicalOffset3_core6_thread4;
44246 input [63:0] value;
44247 reg [5:0] tid;
44248 integer junk;
44249
44250 begin
44251`ifdef AXIS_EMUL_COSIM
44252//Do Nothing
44253`else
44254`ifdef GATESIM
44255//Do Nothing
44256`else
44257`ifdef CORE_6
44258 if (`PARGS.nas_check_on) begin
44259 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 4, 52, value);
44260 tid = 4
44261; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44262 end
44263`endif
44264
44265`endif
44266
44267`endif
44268
44269 end
44270 endtask
44271
44272
44273 task slam_PhysicalOffset3_core6_thread5;
44274 input [63:0] value;
44275 reg [5:0] tid;
44276 integer junk;
44277
44278 begin
44279`ifdef AXIS_EMUL_COSIM
44280//Do Nothing
44281`else
44282`ifdef GATESIM
44283//Do Nothing
44284`else
44285`ifdef CORE_6
44286 if (`PARGS.nas_check_on) begin
44287 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 5, 52, value);
44288 tid = 5
44289; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44290 end
44291`endif
44292
44293`endif
44294
44295`endif
44296
44297 end
44298 endtask
44299
44300
44301 task slam_PhysicalOffset3_core6_thread6;
44302 input [63:0] value;
44303 reg [5:0] tid;
44304 integer junk;
44305
44306 begin
44307`ifdef AXIS_EMUL_COSIM
44308//Do Nothing
44309`else
44310`ifdef GATESIM
44311//Do Nothing
44312`else
44313`ifdef CORE_6
44314 if (`PARGS.nas_check_on) begin
44315 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 6, 52, value);
44316 tid = 6
44317; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44318 end
44319`endif
44320
44321`endif
44322
44323`endif
44324
44325 end
44326 endtask
44327
44328
44329 task slam_PhysicalOffset3_core6_thread7;
44330 input [63:0] value;
44331 reg [5:0] tid;
44332 integer junk;
44333
44334 begin
44335`ifdef AXIS_EMUL_COSIM
44336//Do Nothing
44337`else
44338`ifdef GATESIM
44339//Do Nothing
44340`else
44341`ifdef CORE_6
44342 if (`PARGS.nas_check_on) begin
44343 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 6, 7, 52, value);
44344 tid = 7
44345; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44346 end
44347`endif
44348
44349`endif
44350
44351`endif
44352
44353 end
44354 endtask
44355
44356
44357 task slam_PhysicalOffset3_core7_thread0;
44358 input [63:0] value;
44359 reg [5:0] tid;
44360 integer junk;
44361
44362 begin
44363`ifdef AXIS_EMUL_COSIM
44364//Do Nothing
44365`else
44366`ifdef GATESIM
44367//Do Nothing
44368`else
44369`ifdef CORE_7
44370 if (`PARGS.nas_check_on) begin
44371 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 0, 52, value);
44372 tid = 0
44373; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44374 end
44375`endif
44376
44377`endif
44378
44379`endif
44380
44381 end
44382 endtask
44383
44384
44385 task slam_PhysicalOffset3_core7_thread1;
44386 input [63:0] value;
44387 reg [5:0] tid;
44388 integer junk;
44389
44390 begin
44391`ifdef AXIS_EMUL_COSIM
44392//Do Nothing
44393`else
44394`ifdef GATESIM
44395//Do Nothing
44396`else
44397`ifdef CORE_7
44398 if (`PARGS.nas_check_on) begin
44399 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 1, 52, value);
44400 tid = 1
44401; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44402 end
44403`endif
44404
44405`endif
44406
44407`endif
44408
44409 end
44410 endtask
44411
44412
44413 task slam_PhysicalOffset3_core7_thread2;
44414 input [63:0] value;
44415 reg [5:0] tid;
44416 integer junk;
44417
44418 begin
44419`ifdef AXIS_EMUL_COSIM
44420//Do Nothing
44421`else
44422`ifdef GATESIM
44423//Do Nothing
44424`else
44425`ifdef CORE_7
44426 if (`PARGS.nas_check_on) begin
44427 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 2, 52, value);
44428 tid = 2
44429; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44430 end
44431`endif
44432
44433`endif
44434
44435`endif
44436
44437 end
44438 endtask
44439
44440
44441 task slam_PhysicalOffset3_core7_thread3;
44442 input [63:0] value;
44443 reg [5:0] tid;
44444 integer junk;
44445
44446 begin
44447`ifdef AXIS_EMUL_COSIM
44448//Do Nothing
44449`else
44450`ifdef GATESIM
44451//Do Nothing
44452`else
44453`ifdef CORE_7
44454 if (`PARGS.nas_check_on) begin
44455 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 3, 52, value);
44456 tid = 3
44457; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44458 end
44459`endif
44460
44461`endif
44462
44463`endif
44464
44465 end
44466 endtask
44467
44468
44469 task slam_PhysicalOffset3_core7_thread4;
44470 input [63:0] value;
44471 reg [5:0] tid;
44472 integer junk;
44473
44474 begin
44475`ifdef AXIS_EMUL_COSIM
44476//Do Nothing
44477`else
44478`ifdef GATESIM
44479//Do Nothing
44480`else
44481`ifdef CORE_7
44482 if (`PARGS.nas_check_on) begin
44483 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 4, 52, value);
44484 tid = 4
44485; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44486 end
44487`endif
44488
44489`endif
44490
44491`endif
44492
44493 end
44494 endtask
44495
44496
44497 task slam_PhysicalOffset3_core7_thread5;
44498 input [63:0] value;
44499 reg [5:0] tid;
44500 integer junk;
44501
44502 begin
44503`ifdef AXIS_EMUL_COSIM
44504//Do Nothing
44505`else
44506`ifdef GATESIM
44507//Do Nothing
44508`else
44509`ifdef CORE_7
44510 if (`PARGS.nas_check_on) begin
44511 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 5, 52, value);
44512 tid = 5
44513; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44514 end
44515`endif
44516
44517`endif
44518
44519`endif
44520
44521 end
44522 endtask
44523
44524
44525 task slam_PhysicalOffset3_core7_thread6;
44526 input [63:0] value;
44527 reg [5:0] tid;
44528 integer junk;
44529
44530 begin
44531`ifdef AXIS_EMUL_COSIM
44532//Do Nothing
44533`else
44534`ifdef GATESIM
44535//Do Nothing
44536`else
44537`ifdef CORE_7
44538 if (`PARGS.nas_check_on) begin
44539 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 6, 52, value);
44540 tid = 6
44541; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44542 end
44543`endif
44544
44545`endif
44546
44547`endif
44548
44549 end
44550 endtask
44551
44552
44553 task slam_PhysicalOffset3_core7_thread7;
44554 input [63:0] value;
44555 reg [5:0] tid;
44556 integer junk;
44557
44558 begin
44559`ifdef AXIS_EMUL_COSIM
44560//Do Nothing
44561`else
44562`ifdef GATESIM
44563//Do Nothing
44564`else
44565`ifdef CORE_7
44566 if (`PARGS.nas_check_on) begin
44567 `PR_INFO("pli_reg_slam", `INFO, "C%0d T%0d PLI_ASI_WRITE ASI=0x%h VA=0x52 val=0x%h", 7, 7, 52, value);
44568 tid = 7
44569; junk = $sim_send(`PLI_ASI_WRITE, tid, 8'h52, 64'h220, value);
44570 end
44571`endif
44572
44573`endif
44574
44575`endif
44576
44577 end
44578 endtask
44579
44580
44581 task slam_HwTwEnableConfig_core0_thread0;
44582 input [63:0] value;
44583 reg [5:0] tid;
44584 integer junk;
44585
44586 begin
44587`ifdef AXIS_EMUL_COSIM
44588//Do Nothing
44589`else
44590`ifdef GATESIM
44591//Do Nothing
44592`else
44593`ifdef CORE_0
44594 @(posedge `SPC0.mmu.asi.l1clk_pm1);
44595 force `SPC0.mmu.asi.t0_e_nz_in = value[3:0];
44596 force `SPC0.mmu.asi.t0_e_z_in = value[7:4];
44597 force `SPC0.mmu.asi.t1_e_nz_in = value[11:8];
44598 force `SPC0.mmu.asi.t1_e_z_in = value[15:12];
44599 force `SPC0.mmu.asi.t2_e_nz_in = value[19:16];
44600 force `SPC0.mmu.asi.t2_e_z_in = value[23:20];
44601 force `SPC0.mmu.asi.t3_e_nz_in = value[27:24];
44602 force `SPC0.mmu.asi.t3_e_z_in = value[31:28];
44603 force `SPC0.mmu.asi.t4_e_nz_in = value[35:32];
44604 force `SPC0.mmu.asi.t4_e_z_in = value[39:36];
44605 force `SPC0.mmu.asi.t5_e_nz_in = value[43:40];
44606 force `SPC0.mmu.asi.t5_e_z_in = value[47:44];
44607 force `SPC0.mmu.asi.t6_e_nz_in = value[51:48];
44608 force `SPC0.mmu.asi.t6_e_z_in = value[55:52];
44609 force `SPC0.mmu.asi.t7_e_nz_in = value[59:56];
44610 force `SPC0.mmu.asi.t7_e_z_in = value[63:60];
44611 force `SPC0.mmu.asi.t0_e_nz = value[3:0];
44612 force `SPC0.mmu.asi.t0_e_z = value[7:4];
44613 force `SPC0.mmu.asi.t1_e_nz = value[11:8];
44614 force `SPC0.mmu.asi.t1_e_z = value[15:12];
44615 force `SPC0.mmu.asi.t2_e_nz = value[19:16];
44616 force `SPC0.mmu.asi.t2_e_z = value[23:20];
44617 force `SPC0.mmu.asi.t3_e_nz = value[27:24];
44618 force `SPC0.mmu.asi.t3_e_z = value[31:28];
44619 force `SPC0.mmu.asi.t4_e_nz = value[35:32];
44620 force `SPC0.mmu.asi.t4_e_z = value[39:36];
44621 force `SPC0.mmu.asi.t5_e_nz = value[43:40];
44622 force `SPC0.mmu.asi.t5_e_z = value[47:44];
44623 force `SPC0.mmu.asi.t6_e_nz = value[51:48];
44624 force `SPC0.mmu.asi.t6_e_z = value[55:52];
44625 force `SPC0.mmu.asi.t7_e_nz = value[59:56];
44626 force `SPC0.mmu.asi.t7_e_z = value[63:60];
44627 @(posedge `SPC0.mmu.asi.l1clk_pm1);
44628 release `SPC0.mmu.asi.t0_e_nz_in;
44629 release `SPC0.mmu.asi.t0_e_z_in;
44630 release `SPC0.mmu.asi.t1_e_nz_in;
44631 release `SPC0.mmu.asi.t1_e_z_in;
44632 release `SPC0.mmu.asi.t2_e_nz_in;
44633 release `SPC0.mmu.asi.t2_e_z_in;
44634 release `SPC0.mmu.asi.t3_e_nz_in;
44635 release `SPC0.mmu.asi.t3_e_z_in;
44636 release `SPC0.mmu.asi.t4_e_nz_in;
44637 release `SPC0.mmu.asi.t4_e_z_in;
44638 release `SPC0.mmu.asi.t5_e_nz_in;
44639 release `SPC0.mmu.asi.t5_e_z_in;
44640 release `SPC0.mmu.asi.t6_e_nz_in;
44641 release `SPC0.mmu.asi.t6_e_z_in;
44642 release `SPC0.mmu.asi.t7_e_nz_in;
44643 release `SPC0.mmu.asi.t7_e_z_in;
44644 release `SPC0.mmu.asi.t0_e_nz;
44645 release `SPC0.mmu.asi.t0_e_z;
44646 release `SPC0.mmu.asi.t1_e_nz;
44647 release `SPC0.mmu.asi.t1_e_z;
44648 release `SPC0.mmu.asi.t2_e_nz;
44649 release `SPC0.mmu.asi.t2_e_z;
44650 release `SPC0.mmu.asi.t3_e_nz;
44651 release `SPC0.mmu.asi.t3_e_z;
44652 release `SPC0.mmu.asi.t4_e_nz;
44653 release `SPC0.mmu.asi.t4_e_z;
44654 release `SPC0.mmu.asi.t5_e_nz;
44655 release `SPC0.mmu.asi.t5_e_z;
44656 release `SPC0.mmu.asi.t6_e_nz;
44657 release `SPC0.mmu.asi.t6_e_z;
44658 release `SPC0.mmu.asi.t7_e_nz;
44659 release `SPC0.mmu.asi.t7_e_z;
44660`endif
44661
44662`endif
44663
44664`endif
44665
44666 end
44667 endtask
44668
44669
44670 task slam_HwTwEnableConfig_core1_thread0;
44671 input [63:0] value;
44672 reg [5:0] tid;
44673 integer junk;
44674
44675 begin
44676`ifdef AXIS_EMUL_COSIM
44677//Do Nothing
44678`else
44679`ifdef GATESIM
44680//Do Nothing
44681`else
44682`ifdef CORE_1
44683 @(posedge `SPC1.mmu.asi.l1clk_pm1);
44684 force `SPC1.mmu.asi.t0_e_nz_in = value[3:0];
44685 force `SPC1.mmu.asi.t0_e_z_in = value[7:4];
44686 force `SPC1.mmu.asi.t1_e_nz_in = value[11:8];
44687 force `SPC1.mmu.asi.t1_e_z_in = value[15:12];
44688 force `SPC1.mmu.asi.t2_e_nz_in = value[19:16];
44689 force `SPC1.mmu.asi.t2_e_z_in = value[23:20];
44690 force `SPC1.mmu.asi.t3_e_nz_in = value[27:24];
44691 force `SPC1.mmu.asi.t3_e_z_in = value[31:28];
44692 force `SPC1.mmu.asi.t4_e_nz_in = value[35:32];
44693 force `SPC1.mmu.asi.t4_e_z_in = value[39:36];
44694 force `SPC1.mmu.asi.t5_e_nz_in = value[43:40];
44695 force `SPC1.mmu.asi.t5_e_z_in = value[47:44];
44696 force `SPC1.mmu.asi.t6_e_nz_in = value[51:48];
44697 force `SPC1.mmu.asi.t6_e_z_in = value[55:52];
44698 force `SPC1.mmu.asi.t7_e_nz_in = value[59:56];
44699 force `SPC1.mmu.asi.t7_e_z_in = value[63:60];
44700 force `SPC1.mmu.asi.t0_e_nz = value[3:0];
44701 force `SPC1.mmu.asi.t0_e_z = value[7:4];
44702 force `SPC1.mmu.asi.t1_e_nz = value[11:8];
44703 force `SPC1.mmu.asi.t1_e_z = value[15:12];
44704 force `SPC1.mmu.asi.t2_e_nz = value[19:16];
44705 force `SPC1.mmu.asi.t2_e_z = value[23:20];
44706 force `SPC1.mmu.asi.t3_e_nz = value[27:24];
44707 force `SPC1.mmu.asi.t3_e_z = value[31:28];
44708 force `SPC1.mmu.asi.t4_e_nz = value[35:32];
44709 force `SPC1.mmu.asi.t4_e_z = value[39:36];
44710 force `SPC1.mmu.asi.t5_e_nz = value[43:40];
44711 force `SPC1.mmu.asi.t5_e_z = value[47:44];
44712 force `SPC1.mmu.asi.t6_e_nz = value[51:48];
44713 force `SPC1.mmu.asi.t6_e_z = value[55:52];
44714 force `SPC1.mmu.asi.t7_e_nz = value[59:56];
44715 force `SPC1.mmu.asi.t7_e_z = value[63:60];
44716 @(posedge `SPC1.mmu.asi.l1clk_pm1);
44717 release `SPC1.mmu.asi.t0_e_nz_in;
44718 release `SPC1.mmu.asi.t0_e_z_in;
44719 release `SPC1.mmu.asi.t1_e_nz_in;
44720 release `SPC1.mmu.asi.t1_e_z_in;
44721 release `SPC1.mmu.asi.t2_e_nz_in;
44722 release `SPC1.mmu.asi.t2_e_z_in;
44723 release `SPC1.mmu.asi.t3_e_nz_in;
44724 release `SPC1.mmu.asi.t3_e_z_in;
44725 release `SPC1.mmu.asi.t4_e_nz_in;
44726 release `SPC1.mmu.asi.t4_e_z_in;
44727 release `SPC1.mmu.asi.t5_e_nz_in;
44728 release `SPC1.mmu.asi.t5_e_z_in;
44729 release `SPC1.mmu.asi.t6_e_nz_in;
44730 release `SPC1.mmu.asi.t6_e_z_in;
44731 release `SPC1.mmu.asi.t7_e_nz_in;
44732 release `SPC1.mmu.asi.t7_e_z_in;
44733 release `SPC1.mmu.asi.t0_e_nz;
44734 release `SPC1.mmu.asi.t0_e_z;
44735 release `SPC1.mmu.asi.t1_e_nz;
44736 release `SPC1.mmu.asi.t1_e_z;
44737 release `SPC1.mmu.asi.t2_e_nz;
44738 release `SPC1.mmu.asi.t2_e_z;
44739 release `SPC1.mmu.asi.t3_e_nz;
44740 release `SPC1.mmu.asi.t3_e_z;
44741 release `SPC1.mmu.asi.t4_e_nz;
44742 release `SPC1.mmu.asi.t4_e_z;
44743 release `SPC1.mmu.asi.t5_e_nz;
44744 release `SPC1.mmu.asi.t5_e_z;
44745 release `SPC1.mmu.asi.t6_e_nz;
44746 release `SPC1.mmu.asi.t6_e_z;
44747 release `SPC1.mmu.asi.t7_e_nz;
44748 release `SPC1.mmu.asi.t7_e_z;
44749`endif
44750
44751`endif
44752
44753`endif
44754
44755 end
44756 endtask
44757
44758
44759 task slam_HwTwEnableConfig_core2_thread0;
44760 input [63:0] value;
44761 reg [5:0] tid;
44762 integer junk;
44763
44764 begin
44765`ifdef AXIS_EMUL_COSIM
44766//Do Nothing
44767`else
44768`ifdef GATESIM
44769//Do Nothing
44770`else
44771`ifdef CORE_2
44772 @(posedge `SPC2.mmu.asi.l1clk_pm1);
44773 force `SPC2.mmu.asi.t0_e_nz_in = value[3:0];
44774 force `SPC2.mmu.asi.t0_e_z_in = value[7:4];
44775 force `SPC2.mmu.asi.t1_e_nz_in = value[11:8];
44776 force `SPC2.mmu.asi.t1_e_z_in = value[15:12];
44777 force `SPC2.mmu.asi.t2_e_nz_in = value[19:16];
44778 force `SPC2.mmu.asi.t2_e_z_in = value[23:20];
44779 force `SPC2.mmu.asi.t3_e_nz_in = value[27:24];
44780 force `SPC2.mmu.asi.t3_e_z_in = value[31:28];
44781 force `SPC2.mmu.asi.t4_e_nz_in = value[35:32];
44782 force `SPC2.mmu.asi.t4_e_z_in = value[39:36];
44783 force `SPC2.mmu.asi.t5_e_nz_in = value[43:40];
44784 force `SPC2.mmu.asi.t5_e_z_in = value[47:44];
44785 force `SPC2.mmu.asi.t6_e_nz_in = value[51:48];
44786 force `SPC2.mmu.asi.t6_e_z_in = value[55:52];
44787 force `SPC2.mmu.asi.t7_e_nz_in = value[59:56];
44788 force `SPC2.mmu.asi.t7_e_z_in = value[63:60];
44789 force `SPC2.mmu.asi.t0_e_nz = value[3:0];
44790 force `SPC2.mmu.asi.t0_e_z = value[7:4];
44791 force `SPC2.mmu.asi.t1_e_nz = value[11:8];
44792 force `SPC2.mmu.asi.t1_e_z = value[15:12];
44793 force `SPC2.mmu.asi.t2_e_nz = value[19:16];
44794 force `SPC2.mmu.asi.t2_e_z = value[23:20];
44795 force `SPC2.mmu.asi.t3_e_nz = value[27:24];
44796 force `SPC2.mmu.asi.t3_e_z = value[31:28];
44797 force `SPC2.mmu.asi.t4_e_nz = value[35:32];
44798 force `SPC2.mmu.asi.t4_e_z = value[39:36];
44799 force `SPC2.mmu.asi.t5_e_nz = value[43:40];
44800 force `SPC2.mmu.asi.t5_e_z = value[47:44];
44801 force `SPC2.mmu.asi.t6_e_nz = value[51:48];
44802 force `SPC2.mmu.asi.t6_e_z = value[55:52];
44803 force `SPC2.mmu.asi.t7_e_nz = value[59:56];
44804 force `SPC2.mmu.asi.t7_e_z = value[63:60];
44805 @(posedge `SPC2.mmu.asi.l1clk_pm1);
44806 release `SPC2.mmu.asi.t0_e_nz_in;
44807 release `SPC2.mmu.asi.t0_e_z_in;
44808 release `SPC2.mmu.asi.t1_e_nz_in;
44809 release `SPC2.mmu.asi.t1_e_z_in;
44810 release `SPC2.mmu.asi.t2_e_nz_in;
44811 release `SPC2.mmu.asi.t2_e_z_in;
44812 release `SPC2.mmu.asi.t3_e_nz_in;
44813 release `SPC2.mmu.asi.t3_e_z_in;
44814 release `SPC2.mmu.asi.t4_e_nz_in;
44815 release `SPC2.mmu.asi.t4_e_z_in;
44816 release `SPC2.mmu.asi.t5_e_nz_in;
44817 release `SPC2.mmu.asi.t5_e_z_in;
44818 release `SPC2.mmu.asi.t6_e_nz_in;
44819 release `SPC2.mmu.asi.t6_e_z_in;
44820 release `SPC2.mmu.asi.t7_e_nz_in;
44821 release `SPC2.mmu.asi.t7_e_z_in;
44822 release `SPC2.mmu.asi.t0_e_nz;
44823 release `SPC2.mmu.asi.t0_e_z;
44824 release `SPC2.mmu.asi.t1_e_nz;
44825 release `SPC2.mmu.asi.t1_e_z;
44826 release `SPC2.mmu.asi.t2_e_nz;
44827 release `SPC2.mmu.asi.t2_e_z;
44828 release `SPC2.mmu.asi.t3_e_nz;
44829 release `SPC2.mmu.asi.t3_e_z;
44830 release `SPC2.mmu.asi.t4_e_nz;
44831 release `SPC2.mmu.asi.t4_e_z;
44832 release `SPC2.mmu.asi.t5_e_nz;
44833 release `SPC2.mmu.asi.t5_e_z;
44834 release `SPC2.mmu.asi.t6_e_nz;
44835 release `SPC2.mmu.asi.t6_e_z;
44836 release `SPC2.mmu.asi.t7_e_nz;
44837 release `SPC2.mmu.asi.t7_e_z;
44838`endif
44839
44840`endif
44841
44842`endif
44843
44844 end
44845 endtask
44846
44847
44848 task slam_HwTwEnableConfig_core3_thread0;
44849 input [63:0] value;
44850 reg [5:0] tid;
44851 integer junk;
44852
44853 begin
44854`ifdef AXIS_EMUL_COSIM
44855//Do Nothing
44856`else
44857`ifdef GATESIM
44858//Do Nothing
44859`else
44860`ifdef CORE_3
44861 @(posedge `SPC3.mmu.asi.l1clk_pm1);
44862 force `SPC3.mmu.asi.t0_e_nz_in = value[3:0];
44863 force `SPC3.mmu.asi.t0_e_z_in = value[7:4];
44864 force `SPC3.mmu.asi.t1_e_nz_in = value[11:8];
44865 force `SPC3.mmu.asi.t1_e_z_in = value[15:12];
44866 force `SPC3.mmu.asi.t2_e_nz_in = value[19:16];
44867 force `SPC3.mmu.asi.t2_e_z_in = value[23:20];
44868 force `SPC3.mmu.asi.t3_e_nz_in = value[27:24];
44869 force `SPC3.mmu.asi.t3_e_z_in = value[31:28];
44870 force `SPC3.mmu.asi.t4_e_nz_in = value[35:32];
44871 force `SPC3.mmu.asi.t4_e_z_in = value[39:36];
44872 force `SPC3.mmu.asi.t5_e_nz_in = value[43:40];
44873 force `SPC3.mmu.asi.t5_e_z_in = value[47:44];
44874 force `SPC3.mmu.asi.t6_e_nz_in = value[51:48];
44875 force `SPC3.mmu.asi.t6_e_z_in = value[55:52];
44876 force `SPC3.mmu.asi.t7_e_nz_in = value[59:56];
44877 force `SPC3.mmu.asi.t7_e_z_in = value[63:60];
44878 force `SPC3.mmu.asi.t0_e_nz = value[3:0];
44879 force `SPC3.mmu.asi.t0_e_z = value[7:4];
44880 force `SPC3.mmu.asi.t1_e_nz = value[11:8];
44881 force `SPC3.mmu.asi.t1_e_z = value[15:12];
44882 force `SPC3.mmu.asi.t2_e_nz = value[19:16];
44883 force `SPC3.mmu.asi.t2_e_z = value[23:20];
44884 force `SPC3.mmu.asi.t3_e_nz = value[27:24];
44885 force `SPC3.mmu.asi.t3_e_z = value[31:28];
44886 force `SPC3.mmu.asi.t4_e_nz = value[35:32];
44887 force `SPC3.mmu.asi.t4_e_z = value[39:36];
44888 force `SPC3.mmu.asi.t5_e_nz = value[43:40];
44889 force `SPC3.mmu.asi.t5_e_z = value[47:44];
44890 force `SPC3.mmu.asi.t6_e_nz = value[51:48];
44891 force `SPC3.mmu.asi.t6_e_z = value[55:52];
44892 force `SPC3.mmu.asi.t7_e_nz = value[59:56];
44893 force `SPC3.mmu.asi.t7_e_z = value[63:60];
44894 @(posedge `SPC3.mmu.asi.l1clk_pm1);
44895 release `SPC3.mmu.asi.t0_e_nz_in;
44896 release `SPC3.mmu.asi.t0_e_z_in;
44897 release `SPC3.mmu.asi.t1_e_nz_in;
44898 release `SPC3.mmu.asi.t1_e_z_in;
44899 release `SPC3.mmu.asi.t2_e_nz_in;
44900 release `SPC3.mmu.asi.t2_e_z_in;
44901 release `SPC3.mmu.asi.t3_e_nz_in;
44902 release `SPC3.mmu.asi.t3_e_z_in;
44903 release `SPC3.mmu.asi.t4_e_nz_in;
44904 release `SPC3.mmu.asi.t4_e_z_in;
44905 release `SPC3.mmu.asi.t5_e_nz_in;
44906 release `SPC3.mmu.asi.t5_e_z_in;
44907 release `SPC3.mmu.asi.t6_e_nz_in;
44908 release `SPC3.mmu.asi.t6_e_z_in;
44909 release `SPC3.mmu.asi.t7_e_nz_in;
44910 release `SPC3.mmu.asi.t7_e_z_in;
44911 release `SPC3.mmu.asi.t0_e_nz;
44912 release `SPC3.mmu.asi.t0_e_z;
44913 release `SPC3.mmu.asi.t1_e_nz;
44914 release `SPC3.mmu.asi.t1_e_z;
44915 release `SPC3.mmu.asi.t2_e_nz;
44916 release `SPC3.mmu.asi.t2_e_z;
44917 release `SPC3.mmu.asi.t3_e_nz;
44918 release `SPC3.mmu.asi.t3_e_z;
44919 release `SPC3.mmu.asi.t4_e_nz;
44920 release `SPC3.mmu.asi.t4_e_z;
44921 release `SPC3.mmu.asi.t5_e_nz;
44922 release `SPC3.mmu.asi.t5_e_z;
44923 release `SPC3.mmu.asi.t6_e_nz;
44924 release `SPC3.mmu.asi.t6_e_z;
44925 release `SPC3.mmu.asi.t7_e_nz;
44926 release `SPC3.mmu.asi.t7_e_z;
44927`endif
44928
44929`endif
44930
44931`endif
44932
44933 end
44934 endtask
44935
44936
44937 task slam_HwTwEnableConfig_core4_thread0;
44938 input [63:0] value;
44939 reg [5:0] tid;
44940 integer junk;
44941
44942 begin
44943`ifdef AXIS_EMUL_COSIM
44944//Do Nothing
44945`else
44946`ifdef GATESIM
44947//Do Nothing
44948`else
44949`ifdef CORE_4
44950 @(posedge `SPC4.mmu.asi.l1clk_pm1);
44951 force `SPC4.mmu.asi.t0_e_nz_in = value[3:0];
44952 force `SPC4.mmu.asi.t0_e_z_in = value[7:4];
44953 force `SPC4.mmu.asi.t1_e_nz_in = value[11:8];
44954 force `SPC4.mmu.asi.t1_e_z_in = value[15:12];
44955 force `SPC4.mmu.asi.t2_e_nz_in = value[19:16];
44956 force `SPC4.mmu.asi.t2_e_z_in = value[23:20];
44957 force `SPC4.mmu.asi.t3_e_nz_in = value[27:24];
44958 force `SPC4.mmu.asi.t3_e_z_in = value[31:28];
44959 force `SPC4.mmu.asi.t4_e_nz_in = value[35:32];
44960 force `SPC4.mmu.asi.t4_e_z_in = value[39:36];
44961 force `SPC4.mmu.asi.t5_e_nz_in = value[43:40];
44962 force `SPC4.mmu.asi.t5_e_z_in = value[47:44];
44963 force `SPC4.mmu.asi.t6_e_nz_in = value[51:48];
44964 force `SPC4.mmu.asi.t6_e_z_in = value[55:52];
44965 force `SPC4.mmu.asi.t7_e_nz_in = value[59:56];
44966 force `SPC4.mmu.asi.t7_e_z_in = value[63:60];
44967 force `SPC4.mmu.asi.t0_e_nz = value[3:0];
44968 force `SPC4.mmu.asi.t0_e_z = value[7:4];
44969 force `SPC4.mmu.asi.t1_e_nz = value[11:8];
44970 force `SPC4.mmu.asi.t1_e_z = value[15:12];
44971 force `SPC4.mmu.asi.t2_e_nz = value[19:16];
44972 force `SPC4.mmu.asi.t2_e_z = value[23:20];
44973 force `SPC4.mmu.asi.t3_e_nz = value[27:24];
44974 force `SPC4.mmu.asi.t3_e_z = value[31:28];
44975 force `SPC4.mmu.asi.t4_e_nz = value[35:32];
44976 force `SPC4.mmu.asi.t4_e_z = value[39:36];
44977 force `SPC4.mmu.asi.t5_e_nz = value[43:40];
44978 force `SPC4.mmu.asi.t5_e_z = value[47:44];
44979 force `SPC4.mmu.asi.t6_e_nz = value[51:48];
44980 force `SPC4.mmu.asi.t6_e_z = value[55:52];
44981 force `SPC4.mmu.asi.t7_e_nz = value[59:56];
44982 force `SPC4.mmu.asi.t7_e_z = value[63:60];
44983 @(posedge `SPC4.mmu.asi.l1clk_pm1);
44984 release `SPC4.mmu.asi.t0_e_nz_in;
44985 release `SPC4.mmu.asi.t0_e_z_in;
44986 release `SPC4.mmu.asi.t1_e_nz_in;
44987 release `SPC4.mmu.asi.t1_e_z_in;
44988 release `SPC4.mmu.asi.t2_e_nz_in;
44989 release `SPC4.mmu.asi.t2_e_z_in;
44990 release `SPC4.mmu.asi.t3_e_nz_in;
44991 release `SPC4.mmu.asi.t3_e_z_in;
44992 release `SPC4.mmu.asi.t4_e_nz_in;
44993 release `SPC4.mmu.asi.t4_e_z_in;
44994 release `SPC4.mmu.asi.t5_e_nz_in;
44995 release `SPC4.mmu.asi.t5_e_z_in;
44996 release `SPC4.mmu.asi.t6_e_nz_in;
44997 release `SPC4.mmu.asi.t6_e_z_in;
44998 release `SPC4.mmu.asi.t7_e_nz_in;
44999 release `SPC4.mmu.asi.t7_e_z_in;
45000 release `SPC4.mmu.asi.t0_e_nz;
45001 release `SPC4.mmu.asi.t0_e_z;
45002 release `SPC4.mmu.asi.t1_e_nz;
45003 release `SPC4.mmu.asi.t1_e_z;
45004 release `SPC4.mmu.asi.t2_e_nz;
45005 release `SPC4.mmu.asi.t2_e_z;
45006 release `SPC4.mmu.asi.t3_e_nz;
45007 release `SPC4.mmu.asi.t3_e_z;
45008 release `SPC4.mmu.asi.t4_e_nz;
45009 release `SPC4.mmu.asi.t4_e_z;
45010 release `SPC4.mmu.asi.t5_e_nz;
45011 release `SPC4.mmu.asi.t5_e_z;
45012 release `SPC4.mmu.asi.t6_e_nz;
45013 release `SPC4.mmu.asi.t6_e_z;
45014 release `SPC4.mmu.asi.t7_e_nz;
45015 release `SPC4.mmu.asi.t7_e_z;
45016`endif
45017
45018`endif
45019
45020`endif
45021
45022 end
45023 endtask
45024
45025
45026 task slam_HwTwEnableConfig_core5_thread0;
45027 input [63:0] value;
45028 reg [5:0] tid;
45029 integer junk;
45030
45031 begin
45032`ifdef AXIS_EMUL_COSIM
45033//Do Nothing
45034`else
45035`ifdef GATESIM
45036//Do Nothing
45037`else
45038`ifdef CORE_5
45039 @(posedge `SPC5.mmu.asi.l1clk_pm1);
45040 force `SPC5.mmu.asi.t0_e_nz_in = value[3:0];
45041 force `SPC5.mmu.asi.t0_e_z_in = value[7:4];
45042 force `SPC5.mmu.asi.t1_e_nz_in = value[11:8];
45043 force `SPC5.mmu.asi.t1_e_z_in = value[15:12];
45044 force `SPC5.mmu.asi.t2_e_nz_in = value[19:16];
45045 force `SPC5.mmu.asi.t2_e_z_in = value[23:20];
45046 force `SPC5.mmu.asi.t3_e_nz_in = value[27:24];
45047 force `SPC5.mmu.asi.t3_e_z_in = value[31:28];
45048 force `SPC5.mmu.asi.t4_e_nz_in = value[35:32];
45049 force `SPC5.mmu.asi.t4_e_z_in = value[39:36];
45050 force `SPC5.mmu.asi.t5_e_nz_in = value[43:40];
45051 force `SPC5.mmu.asi.t5_e_z_in = value[47:44];
45052 force `SPC5.mmu.asi.t6_e_nz_in = value[51:48];
45053 force `SPC5.mmu.asi.t6_e_z_in = value[55:52];
45054 force `SPC5.mmu.asi.t7_e_nz_in = value[59:56];
45055 force `SPC5.mmu.asi.t7_e_z_in = value[63:60];
45056 force `SPC5.mmu.asi.t0_e_nz = value[3:0];
45057 force `SPC5.mmu.asi.t0_e_z = value[7:4];
45058 force `SPC5.mmu.asi.t1_e_nz = value[11:8];
45059 force `SPC5.mmu.asi.t1_e_z = value[15:12];
45060 force `SPC5.mmu.asi.t2_e_nz = value[19:16];
45061 force `SPC5.mmu.asi.t2_e_z = value[23:20];
45062 force `SPC5.mmu.asi.t3_e_nz = value[27:24];
45063 force `SPC5.mmu.asi.t3_e_z = value[31:28];
45064 force `SPC5.mmu.asi.t4_e_nz = value[35:32];
45065 force `SPC5.mmu.asi.t4_e_z = value[39:36];
45066 force `SPC5.mmu.asi.t5_e_nz = value[43:40];
45067 force `SPC5.mmu.asi.t5_e_z = value[47:44];
45068 force `SPC5.mmu.asi.t6_e_nz = value[51:48];
45069 force `SPC5.mmu.asi.t6_e_z = value[55:52];
45070 force `SPC5.mmu.asi.t7_e_nz = value[59:56];
45071 force `SPC5.mmu.asi.t7_e_z = value[63:60];
45072 @(posedge `SPC5.mmu.asi.l1clk_pm1);
45073 release `SPC5.mmu.asi.t0_e_nz_in;
45074 release `SPC5.mmu.asi.t0_e_z_in;
45075 release `SPC5.mmu.asi.t1_e_nz_in;
45076 release `SPC5.mmu.asi.t1_e_z_in;
45077 release `SPC5.mmu.asi.t2_e_nz_in;
45078 release `SPC5.mmu.asi.t2_e_z_in;
45079 release `SPC5.mmu.asi.t3_e_nz_in;
45080 release `SPC5.mmu.asi.t3_e_z_in;
45081 release `SPC5.mmu.asi.t4_e_nz_in;
45082 release `SPC5.mmu.asi.t4_e_z_in;
45083 release `SPC5.mmu.asi.t5_e_nz_in;
45084 release `SPC5.mmu.asi.t5_e_z_in;
45085 release `SPC5.mmu.asi.t6_e_nz_in;
45086 release `SPC5.mmu.asi.t6_e_z_in;
45087 release `SPC5.mmu.asi.t7_e_nz_in;
45088 release `SPC5.mmu.asi.t7_e_z_in;
45089 release `SPC5.mmu.asi.t0_e_nz;
45090 release `SPC5.mmu.asi.t0_e_z;
45091 release `SPC5.mmu.asi.t1_e_nz;
45092 release `SPC5.mmu.asi.t1_e_z;
45093 release `SPC5.mmu.asi.t2_e_nz;
45094 release `SPC5.mmu.asi.t2_e_z;
45095 release `SPC5.mmu.asi.t3_e_nz;
45096 release `SPC5.mmu.asi.t3_e_z;
45097 release `SPC5.mmu.asi.t4_e_nz;
45098 release `SPC5.mmu.asi.t4_e_z;
45099 release `SPC5.mmu.asi.t5_e_nz;
45100 release `SPC5.mmu.asi.t5_e_z;
45101 release `SPC5.mmu.asi.t6_e_nz;
45102 release `SPC5.mmu.asi.t6_e_z;
45103 release `SPC5.mmu.asi.t7_e_nz;
45104 release `SPC5.mmu.asi.t7_e_z;
45105`endif
45106
45107`endif
45108
45109`endif
45110
45111 end
45112 endtask
45113
45114
45115 task slam_HwTwEnableConfig_core6_thread0;
45116 input [63:0] value;
45117 reg [5:0] tid;
45118 integer junk;
45119
45120 begin
45121`ifdef AXIS_EMUL_COSIM
45122//Do Nothing
45123`else
45124`ifdef GATESIM
45125//Do Nothing
45126`else
45127`ifdef CORE_6
45128 @(posedge `SPC6.mmu.asi.l1clk_pm1);
45129 force `SPC6.mmu.asi.t0_e_nz_in = value[3:0];
45130 force `SPC6.mmu.asi.t0_e_z_in = value[7:4];
45131 force `SPC6.mmu.asi.t1_e_nz_in = value[11:8];
45132 force `SPC6.mmu.asi.t1_e_z_in = value[15:12];
45133 force `SPC6.mmu.asi.t2_e_nz_in = value[19:16];
45134 force `SPC6.mmu.asi.t2_e_z_in = value[23:20];
45135 force `SPC6.mmu.asi.t3_e_nz_in = value[27:24];
45136 force `SPC6.mmu.asi.t3_e_z_in = value[31:28];
45137 force `SPC6.mmu.asi.t4_e_nz_in = value[35:32];
45138 force `SPC6.mmu.asi.t4_e_z_in = value[39:36];
45139 force `SPC6.mmu.asi.t5_e_nz_in = value[43:40];
45140 force `SPC6.mmu.asi.t5_e_z_in = value[47:44];
45141 force `SPC6.mmu.asi.t6_e_nz_in = value[51:48];
45142 force `SPC6.mmu.asi.t6_e_z_in = value[55:52];
45143 force `SPC6.mmu.asi.t7_e_nz_in = value[59:56];
45144 force `SPC6.mmu.asi.t7_e_z_in = value[63:60];
45145 force `SPC6.mmu.asi.t0_e_nz = value[3:0];
45146 force `SPC6.mmu.asi.t0_e_z = value[7:4];
45147 force `SPC6.mmu.asi.t1_e_nz = value[11:8];
45148 force `SPC6.mmu.asi.t1_e_z = value[15:12];
45149 force `SPC6.mmu.asi.t2_e_nz = value[19:16];
45150 force `SPC6.mmu.asi.t2_e_z = value[23:20];
45151 force `SPC6.mmu.asi.t3_e_nz = value[27:24];
45152 force `SPC6.mmu.asi.t3_e_z = value[31:28];
45153 force `SPC6.mmu.asi.t4_e_nz = value[35:32];
45154 force `SPC6.mmu.asi.t4_e_z = value[39:36];
45155 force `SPC6.mmu.asi.t5_e_nz = value[43:40];
45156 force `SPC6.mmu.asi.t5_e_z = value[47:44];
45157 force `SPC6.mmu.asi.t6_e_nz = value[51:48];
45158 force `SPC6.mmu.asi.t6_e_z = value[55:52];
45159 force `SPC6.mmu.asi.t7_e_nz = value[59:56];
45160 force `SPC6.mmu.asi.t7_e_z = value[63:60];
45161 @(posedge `SPC6.mmu.asi.l1clk_pm1);
45162 release `SPC6.mmu.asi.t0_e_nz_in;
45163 release `SPC6.mmu.asi.t0_e_z_in;
45164 release `SPC6.mmu.asi.t1_e_nz_in;
45165 release `SPC6.mmu.asi.t1_e_z_in;
45166 release `SPC6.mmu.asi.t2_e_nz_in;
45167 release `SPC6.mmu.asi.t2_e_z_in;
45168 release `SPC6.mmu.asi.t3_e_nz_in;
45169 release `SPC6.mmu.asi.t3_e_z_in;
45170 release `SPC6.mmu.asi.t4_e_nz_in;
45171 release `SPC6.mmu.asi.t4_e_z_in;
45172 release `SPC6.mmu.asi.t5_e_nz_in;
45173 release `SPC6.mmu.asi.t5_e_z_in;
45174 release `SPC6.mmu.asi.t6_e_nz_in;
45175 release `SPC6.mmu.asi.t6_e_z_in;
45176 release `SPC6.mmu.asi.t7_e_nz_in;
45177 release `SPC6.mmu.asi.t7_e_z_in;
45178 release `SPC6.mmu.asi.t0_e_nz;
45179 release `SPC6.mmu.asi.t0_e_z;
45180 release `SPC6.mmu.asi.t1_e_nz;
45181 release `SPC6.mmu.asi.t1_e_z;
45182 release `SPC6.mmu.asi.t2_e_nz;
45183 release `SPC6.mmu.asi.t2_e_z;
45184 release `SPC6.mmu.asi.t3_e_nz;
45185 release `SPC6.mmu.asi.t3_e_z;
45186 release `SPC6.mmu.asi.t4_e_nz;
45187 release `SPC6.mmu.asi.t4_e_z;
45188 release `SPC6.mmu.asi.t5_e_nz;
45189 release `SPC6.mmu.asi.t5_e_z;
45190 release `SPC6.mmu.asi.t6_e_nz;
45191 release `SPC6.mmu.asi.t6_e_z;
45192 release `SPC6.mmu.asi.t7_e_nz;
45193 release `SPC6.mmu.asi.t7_e_z;
45194`endif
45195
45196`endif
45197
45198`endif
45199
45200 end
45201 endtask
45202
45203
45204 task slam_HwTwEnableConfig_core7_thread0;
45205 input [63:0] value;
45206 reg [5:0] tid;
45207 integer junk;
45208
45209 begin
45210`ifdef AXIS_EMUL_COSIM
45211//Do Nothing
45212`else
45213`ifdef GATESIM
45214//Do Nothing
45215`else
45216`ifdef CORE_7
45217 @(posedge `SPC7.mmu.asi.l1clk_pm1);
45218 force `SPC7.mmu.asi.t0_e_nz_in = value[3:0];
45219 force `SPC7.mmu.asi.t0_e_z_in = value[7:4];
45220 force `SPC7.mmu.asi.t1_e_nz_in = value[11:8];
45221 force `SPC7.mmu.asi.t1_e_z_in = value[15:12];
45222 force `SPC7.mmu.asi.t2_e_nz_in = value[19:16];
45223 force `SPC7.mmu.asi.t2_e_z_in = value[23:20];
45224 force `SPC7.mmu.asi.t3_e_nz_in = value[27:24];
45225 force `SPC7.mmu.asi.t3_e_z_in = value[31:28];
45226 force `SPC7.mmu.asi.t4_e_nz_in = value[35:32];
45227 force `SPC7.mmu.asi.t4_e_z_in = value[39:36];
45228 force `SPC7.mmu.asi.t5_e_nz_in = value[43:40];
45229 force `SPC7.mmu.asi.t5_e_z_in = value[47:44];
45230 force `SPC7.mmu.asi.t6_e_nz_in = value[51:48];
45231 force `SPC7.mmu.asi.t6_e_z_in = value[55:52];
45232 force `SPC7.mmu.asi.t7_e_nz_in = value[59:56];
45233 force `SPC7.mmu.asi.t7_e_z_in = value[63:60];
45234 force `SPC7.mmu.asi.t0_e_nz = value[3:0];
45235 force `SPC7.mmu.asi.t0_e_z = value[7:4];
45236 force `SPC7.mmu.asi.t1_e_nz = value[11:8];
45237 force `SPC7.mmu.asi.t1_e_z = value[15:12];
45238 force `SPC7.mmu.asi.t2_e_nz = value[19:16];
45239 force `SPC7.mmu.asi.t2_e_z = value[23:20];
45240 force `SPC7.mmu.asi.t3_e_nz = value[27:24];
45241 force `SPC7.mmu.asi.t3_e_z = value[31:28];
45242 force `SPC7.mmu.asi.t4_e_nz = value[35:32];
45243 force `SPC7.mmu.asi.t4_e_z = value[39:36];
45244 force `SPC7.mmu.asi.t5_e_nz = value[43:40];
45245 force `SPC7.mmu.asi.t5_e_z = value[47:44];
45246 force `SPC7.mmu.asi.t6_e_nz = value[51:48];
45247 force `SPC7.mmu.asi.t6_e_z = value[55:52];
45248 force `SPC7.mmu.asi.t7_e_nz = value[59:56];
45249 force `SPC7.mmu.asi.t7_e_z = value[63:60];
45250 @(posedge `SPC7.mmu.asi.l1clk_pm1);
45251 release `SPC7.mmu.asi.t0_e_nz_in;
45252 release `SPC7.mmu.asi.t0_e_z_in;
45253 release `SPC7.mmu.asi.t1_e_nz_in;
45254 release `SPC7.mmu.asi.t1_e_z_in;
45255 release `SPC7.mmu.asi.t2_e_nz_in;
45256 release `SPC7.mmu.asi.t2_e_z_in;
45257 release `SPC7.mmu.asi.t3_e_nz_in;
45258 release `SPC7.mmu.asi.t3_e_z_in;
45259 release `SPC7.mmu.asi.t4_e_nz_in;
45260 release `SPC7.mmu.asi.t4_e_z_in;
45261 release `SPC7.mmu.asi.t5_e_nz_in;
45262 release `SPC7.mmu.asi.t5_e_z_in;
45263 release `SPC7.mmu.asi.t6_e_nz_in;
45264 release `SPC7.mmu.asi.t6_e_z_in;
45265 release `SPC7.mmu.asi.t7_e_nz_in;
45266 release `SPC7.mmu.asi.t7_e_z_in;
45267 release `SPC7.mmu.asi.t0_e_nz;
45268 release `SPC7.mmu.asi.t0_e_z;
45269 release `SPC7.mmu.asi.t1_e_nz;
45270 release `SPC7.mmu.asi.t1_e_z;
45271 release `SPC7.mmu.asi.t2_e_nz;
45272 release `SPC7.mmu.asi.t2_e_z;
45273 release `SPC7.mmu.asi.t3_e_nz;
45274 release `SPC7.mmu.asi.t3_e_z;
45275 release `SPC7.mmu.asi.t4_e_nz;
45276 release `SPC7.mmu.asi.t4_e_z;
45277 release `SPC7.mmu.asi.t5_e_nz;
45278 release `SPC7.mmu.asi.t5_e_z;
45279 release `SPC7.mmu.asi.t6_e_nz;
45280 release `SPC7.mmu.asi.t6_e_z;
45281 release `SPC7.mmu.asi.t7_e_nz;
45282 release `SPC7.mmu.asi.t7_e_z;
45283`endif
45284
45285`endif
45286
45287`endif
45288
45289 end
45290 endtask
45291
45292
45293endmodule
Full OpenSPARC design & verification tarball including full HDL.