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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_mcu_csr_probe.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `include "fc.vh" | |
36 | `include "defines.vh" | |
37 | ||
38 | ||
39 | module fc_mcu_csr_probe; | |
40 | ||
41 | wire [39:0] mcu0_ucb_addr; | |
42 | wire [63:0] mcu0_ucb_data; | |
43 | ||
44 | assign mcu0_ucb_rd_vld = `CPU.mcu0.ucb.ucb_rd_req_vld0; | |
45 | assign mcu0_ucb_rd_accepted = `CPU.mcu0.ucb.mcu_ucb_req_acpted; | |
46 | assign mcu0_ucb_ack_vld = `CPU.mcu0.ucb.mcu_ucb_ack_vld; | |
47 | assign mcu0_ucb_nack_vld = `CPU.mcu0.ucb.mcu_ucb_nack_vld; | |
48 | assign mcu0_ucb_addr = `CPU.mcu0.ucb.addr_in; | |
49 | assign mcu0_ucb_data = `CPU.mcu0.ucb.mcu_ucb_data; | |
50 | assign mcu0_iol2clk = `CPU.mcu0.ucb.iol2clk; | |
51 | ||
52 | ||
53 | ||
54 | ||
55 | ||
56 | mcu_csr_probe mcu0_csr_probe ( .mcu_id(2'b00), .ucb_rd_vld(mcu0_ucb_rd_vld), .ucb_rd_accepted(mcu0_ucb_rd_accepted), .ucb_ack_vld(mcu0_ucb_ack_vld), .ucb_nack_vld(mcu0_ucb_nack_vld), .ucb_addr(mcu0_ucb_addr), .ucb_data(mcu0_ucb_data), .mcu_clk(mcu0_iol2clk)); | |
57 | ||
58 | wire [39:0] mcu1_ucb_addr; | |
59 | wire [63:0] mcu1_ucb_data; | |
60 | ||
61 | assign mcu1_ucb_rd_vld = `CPU.mcu1.ucb.ucb_rd_req_vld0; | |
62 | assign mcu1_ucb_rd_accepted = `CPU.mcu1.ucb.mcu_ucb_req_acpted; | |
63 | assign mcu1_ucb_ack_vld = `CPU.mcu1.ucb.mcu_ucb_ack_vld; | |
64 | assign mcu1_ucb_nack_vld = `CPU.mcu1.ucb.mcu_ucb_nack_vld; | |
65 | assign mcu1_ucb_addr = `CPU.mcu1.ucb.addr_in; | |
66 | assign mcu1_ucb_data = `CPU.mcu1.ucb.mcu_ucb_data; | |
67 | assign mcu1_iol2clk = `CPU.mcu1.ucb.iol2clk; | |
68 | ||
69 | ||
70 | mcu_csr_probe mcu1_csr_probe ( .mcu_id(2'b00), .ucb_rd_vld(mcu1_ucb_rd_vld), .ucb_rd_accepted(mcu1_ucb_rd_accepted), .ucb_ack_vld(mcu1_ucb_ack_vld), .ucb_nack_vld(mcu1_ucb_nack_vld), .ucb_addr(mcu1_ucb_addr), .ucb_data(mcu1_ucb_data), .mcu_clk(mcu1_iol2clk)); | |
71 | ||
72 | wire [39:0] mcu2_ucb_addr; | |
73 | wire [63:0] mcu2_ucb_data; | |
74 | ||
75 | assign mcu2_ucb_rd_vld = `CPU.mcu2.ucb.ucb_rd_req_vld0; | |
76 | assign mcu2_ucb_rd_accepted = `CPU.mcu2.ucb.mcu_ucb_req_acpted; | |
77 | assign mcu2_ucb_ack_vld = `CPU.mcu2.ucb.mcu_ucb_ack_vld; | |
78 | assign mcu2_ucb_nack_vld = `CPU.mcu2.ucb.mcu_ucb_nack_vld; | |
79 | assign mcu2_ucb_addr = `CPU.mcu2.ucb.addr_in; | |
80 | assign mcu2_ucb_data = `CPU.mcu2.ucb.mcu_ucb_data; | |
81 | assign mcu2_iol2clk = `CPU.mcu2.ucb.iol2clk; | |
82 | ||
83 | ||
84 | mcu_csr_probe mcu2_csr_probe ( .mcu_id(2'b00), .ucb_rd_vld(mcu2_ucb_rd_vld), .ucb_rd_accepted(mcu2_ucb_rd_accepted), .ucb_ack_vld(mcu2_ucb_ack_vld), .ucb_nack_vld(mcu2_ucb_nack_vld), .ucb_addr(mcu2_ucb_addr), .ucb_data(mcu2_ucb_data), .mcu_clk(mcu2_iol2clk)); | |
85 | ||
86 | wire [39:0] mcu3_ucb_addr; | |
87 | wire [63:0] mcu3_ucb_data; | |
88 | ||
89 | assign mcu3_ucb_rd_vld = `CPU.mcu3.ucb.ucb_rd_req_vld0; | |
90 | assign mcu3_ucb_rd_accepted = `CPU.mcu3.ucb.mcu_ucb_req_acpted; | |
91 | assign mcu3_ucb_ack_vld = `CPU.mcu3.ucb.mcu_ucb_ack_vld; | |
92 | assign mcu3_ucb_nack_vld = `CPU.mcu3.ucb.mcu_ucb_nack_vld; | |
93 | assign mcu3_ucb_addr = `CPU.mcu3.ucb.addr_in; | |
94 | assign mcu3_ucb_data = `CPU.mcu3.ucb.mcu_ucb_data; | |
95 | assign mcu3_iol2clk = `CPU.mcu3.ucb.iol2clk; | |
96 | ||
97 | ||
98 | mcu_csr_probe mcu3_csr_probe ( .mcu_id(2'b00), .ucb_rd_vld(mcu3_ucb_rd_vld), .ucb_rd_accepted(mcu3_ucb_rd_accepted), .ucb_ack_vld(mcu3_ucb_ack_vld), .ucb_nack_vld(mcu3_ucb_nack_vld), .ucb_addr(mcu3_ucb_addr), .ucb_data(mcu3_ucb_data), .mcu_clk(mcu3_iol2clk)); | |
99 | ||
100 | endmodule | |
101 | ||
102 | ||
103 | module mcu_csr_probe ( mcu_id, ucb_rd_vld, ucb_ack_vld, ucb_rd_accepted, ucb_nack_vld, ucb_addr, ucb_data, mcu_clk); | |
104 | ||
105 | input [1:0] mcu_id; | |
106 | input ucb_rd_vld; | |
107 | input ucb_rd_accepted; | |
108 | input ucb_ack_vld; | |
109 | input ucb_nack_vld; | |
110 | input [39:0] ucb_addr; | |
111 | input [63:0] ucb_data; | |
112 | input mcu_clk; | |
113 | ||
114 | reg [63:0] ucb_addr_reg; | |
115 | reg [63:0] ucb_data_reg; | |
116 | ||
117 | integer mcu_csr; | |
118 | ||
119 | reg [1:0] state; | |
120 | ||
121 | parameter IDLE = 0, ADDR = 1, DATA = 2; | |
122 | ||
123 | //Detected esr/ear etc | |
124 | ||
125 | assign d_esr_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h280)); | |
126 | assign d_ear_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h288)); | |
127 | assign d_eir_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h290)); | |
128 | assign d_ecr_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h298)); | |
129 | assign d_elr_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h2a0)); | |
130 | assign d_err_det = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h2a8)); | |
131 | assign d_chan_reset = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'h810)); | |
132 | assign d_fbd_err_syndrome = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'hc00)); | |
133 | assign d_fbd_inj_err = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'hc00)); | |
134 | assign d_fbr_count_reg = ((ucb_addr[39:32] == 8'h84) & (ucb_addr[11:0] == 12'hc10)); | |
135 | ||
136 | assign error_reg_det = (d_esr_det | d_ear_det | d_eir_det | d_ecr_det | d_elr_det | d_err_det | | |
137 | d_chan_reset | d_fbd_err_syndrome | d_fbd_inj_err | d_fbr_count_reg); | |
138 | ||
139 | ||
140 | always @(negedge mcu_clk) begin | |
141 | case(state) | |
142 | IDLE: | |
143 | if (ucb_rd_accepted & ucb_rd_vld & error_reg_det) begin | |
144 | state = ADDR; | |
145 | ucb_addr_reg = {24'b0,ucb_addr}; | |
146 | end | |
147 | ADDR: | |
148 | if (ucb_ack_vld | ucb_nack_vld) begin | |
149 | ucb_data_reg = ucb_data; | |
150 | $display("addr = %x data = %x\n", ucb_addr_reg, ucb_data_reg); | |
151 | `PR_INFO ("mcu_csr_probe", `INFO, "ts=%0d MCU CSR READ RETURN: address %x data %x ", | |
152 | `TOP.core_cycle_cnt-1, ucb_addr_reg, ucb_data_reg); | |
153 | if (`PARGS.nas_check_on ) | |
154 | mcu_csr = $sim_send(`PLI_CSR_READ, ucb_addr_reg, ucb_data_reg, 8'h00); | |
155 | state = IDLE; | |
156 | end | |
157 | default: | |
158 | state = IDLE; | |
159 | endcase | |
160 | end | |
161 | ||
162 | ||
163 | endmodule |