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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: dtlb_wr.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | `ifdef CORE_0 | |
| 36 | ||
| 37 | module dtlb_wr_c0 (); | |
| 38 | `ifndef GATESIM | |
| 39 | ||
| 40 | `include "tlb_sync.vh" | |
| 41 | `include "nas.vh" | |
| 42 | parameter NUM_TLB=128; | |
| 43 | ||
| 44 | wire [7:0] data_in; | |
| 45 | wire [7:0] tlb_wr; | |
| 46 | wire wr_en; | |
| 47 | wire [7:0] entry; | |
| 48 | wire [7:0] asi_num; | |
| 49 | wire asi_enable0; // 1 per thread group | |
| 50 | wire asi_enable1; | |
| 51 | wire [7:0] store_asi; // 1 per thread | |
| 52 | wire [3:0] demap; | |
| 53 | reg [3:0] demap_1; | |
| 54 | wire demap_page; | |
| 55 | wire demap_context; | |
| 56 | wire demap_real; | |
| 57 | wire demap_all; | |
| 58 | wire skip_demap; | |
| 59 | wire demap_active; | |
| 60 | wire auto_demap; | |
| 61 | wire [2:0] demap_tid; | |
| 62 | reg [2:0] demap_tid_1; | |
| 63 | reg [5:0] demap_tnum_1; | |
| 64 | ||
| 65 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 66 | reg hwtw; | |
| 67 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 68 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 69 | ||
| 70 | reg [2:0] mytid; | |
| 71 | reg [5:0] mytnum; | |
| 72 | wire [2:0] mycid; | |
| 73 | integer junk; | |
| 74 | integer i; | |
| 75 | reg [7:0] cnt; | |
| 76 | wire ready; | |
| 77 | ||
| 78 | assign mycid = 0; | |
| 79 | ||
| 80 | `ifdef DEBUG_TLB | |
| 81 | wire [7:0] my_asi0 = my_asi[0]; | |
| 82 | wire [7:0] my_asi1 = my_asi[1]; | |
| 83 | wire [7:0] my_asi2 = my_asi[2]; | |
| 84 | wire [7:0] my_asi3 = my_asi[3]; | |
| 85 | wire [7:0] my_asi4 = my_asi[4]; | |
| 86 | wire [7:0] my_asi5 = my_asi[5]; | |
| 87 | wire [7:0] my_asi6 = my_asi[6]; | |
| 88 | wire [7:0] my_asi7 = my_asi[7]; | |
| 89 | `endif | |
| 90 | ||
| 91 | //---------------------------------------------------------- | |
| 92 | // Instantiate fifo - 1 entry per thread | |
| 93 | fifo fifo (); | |
| 94 | // Define fifo parameters | |
| 95 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 96 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 97 | defparam fifo.PTR_BITS = 4; | |
| 98 | ||
| 99 | //---------------------------------------------------------- | |
| 100 | // DUT probes | |
| 101 | ||
| 102 | assign data_in = `SPC0.mmu.asi.wrote_dtlb; | |
| 103 | assign tlb_wr = `SPC0.mmu_reload_done; | |
| 104 | assign wr_en = `SPC0.lsu.tlb.tlb_wr_1_in_dout; | |
| 105 | ||
| 106 | assign entry = `SPC0.lsu.tlb.rw_index_1[6:0]; | |
| 107 | ||
| 108 | assign asi_num = `PROBES0.asi_num; | |
| 109 | assign asi_enable0 = `PROBES0.tlb_rd_vld_b & | |
| 110 | !`PROBES0.tlb_bypass_b & | |
| 111 | `SPC0.tlu.fls0.lsu_inst_b; | |
| 112 | assign asi_enable1 = `PROBES0.tlb_rd_vld_b & | |
| 113 | !`PROBES0.tlb_bypass_b & | |
| 114 | `SPC0.tlu.fls1.lsu_inst_b; | |
| 115 | ||
| 116 | assign store_asi[3:0] = asi_enable0 ? `PROBES0.select_pc_b[3:0] : 4'b0; | |
| 117 | assign store_asi[7:4] = asi_enable1 ? `PROBES0.select_pc_b[7:4] : 4'b0; | |
| 118 | ||
| 119 | assign demap_page = `SPC0.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 120 | assign demap_context = `SPC0.lsu.tlc_demap_context; | |
| 121 | assign demap_real = `SPC0.lsu.tlc_demap_real; | |
| 122 | assign demap_all = `SPC0.lsu.tlc_demap_all; | |
| 123 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 124 | assign skip_demap =`SPC0.lsu.tlc_wr_u_en; | |
| 125 | assign demap_tid = `SPC0.lsu.tld.tte1[37:35]; | |
| 126 | ||
| 127 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 128 | assign demap_active = |demap_1 && !skip_demap; | |
| 129 | assign auto_demap = |demap_1 && skip_demap; | |
| 130 | ||
| 131 | //--------------------- | |
| 132 | // Probes for debugging | |
| 133 | ||
| 134 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 135 | ||
| 136 | // n2_tlb_tl_128x59_cam.sv | |
| 137 | ||
| 138 | `define CNTX1_HI 65 | |
| 139 | `define CNTX1_LO 53 | |
| 140 | `define PID_HI 52 | |
| 141 | `define PID_LO 50 | |
| 142 | `define REAL_BIT 49 | |
| 143 | `define VA_47 48 | |
| 144 | `define VA_28 29 | |
| 145 | `define VA_27 28 | |
| 146 | `define VA_22 23 | |
| 147 | `define TTE_VALID 22 | |
| 148 | `define VA_21 21 | |
| 149 | `define VA_16 16 | |
| 150 | `define VA_15 15 | |
| 151 | `define VA_13 13 | |
| 152 | `define CNTX0_HI 12 | |
| 153 | `define CNTX0_LO 0 | |
| 154 | ||
| 155 | // n2_tlb_tl_128x59_ram.sv | |
| 156 | ||
| 157 | `define DATA_PARITY 36 | |
| 158 | `define DATA_PA_39_28_HI 35 | |
| 159 | `define DATA_PA_39_28_LO 24 | |
| 160 | `define DATA_PA_27_22_HI 23 | |
| 161 | `define DATA_PA_27_22_LO 18 | |
| 162 | `define DATA_VA_27_22_V 17 | |
| 163 | `define DATA_PA_21_16_HI 16 | |
| 164 | `define DATA_PA_21_16_LO 11 | |
| 165 | `define DATA_VA_21_16_V 10 | |
| 166 | `define DATA_PA_15_13_HI 9 | |
| 167 | `define DATA_PA_15_13_LO 7 | |
| 168 | `define DATA_VA_15_13_V 6 | |
| 169 | `define DATA_NFO 5 | |
| 170 | `define DATA_IE 4 | |
| 171 | `define DATA_CP 3 | |
| 172 | `define DATA_X 2 | |
| 173 | `define DATA_P 1 | |
| 174 | `define DATA_W 0 | |
| 175 | ||
| 176 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 177 | wire [(NUM_TLB-1):0] tlb_match; | |
| 178 | wire tte_valid; | |
| 179 | wire [47:0] tte_va; | |
| 180 | wire [12:0] tte_context; | |
| 181 | wire tte_real; | |
| 182 | wire [2:0] tte_pid; | |
| 183 | wire [2:0] tte_page_mask; | |
| 184 | wire [39:0] tte_pa; | |
| 185 | wire tte_nfo; | |
| 186 | wire tte_ie; | |
| 187 | wire tte_cp; | |
| 188 | wire tte_e; | |
| 189 | wire tte_p; | |
| 190 | wire tte_w; | |
| 191 | wire tte_ep; | |
| 192 | ||
| 193 | ||
| 194 | assign tlb_valid = `SPC0.lsu.tlb.array.cam.valid; | |
| 195 | assign tlb_match = `SPC0.lsu.tlb.array.cam.match; | |
| 196 | ||
| 197 | assign tte_va = {`SPC0.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 198 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 199 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 200 | `SPC0.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 201 | 13'b0 | |
| 202 | }; | |
| 203 | assign tte_context = `SPC0.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 204 | assign tte_pid = `SPC0.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 205 | assign tte_real = `SPC0.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 206 | assign tte_valid = `SPC0.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 207 | ||
| 208 | assign tte_page_mask = `SPC0.lsu.tlb.tte_page_size_mask_1; | |
| 209 | ||
| 210 | assign tte_pa = {`SPC0.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 211 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 212 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 213 | `SPC0.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 214 | 13'b0 | |
| 215 | }; | |
| 216 | assign tte_nfo = `SPC0.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 217 | assign tte_ie = `SPC0.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 218 | assign tte_cp = `SPC0.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 219 | assign tte_e = `SPC0.lsu.tlb.tte_data_1[`DATA_X]; | |
| 220 | assign tte_p = `SPC0.lsu.tlb.tte_data_1[`DATA_P]; | |
| 221 | assign tte_w = `SPC0.lsu.tlb.tte_data_1[`DATA_W]; | |
| 222 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 223 | ||
| 224 | assign ready = `PARGS.tlb_sync_on & !`SPC0.tcu_spc_mbist_start; | |
| 225 | ||
| 226 | //---------------------------------------------------------- | |
| 227 | // Initialize state machine to idle state | |
| 228 | initial begin // { | |
| 229 | #1; | |
| 230 | hwtw = 1'b0; | |
| 231 | for (i=0; i<=7; i=i+1) begin | |
| 232 | my_asi[i] = 8'b0; | |
| 233 | end | |
| 234 | @ (posedge `SPC0.l2clk); | |
| 235 | ||
| 236 | end // } | |
| 237 | ||
| 238 | //---------------------------------------------------------- | |
| 239 | // Must use negedge to avoid race condition | |
| 240 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 241 | ||
| 242 | always @ (negedge (`SPC0.l2clk & ready)) begin // { | |
| 243 | ||
| 244 | tstamp = `TOP.core_cycle_cnt; | |
| 245 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 246 | ||
| 247 | // Delay by 1 cycle to align with skip_demap | |
| 248 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 249 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 250 | demap_1 <= demap; | |
| 251 | ||
| 252 | //---------------------------------------------------------- | |
| 253 | // Send I/DTLBWRITE due to demap | |
| 254 | // | |
| 255 | ||
| 256 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 257 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 258 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 259 | mycid,demap_tid_1); | |
| 260 | end // } | |
| 261 | ||
| 262 | if (demap_active) begin // { | |
| 263 | fifo.pop_fifo ({hwtw,mytid}); | |
| 264 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 265 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 266 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 267 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 268 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 269 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 270 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 271 | ||
| 272 | // sstep_sent is asserted when data_in is asserted | |
| 273 | // Check to see if sstep was sent early | |
| 274 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 275 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 276 | end //} | |
| 277 | ||
| 278 | end //} | |
| 279 | end //} | |
| 280 | ||
| 281 | //-------------------- | |
| 282 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 283 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 284 | ||
| 285 | if (demap_active) begin | |
| 286 | case (demap_1) | |
| 287 | 4'b0001: $write ("type=real "); | |
| 288 | 4'b0010: $write ("type=cntx "); | |
| 289 | 4'b0100: $write ("type=page "); | |
| 290 | 4'b1000: $write ("type=all "); | |
| 291 | default: | |
| 292 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 293 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 294 | endcase | |
| 295 | end | |
| 296 | else begin | |
| 297 | $write ("type=autodemap "); | |
| 298 | end | |
| 299 | ||
| 300 | $display ("match=%h ts=%0d", | |
| 301 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 302 | ||
| 303 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 304 | if (tlb_match[cnt]==1'b1) begin // { | |
| 305 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 306 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 307 | end // } | |
| 308 | end // } | |
| 309 | //-------------------- | |
| 310 | end // } | |
| 311 | ||
| 312 | //---------------------------------------------------------- | |
| 313 | // Send I/DHWTW due to HWTW | |
| 314 | // Send I/DTLBWRITE due to ASI write | |
| 315 | ||
| 316 | // Save asi num when DTLBREAD happens. | |
| 317 | // Otherwise, hold state. | |
| 318 | // Send asi num later with DHWTW | |
| 319 | for (i=0;i<=7;i=i+1) begin // { | |
| 320 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 321 | end // } | |
| 322 | ||
| 323 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 324 | // These signals will be interleaved between the threads. | |
| 325 | // Need to queue up the signals over time so they can be processed in order. | |
| 326 | // Each thread will only be doing 1 thing at a time. | |
| 327 | ||
| 328 | for (i=0;i<=7;i=i+1) begin // { | |
| 329 | ||
| 330 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 331 | ||
| 332 | // data_in[tid] determines which thread will write next | |
| 333 | // Use fifo to save the tids of the data_in signals in order | |
| 334 | ||
| 335 | if (data_in[i]) begin // { | |
| 336 | if (tlb_wr[i]) begin // { | |
| 337 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 338 | end // } | |
| 339 | else begin // { | |
| 340 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 341 | ||
| 342 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 343 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 344 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 345 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 346 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 347 | end // } | |
| 348 | end // } | |
| 349 | ||
| 350 | end // } | |
| 351 | ||
| 352 | //---------------------------------------------------------- | |
| 353 | // wr_en means that the write is occurring | |
| 354 | if (wr_en) begin // { | |
| 355 | fifo.pop_fifo ({hwtw,mytid}); | |
| 356 | mytnum = (mycid * 8) + mytid; | |
| 357 | ||
| 358 | if (hwtw) begin // { | |
| 359 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 360 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 361 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 362 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 363 | ||
| 364 | end //} | |
| 365 | end // } | |
| 366 | else begin // { | |
| 367 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 368 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 369 | mycid,mytid,mytnum,tstamp,entry); | |
| 370 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 371 | mycid,mytid,mytnum,tstamp); | |
| 372 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 373 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 374 | ||
| 375 | // Check to see if sstep was sent early | |
| 376 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 377 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 378 | end //} | |
| 379 | ||
| 380 | end //} | |
| 381 | end // } | |
| 382 | ||
| 383 | //-------------------- | |
| 384 | if (`PARGS.show_tlb_on) begin // { | |
| 385 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 386 | ||
| 387 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 388 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 389 | ||
| 390 | case (tte_page_mask) | |
| 391 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 392 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 393 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 394 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 395 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 396 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 397 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 398 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 399 | endcase | |
| 400 | ||
| 401 | if (hwtw) $display (" (hwtw)"); | |
| 402 | else $display (""); | |
| 403 | ||
| 404 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 405 | ||
| 406 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 407 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 408 | end // } | |
| 409 | //-------------------- | |
| 410 | ||
| 411 | end // } | |
| 412 | ||
| 413 | end // always} | |
| 414 | ||
| 415 | //---------------------------------------------------------- | |
| 416 | `endif | |
| 417 | endmodule | |
| 418 | ||
| 419 | `endif | |
| 420 | `ifdef CORE_1 | |
| 421 | ||
| 422 | module dtlb_wr_c1 (); | |
| 423 | `ifndef GATESIM | |
| 424 | ||
| 425 | `include "tlb_sync.vh" | |
| 426 | `include "nas.vh" | |
| 427 | parameter NUM_TLB=128; | |
| 428 | ||
| 429 | wire [7:0] data_in; | |
| 430 | wire [7:0] tlb_wr; | |
| 431 | wire wr_en; | |
| 432 | wire [7:0] entry; | |
| 433 | wire [7:0] asi_num; | |
| 434 | wire asi_enable0; // 1 per thread group | |
| 435 | wire asi_enable1; | |
| 436 | wire [7:0] store_asi; // 1 per thread | |
| 437 | wire [3:0] demap; | |
| 438 | reg [3:0] demap_1; | |
| 439 | wire demap_page; | |
| 440 | wire demap_context; | |
| 441 | wire demap_real; | |
| 442 | wire demap_all; | |
| 443 | wire skip_demap; | |
| 444 | wire demap_active; | |
| 445 | wire auto_demap; | |
| 446 | wire [2:0] demap_tid; | |
| 447 | reg [2:0] demap_tid_1; | |
| 448 | reg [5:0] demap_tnum_1; | |
| 449 | ||
| 450 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 451 | reg hwtw; | |
| 452 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 453 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 454 | ||
| 455 | reg [2:0] mytid; | |
| 456 | reg [5:0] mytnum; | |
| 457 | wire [2:0] mycid; | |
| 458 | integer junk; | |
| 459 | integer i; | |
| 460 | reg [7:0] cnt; | |
| 461 | wire ready; | |
| 462 | ||
| 463 | assign mycid = 1; | |
| 464 | ||
| 465 | `ifdef DEBUG_TLB | |
| 466 | wire [7:0] my_asi0 = my_asi[0]; | |
| 467 | wire [7:0] my_asi1 = my_asi[1]; | |
| 468 | wire [7:0] my_asi2 = my_asi[2]; | |
| 469 | wire [7:0] my_asi3 = my_asi[3]; | |
| 470 | wire [7:0] my_asi4 = my_asi[4]; | |
| 471 | wire [7:0] my_asi5 = my_asi[5]; | |
| 472 | wire [7:0] my_asi6 = my_asi[6]; | |
| 473 | wire [7:0] my_asi7 = my_asi[7]; | |
| 474 | `endif | |
| 475 | ||
| 476 | //---------------------------------------------------------- | |
| 477 | // Instantiate fifo - 1 entry per thread | |
| 478 | fifo fifo (); | |
| 479 | // Define fifo parameters | |
| 480 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 481 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 482 | defparam fifo.PTR_BITS = 4; | |
| 483 | ||
| 484 | //---------------------------------------------------------- | |
| 485 | // DUT probes | |
| 486 | ||
| 487 | assign data_in = `SPC1.mmu.asi.wrote_dtlb; | |
| 488 | assign tlb_wr = `SPC1.mmu_reload_done; | |
| 489 | assign wr_en = `SPC1.lsu.tlb.tlb_wr_1_in_dout; | |
| 490 | ||
| 491 | assign entry = `SPC1.lsu.tlb.rw_index_1[6:0]; | |
| 492 | ||
| 493 | assign asi_num = `PROBES1.asi_num; | |
| 494 | assign asi_enable0 = `PROBES1.tlb_rd_vld_b & | |
| 495 | !`PROBES1.tlb_bypass_b & | |
| 496 | `SPC1.tlu.fls0.lsu_inst_b; | |
| 497 | assign asi_enable1 = `PROBES1.tlb_rd_vld_b & | |
| 498 | !`PROBES1.tlb_bypass_b & | |
| 499 | `SPC1.tlu.fls1.lsu_inst_b; | |
| 500 | ||
| 501 | assign store_asi[3:0] = asi_enable0 ? `PROBES1.select_pc_b[3:0] : 4'b0; | |
| 502 | assign store_asi[7:4] = asi_enable1 ? `PROBES1.select_pc_b[7:4] : 4'b0; | |
| 503 | ||
| 504 | assign demap_page = `SPC1.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 505 | assign demap_context = `SPC1.lsu.tlc_demap_context; | |
| 506 | assign demap_real = `SPC1.lsu.tlc_demap_real; | |
| 507 | assign demap_all = `SPC1.lsu.tlc_demap_all; | |
| 508 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 509 | assign skip_demap =`SPC1.lsu.tlc_wr_u_en; | |
| 510 | assign demap_tid = `SPC1.lsu.tld.tte1[37:35]; | |
| 511 | ||
| 512 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 513 | assign demap_active = |demap_1 && !skip_demap; | |
| 514 | assign auto_demap = |demap_1 && skip_demap; | |
| 515 | ||
| 516 | //--------------------- | |
| 517 | // Probes for debugging | |
| 518 | ||
| 519 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 520 | ||
| 521 | // n2_tlb_tl_128x59_cam.sv | |
| 522 | ||
| 523 | `define CNTX1_HI 65 | |
| 524 | `define CNTX1_LO 53 | |
| 525 | `define PID_HI 52 | |
| 526 | `define PID_LO 50 | |
| 527 | `define REAL_BIT 49 | |
| 528 | `define VA_47 48 | |
| 529 | `define VA_28 29 | |
| 530 | `define VA_27 28 | |
| 531 | `define VA_22 23 | |
| 532 | `define TTE_VALID 22 | |
| 533 | `define VA_21 21 | |
| 534 | `define VA_16 16 | |
| 535 | `define VA_15 15 | |
| 536 | `define VA_13 13 | |
| 537 | `define CNTX0_HI 12 | |
| 538 | `define CNTX0_LO 0 | |
| 539 | ||
| 540 | // n2_tlb_tl_128x59_ram.sv | |
| 541 | ||
| 542 | `define DATA_PARITY 36 | |
| 543 | `define DATA_PA_39_28_HI 35 | |
| 544 | `define DATA_PA_39_28_LO 24 | |
| 545 | `define DATA_PA_27_22_HI 23 | |
| 546 | `define DATA_PA_27_22_LO 18 | |
| 547 | `define DATA_VA_27_22_V 17 | |
| 548 | `define DATA_PA_21_16_HI 16 | |
| 549 | `define DATA_PA_21_16_LO 11 | |
| 550 | `define DATA_VA_21_16_V 10 | |
| 551 | `define DATA_PA_15_13_HI 9 | |
| 552 | `define DATA_PA_15_13_LO 7 | |
| 553 | `define DATA_VA_15_13_V 6 | |
| 554 | `define DATA_NFO 5 | |
| 555 | `define DATA_IE 4 | |
| 556 | `define DATA_CP 3 | |
| 557 | `define DATA_X 2 | |
| 558 | `define DATA_P 1 | |
| 559 | `define DATA_W 0 | |
| 560 | ||
| 561 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 562 | wire [(NUM_TLB-1):0] tlb_match; | |
| 563 | wire tte_valid; | |
| 564 | wire [47:0] tte_va; | |
| 565 | wire [12:0] tte_context; | |
| 566 | wire tte_real; | |
| 567 | wire [2:0] tte_pid; | |
| 568 | wire [2:0] tte_page_mask; | |
| 569 | wire [39:0] tte_pa; | |
| 570 | wire tte_nfo; | |
| 571 | wire tte_ie; | |
| 572 | wire tte_cp; | |
| 573 | wire tte_e; | |
| 574 | wire tte_p; | |
| 575 | wire tte_w; | |
| 576 | wire tte_ep; | |
| 577 | ||
| 578 | ||
| 579 | assign tlb_valid = `SPC1.lsu.tlb.array.cam.valid; | |
| 580 | assign tlb_match = `SPC1.lsu.tlb.array.cam.match; | |
| 581 | ||
| 582 | assign tte_va = {`SPC1.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 583 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 584 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 585 | `SPC1.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 586 | 13'b0 | |
| 587 | }; | |
| 588 | assign tte_context = `SPC1.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 589 | assign tte_pid = `SPC1.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 590 | assign tte_real = `SPC1.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 591 | assign tte_valid = `SPC1.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 592 | ||
| 593 | assign tte_page_mask = `SPC1.lsu.tlb.tte_page_size_mask_1; | |
| 594 | ||
| 595 | assign tte_pa = {`SPC1.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 596 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 597 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 598 | `SPC1.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 599 | 13'b0 | |
| 600 | }; | |
| 601 | assign tte_nfo = `SPC1.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 602 | assign tte_ie = `SPC1.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 603 | assign tte_cp = `SPC1.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 604 | assign tte_e = `SPC1.lsu.tlb.tte_data_1[`DATA_X]; | |
| 605 | assign tte_p = `SPC1.lsu.tlb.tte_data_1[`DATA_P]; | |
| 606 | assign tte_w = `SPC1.lsu.tlb.tte_data_1[`DATA_W]; | |
| 607 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 608 | ||
| 609 | assign ready = `PARGS.tlb_sync_on & !`SPC1.tcu_spc_mbist_start; | |
| 610 | ||
| 611 | //---------------------------------------------------------- | |
| 612 | // Initialize state machine to idle state | |
| 613 | initial begin // { | |
| 614 | #1; | |
| 615 | hwtw = 1'b0; | |
| 616 | for (i=0; i<=7; i=i+1) begin | |
| 617 | my_asi[i] = 8'b0; | |
| 618 | end | |
| 619 | @ (posedge `SPC1.l2clk); | |
| 620 | ||
| 621 | end // } | |
| 622 | ||
| 623 | //---------------------------------------------------------- | |
| 624 | // Must use negedge to avoid race condition | |
| 625 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 626 | ||
| 627 | always @ (negedge (`SPC1.l2clk & ready)) begin // { | |
| 628 | ||
| 629 | tstamp = `TOP.core_cycle_cnt; | |
| 630 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 631 | ||
| 632 | // Delay by 1 cycle to align with skip_demap | |
| 633 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 634 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 635 | demap_1 <= demap; | |
| 636 | ||
| 637 | //---------------------------------------------------------- | |
| 638 | // Send I/DTLBWRITE due to demap | |
| 639 | // | |
| 640 | ||
| 641 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 642 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 643 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 644 | mycid,demap_tid_1); | |
| 645 | end // } | |
| 646 | ||
| 647 | if (demap_active) begin // { | |
| 648 | fifo.pop_fifo ({hwtw,mytid}); | |
| 649 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 650 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 651 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 652 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 653 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 654 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 655 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 656 | ||
| 657 | // sstep_sent is asserted when data_in is asserted | |
| 658 | // Check to see if sstep was sent early | |
| 659 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 660 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 661 | end //} | |
| 662 | ||
| 663 | end //} | |
| 664 | end //} | |
| 665 | ||
| 666 | //-------------------- | |
| 667 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 668 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 669 | ||
| 670 | if (demap_active) begin | |
| 671 | case (demap_1) | |
| 672 | 4'b0001: $write ("type=real "); | |
| 673 | 4'b0010: $write ("type=cntx "); | |
| 674 | 4'b0100: $write ("type=page "); | |
| 675 | 4'b1000: $write ("type=all "); | |
| 676 | default: | |
| 677 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 678 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 679 | endcase | |
| 680 | end | |
| 681 | else begin | |
| 682 | $write ("type=autodemap "); | |
| 683 | end | |
| 684 | ||
| 685 | $display ("match=%h ts=%0d", | |
| 686 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 687 | ||
| 688 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 689 | if (tlb_match[cnt]==1'b1) begin // { | |
| 690 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 691 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 692 | end // } | |
| 693 | end // } | |
| 694 | //-------------------- | |
| 695 | end // } | |
| 696 | ||
| 697 | //---------------------------------------------------------- | |
| 698 | // Send I/DHWTW due to HWTW | |
| 699 | // Send I/DTLBWRITE due to ASI write | |
| 700 | ||
| 701 | // Save asi num when DTLBREAD happens. | |
| 702 | // Otherwise, hold state. | |
| 703 | // Send asi num later with DHWTW | |
| 704 | for (i=0;i<=7;i=i+1) begin // { | |
| 705 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 706 | end // } | |
| 707 | ||
| 708 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 709 | // These signals will be interleaved between the threads. | |
| 710 | // Need to queue up the signals over time so they can be processed in order. | |
| 711 | // Each thread will only be doing 1 thing at a time. | |
| 712 | ||
| 713 | for (i=0;i<=7;i=i+1) begin // { | |
| 714 | ||
| 715 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 716 | ||
| 717 | // data_in[tid] determines which thread will write next | |
| 718 | // Use fifo to save the tids of the data_in signals in order | |
| 719 | ||
| 720 | if (data_in[i]) begin // { | |
| 721 | if (tlb_wr[i]) begin // { | |
| 722 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 723 | end // } | |
| 724 | else begin // { | |
| 725 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 726 | ||
| 727 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 728 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 729 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 730 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 731 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 732 | end // } | |
| 733 | end // } | |
| 734 | ||
| 735 | end // } | |
| 736 | ||
| 737 | //---------------------------------------------------------- | |
| 738 | // wr_en means that the write is occurring | |
| 739 | if (wr_en) begin // { | |
| 740 | fifo.pop_fifo ({hwtw,mytid}); | |
| 741 | mytnum = (mycid * 8) + mytid; | |
| 742 | ||
| 743 | if (hwtw) begin // { | |
| 744 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 745 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 746 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 747 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 748 | ||
| 749 | end //} | |
| 750 | end // } | |
| 751 | else begin // { | |
| 752 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 753 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 754 | mycid,mytid,mytnum,tstamp,entry); | |
| 755 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 756 | mycid,mytid,mytnum,tstamp); | |
| 757 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 758 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 759 | ||
| 760 | // Check to see if sstep was sent early | |
| 761 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 762 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 763 | end //} | |
| 764 | ||
| 765 | end //} | |
| 766 | end // } | |
| 767 | ||
| 768 | //-------------------- | |
| 769 | if (`PARGS.show_tlb_on) begin // { | |
| 770 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 771 | ||
| 772 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 773 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 774 | ||
| 775 | case (tte_page_mask) | |
| 776 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 777 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 778 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 779 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 780 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 781 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 782 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 783 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 784 | endcase | |
| 785 | ||
| 786 | if (hwtw) $display (" (hwtw)"); | |
| 787 | else $display (""); | |
| 788 | ||
| 789 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 790 | ||
| 791 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 792 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 793 | end // } | |
| 794 | //-------------------- | |
| 795 | ||
| 796 | end // } | |
| 797 | ||
| 798 | end // always} | |
| 799 | ||
| 800 | //---------------------------------------------------------- | |
| 801 | `endif | |
| 802 | endmodule | |
| 803 | ||
| 804 | `endif | |
| 805 | `ifdef CORE_2 | |
| 806 | ||
| 807 | module dtlb_wr_c2 (); | |
| 808 | `ifndef GATESIM | |
| 809 | ||
| 810 | `include "tlb_sync.vh" | |
| 811 | `include "nas.vh" | |
| 812 | parameter NUM_TLB=128; | |
| 813 | ||
| 814 | wire [7:0] data_in; | |
| 815 | wire [7:0] tlb_wr; | |
| 816 | wire wr_en; | |
| 817 | wire [7:0] entry; | |
| 818 | wire [7:0] asi_num; | |
| 819 | wire asi_enable0; // 1 per thread group | |
| 820 | wire asi_enable1; | |
| 821 | wire [7:0] store_asi; // 1 per thread | |
| 822 | wire [3:0] demap; | |
| 823 | reg [3:0] demap_1; | |
| 824 | wire demap_page; | |
| 825 | wire demap_context; | |
| 826 | wire demap_real; | |
| 827 | wire demap_all; | |
| 828 | wire skip_demap; | |
| 829 | wire demap_active; | |
| 830 | wire auto_demap; | |
| 831 | wire [2:0] demap_tid; | |
| 832 | reg [2:0] demap_tid_1; | |
| 833 | reg [5:0] demap_tnum_1; | |
| 834 | ||
| 835 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 836 | reg hwtw; | |
| 837 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 838 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 839 | ||
| 840 | reg [2:0] mytid; | |
| 841 | reg [5:0] mytnum; | |
| 842 | wire [2:0] mycid; | |
| 843 | integer junk; | |
| 844 | integer i; | |
| 845 | reg [7:0] cnt; | |
| 846 | wire ready; | |
| 847 | ||
| 848 | assign mycid = 2; | |
| 849 | ||
| 850 | `ifdef DEBUG_TLB | |
| 851 | wire [7:0] my_asi0 = my_asi[0]; | |
| 852 | wire [7:0] my_asi1 = my_asi[1]; | |
| 853 | wire [7:0] my_asi2 = my_asi[2]; | |
| 854 | wire [7:0] my_asi3 = my_asi[3]; | |
| 855 | wire [7:0] my_asi4 = my_asi[4]; | |
| 856 | wire [7:0] my_asi5 = my_asi[5]; | |
| 857 | wire [7:0] my_asi6 = my_asi[6]; | |
| 858 | wire [7:0] my_asi7 = my_asi[7]; | |
| 859 | `endif | |
| 860 | ||
| 861 | //---------------------------------------------------------- | |
| 862 | // Instantiate fifo - 1 entry per thread | |
| 863 | fifo fifo (); | |
| 864 | // Define fifo parameters | |
| 865 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 866 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 867 | defparam fifo.PTR_BITS = 4; | |
| 868 | ||
| 869 | //---------------------------------------------------------- | |
| 870 | // DUT probes | |
| 871 | ||
| 872 | assign data_in = `SPC2.mmu.asi.wrote_dtlb; | |
| 873 | assign tlb_wr = `SPC2.mmu_reload_done; | |
| 874 | assign wr_en = `SPC2.lsu.tlb.tlb_wr_1_in_dout; | |
| 875 | ||
| 876 | assign entry = `SPC2.lsu.tlb.rw_index_1[6:0]; | |
| 877 | ||
| 878 | assign asi_num = `PROBES2.asi_num; | |
| 879 | assign asi_enable0 = `PROBES2.tlb_rd_vld_b & | |
| 880 | !`PROBES2.tlb_bypass_b & | |
| 881 | `SPC2.tlu.fls0.lsu_inst_b; | |
| 882 | assign asi_enable1 = `PROBES2.tlb_rd_vld_b & | |
| 883 | !`PROBES2.tlb_bypass_b & | |
| 884 | `SPC2.tlu.fls1.lsu_inst_b; | |
| 885 | ||
| 886 | assign store_asi[3:0] = asi_enable0 ? `PROBES2.select_pc_b[3:0] : 4'b0; | |
| 887 | assign store_asi[7:4] = asi_enable1 ? `PROBES2.select_pc_b[7:4] : 4'b0; | |
| 888 | ||
| 889 | assign demap_page = `SPC2.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 890 | assign demap_context = `SPC2.lsu.tlc_demap_context; | |
| 891 | assign demap_real = `SPC2.lsu.tlc_demap_real; | |
| 892 | assign demap_all = `SPC2.lsu.tlc_demap_all; | |
| 893 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 894 | assign skip_demap =`SPC2.lsu.tlc_wr_u_en; | |
| 895 | assign demap_tid = `SPC2.lsu.tld.tte1[37:35]; | |
| 896 | ||
| 897 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 898 | assign demap_active = |demap_1 && !skip_demap; | |
| 899 | assign auto_demap = |demap_1 && skip_demap; | |
| 900 | ||
| 901 | //--------------------- | |
| 902 | // Probes for debugging | |
| 903 | ||
| 904 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 905 | ||
| 906 | // n2_tlb_tl_128x59_cam.sv | |
| 907 | ||
| 908 | `define CNTX1_HI 65 | |
| 909 | `define CNTX1_LO 53 | |
| 910 | `define PID_HI 52 | |
| 911 | `define PID_LO 50 | |
| 912 | `define REAL_BIT 49 | |
| 913 | `define VA_47 48 | |
| 914 | `define VA_28 29 | |
| 915 | `define VA_27 28 | |
| 916 | `define VA_22 23 | |
| 917 | `define TTE_VALID 22 | |
| 918 | `define VA_21 21 | |
| 919 | `define VA_16 16 | |
| 920 | `define VA_15 15 | |
| 921 | `define VA_13 13 | |
| 922 | `define CNTX0_HI 12 | |
| 923 | `define CNTX0_LO 0 | |
| 924 | ||
| 925 | // n2_tlb_tl_128x59_ram.sv | |
| 926 | ||
| 927 | `define DATA_PARITY 36 | |
| 928 | `define DATA_PA_39_28_HI 35 | |
| 929 | `define DATA_PA_39_28_LO 24 | |
| 930 | `define DATA_PA_27_22_HI 23 | |
| 931 | `define DATA_PA_27_22_LO 18 | |
| 932 | `define DATA_VA_27_22_V 17 | |
| 933 | `define DATA_PA_21_16_HI 16 | |
| 934 | `define DATA_PA_21_16_LO 11 | |
| 935 | `define DATA_VA_21_16_V 10 | |
| 936 | `define DATA_PA_15_13_HI 9 | |
| 937 | `define DATA_PA_15_13_LO 7 | |
| 938 | `define DATA_VA_15_13_V 6 | |
| 939 | `define DATA_NFO 5 | |
| 940 | `define DATA_IE 4 | |
| 941 | `define DATA_CP 3 | |
| 942 | `define DATA_X 2 | |
| 943 | `define DATA_P 1 | |
| 944 | `define DATA_W 0 | |
| 945 | ||
| 946 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 947 | wire [(NUM_TLB-1):0] tlb_match; | |
| 948 | wire tte_valid; | |
| 949 | wire [47:0] tte_va; | |
| 950 | wire [12:0] tte_context; | |
| 951 | wire tte_real; | |
| 952 | wire [2:0] tte_pid; | |
| 953 | wire [2:0] tte_page_mask; | |
| 954 | wire [39:0] tte_pa; | |
| 955 | wire tte_nfo; | |
| 956 | wire tte_ie; | |
| 957 | wire tte_cp; | |
| 958 | wire tte_e; | |
| 959 | wire tte_p; | |
| 960 | wire tte_w; | |
| 961 | wire tte_ep; | |
| 962 | ||
| 963 | ||
| 964 | assign tlb_valid = `SPC2.lsu.tlb.array.cam.valid; | |
| 965 | assign tlb_match = `SPC2.lsu.tlb.array.cam.match; | |
| 966 | ||
| 967 | assign tte_va = {`SPC2.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 968 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 969 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 970 | `SPC2.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 971 | 13'b0 | |
| 972 | }; | |
| 973 | assign tte_context = `SPC2.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 974 | assign tte_pid = `SPC2.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 975 | assign tte_real = `SPC2.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 976 | assign tte_valid = `SPC2.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 977 | ||
| 978 | assign tte_page_mask = `SPC2.lsu.tlb.tte_page_size_mask_1; | |
| 979 | ||
| 980 | assign tte_pa = {`SPC2.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 981 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 982 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 983 | `SPC2.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 984 | 13'b0 | |
| 985 | }; | |
| 986 | assign tte_nfo = `SPC2.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 987 | assign tte_ie = `SPC2.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 988 | assign tte_cp = `SPC2.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 989 | assign tte_e = `SPC2.lsu.tlb.tte_data_1[`DATA_X]; | |
| 990 | assign tte_p = `SPC2.lsu.tlb.tte_data_1[`DATA_P]; | |
| 991 | assign tte_w = `SPC2.lsu.tlb.tte_data_1[`DATA_W]; | |
| 992 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 993 | ||
| 994 | assign ready = `PARGS.tlb_sync_on & !`SPC2.tcu_spc_mbist_start; | |
| 995 | ||
| 996 | //---------------------------------------------------------- | |
| 997 | // Initialize state machine to idle state | |
| 998 | initial begin // { | |
| 999 | #1; | |
| 1000 | hwtw = 1'b0; | |
| 1001 | for (i=0; i<=7; i=i+1) begin | |
| 1002 | my_asi[i] = 8'b0; | |
| 1003 | end | |
| 1004 | @ (posedge `SPC2.l2clk); | |
| 1005 | ||
| 1006 | end // } | |
| 1007 | ||
| 1008 | //---------------------------------------------------------- | |
| 1009 | // Must use negedge to avoid race condition | |
| 1010 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 1011 | ||
| 1012 | always @ (negedge (`SPC2.l2clk & ready)) begin // { | |
| 1013 | ||
| 1014 | tstamp = `TOP.core_cycle_cnt; | |
| 1015 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 1016 | ||
| 1017 | // Delay by 1 cycle to align with skip_demap | |
| 1018 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 1019 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 1020 | demap_1 <= demap; | |
| 1021 | ||
| 1022 | //---------------------------------------------------------- | |
| 1023 | // Send I/DTLBWRITE due to demap | |
| 1024 | // | |
| 1025 | ||
| 1026 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1027 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1028 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 1029 | mycid,demap_tid_1); | |
| 1030 | end // } | |
| 1031 | ||
| 1032 | if (demap_active) begin // { | |
| 1033 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1034 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1035 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1036 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1037 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1038 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 1039 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1040 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1041 | ||
| 1042 | // sstep_sent is asserted when data_in is asserted | |
| 1043 | // Check to see if sstep was sent early | |
| 1044 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1045 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1046 | end //} | |
| 1047 | ||
| 1048 | end //} | |
| 1049 | end //} | |
| 1050 | ||
| 1051 | //-------------------- | |
| 1052 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1053 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1054 | ||
| 1055 | if (demap_active) begin | |
| 1056 | case (demap_1) | |
| 1057 | 4'b0001: $write ("type=real "); | |
| 1058 | 4'b0010: $write ("type=cntx "); | |
| 1059 | 4'b0100: $write ("type=page "); | |
| 1060 | 4'b1000: $write ("type=all "); | |
| 1061 | default: | |
| 1062 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1063 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1064 | endcase | |
| 1065 | end | |
| 1066 | else begin | |
| 1067 | $write ("type=autodemap "); | |
| 1068 | end | |
| 1069 | ||
| 1070 | $display ("match=%h ts=%0d", | |
| 1071 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1072 | ||
| 1073 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1074 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1075 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1076 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1077 | end // } | |
| 1078 | end // } | |
| 1079 | //-------------------- | |
| 1080 | end // } | |
| 1081 | ||
| 1082 | //---------------------------------------------------------- | |
| 1083 | // Send I/DHWTW due to HWTW | |
| 1084 | // Send I/DTLBWRITE due to ASI write | |
| 1085 | ||
| 1086 | // Save asi num when DTLBREAD happens. | |
| 1087 | // Otherwise, hold state. | |
| 1088 | // Send asi num later with DHWTW | |
| 1089 | for (i=0;i<=7;i=i+1) begin // { | |
| 1090 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 1091 | end // } | |
| 1092 | ||
| 1093 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1094 | // These signals will be interleaved between the threads. | |
| 1095 | // Need to queue up the signals over time so they can be processed in order. | |
| 1096 | // Each thread will only be doing 1 thing at a time. | |
| 1097 | ||
| 1098 | for (i=0;i<=7;i=i+1) begin // { | |
| 1099 | ||
| 1100 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 1101 | ||
| 1102 | // data_in[tid] determines which thread will write next | |
| 1103 | // Use fifo to save the tids of the data_in signals in order | |
| 1104 | ||
| 1105 | if (data_in[i]) begin // { | |
| 1106 | if (tlb_wr[i]) begin // { | |
| 1107 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1108 | end // } | |
| 1109 | else begin // { | |
| 1110 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1111 | ||
| 1112 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 1113 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 1114 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1115 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1116 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 1117 | end // } | |
| 1118 | end // } | |
| 1119 | ||
| 1120 | end // } | |
| 1121 | ||
| 1122 | //---------------------------------------------------------- | |
| 1123 | // wr_en means that the write is occurring | |
| 1124 | if (wr_en) begin // { | |
| 1125 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1126 | mytnum = (mycid * 8) + mytid; | |
| 1127 | ||
| 1128 | if (hwtw) begin // { | |
| 1129 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1130 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 1131 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1132 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1133 | ||
| 1134 | end //} | |
| 1135 | end // } | |
| 1136 | else begin // { | |
| 1137 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1138 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 1139 | mycid,mytid,mytnum,tstamp,entry); | |
| 1140 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1141 | mycid,mytid,mytnum,tstamp); | |
| 1142 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 1143 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1144 | ||
| 1145 | // Check to see if sstep was sent early | |
| 1146 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1147 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1148 | end //} | |
| 1149 | ||
| 1150 | end //} | |
| 1151 | end // } | |
| 1152 | ||
| 1153 | //-------------------- | |
| 1154 | if (`PARGS.show_tlb_on) begin // { | |
| 1155 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1156 | ||
| 1157 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1158 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1159 | ||
| 1160 | case (tte_page_mask) | |
| 1161 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1162 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1163 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1164 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1165 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1166 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1167 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1168 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1169 | endcase | |
| 1170 | ||
| 1171 | if (hwtw) $display (" (hwtw)"); | |
| 1172 | else $display (""); | |
| 1173 | ||
| 1174 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1175 | ||
| 1176 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 1177 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 1178 | end // } | |
| 1179 | //-------------------- | |
| 1180 | ||
| 1181 | end // } | |
| 1182 | ||
| 1183 | end // always} | |
| 1184 | ||
| 1185 | //---------------------------------------------------------- | |
| 1186 | `endif | |
| 1187 | endmodule | |
| 1188 | ||
| 1189 | `endif | |
| 1190 | `ifdef CORE_3 | |
| 1191 | ||
| 1192 | module dtlb_wr_c3 (); | |
| 1193 | `ifndef GATESIM | |
| 1194 | ||
| 1195 | `include "tlb_sync.vh" | |
| 1196 | `include "nas.vh" | |
| 1197 | parameter NUM_TLB=128; | |
| 1198 | ||
| 1199 | wire [7:0] data_in; | |
| 1200 | wire [7:0] tlb_wr; | |
| 1201 | wire wr_en; | |
| 1202 | wire [7:0] entry; | |
| 1203 | wire [7:0] asi_num; | |
| 1204 | wire asi_enable0; // 1 per thread group | |
| 1205 | wire asi_enable1; | |
| 1206 | wire [7:0] store_asi; // 1 per thread | |
| 1207 | wire [3:0] demap; | |
| 1208 | reg [3:0] demap_1; | |
| 1209 | wire demap_page; | |
| 1210 | wire demap_context; | |
| 1211 | wire demap_real; | |
| 1212 | wire demap_all; | |
| 1213 | wire skip_demap; | |
| 1214 | wire demap_active; | |
| 1215 | wire auto_demap; | |
| 1216 | wire [2:0] demap_tid; | |
| 1217 | reg [2:0] demap_tid_1; | |
| 1218 | reg [5:0] demap_tnum_1; | |
| 1219 | ||
| 1220 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1221 | reg hwtw; | |
| 1222 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 1223 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1224 | ||
| 1225 | reg [2:0] mytid; | |
| 1226 | reg [5:0] mytnum; | |
| 1227 | wire [2:0] mycid; | |
| 1228 | integer junk; | |
| 1229 | integer i; | |
| 1230 | reg [7:0] cnt; | |
| 1231 | wire ready; | |
| 1232 | ||
| 1233 | assign mycid = 3; | |
| 1234 | ||
| 1235 | `ifdef DEBUG_TLB | |
| 1236 | wire [7:0] my_asi0 = my_asi[0]; | |
| 1237 | wire [7:0] my_asi1 = my_asi[1]; | |
| 1238 | wire [7:0] my_asi2 = my_asi[2]; | |
| 1239 | wire [7:0] my_asi3 = my_asi[3]; | |
| 1240 | wire [7:0] my_asi4 = my_asi[4]; | |
| 1241 | wire [7:0] my_asi5 = my_asi[5]; | |
| 1242 | wire [7:0] my_asi6 = my_asi[6]; | |
| 1243 | wire [7:0] my_asi7 = my_asi[7]; | |
| 1244 | `endif | |
| 1245 | ||
| 1246 | //---------------------------------------------------------- | |
| 1247 | // Instantiate fifo - 1 entry per thread | |
| 1248 | fifo fifo (); | |
| 1249 | // Define fifo parameters | |
| 1250 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 1251 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 1252 | defparam fifo.PTR_BITS = 4; | |
| 1253 | ||
| 1254 | //---------------------------------------------------------- | |
| 1255 | // DUT probes | |
| 1256 | ||
| 1257 | assign data_in = `SPC3.mmu.asi.wrote_dtlb; | |
| 1258 | assign tlb_wr = `SPC3.mmu_reload_done; | |
| 1259 | assign wr_en = `SPC3.lsu.tlb.tlb_wr_1_in_dout; | |
| 1260 | ||
| 1261 | assign entry = `SPC3.lsu.tlb.rw_index_1[6:0]; | |
| 1262 | ||
| 1263 | assign asi_num = `PROBES3.asi_num; | |
| 1264 | assign asi_enable0 = `PROBES3.tlb_rd_vld_b & | |
| 1265 | !`PROBES3.tlb_bypass_b & | |
| 1266 | `SPC3.tlu.fls0.lsu_inst_b; | |
| 1267 | assign asi_enable1 = `PROBES3.tlb_rd_vld_b & | |
| 1268 | !`PROBES3.tlb_bypass_b & | |
| 1269 | `SPC3.tlu.fls1.lsu_inst_b; | |
| 1270 | ||
| 1271 | assign store_asi[3:0] = asi_enable0 ? `PROBES3.select_pc_b[3:0] : 4'b0; | |
| 1272 | assign store_asi[7:4] = asi_enable1 ? `PROBES3.select_pc_b[7:4] : 4'b0; | |
| 1273 | ||
| 1274 | assign demap_page = `SPC3.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 1275 | assign demap_context = `SPC3.lsu.tlc_demap_context; | |
| 1276 | assign demap_real = `SPC3.lsu.tlc_demap_real; | |
| 1277 | assign demap_all = `SPC3.lsu.tlc_demap_all; | |
| 1278 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 1279 | assign skip_demap =`SPC3.lsu.tlc_wr_u_en; | |
| 1280 | assign demap_tid = `SPC3.lsu.tld.tte1[37:35]; | |
| 1281 | ||
| 1282 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 1283 | assign demap_active = |demap_1 && !skip_demap; | |
| 1284 | assign auto_demap = |demap_1 && skip_demap; | |
| 1285 | ||
| 1286 | //--------------------- | |
| 1287 | // Probes for debugging | |
| 1288 | ||
| 1289 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 1290 | ||
| 1291 | // n2_tlb_tl_128x59_cam.sv | |
| 1292 | ||
| 1293 | `define CNTX1_HI 65 | |
| 1294 | `define CNTX1_LO 53 | |
| 1295 | `define PID_HI 52 | |
| 1296 | `define PID_LO 50 | |
| 1297 | `define REAL_BIT 49 | |
| 1298 | `define VA_47 48 | |
| 1299 | `define VA_28 29 | |
| 1300 | `define VA_27 28 | |
| 1301 | `define VA_22 23 | |
| 1302 | `define TTE_VALID 22 | |
| 1303 | `define VA_21 21 | |
| 1304 | `define VA_16 16 | |
| 1305 | `define VA_15 15 | |
| 1306 | `define VA_13 13 | |
| 1307 | `define CNTX0_HI 12 | |
| 1308 | `define CNTX0_LO 0 | |
| 1309 | ||
| 1310 | // n2_tlb_tl_128x59_ram.sv | |
| 1311 | ||
| 1312 | `define DATA_PARITY 36 | |
| 1313 | `define DATA_PA_39_28_HI 35 | |
| 1314 | `define DATA_PA_39_28_LO 24 | |
| 1315 | `define DATA_PA_27_22_HI 23 | |
| 1316 | `define DATA_PA_27_22_LO 18 | |
| 1317 | `define DATA_VA_27_22_V 17 | |
| 1318 | `define DATA_PA_21_16_HI 16 | |
| 1319 | `define DATA_PA_21_16_LO 11 | |
| 1320 | `define DATA_VA_21_16_V 10 | |
| 1321 | `define DATA_PA_15_13_HI 9 | |
| 1322 | `define DATA_PA_15_13_LO 7 | |
| 1323 | `define DATA_VA_15_13_V 6 | |
| 1324 | `define DATA_NFO 5 | |
| 1325 | `define DATA_IE 4 | |
| 1326 | `define DATA_CP 3 | |
| 1327 | `define DATA_X 2 | |
| 1328 | `define DATA_P 1 | |
| 1329 | `define DATA_W 0 | |
| 1330 | ||
| 1331 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 1332 | wire [(NUM_TLB-1):0] tlb_match; | |
| 1333 | wire tte_valid; | |
| 1334 | wire [47:0] tte_va; | |
| 1335 | wire [12:0] tte_context; | |
| 1336 | wire tte_real; | |
| 1337 | wire [2:0] tte_pid; | |
| 1338 | wire [2:0] tte_page_mask; | |
| 1339 | wire [39:0] tte_pa; | |
| 1340 | wire tte_nfo; | |
| 1341 | wire tte_ie; | |
| 1342 | wire tte_cp; | |
| 1343 | wire tte_e; | |
| 1344 | wire tte_p; | |
| 1345 | wire tte_w; | |
| 1346 | wire tte_ep; | |
| 1347 | ||
| 1348 | ||
| 1349 | assign tlb_valid = `SPC3.lsu.tlb.array.cam.valid; | |
| 1350 | assign tlb_match = `SPC3.lsu.tlb.array.cam.match; | |
| 1351 | ||
| 1352 | assign tte_va = {`SPC3.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 1353 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 1354 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 1355 | `SPC3.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 1356 | 13'b0 | |
| 1357 | }; | |
| 1358 | assign tte_context = `SPC3.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 1359 | assign tte_pid = `SPC3.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 1360 | assign tte_real = `SPC3.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 1361 | assign tte_valid = `SPC3.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 1362 | ||
| 1363 | assign tte_page_mask = `SPC3.lsu.tlb.tte_page_size_mask_1; | |
| 1364 | ||
| 1365 | assign tte_pa = {`SPC3.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 1366 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 1367 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 1368 | `SPC3.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 1369 | 13'b0 | |
| 1370 | }; | |
| 1371 | assign tte_nfo = `SPC3.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 1372 | assign tte_ie = `SPC3.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 1373 | assign tte_cp = `SPC3.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 1374 | assign tte_e = `SPC3.lsu.tlb.tte_data_1[`DATA_X]; | |
| 1375 | assign tte_p = `SPC3.lsu.tlb.tte_data_1[`DATA_P]; | |
| 1376 | assign tte_w = `SPC3.lsu.tlb.tte_data_1[`DATA_W]; | |
| 1377 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 1378 | ||
| 1379 | assign ready = `PARGS.tlb_sync_on & !`SPC3.tcu_spc_mbist_start; | |
| 1380 | ||
| 1381 | //---------------------------------------------------------- | |
| 1382 | // Initialize state machine to idle state | |
| 1383 | initial begin // { | |
| 1384 | #1; | |
| 1385 | hwtw = 1'b0; | |
| 1386 | for (i=0; i<=7; i=i+1) begin | |
| 1387 | my_asi[i] = 8'b0; | |
| 1388 | end | |
| 1389 | @ (posedge `SPC3.l2clk); | |
| 1390 | ||
| 1391 | end // } | |
| 1392 | ||
| 1393 | //---------------------------------------------------------- | |
| 1394 | // Must use negedge to avoid race condition | |
| 1395 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 1396 | ||
| 1397 | always @ (negedge (`SPC3.l2clk & ready)) begin // { | |
| 1398 | ||
| 1399 | tstamp = `TOP.core_cycle_cnt; | |
| 1400 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 1401 | ||
| 1402 | // Delay by 1 cycle to align with skip_demap | |
| 1403 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 1404 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 1405 | demap_1 <= demap; | |
| 1406 | ||
| 1407 | //---------------------------------------------------------- | |
| 1408 | // Send I/DTLBWRITE due to demap | |
| 1409 | // | |
| 1410 | ||
| 1411 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1412 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1413 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 1414 | mycid,demap_tid_1); | |
| 1415 | end // } | |
| 1416 | ||
| 1417 | if (demap_active) begin // { | |
| 1418 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1419 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1420 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1421 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1422 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1423 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 1424 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1425 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1426 | ||
| 1427 | // sstep_sent is asserted when data_in is asserted | |
| 1428 | // Check to see if sstep was sent early | |
| 1429 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1430 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1431 | end //} | |
| 1432 | ||
| 1433 | end //} | |
| 1434 | end //} | |
| 1435 | ||
| 1436 | //-------------------- | |
| 1437 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1438 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1439 | ||
| 1440 | if (demap_active) begin | |
| 1441 | case (demap_1) | |
| 1442 | 4'b0001: $write ("type=real "); | |
| 1443 | 4'b0010: $write ("type=cntx "); | |
| 1444 | 4'b0100: $write ("type=page "); | |
| 1445 | 4'b1000: $write ("type=all "); | |
| 1446 | default: | |
| 1447 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1448 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1449 | endcase | |
| 1450 | end | |
| 1451 | else begin | |
| 1452 | $write ("type=autodemap "); | |
| 1453 | end | |
| 1454 | ||
| 1455 | $display ("match=%h ts=%0d", | |
| 1456 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1457 | ||
| 1458 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1459 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1460 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1461 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1462 | end // } | |
| 1463 | end // } | |
| 1464 | //-------------------- | |
| 1465 | end // } | |
| 1466 | ||
| 1467 | //---------------------------------------------------------- | |
| 1468 | // Send I/DHWTW due to HWTW | |
| 1469 | // Send I/DTLBWRITE due to ASI write | |
| 1470 | ||
| 1471 | // Save asi num when DTLBREAD happens. | |
| 1472 | // Otherwise, hold state. | |
| 1473 | // Send asi num later with DHWTW | |
| 1474 | for (i=0;i<=7;i=i+1) begin // { | |
| 1475 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 1476 | end // } | |
| 1477 | ||
| 1478 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1479 | // These signals will be interleaved between the threads. | |
| 1480 | // Need to queue up the signals over time so they can be processed in order. | |
| 1481 | // Each thread will only be doing 1 thing at a time. | |
| 1482 | ||
| 1483 | for (i=0;i<=7;i=i+1) begin // { | |
| 1484 | ||
| 1485 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 1486 | ||
| 1487 | // data_in[tid] determines which thread will write next | |
| 1488 | // Use fifo to save the tids of the data_in signals in order | |
| 1489 | ||
| 1490 | if (data_in[i]) begin // { | |
| 1491 | if (tlb_wr[i]) begin // { | |
| 1492 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1493 | end // } | |
| 1494 | else begin // { | |
| 1495 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1496 | ||
| 1497 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 1498 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 1499 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1500 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1501 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 1502 | end // } | |
| 1503 | end // } | |
| 1504 | ||
| 1505 | end // } | |
| 1506 | ||
| 1507 | //---------------------------------------------------------- | |
| 1508 | // wr_en means that the write is occurring | |
| 1509 | if (wr_en) begin // { | |
| 1510 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1511 | mytnum = (mycid * 8) + mytid; | |
| 1512 | ||
| 1513 | if (hwtw) begin // { | |
| 1514 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1515 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 1516 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1517 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1518 | ||
| 1519 | end //} | |
| 1520 | end // } | |
| 1521 | else begin // { | |
| 1522 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1523 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 1524 | mycid,mytid,mytnum,tstamp,entry); | |
| 1525 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1526 | mycid,mytid,mytnum,tstamp); | |
| 1527 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 1528 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1529 | ||
| 1530 | // Check to see if sstep was sent early | |
| 1531 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1532 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1533 | end //} | |
| 1534 | ||
| 1535 | end //} | |
| 1536 | end // } | |
| 1537 | ||
| 1538 | //-------------------- | |
| 1539 | if (`PARGS.show_tlb_on) begin // { | |
| 1540 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1541 | ||
| 1542 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1543 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1544 | ||
| 1545 | case (tte_page_mask) | |
| 1546 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1547 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1548 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1549 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1550 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1551 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1552 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1553 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1554 | endcase | |
| 1555 | ||
| 1556 | if (hwtw) $display (" (hwtw)"); | |
| 1557 | else $display (""); | |
| 1558 | ||
| 1559 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1560 | ||
| 1561 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 1562 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 1563 | end // } | |
| 1564 | //-------------------- | |
| 1565 | ||
| 1566 | end // } | |
| 1567 | ||
| 1568 | end // always} | |
| 1569 | ||
| 1570 | //---------------------------------------------------------- | |
| 1571 | `endif | |
| 1572 | endmodule | |
| 1573 | ||
| 1574 | `endif | |
| 1575 | `ifdef CORE_4 | |
| 1576 | ||
| 1577 | module dtlb_wr_c4 (); | |
| 1578 | `ifndef GATESIM | |
| 1579 | ||
| 1580 | `include "tlb_sync.vh" | |
| 1581 | `include "nas.vh" | |
| 1582 | parameter NUM_TLB=128; | |
| 1583 | ||
| 1584 | wire [7:0] data_in; | |
| 1585 | wire [7:0] tlb_wr; | |
| 1586 | wire wr_en; | |
| 1587 | wire [7:0] entry; | |
| 1588 | wire [7:0] asi_num; | |
| 1589 | wire asi_enable0; // 1 per thread group | |
| 1590 | wire asi_enable1; | |
| 1591 | wire [7:0] store_asi; // 1 per thread | |
| 1592 | wire [3:0] demap; | |
| 1593 | reg [3:0] demap_1; | |
| 1594 | wire demap_page; | |
| 1595 | wire demap_context; | |
| 1596 | wire demap_real; | |
| 1597 | wire demap_all; | |
| 1598 | wire skip_demap; | |
| 1599 | wire demap_active; | |
| 1600 | wire auto_demap; | |
| 1601 | wire [2:0] demap_tid; | |
| 1602 | reg [2:0] demap_tid_1; | |
| 1603 | reg [5:0] demap_tnum_1; | |
| 1604 | ||
| 1605 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1606 | reg hwtw; | |
| 1607 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 1608 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1609 | ||
| 1610 | reg [2:0] mytid; | |
| 1611 | reg [5:0] mytnum; | |
| 1612 | wire [2:0] mycid; | |
| 1613 | integer junk; | |
| 1614 | integer i; | |
| 1615 | reg [7:0] cnt; | |
| 1616 | wire ready; | |
| 1617 | ||
| 1618 | assign mycid = 4; | |
| 1619 | ||
| 1620 | `ifdef DEBUG_TLB | |
| 1621 | wire [7:0] my_asi0 = my_asi[0]; | |
| 1622 | wire [7:0] my_asi1 = my_asi[1]; | |
| 1623 | wire [7:0] my_asi2 = my_asi[2]; | |
| 1624 | wire [7:0] my_asi3 = my_asi[3]; | |
| 1625 | wire [7:0] my_asi4 = my_asi[4]; | |
| 1626 | wire [7:0] my_asi5 = my_asi[5]; | |
| 1627 | wire [7:0] my_asi6 = my_asi[6]; | |
| 1628 | wire [7:0] my_asi7 = my_asi[7]; | |
| 1629 | `endif | |
| 1630 | ||
| 1631 | //---------------------------------------------------------- | |
| 1632 | // Instantiate fifo - 1 entry per thread | |
| 1633 | fifo fifo (); | |
| 1634 | // Define fifo parameters | |
| 1635 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 1636 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 1637 | defparam fifo.PTR_BITS = 4; | |
| 1638 | ||
| 1639 | //---------------------------------------------------------- | |
| 1640 | // DUT probes | |
| 1641 | ||
| 1642 | assign data_in = `SPC4.mmu.asi.wrote_dtlb; | |
| 1643 | assign tlb_wr = `SPC4.mmu_reload_done; | |
| 1644 | assign wr_en = `SPC4.lsu.tlb.tlb_wr_1_in_dout; | |
| 1645 | ||
| 1646 | assign entry = `SPC4.lsu.tlb.rw_index_1[6:0]; | |
| 1647 | ||
| 1648 | assign asi_num = `PROBES4.asi_num; | |
| 1649 | assign asi_enable0 = `PROBES4.tlb_rd_vld_b & | |
| 1650 | !`PROBES4.tlb_bypass_b & | |
| 1651 | `SPC4.tlu.fls0.lsu_inst_b; | |
| 1652 | assign asi_enable1 = `PROBES4.tlb_rd_vld_b & | |
| 1653 | !`PROBES4.tlb_bypass_b & | |
| 1654 | `SPC4.tlu.fls1.lsu_inst_b; | |
| 1655 | ||
| 1656 | assign store_asi[3:0] = asi_enable0 ? `PROBES4.select_pc_b[3:0] : 4'b0; | |
| 1657 | assign store_asi[7:4] = asi_enable1 ? `PROBES4.select_pc_b[7:4] : 4'b0; | |
| 1658 | ||
| 1659 | assign demap_page = `SPC4.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 1660 | assign demap_context = `SPC4.lsu.tlc_demap_context; | |
| 1661 | assign demap_real = `SPC4.lsu.tlc_demap_real; | |
| 1662 | assign demap_all = `SPC4.lsu.tlc_demap_all; | |
| 1663 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 1664 | assign skip_demap =`SPC4.lsu.tlc_wr_u_en; | |
| 1665 | assign demap_tid = `SPC4.lsu.tld.tte1[37:35]; | |
| 1666 | ||
| 1667 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 1668 | assign demap_active = |demap_1 && !skip_demap; | |
| 1669 | assign auto_demap = |demap_1 && skip_demap; | |
| 1670 | ||
| 1671 | //--------------------- | |
| 1672 | // Probes for debugging | |
| 1673 | ||
| 1674 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 1675 | ||
| 1676 | // n2_tlb_tl_128x59_cam.sv | |
| 1677 | ||
| 1678 | `define CNTX1_HI 65 | |
| 1679 | `define CNTX1_LO 53 | |
| 1680 | `define PID_HI 52 | |
| 1681 | `define PID_LO 50 | |
| 1682 | `define REAL_BIT 49 | |
| 1683 | `define VA_47 48 | |
| 1684 | `define VA_28 29 | |
| 1685 | `define VA_27 28 | |
| 1686 | `define VA_22 23 | |
| 1687 | `define TTE_VALID 22 | |
| 1688 | `define VA_21 21 | |
| 1689 | `define VA_16 16 | |
| 1690 | `define VA_15 15 | |
| 1691 | `define VA_13 13 | |
| 1692 | `define CNTX0_HI 12 | |
| 1693 | `define CNTX0_LO 0 | |
| 1694 | ||
| 1695 | // n2_tlb_tl_128x59_ram.sv | |
| 1696 | ||
| 1697 | `define DATA_PARITY 36 | |
| 1698 | `define DATA_PA_39_28_HI 35 | |
| 1699 | `define DATA_PA_39_28_LO 24 | |
| 1700 | `define DATA_PA_27_22_HI 23 | |
| 1701 | `define DATA_PA_27_22_LO 18 | |
| 1702 | `define DATA_VA_27_22_V 17 | |
| 1703 | `define DATA_PA_21_16_HI 16 | |
| 1704 | `define DATA_PA_21_16_LO 11 | |
| 1705 | `define DATA_VA_21_16_V 10 | |
| 1706 | `define DATA_PA_15_13_HI 9 | |
| 1707 | `define DATA_PA_15_13_LO 7 | |
| 1708 | `define DATA_VA_15_13_V 6 | |
| 1709 | `define DATA_NFO 5 | |
| 1710 | `define DATA_IE 4 | |
| 1711 | `define DATA_CP 3 | |
| 1712 | `define DATA_X 2 | |
| 1713 | `define DATA_P 1 | |
| 1714 | `define DATA_W 0 | |
| 1715 | ||
| 1716 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 1717 | wire [(NUM_TLB-1):0] tlb_match; | |
| 1718 | wire tte_valid; | |
| 1719 | wire [47:0] tte_va; | |
| 1720 | wire [12:0] tte_context; | |
| 1721 | wire tte_real; | |
| 1722 | wire [2:0] tte_pid; | |
| 1723 | wire [2:0] tte_page_mask; | |
| 1724 | wire [39:0] tte_pa; | |
| 1725 | wire tte_nfo; | |
| 1726 | wire tte_ie; | |
| 1727 | wire tte_cp; | |
| 1728 | wire tte_e; | |
| 1729 | wire tte_p; | |
| 1730 | wire tte_w; | |
| 1731 | wire tte_ep; | |
| 1732 | ||
| 1733 | ||
| 1734 | assign tlb_valid = `SPC4.lsu.tlb.array.cam.valid; | |
| 1735 | assign tlb_match = `SPC4.lsu.tlb.array.cam.match; | |
| 1736 | ||
| 1737 | assign tte_va = {`SPC4.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 1738 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 1739 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 1740 | `SPC4.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 1741 | 13'b0 | |
| 1742 | }; | |
| 1743 | assign tte_context = `SPC4.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 1744 | assign tte_pid = `SPC4.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 1745 | assign tte_real = `SPC4.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 1746 | assign tte_valid = `SPC4.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 1747 | ||
| 1748 | assign tte_page_mask = `SPC4.lsu.tlb.tte_page_size_mask_1; | |
| 1749 | ||
| 1750 | assign tte_pa = {`SPC4.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 1751 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 1752 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 1753 | `SPC4.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 1754 | 13'b0 | |
| 1755 | }; | |
| 1756 | assign tte_nfo = `SPC4.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 1757 | assign tte_ie = `SPC4.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 1758 | assign tte_cp = `SPC4.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 1759 | assign tte_e = `SPC4.lsu.tlb.tte_data_1[`DATA_X]; | |
| 1760 | assign tte_p = `SPC4.lsu.tlb.tte_data_1[`DATA_P]; | |
| 1761 | assign tte_w = `SPC4.lsu.tlb.tte_data_1[`DATA_W]; | |
| 1762 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 1763 | ||
| 1764 | assign ready = `PARGS.tlb_sync_on & !`SPC4.tcu_spc_mbist_start; | |
| 1765 | ||
| 1766 | //---------------------------------------------------------- | |
| 1767 | // Initialize state machine to idle state | |
| 1768 | initial begin // { | |
| 1769 | #1; | |
| 1770 | hwtw = 1'b0; | |
| 1771 | for (i=0; i<=7; i=i+1) begin | |
| 1772 | my_asi[i] = 8'b0; | |
| 1773 | end | |
| 1774 | @ (posedge `SPC4.l2clk); | |
| 1775 | ||
| 1776 | end // } | |
| 1777 | ||
| 1778 | //---------------------------------------------------------- | |
| 1779 | // Must use negedge to avoid race condition | |
| 1780 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 1781 | ||
| 1782 | always @ (negedge (`SPC4.l2clk & ready)) begin // { | |
| 1783 | ||
| 1784 | tstamp = `TOP.core_cycle_cnt; | |
| 1785 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 1786 | ||
| 1787 | // Delay by 1 cycle to align with skip_demap | |
| 1788 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 1789 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 1790 | demap_1 <= demap; | |
| 1791 | ||
| 1792 | //---------------------------------------------------------- | |
| 1793 | // Send I/DTLBWRITE due to demap | |
| 1794 | // | |
| 1795 | ||
| 1796 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 1797 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1798 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 1799 | mycid,demap_tid_1); | |
| 1800 | end // } | |
| 1801 | ||
| 1802 | if (demap_active) begin // { | |
| 1803 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1804 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1805 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 1806 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 1807 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1808 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 1809 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 1810 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 1811 | ||
| 1812 | // sstep_sent is asserted when data_in is asserted | |
| 1813 | // Check to see if sstep was sent early | |
| 1814 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 1815 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1816 | end //} | |
| 1817 | ||
| 1818 | end //} | |
| 1819 | end //} | |
| 1820 | ||
| 1821 | //-------------------- | |
| 1822 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 1823 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 1824 | ||
| 1825 | if (demap_active) begin | |
| 1826 | case (demap_1) | |
| 1827 | 4'b0001: $write ("type=real "); | |
| 1828 | 4'b0010: $write ("type=cntx "); | |
| 1829 | 4'b0100: $write ("type=page "); | |
| 1830 | 4'b1000: $write ("type=all "); | |
| 1831 | default: | |
| 1832 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 1833 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 1834 | endcase | |
| 1835 | end | |
| 1836 | else begin | |
| 1837 | $write ("type=autodemap "); | |
| 1838 | end | |
| 1839 | ||
| 1840 | $display ("match=%h ts=%0d", | |
| 1841 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 1842 | ||
| 1843 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 1844 | if (tlb_match[cnt]==1'b1) begin // { | |
| 1845 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 1846 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 1847 | end // } | |
| 1848 | end // } | |
| 1849 | //-------------------- | |
| 1850 | end // } | |
| 1851 | ||
| 1852 | //---------------------------------------------------------- | |
| 1853 | // Send I/DHWTW due to HWTW | |
| 1854 | // Send I/DTLBWRITE due to ASI write | |
| 1855 | ||
| 1856 | // Save asi num when DTLBREAD happens. | |
| 1857 | // Otherwise, hold state. | |
| 1858 | // Send asi num later with DHWTW | |
| 1859 | for (i=0;i<=7;i=i+1) begin // { | |
| 1860 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 1861 | end // } | |
| 1862 | ||
| 1863 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 1864 | // These signals will be interleaved between the threads. | |
| 1865 | // Need to queue up the signals over time so they can be processed in order. | |
| 1866 | // Each thread will only be doing 1 thing at a time. | |
| 1867 | ||
| 1868 | for (i=0;i<=7;i=i+1) begin // { | |
| 1869 | ||
| 1870 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 1871 | ||
| 1872 | // data_in[tid] determines which thread will write next | |
| 1873 | // Use fifo to save the tids of the data_in signals in order | |
| 1874 | ||
| 1875 | if (data_in[i]) begin // { | |
| 1876 | if (tlb_wr[i]) begin // { | |
| 1877 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 1878 | end // } | |
| 1879 | else begin // { | |
| 1880 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 1881 | ||
| 1882 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 1883 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 1884 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 1885 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 1886 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 1887 | end // } | |
| 1888 | end // } | |
| 1889 | ||
| 1890 | end // } | |
| 1891 | ||
| 1892 | //---------------------------------------------------------- | |
| 1893 | // wr_en means that the write is occurring | |
| 1894 | if (wr_en) begin // { | |
| 1895 | fifo.pop_fifo ({hwtw,mytid}); | |
| 1896 | mytnum = (mycid * 8) + mytid; | |
| 1897 | ||
| 1898 | if (hwtw) begin // { | |
| 1899 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1900 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 1901 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1902 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 1903 | ||
| 1904 | end //} | |
| 1905 | end // } | |
| 1906 | else begin // { | |
| 1907 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 1908 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 1909 | mycid,mytid,mytnum,tstamp,entry); | |
| 1910 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 1911 | mycid,mytid,mytnum,tstamp); | |
| 1912 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 1913 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 1914 | ||
| 1915 | // Check to see if sstep was sent early | |
| 1916 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 1917 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 1918 | end //} | |
| 1919 | ||
| 1920 | end //} | |
| 1921 | end // } | |
| 1922 | ||
| 1923 | //-------------------- | |
| 1924 | if (`PARGS.show_tlb_on) begin // { | |
| 1925 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1926 | ||
| 1927 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 1928 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 1929 | ||
| 1930 | case (tte_page_mask) | |
| 1931 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 1932 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1933 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 1934 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1935 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 1936 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1937 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 1938 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 1939 | endcase | |
| 1940 | ||
| 1941 | if (hwtw) $display (" (hwtw)"); | |
| 1942 | else $display (""); | |
| 1943 | ||
| 1944 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 1945 | ||
| 1946 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 1947 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 1948 | end // } | |
| 1949 | //-------------------- | |
| 1950 | ||
| 1951 | end // } | |
| 1952 | ||
| 1953 | end // always} | |
| 1954 | ||
| 1955 | //---------------------------------------------------------- | |
| 1956 | `endif | |
| 1957 | endmodule | |
| 1958 | ||
| 1959 | `endif | |
| 1960 | `ifdef CORE_5 | |
| 1961 | ||
| 1962 | module dtlb_wr_c5 (); | |
| 1963 | `ifndef GATESIM | |
| 1964 | ||
| 1965 | `include "tlb_sync.vh" | |
| 1966 | `include "nas.vh" | |
| 1967 | parameter NUM_TLB=128; | |
| 1968 | ||
| 1969 | wire [7:0] data_in; | |
| 1970 | wire [7:0] tlb_wr; | |
| 1971 | wire wr_en; | |
| 1972 | wire [7:0] entry; | |
| 1973 | wire [7:0] asi_num; | |
| 1974 | wire asi_enable0; // 1 per thread group | |
| 1975 | wire asi_enable1; | |
| 1976 | wire [7:0] store_asi; // 1 per thread | |
| 1977 | wire [3:0] demap; | |
| 1978 | reg [3:0] demap_1; | |
| 1979 | wire demap_page; | |
| 1980 | wire demap_context; | |
| 1981 | wire demap_real; | |
| 1982 | wire demap_all; | |
| 1983 | wire skip_demap; | |
| 1984 | wire demap_active; | |
| 1985 | wire auto_demap; | |
| 1986 | wire [2:0] demap_tid; | |
| 1987 | reg [2:0] demap_tid_1; | |
| 1988 | reg [5:0] demap_tnum_1; | |
| 1989 | ||
| 1990 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 1991 | reg hwtw; | |
| 1992 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 1993 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 1994 | ||
| 1995 | reg [2:0] mytid; | |
| 1996 | reg [5:0] mytnum; | |
| 1997 | wire [2:0] mycid; | |
| 1998 | integer junk; | |
| 1999 | integer i; | |
| 2000 | reg [7:0] cnt; | |
| 2001 | wire ready; | |
| 2002 | ||
| 2003 | assign mycid = 5; | |
| 2004 | ||
| 2005 | `ifdef DEBUG_TLB | |
| 2006 | wire [7:0] my_asi0 = my_asi[0]; | |
| 2007 | wire [7:0] my_asi1 = my_asi[1]; | |
| 2008 | wire [7:0] my_asi2 = my_asi[2]; | |
| 2009 | wire [7:0] my_asi3 = my_asi[3]; | |
| 2010 | wire [7:0] my_asi4 = my_asi[4]; | |
| 2011 | wire [7:0] my_asi5 = my_asi[5]; | |
| 2012 | wire [7:0] my_asi6 = my_asi[6]; | |
| 2013 | wire [7:0] my_asi7 = my_asi[7]; | |
| 2014 | `endif | |
| 2015 | ||
| 2016 | //---------------------------------------------------------- | |
| 2017 | // Instantiate fifo - 1 entry per thread | |
| 2018 | fifo fifo (); | |
| 2019 | // Define fifo parameters | |
| 2020 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 2021 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 2022 | defparam fifo.PTR_BITS = 4; | |
| 2023 | ||
| 2024 | //---------------------------------------------------------- | |
| 2025 | // DUT probes | |
| 2026 | ||
| 2027 | assign data_in = `SPC5.mmu.asi.wrote_dtlb; | |
| 2028 | assign tlb_wr = `SPC5.mmu_reload_done; | |
| 2029 | assign wr_en = `SPC5.lsu.tlb.tlb_wr_1_in_dout; | |
| 2030 | ||
| 2031 | assign entry = `SPC5.lsu.tlb.rw_index_1[6:0]; | |
| 2032 | ||
| 2033 | assign asi_num = `PROBES5.asi_num; | |
| 2034 | assign asi_enable0 = `PROBES5.tlb_rd_vld_b & | |
| 2035 | !`PROBES5.tlb_bypass_b & | |
| 2036 | `SPC5.tlu.fls0.lsu_inst_b; | |
| 2037 | assign asi_enable1 = `PROBES5.tlb_rd_vld_b & | |
| 2038 | !`PROBES5.tlb_bypass_b & | |
| 2039 | `SPC5.tlu.fls1.lsu_inst_b; | |
| 2040 | ||
| 2041 | assign store_asi[3:0] = asi_enable0 ? `PROBES5.select_pc_b[3:0] : 4'b0; | |
| 2042 | assign store_asi[7:4] = asi_enable1 ? `PROBES5.select_pc_b[7:4] : 4'b0; | |
| 2043 | ||
| 2044 | assign demap_page = `SPC5.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 2045 | assign demap_context = `SPC5.lsu.tlc_demap_context; | |
| 2046 | assign demap_real = `SPC5.lsu.tlc_demap_real; | |
| 2047 | assign demap_all = `SPC5.lsu.tlc_demap_all; | |
| 2048 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 2049 | assign skip_demap =`SPC5.lsu.tlc_wr_u_en; | |
| 2050 | assign demap_tid = `SPC5.lsu.tld.tte1[37:35]; | |
| 2051 | ||
| 2052 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2053 | assign demap_active = |demap_1 && !skip_demap; | |
| 2054 | assign auto_demap = |demap_1 && skip_demap; | |
| 2055 | ||
| 2056 | //--------------------- | |
| 2057 | // Probes for debugging | |
| 2058 | ||
| 2059 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 2060 | ||
| 2061 | // n2_tlb_tl_128x59_cam.sv | |
| 2062 | ||
| 2063 | `define CNTX1_HI 65 | |
| 2064 | `define CNTX1_LO 53 | |
| 2065 | `define PID_HI 52 | |
| 2066 | `define PID_LO 50 | |
| 2067 | `define REAL_BIT 49 | |
| 2068 | `define VA_47 48 | |
| 2069 | `define VA_28 29 | |
| 2070 | `define VA_27 28 | |
| 2071 | `define VA_22 23 | |
| 2072 | `define TTE_VALID 22 | |
| 2073 | `define VA_21 21 | |
| 2074 | `define VA_16 16 | |
| 2075 | `define VA_15 15 | |
| 2076 | `define VA_13 13 | |
| 2077 | `define CNTX0_HI 12 | |
| 2078 | `define CNTX0_LO 0 | |
| 2079 | ||
| 2080 | // n2_tlb_tl_128x59_ram.sv | |
| 2081 | ||
| 2082 | `define DATA_PARITY 36 | |
| 2083 | `define DATA_PA_39_28_HI 35 | |
| 2084 | `define DATA_PA_39_28_LO 24 | |
| 2085 | `define DATA_PA_27_22_HI 23 | |
| 2086 | `define DATA_PA_27_22_LO 18 | |
| 2087 | `define DATA_VA_27_22_V 17 | |
| 2088 | `define DATA_PA_21_16_HI 16 | |
| 2089 | `define DATA_PA_21_16_LO 11 | |
| 2090 | `define DATA_VA_21_16_V 10 | |
| 2091 | `define DATA_PA_15_13_HI 9 | |
| 2092 | `define DATA_PA_15_13_LO 7 | |
| 2093 | `define DATA_VA_15_13_V 6 | |
| 2094 | `define DATA_NFO 5 | |
| 2095 | `define DATA_IE 4 | |
| 2096 | `define DATA_CP 3 | |
| 2097 | `define DATA_X 2 | |
| 2098 | `define DATA_P 1 | |
| 2099 | `define DATA_W 0 | |
| 2100 | ||
| 2101 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2102 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2103 | wire tte_valid; | |
| 2104 | wire [47:0] tte_va; | |
| 2105 | wire [12:0] tte_context; | |
| 2106 | wire tte_real; | |
| 2107 | wire [2:0] tte_pid; | |
| 2108 | wire [2:0] tte_page_mask; | |
| 2109 | wire [39:0] tte_pa; | |
| 2110 | wire tte_nfo; | |
| 2111 | wire tte_ie; | |
| 2112 | wire tte_cp; | |
| 2113 | wire tte_e; | |
| 2114 | wire tte_p; | |
| 2115 | wire tte_w; | |
| 2116 | wire tte_ep; | |
| 2117 | ||
| 2118 | ||
| 2119 | assign tlb_valid = `SPC5.lsu.tlb.array.cam.valid; | |
| 2120 | assign tlb_match = `SPC5.lsu.tlb.array.cam.match; | |
| 2121 | ||
| 2122 | assign tte_va = {`SPC5.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2123 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2124 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2125 | `SPC5.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2126 | 13'b0 | |
| 2127 | }; | |
| 2128 | assign tte_context = `SPC5.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2129 | assign tte_pid = `SPC5.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2130 | assign tte_real = `SPC5.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 2131 | assign tte_valid = `SPC5.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 2132 | ||
| 2133 | assign tte_page_mask = `SPC5.lsu.tlb.tte_page_size_mask_1; | |
| 2134 | ||
| 2135 | assign tte_pa = {`SPC5.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2136 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2137 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2138 | `SPC5.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2139 | 13'b0 | |
| 2140 | }; | |
| 2141 | assign tte_nfo = `SPC5.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 2142 | assign tte_ie = `SPC5.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 2143 | assign tte_cp = `SPC5.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 2144 | assign tte_e = `SPC5.lsu.tlb.tte_data_1[`DATA_X]; | |
| 2145 | assign tte_p = `SPC5.lsu.tlb.tte_data_1[`DATA_P]; | |
| 2146 | assign tte_w = `SPC5.lsu.tlb.tte_data_1[`DATA_W]; | |
| 2147 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 2148 | ||
| 2149 | assign ready = `PARGS.tlb_sync_on & !`SPC5.tcu_spc_mbist_start; | |
| 2150 | ||
| 2151 | //---------------------------------------------------------- | |
| 2152 | // Initialize state machine to idle state | |
| 2153 | initial begin // { | |
| 2154 | #1; | |
| 2155 | hwtw = 1'b0; | |
| 2156 | for (i=0; i<=7; i=i+1) begin | |
| 2157 | my_asi[i] = 8'b0; | |
| 2158 | end | |
| 2159 | @ (posedge `SPC5.l2clk); | |
| 2160 | ||
| 2161 | end // } | |
| 2162 | ||
| 2163 | //---------------------------------------------------------- | |
| 2164 | // Must use negedge to avoid race condition | |
| 2165 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 2166 | ||
| 2167 | always @ (negedge (`SPC5.l2clk & ready)) begin // { | |
| 2168 | ||
| 2169 | tstamp = `TOP.core_cycle_cnt; | |
| 2170 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2171 | ||
| 2172 | // Delay by 1 cycle to align with skip_demap | |
| 2173 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2174 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2175 | demap_1 <= demap; | |
| 2176 | ||
| 2177 | //---------------------------------------------------------- | |
| 2178 | // Send I/DTLBWRITE due to demap | |
| 2179 | // | |
| 2180 | ||
| 2181 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2182 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2183 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 2184 | mycid,demap_tid_1); | |
| 2185 | end // } | |
| 2186 | ||
| 2187 | if (demap_active) begin // { | |
| 2188 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2189 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2190 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2191 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2192 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2193 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 2194 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2195 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2196 | ||
| 2197 | // sstep_sent is asserted when data_in is asserted | |
| 2198 | // Check to see if sstep was sent early | |
| 2199 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2200 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2201 | end //} | |
| 2202 | ||
| 2203 | end //} | |
| 2204 | end //} | |
| 2205 | ||
| 2206 | //-------------------- | |
| 2207 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2208 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2209 | ||
| 2210 | if (demap_active) begin | |
| 2211 | case (demap_1) | |
| 2212 | 4'b0001: $write ("type=real "); | |
| 2213 | 4'b0010: $write ("type=cntx "); | |
| 2214 | 4'b0100: $write ("type=page "); | |
| 2215 | 4'b1000: $write ("type=all "); | |
| 2216 | default: | |
| 2217 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2218 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2219 | endcase | |
| 2220 | end | |
| 2221 | else begin | |
| 2222 | $write ("type=autodemap "); | |
| 2223 | end | |
| 2224 | ||
| 2225 | $display ("match=%h ts=%0d", | |
| 2226 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2227 | ||
| 2228 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2229 | if (tlb_match[cnt]==1'b1) begin // { | |
| 2230 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 2231 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 2232 | end // } | |
| 2233 | end // } | |
| 2234 | //-------------------- | |
| 2235 | end // } | |
| 2236 | ||
| 2237 | //---------------------------------------------------------- | |
| 2238 | // Send I/DHWTW due to HWTW | |
| 2239 | // Send I/DTLBWRITE due to ASI write | |
| 2240 | ||
| 2241 | // Save asi num when DTLBREAD happens. | |
| 2242 | // Otherwise, hold state. | |
| 2243 | // Send asi num later with DHWTW | |
| 2244 | for (i=0;i<=7;i=i+1) begin // { | |
| 2245 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 2246 | end // } | |
| 2247 | ||
| 2248 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 2249 | // These signals will be interleaved between the threads. | |
| 2250 | // Need to queue up the signals over time so they can be processed in order. | |
| 2251 | // Each thread will only be doing 1 thing at a time. | |
| 2252 | ||
| 2253 | for (i=0;i<=7;i=i+1) begin // { | |
| 2254 | ||
| 2255 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 2256 | ||
| 2257 | // data_in[tid] determines which thread will write next | |
| 2258 | // Use fifo to save the tids of the data_in signals in order | |
| 2259 | ||
| 2260 | if (data_in[i]) begin // { | |
| 2261 | if (tlb_wr[i]) begin // { | |
| 2262 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 2263 | end // } | |
| 2264 | else begin // { | |
| 2265 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 2266 | ||
| 2267 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 2268 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 2269 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 2270 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 2271 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 2272 | end // } | |
| 2273 | end // } | |
| 2274 | ||
| 2275 | end // } | |
| 2276 | ||
| 2277 | //---------------------------------------------------------- | |
| 2278 | // wr_en means that the write is occurring | |
| 2279 | if (wr_en) begin // { | |
| 2280 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2281 | mytnum = (mycid * 8) + mytid; | |
| 2282 | ||
| 2283 | if (hwtw) begin // { | |
| 2284 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2285 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 2286 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 2287 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 2288 | ||
| 2289 | end //} | |
| 2290 | end // } | |
| 2291 | else begin // { | |
| 2292 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2293 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 2294 | mycid,mytid,mytnum,tstamp,entry); | |
| 2295 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2296 | mycid,mytid,mytnum,tstamp); | |
| 2297 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 2298 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 2299 | ||
| 2300 | // Check to see if sstep was sent early | |
| 2301 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 2302 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2303 | end //} | |
| 2304 | ||
| 2305 | end //} | |
| 2306 | end // } | |
| 2307 | ||
| 2308 | //-------------------- | |
| 2309 | if (`PARGS.show_tlb_on) begin // { | |
| 2310 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2311 | ||
| 2312 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 2313 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 2314 | ||
| 2315 | case (tte_page_mask) | |
| 2316 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 2317 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2318 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 2319 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2320 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 2321 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2322 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 2323 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2324 | endcase | |
| 2325 | ||
| 2326 | if (hwtw) $display (" (hwtw)"); | |
| 2327 | else $display (""); | |
| 2328 | ||
| 2329 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2330 | ||
| 2331 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 2332 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 2333 | end // } | |
| 2334 | //-------------------- | |
| 2335 | ||
| 2336 | end // } | |
| 2337 | ||
| 2338 | end // always} | |
| 2339 | ||
| 2340 | //---------------------------------------------------------- | |
| 2341 | `endif | |
| 2342 | endmodule | |
| 2343 | ||
| 2344 | `endif | |
| 2345 | `ifdef CORE_6 | |
| 2346 | ||
| 2347 | module dtlb_wr_c6 (); | |
| 2348 | `ifndef GATESIM | |
| 2349 | ||
| 2350 | `include "tlb_sync.vh" | |
| 2351 | `include "nas.vh" | |
| 2352 | parameter NUM_TLB=128; | |
| 2353 | ||
| 2354 | wire [7:0] data_in; | |
| 2355 | wire [7:0] tlb_wr; | |
| 2356 | wire wr_en; | |
| 2357 | wire [7:0] entry; | |
| 2358 | wire [7:0] asi_num; | |
| 2359 | wire asi_enable0; // 1 per thread group | |
| 2360 | wire asi_enable1; | |
| 2361 | wire [7:0] store_asi; // 1 per thread | |
| 2362 | wire [3:0] demap; | |
| 2363 | reg [3:0] demap_1; | |
| 2364 | wire demap_page; | |
| 2365 | wire demap_context; | |
| 2366 | wire demap_real; | |
| 2367 | wire demap_all; | |
| 2368 | wire skip_demap; | |
| 2369 | wire demap_active; | |
| 2370 | wire auto_demap; | |
| 2371 | wire [2:0] demap_tid; | |
| 2372 | reg [2:0] demap_tid_1; | |
| 2373 | reg [5:0] demap_tnum_1; | |
| 2374 | ||
| 2375 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 2376 | reg hwtw; | |
| 2377 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 2378 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 2379 | ||
| 2380 | reg [2:0] mytid; | |
| 2381 | reg [5:0] mytnum; | |
| 2382 | wire [2:0] mycid; | |
| 2383 | integer junk; | |
| 2384 | integer i; | |
| 2385 | reg [7:0] cnt; | |
| 2386 | wire ready; | |
| 2387 | ||
| 2388 | assign mycid = 6; | |
| 2389 | ||
| 2390 | `ifdef DEBUG_TLB | |
| 2391 | wire [7:0] my_asi0 = my_asi[0]; | |
| 2392 | wire [7:0] my_asi1 = my_asi[1]; | |
| 2393 | wire [7:0] my_asi2 = my_asi[2]; | |
| 2394 | wire [7:0] my_asi3 = my_asi[3]; | |
| 2395 | wire [7:0] my_asi4 = my_asi[4]; | |
| 2396 | wire [7:0] my_asi5 = my_asi[5]; | |
| 2397 | wire [7:0] my_asi6 = my_asi[6]; | |
| 2398 | wire [7:0] my_asi7 = my_asi[7]; | |
| 2399 | `endif | |
| 2400 | ||
| 2401 | //---------------------------------------------------------- | |
| 2402 | // Instantiate fifo - 1 entry per thread | |
| 2403 | fifo fifo (); | |
| 2404 | // Define fifo parameters | |
| 2405 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 2406 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 2407 | defparam fifo.PTR_BITS = 4; | |
| 2408 | ||
| 2409 | //---------------------------------------------------------- | |
| 2410 | // DUT probes | |
| 2411 | ||
| 2412 | assign data_in = `SPC6.mmu.asi.wrote_dtlb; | |
| 2413 | assign tlb_wr = `SPC6.mmu_reload_done; | |
| 2414 | assign wr_en = `SPC6.lsu.tlb.tlb_wr_1_in_dout; | |
| 2415 | ||
| 2416 | assign entry = `SPC6.lsu.tlb.rw_index_1[6:0]; | |
| 2417 | ||
| 2418 | assign asi_num = `PROBES6.asi_num; | |
| 2419 | assign asi_enable0 = `PROBES6.tlb_rd_vld_b & | |
| 2420 | !`PROBES6.tlb_bypass_b & | |
| 2421 | `SPC6.tlu.fls0.lsu_inst_b; | |
| 2422 | assign asi_enable1 = `PROBES6.tlb_rd_vld_b & | |
| 2423 | !`PROBES6.tlb_bypass_b & | |
| 2424 | `SPC6.tlu.fls1.lsu_inst_b; | |
| 2425 | ||
| 2426 | assign store_asi[3:0] = asi_enable0 ? `PROBES6.select_pc_b[3:0] : 4'b0; | |
| 2427 | assign store_asi[7:4] = asi_enable1 ? `PROBES6.select_pc_b[7:4] : 4'b0; | |
| 2428 | ||
| 2429 | assign demap_page = `SPC6.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 2430 | assign demap_context = `SPC6.lsu.tlc_demap_context; | |
| 2431 | assign demap_real = `SPC6.lsu.tlc_demap_real; | |
| 2432 | assign demap_all = `SPC6.lsu.tlc_demap_all; | |
| 2433 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 2434 | assign skip_demap =`SPC6.lsu.tlc_wr_u_en; | |
| 2435 | assign demap_tid = `SPC6.lsu.tld.tte1[37:35]; | |
| 2436 | ||
| 2437 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2438 | assign demap_active = |demap_1 && !skip_demap; | |
| 2439 | assign auto_demap = |demap_1 && skip_demap; | |
| 2440 | ||
| 2441 | //--------------------- | |
| 2442 | // Probes for debugging | |
| 2443 | ||
| 2444 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 2445 | ||
| 2446 | // n2_tlb_tl_128x59_cam.sv | |
| 2447 | ||
| 2448 | `define CNTX1_HI 65 | |
| 2449 | `define CNTX1_LO 53 | |
| 2450 | `define PID_HI 52 | |
| 2451 | `define PID_LO 50 | |
| 2452 | `define REAL_BIT 49 | |
| 2453 | `define VA_47 48 | |
| 2454 | `define VA_28 29 | |
| 2455 | `define VA_27 28 | |
| 2456 | `define VA_22 23 | |
| 2457 | `define TTE_VALID 22 | |
| 2458 | `define VA_21 21 | |
| 2459 | `define VA_16 16 | |
| 2460 | `define VA_15 15 | |
| 2461 | `define VA_13 13 | |
| 2462 | `define CNTX0_HI 12 | |
| 2463 | `define CNTX0_LO 0 | |
| 2464 | ||
| 2465 | // n2_tlb_tl_128x59_ram.sv | |
| 2466 | ||
| 2467 | `define DATA_PARITY 36 | |
| 2468 | `define DATA_PA_39_28_HI 35 | |
| 2469 | `define DATA_PA_39_28_LO 24 | |
| 2470 | `define DATA_PA_27_22_HI 23 | |
| 2471 | `define DATA_PA_27_22_LO 18 | |
| 2472 | `define DATA_VA_27_22_V 17 | |
| 2473 | `define DATA_PA_21_16_HI 16 | |
| 2474 | `define DATA_PA_21_16_LO 11 | |
| 2475 | `define DATA_VA_21_16_V 10 | |
| 2476 | `define DATA_PA_15_13_HI 9 | |
| 2477 | `define DATA_PA_15_13_LO 7 | |
| 2478 | `define DATA_VA_15_13_V 6 | |
| 2479 | `define DATA_NFO 5 | |
| 2480 | `define DATA_IE 4 | |
| 2481 | `define DATA_CP 3 | |
| 2482 | `define DATA_X 2 | |
| 2483 | `define DATA_P 1 | |
| 2484 | `define DATA_W 0 | |
| 2485 | ||
| 2486 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2487 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2488 | wire tte_valid; | |
| 2489 | wire [47:0] tte_va; | |
| 2490 | wire [12:0] tte_context; | |
| 2491 | wire tte_real; | |
| 2492 | wire [2:0] tte_pid; | |
| 2493 | wire [2:0] tte_page_mask; | |
| 2494 | wire [39:0] tte_pa; | |
| 2495 | wire tte_nfo; | |
| 2496 | wire tte_ie; | |
| 2497 | wire tte_cp; | |
| 2498 | wire tte_e; | |
| 2499 | wire tte_p; | |
| 2500 | wire tte_w; | |
| 2501 | wire tte_ep; | |
| 2502 | ||
| 2503 | ||
| 2504 | assign tlb_valid = `SPC6.lsu.tlb.array.cam.valid; | |
| 2505 | assign tlb_match = `SPC6.lsu.tlb.array.cam.match; | |
| 2506 | ||
| 2507 | assign tte_va = {`SPC6.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2508 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2509 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2510 | `SPC6.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2511 | 13'b0 | |
| 2512 | }; | |
| 2513 | assign tte_context = `SPC6.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2514 | assign tte_pid = `SPC6.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2515 | assign tte_real = `SPC6.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 2516 | assign tte_valid = `SPC6.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 2517 | ||
| 2518 | assign tte_page_mask = `SPC6.lsu.tlb.tte_page_size_mask_1; | |
| 2519 | ||
| 2520 | assign tte_pa = {`SPC6.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2521 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2522 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2523 | `SPC6.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2524 | 13'b0 | |
| 2525 | }; | |
| 2526 | assign tte_nfo = `SPC6.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 2527 | assign tte_ie = `SPC6.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 2528 | assign tte_cp = `SPC6.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 2529 | assign tte_e = `SPC6.lsu.tlb.tte_data_1[`DATA_X]; | |
| 2530 | assign tte_p = `SPC6.lsu.tlb.tte_data_1[`DATA_P]; | |
| 2531 | assign tte_w = `SPC6.lsu.tlb.tte_data_1[`DATA_W]; | |
| 2532 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 2533 | ||
| 2534 | assign ready = `PARGS.tlb_sync_on & !`SPC6.tcu_spc_mbist_start; | |
| 2535 | ||
| 2536 | //---------------------------------------------------------- | |
| 2537 | // Initialize state machine to idle state | |
| 2538 | initial begin // { | |
| 2539 | #1; | |
| 2540 | hwtw = 1'b0; | |
| 2541 | for (i=0; i<=7; i=i+1) begin | |
| 2542 | my_asi[i] = 8'b0; | |
| 2543 | end | |
| 2544 | @ (posedge `SPC6.l2clk); | |
| 2545 | ||
| 2546 | end // } | |
| 2547 | ||
| 2548 | //---------------------------------------------------------- | |
| 2549 | // Must use negedge to avoid race condition | |
| 2550 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 2551 | ||
| 2552 | always @ (negedge (`SPC6.l2clk & ready)) begin // { | |
| 2553 | ||
| 2554 | tstamp = `TOP.core_cycle_cnt; | |
| 2555 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2556 | ||
| 2557 | // Delay by 1 cycle to align with skip_demap | |
| 2558 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2559 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2560 | demap_1 <= demap; | |
| 2561 | ||
| 2562 | //---------------------------------------------------------- | |
| 2563 | // Send I/DTLBWRITE due to demap | |
| 2564 | // | |
| 2565 | ||
| 2566 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2567 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2568 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 2569 | mycid,demap_tid_1); | |
| 2570 | end // } | |
| 2571 | ||
| 2572 | if (demap_active) begin // { | |
| 2573 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2574 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2575 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2576 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2577 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2578 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 2579 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2580 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2581 | ||
| 2582 | // sstep_sent is asserted when data_in is asserted | |
| 2583 | // Check to see if sstep was sent early | |
| 2584 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2585 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2586 | end //} | |
| 2587 | ||
| 2588 | end //} | |
| 2589 | end //} | |
| 2590 | ||
| 2591 | //-------------------- | |
| 2592 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2593 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2594 | ||
| 2595 | if (demap_active) begin | |
| 2596 | case (demap_1) | |
| 2597 | 4'b0001: $write ("type=real "); | |
| 2598 | 4'b0010: $write ("type=cntx "); | |
| 2599 | 4'b0100: $write ("type=page "); | |
| 2600 | 4'b1000: $write ("type=all "); | |
| 2601 | default: | |
| 2602 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2603 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2604 | endcase | |
| 2605 | end | |
| 2606 | else begin | |
| 2607 | $write ("type=autodemap "); | |
| 2608 | end | |
| 2609 | ||
| 2610 | $display ("match=%h ts=%0d", | |
| 2611 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2612 | ||
| 2613 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2614 | if (tlb_match[cnt]==1'b1) begin // { | |
| 2615 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 2616 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 2617 | end // } | |
| 2618 | end // } | |
| 2619 | //-------------------- | |
| 2620 | end // } | |
| 2621 | ||
| 2622 | //---------------------------------------------------------- | |
| 2623 | // Send I/DHWTW due to HWTW | |
| 2624 | // Send I/DTLBWRITE due to ASI write | |
| 2625 | ||
| 2626 | // Save asi num when DTLBREAD happens. | |
| 2627 | // Otherwise, hold state. | |
| 2628 | // Send asi num later with DHWTW | |
| 2629 | for (i=0;i<=7;i=i+1) begin // { | |
| 2630 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 2631 | end // } | |
| 2632 | ||
| 2633 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 2634 | // These signals will be interleaved between the threads. | |
| 2635 | // Need to queue up the signals over time so they can be processed in order. | |
| 2636 | // Each thread will only be doing 1 thing at a time. | |
| 2637 | ||
| 2638 | for (i=0;i<=7;i=i+1) begin // { | |
| 2639 | ||
| 2640 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 2641 | ||
| 2642 | // data_in[tid] determines which thread will write next | |
| 2643 | // Use fifo to save the tids of the data_in signals in order | |
| 2644 | ||
| 2645 | if (data_in[i]) begin // { | |
| 2646 | if (tlb_wr[i]) begin // { | |
| 2647 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 2648 | end // } | |
| 2649 | else begin // { | |
| 2650 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 2651 | ||
| 2652 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 2653 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 2654 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 2655 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 2656 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 2657 | end // } | |
| 2658 | end // } | |
| 2659 | ||
| 2660 | end // } | |
| 2661 | ||
| 2662 | //---------------------------------------------------------- | |
| 2663 | // wr_en means that the write is occurring | |
| 2664 | if (wr_en) begin // { | |
| 2665 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2666 | mytnum = (mycid * 8) + mytid; | |
| 2667 | ||
| 2668 | if (hwtw) begin // { | |
| 2669 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2670 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 2671 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 2672 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 2673 | ||
| 2674 | end //} | |
| 2675 | end // } | |
| 2676 | else begin // { | |
| 2677 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2678 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 2679 | mycid,mytid,mytnum,tstamp,entry); | |
| 2680 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2681 | mycid,mytid,mytnum,tstamp); | |
| 2682 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 2683 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 2684 | ||
| 2685 | // Check to see if sstep was sent early | |
| 2686 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 2687 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2688 | end //} | |
| 2689 | ||
| 2690 | end //} | |
| 2691 | end // } | |
| 2692 | ||
| 2693 | //-------------------- | |
| 2694 | if (`PARGS.show_tlb_on) begin // { | |
| 2695 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2696 | ||
| 2697 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 2698 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 2699 | ||
| 2700 | case (tte_page_mask) | |
| 2701 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 2702 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2703 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 2704 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2705 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 2706 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2707 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 2708 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 2709 | endcase | |
| 2710 | ||
| 2711 | if (hwtw) $display (" (hwtw)"); | |
| 2712 | else $display (""); | |
| 2713 | ||
| 2714 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 2715 | ||
| 2716 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 2717 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 2718 | end // } | |
| 2719 | //-------------------- | |
| 2720 | ||
| 2721 | end // } | |
| 2722 | ||
| 2723 | end // always} | |
| 2724 | ||
| 2725 | //---------------------------------------------------------- | |
| 2726 | `endif | |
| 2727 | endmodule | |
| 2728 | ||
| 2729 | `endif | |
| 2730 | `ifdef CORE_7 | |
| 2731 | ||
| 2732 | module dtlb_wr_c7 (); | |
| 2733 | `ifndef GATESIM | |
| 2734 | ||
| 2735 | `include "tlb_sync.vh" | |
| 2736 | `include "nas.vh" | |
| 2737 | parameter NUM_TLB=128; | |
| 2738 | ||
| 2739 | wire [7:0] data_in; | |
| 2740 | wire [7:0] tlb_wr; | |
| 2741 | wire wr_en; | |
| 2742 | wire [7:0] entry; | |
| 2743 | wire [7:0] asi_num; | |
| 2744 | wire asi_enable0; // 1 per thread group | |
| 2745 | wire asi_enable1; | |
| 2746 | wire [7:0] store_asi; // 1 per thread | |
| 2747 | wire [3:0] demap; | |
| 2748 | reg [3:0] demap_1; | |
| 2749 | wire demap_page; | |
| 2750 | wire demap_context; | |
| 2751 | wire demap_real; | |
| 2752 | wire demap_all; | |
| 2753 | wire skip_demap; | |
| 2754 | wire demap_active; | |
| 2755 | wire auto_demap; | |
| 2756 | wire [2:0] demap_tid; | |
| 2757 | reg [2:0] demap_tid_1; | |
| 2758 | reg [5:0] demap_tnum_1; | |
| 2759 | ||
| 2760 | reg [(`TS_WIDTH-1):0] tstamp; | |
| 2761 | reg hwtw; | |
| 2762 | reg [7:0] my_asi [0:7]; // 1 asi number stored per thread | |
| 2763 | reg [(`TS_WIDTH-1):0] demap_tstamp; | |
| 2764 | ||
| 2765 | reg [2:0] mytid; | |
| 2766 | reg [5:0] mytnum; | |
| 2767 | wire [2:0] mycid; | |
| 2768 | integer junk; | |
| 2769 | integer i; | |
| 2770 | reg [7:0] cnt; | |
| 2771 | wire ready; | |
| 2772 | ||
| 2773 | assign mycid = 7; | |
| 2774 | ||
| 2775 | `ifdef DEBUG_TLB | |
| 2776 | wire [7:0] my_asi0 = my_asi[0]; | |
| 2777 | wire [7:0] my_asi1 = my_asi[1]; | |
| 2778 | wire [7:0] my_asi2 = my_asi[2]; | |
| 2779 | wire [7:0] my_asi3 = my_asi[3]; | |
| 2780 | wire [7:0] my_asi4 = my_asi[4]; | |
| 2781 | wire [7:0] my_asi5 = my_asi[5]; | |
| 2782 | wire [7:0] my_asi6 = my_asi[6]; | |
| 2783 | wire [7:0] my_asi7 = my_asi[7]; | |
| 2784 | `endif | |
| 2785 | ||
| 2786 | //---------------------------------------------------------- | |
| 2787 | // Instantiate fifo - 1 entry per thread | |
| 2788 | fifo fifo (); | |
| 2789 | // Define fifo parameters | |
| 2790 | defparam fifo.ENTRY_BITS = 4; // {hwtw,tid[2:0]} | |
| 2791 | defparam fifo.DEPTH = 9; // 1 extra entry for overflow detection | |
| 2792 | defparam fifo.PTR_BITS = 4; | |
| 2793 | ||
| 2794 | //---------------------------------------------------------- | |
| 2795 | // DUT probes | |
| 2796 | ||
| 2797 | assign data_in = `SPC7.mmu.asi.wrote_dtlb; | |
| 2798 | assign tlb_wr = `SPC7.mmu_reload_done; | |
| 2799 | assign wr_en = `SPC7.lsu.tlb.tlb_wr_1_in_dout; | |
| 2800 | ||
| 2801 | assign entry = `SPC7.lsu.tlb.rw_index_1[6:0]; | |
| 2802 | ||
| 2803 | assign asi_num = `PROBES7.asi_num; | |
| 2804 | assign asi_enable0 = `PROBES7.tlb_rd_vld_b & | |
| 2805 | !`PROBES7.tlb_bypass_b & | |
| 2806 | `SPC7.tlu.fls0.lsu_inst_b; | |
| 2807 | assign asi_enable1 = `PROBES7.tlb_rd_vld_b & | |
| 2808 | !`PROBES7.tlb_bypass_b & | |
| 2809 | `SPC7.tlu.fls1.lsu_inst_b; | |
| 2810 | ||
| 2811 | assign store_asi[3:0] = asi_enable0 ? `PROBES7.select_pc_b[3:0] : 4'b0; | |
| 2812 | assign store_asi[7:4] = asi_enable1 ? `PROBES7.select_pc_b[7:4] : 4'b0; | |
| 2813 | ||
| 2814 | assign demap_page = `SPC7.lsu.tlc_demap & ~(demap_context | demap_real | demap_all); | |
| 2815 | assign demap_context = `SPC7.lsu.tlc_demap_context; | |
| 2816 | assign demap_real = `SPC7.lsu.tlc_demap_real; | |
| 2817 | assign demap_all = `SPC7.lsu.tlc_demap_all; | |
| 2818 | assign demap = {demap_all,demap_page,demap_context,demap_real}; | |
| 2819 | assign skip_demap =`SPC7.lsu.tlc_wr_u_en; | |
| 2820 | assign demap_tid = `SPC7.lsu.tld.tte1[37:35]; | |
| 2821 | ||
| 2822 | // if (|demap_1 && skip_demap ), then Implicit demap so don't send to NAS | |
| 2823 | assign demap_active = |demap_1 && !skip_demap; | |
| 2824 | assign auto_demap = |demap_1 && skip_demap; | |
| 2825 | ||
| 2826 | //--------------------- | |
| 2827 | // Probes for debugging | |
| 2828 | ||
| 2829 | // defines copied from :/libs/n2sram/tlbs/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl | |
| 2830 | ||
| 2831 | // n2_tlb_tl_128x59_cam.sv | |
| 2832 | ||
| 2833 | `define CNTX1_HI 65 | |
| 2834 | `define CNTX1_LO 53 | |
| 2835 | `define PID_HI 52 | |
| 2836 | `define PID_LO 50 | |
| 2837 | `define REAL_BIT 49 | |
| 2838 | `define VA_47 48 | |
| 2839 | `define VA_28 29 | |
| 2840 | `define VA_27 28 | |
| 2841 | `define VA_22 23 | |
| 2842 | `define TTE_VALID 22 | |
| 2843 | `define VA_21 21 | |
| 2844 | `define VA_16 16 | |
| 2845 | `define VA_15 15 | |
| 2846 | `define VA_13 13 | |
| 2847 | `define CNTX0_HI 12 | |
| 2848 | `define CNTX0_LO 0 | |
| 2849 | ||
| 2850 | // n2_tlb_tl_128x59_ram.sv | |
| 2851 | ||
| 2852 | `define DATA_PARITY 36 | |
| 2853 | `define DATA_PA_39_28_HI 35 | |
| 2854 | `define DATA_PA_39_28_LO 24 | |
| 2855 | `define DATA_PA_27_22_HI 23 | |
| 2856 | `define DATA_PA_27_22_LO 18 | |
| 2857 | `define DATA_VA_27_22_V 17 | |
| 2858 | `define DATA_PA_21_16_HI 16 | |
| 2859 | `define DATA_PA_21_16_LO 11 | |
| 2860 | `define DATA_VA_21_16_V 10 | |
| 2861 | `define DATA_PA_15_13_HI 9 | |
| 2862 | `define DATA_PA_15_13_LO 7 | |
| 2863 | `define DATA_VA_15_13_V 6 | |
| 2864 | `define DATA_NFO 5 | |
| 2865 | `define DATA_IE 4 | |
| 2866 | `define DATA_CP 3 | |
| 2867 | `define DATA_X 2 | |
| 2868 | `define DATA_P 1 | |
| 2869 | `define DATA_W 0 | |
| 2870 | ||
| 2871 | wire [(NUM_TLB-1):0] tlb_valid; | |
| 2872 | wire [(NUM_TLB-1):0] tlb_match; | |
| 2873 | wire tte_valid; | |
| 2874 | wire [47:0] tte_va; | |
| 2875 | wire [12:0] tte_context; | |
| 2876 | wire tte_real; | |
| 2877 | wire [2:0] tte_pid; | |
| 2878 | wire [2:0] tte_page_mask; | |
| 2879 | wire [39:0] tte_pa; | |
| 2880 | wire tte_nfo; | |
| 2881 | wire tte_ie; | |
| 2882 | wire tte_cp; | |
| 2883 | wire tte_e; | |
| 2884 | wire tte_p; | |
| 2885 | wire tte_w; | |
| 2886 | wire tte_ep; | |
| 2887 | ||
| 2888 | ||
| 2889 | assign tlb_valid = `SPC7.lsu.tlb.array.cam.valid; | |
| 2890 | assign tlb_match = `SPC7.lsu.tlb.array.cam.match; | |
| 2891 | ||
| 2892 | assign tte_va = {`SPC7.lsu.tlb.tte_tag_1_dout[`VA_47:`VA_28], | |
| 2893 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_27:`VA_22], | |
| 2894 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_21:`VA_16], | |
| 2895 | `SPC7.lsu.tlb.tte_tag_1_dout[`VA_15:`VA_13], | |
| 2896 | 13'b0 | |
| 2897 | }; | |
| 2898 | assign tte_context = `SPC7.lsu.tlb.tte_tag_1_dout[`CNTX1_HI:`CNTX1_LO]; | |
| 2899 | assign tte_pid = `SPC7.lsu.tlb.tte_tag_1_dout[`PID_HI:`PID_LO]; | |
| 2900 | assign tte_real = `SPC7.lsu.tlb.tte_tag_1_dout[`REAL_BIT]; | |
| 2901 | assign tte_valid = `SPC7.lsu.tlb.tte_tag_1_dout[`TTE_VALID]; | |
| 2902 | ||
| 2903 | assign tte_page_mask = `SPC7.lsu.tlb.tte_page_size_mask_1; | |
| 2904 | ||
| 2905 | assign tte_pa = {`SPC7.lsu.tlb.tte_data_1[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], | |
| 2906 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], | |
| 2907 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], | |
| 2908 | `SPC7.lsu.tlb.tte_data_1[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO], | |
| 2909 | 13'b0 | |
| 2910 | }; | |
| 2911 | assign tte_nfo = `SPC7.lsu.tlb.tte_data_1[`DATA_NFO]; | |
| 2912 | assign tte_ie = `SPC7.lsu.tlb.tte_data_1[`DATA_IE]; | |
| 2913 | assign tte_cp = `SPC7.lsu.tlb.tte_data_1[`DATA_CP]; | |
| 2914 | assign tte_e = `SPC7.lsu.tlb.tte_data_1[`DATA_X]; | |
| 2915 | assign tte_p = `SPC7.lsu.tlb.tte_data_1[`DATA_P]; | |
| 2916 | assign tte_w = `SPC7.lsu.tlb.tte_data_1[`DATA_W]; | |
| 2917 | assign tte_ep = 1'bx; // Does not apply for DTLB | |
| 2918 | ||
| 2919 | assign ready = `PARGS.tlb_sync_on & !`SPC7.tcu_spc_mbist_start; | |
| 2920 | ||
| 2921 | //---------------------------------------------------------- | |
| 2922 | // Initialize state machine to idle state | |
| 2923 | initial begin // { | |
| 2924 | #1; | |
| 2925 | hwtw = 1'b0; | |
| 2926 | for (i=0; i<=7; i=i+1) begin | |
| 2927 | my_asi[i] = 8'b0; | |
| 2928 | end | |
| 2929 | @ (posedge `SPC7.l2clk); | |
| 2930 | ||
| 2931 | end // } | |
| 2932 | ||
| 2933 | //---------------------------------------------------------- | |
| 2934 | // Must use negedge to avoid race condition | |
| 2935 | // tlb_entry_replace (aka entry) is created in always block using blocking assignments | |
| 2936 | ||
| 2937 | always @ (negedge (`SPC7.l2clk & ready)) begin // { | |
| 2938 | ||
| 2939 | tstamp = `TOP.core_cycle_cnt; | |
| 2940 | demap_tstamp = `TOP.core_cycle_cnt; | |
| 2941 | ||
| 2942 | // Delay by 1 cycle to align with skip_demap | |
| 2943 | demap_tid_1 <= demap_tid; // demap_tid is active when demap is asserted | |
| 2944 | demap_tnum_1 <= (mycid * 8) + demap_tid; | |
| 2945 | demap_1 <= demap; | |
| 2946 | ||
| 2947 | //---------------------------------------------------------- | |
| 2948 | // Send I/DTLBWRITE due to demap | |
| 2949 | // | |
| 2950 | ||
| 2951 | if ((demap!=0) && (demap_1!=0)) begin // { | |
| 2952 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2953 | "C%0d T%0d Illegal Back to Back DTLB demap", | |
| 2954 | mycid,demap_tid_1); | |
| 2955 | end // } | |
| 2956 | ||
| 2957 | if (demap_active) begin // { | |
| 2958 | fifo.pop_fifo ({hwtw,mytid}); | |
| 2959 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 2960 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h (demap)", | |
| 2961 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp,8'hff); | |
| 2962 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 2963 | mycid,demap_tid_1,demap_tnum_1,demap_tstamp); | |
| 2964 | junk = $sim_send(`PLI_DTLBWRITE, demap_tnum_1,demap_tstamp,8'hff); | |
| 2965 | junk = $sim_send(`PLI_SSTEP, demap_tnum_1); | |
| 2966 | ||
| 2967 | // sstep_sent is asserted when data_in is asserted | |
| 2968 | // Check to see if sstep was sent early | |
| 2969 | if (`NASTOP.sstep_sent[demap_tnum_1]==1) begin // { | |
| 2970 | `NASTOP.sstep_early[demap_tnum_1] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 2971 | end //} | |
| 2972 | ||
| 2973 | end //} | |
| 2974 | end //} | |
| 2975 | ||
| 2976 | //-------------------- | |
| 2977 | if (`PARGS.show_tlb_on & (|demap_1)) begin // { | |
| 2978 | $write ("SHOW_TLB: DTLB_DEMAP C%0d T%0d ",mycid,demap_tid_1); | |
| 2979 | ||
| 2980 | if (demap_active) begin | |
| 2981 | case (demap_1) | |
| 2982 | 4'b0001: $write ("type=real "); | |
| 2983 | 4'b0010: $write ("type=cntx "); | |
| 2984 | 4'b0100: $write ("type=page "); | |
| 2985 | 4'b1000: $write ("type=all "); | |
| 2986 | default: | |
| 2987 | `PR_ERROR ("tlb_sync", `ERROR, | |
| 2988 | "Bench Problem - demap_1(%b) should be one-hot.",demap_1); | |
| 2989 | endcase | |
| 2990 | end | |
| 2991 | else begin | |
| 2992 | $write ("type=autodemap "); | |
| 2993 | end | |
| 2994 | ||
| 2995 | $display ("match=%h ts=%0d", | |
| 2996 | tlb_match,demap_tstamp*`TOP.core_period); | |
| 2997 | ||
| 2998 | for (cnt=0; cnt<=NUM_TLB; cnt=cnt+1) begin // { | |
| 2999 | if (tlb_match[cnt]==1'b1) begin // { | |
| 3000 | $display ("SHOW_TLB: DTLB_DEMAP C%0d T%0d entry=%h V=0 ts=%0d", | |
| 3001 | mycid,demap_tid_1,cnt,demap_tstamp*`TOP.core_period); | |
| 3002 | end // } | |
| 3003 | end // } | |
| 3004 | //-------------------- | |
| 3005 | end // } | |
| 3006 | ||
| 3007 | //---------------------------------------------------------- | |
| 3008 | // Send I/DHWTW due to HWTW | |
| 3009 | // Send I/DTLBWRITE due to ASI write | |
| 3010 | ||
| 3011 | // Save asi num when DTLBREAD happens. | |
| 3012 | // Otherwise, hold state. | |
| 3013 | // Send asi num later with DHWTW | |
| 3014 | for (i=0;i<=7;i=i+1) begin // { | |
| 3015 | my_asi[i] = (store_asi[i]) ? asi_num : my_asi[i]; | |
| 3016 | end // } | |
| 3017 | ||
| 3018 | // There are 3 main signals to watch for TLBWRITE (data_in, tlb_wr, wr_en) | |
| 3019 | // These signals will be interleaved between the threads. | |
| 3020 | // Need to queue up the signals over time so they can be processed in order. | |
| 3021 | // Each thread will only be doing 1 thing at a time. | |
| 3022 | ||
| 3023 | for (i=0;i<=7;i=i+1) begin // { | |
| 3024 | ||
| 3025 | // tlb_wr[tid] determines if the write is HWTW or TLBWRITE | |
| 3026 | ||
| 3027 | // data_in[tid] determines which thread will write next | |
| 3028 | // Use fifo to save the tids of the data_in signals in order | |
| 3029 | ||
| 3030 | if (data_in[i]) begin // { | |
| 3031 | if (tlb_wr[i]) begin // { | |
| 3032 | fifo.push_fifo ({1'b1,i[2:0]}); // {hwtw,tid[2:0]} | |
| 3033 | end // } | |
| 3034 | else begin // { | |
| 3035 | fifo.push_fifo ({1'b0,i[2:0]}); // {!hwtw,tid[2:0]} | |
| 3036 | ||
| 3037 | // Signal to nas_pipe to suppress SSTEP as soon we know a tlb write or demap is coming (data_in=1) | |
| 3038 | // Cannot wait for wr_en because it is possible to miss an SSTEP. | |
| 3039 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: suppress sstep. sstep_sent=1)", | |
| 3040 | mycid,i,((mycid * 6'h8) + i[2:0]),tstamp); | |
| 3041 | `NASTOP.sstep_sent[(mycid * 6'h8) + i[2:0]] <= 1'b1; // suppress SSTEP | |
| 3042 | end // } | |
| 3043 | end // } | |
| 3044 | ||
| 3045 | end // } | |
| 3046 | ||
| 3047 | //---------------------------------------------------------- | |
| 3048 | // wr_en means that the write is occurring | |
| 3049 | if (wr_en) begin // { | |
| 3050 | fifo.pop_fifo ({hwtw,mytid}); | |
| 3051 | mytnum = (mycid * 8) + mytid; | |
| 3052 | ||
| 3053 | if (hwtw) begin // { | |
| 3054 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 3055 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DHWTW tid=%d ts=%0d va=%h asi=%h entry=%h", | |
| 3056 | mycid,mytid,mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 3057 | junk = $sim_send(`PLI_DHWTW, mytnum,tstamp,tte_va,my_asi[mytid],entry); | |
| 3058 | ||
| 3059 | end //} | |
| 3060 | end // } | |
| 3061 | else begin // { | |
| 3062 | if (`PARGS.nas_check_on && `PARGS.tlb_sync_on) begin // { | |
| 3063 | `PR_INFO ("pli_tlb", `INFO, " C%0d T%0d PLI_DTLBWRITE tid=%d ts=%0d entry=%h", | |
| 3064 | mycid,mytid,mytnum,tstamp,entry); | |
| 3065 | `PR_INFO ("pli_nas", `INFO, " C%0d T%0d PLI_SSTEP tid=%d ts=%0d (tlb_sync: send SSTEP)", | |
| 3066 | mycid,mytid,mytnum,tstamp); | |
| 3067 | junk = $sim_send(`PLI_DTLBWRITE, mytnum,tstamp,entry); | |
| 3068 | junk = $sim_send(`PLI_SSTEP, mytnum); | |
| 3069 | ||
| 3070 | // Check to see if sstep was sent early | |
| 3071 | if (`NASTOP.sstep_sent[mytnum]==1) begin // { | |
| 3072 | `NASTOP.sstep_early[mytnum] <= 1'b1; // SSTEP was sent before nas_pipe capture | |
| 3073 | end //} | |
| 3074 | ||
| 3075 | end //} | |
| 3076 | end // } | |
| 3077 | ||
| 3078 | //-------------------- | |
| 3079 | if (`PARGS.show_tlb_on) begin // { | |
| 3080 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 3081 | ||
| 3082 | if (tte_real==0) $write ("entry=%h V=%b VA=%h ",entry,tte_valid,tte_va); | |
| 3083 | else $write ("entry=%h V=%b RA=%h ",entry,tte_valid,tte_va); | |
| 3084 | ||
| 3085 | case (tte_page_mask) | |
| 3086 | 3'b000: $write("R=%b CNTX=%h PID=%h sz=8k ts=%0d", | |
| 3087 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3088 | 3'b001: $write("R=%b CNTX=%h PID=%h sz=64k ts=%0d", | |
| 3089 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3090 | 3'b011: $write("R=%b CNTX=%h PID=%h sz=4MB ts=%0d", | |
| 3091 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3092 | 3'b111: $write("R=%b CNTX=%h PID=%h sz=256MB ts=%0d", | |
| 3093 | tte_real,tte_context,tte_pid,tstamp*`TOP.core_period); | |
| 3094 | endcase | |
| 3095 | ||
| 3096 | if (hwtw) $display (" (hwtw)"); | |
| 3097 | else $display (""); | |
| 3098 | ||
| 3099 | $write ("SHOW_TLB: DTLB_WRITE C%0d T%0d ",mycid,mytid); | |
| 3100 | ||
| 3101 | $display (" PA=00%h P=%b IE=%b CP=%b NFO=%b E=%b EP=X W=%b ts=%0d", | |
| 3102 | tte_pa,tte_p,tte_ie,tte_cp,tte_nfo,tte_e,tte_w,tstamp*`TOP.core_period); | |
| 3103 | end // } | |
| 3104 | //-------------------- | |
| 3105 | ||
| 3106 | end // } | |
| 3107 | ||
| 3108 | end // always} | |
| 3109 | ||
| 3110 | //---------------------------------------------------------- | |
| 3111 | `endif | |
| 3112 | endmodule | |
| 3113 | ||
| 3114 | `endif | |
| 3115 | ||
| 3116 | //---------------------------------------------------------- | |
| 3117 | //---------------------------------------------------------- |