Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / config / dram.config

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dram.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
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// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
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// ========== Copyright Header End ============================================
<dram>
   -vera_vcon_file=dram_top.vcon
   -flist=$DV_ROOT/design/sys/iop/include/Flist.iop_include
   -flist=$DV_ROOT/design/sys/iop/rtl/Flist.iop_top
   -flist=$DV_ROOT/design/sys/iop/dram/rtl/Flist.dram
   -flist=$DV_ROOT/design/sys/iop/pads/pad_common/rtl/Flist.impctl_common
   -flist=$DV_ROOT/design/sys/iop/pads/pad_common/rtl/Flist.sstl_bscan_common
   -flist=$DV_ROOT/design/sys/iop/pads/pad_common/rtl/Flist.pscan_common
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr_common/rtl/Flist.ddr_impctl_common
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr_common/rtl/Flist.pad_ddr_common
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr0/rtl/Flist.pad_ddr0
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr1/rtl/Flist.pad_ddr1
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr2/rtl/Flist.pad_ddr2
   -flist=$DV_ROOT/design/sys/iop/pads/pad_ddr3/rtl/Flist.pad_ddr3
   -flist=$DV_ROOT/design/sys/iop/common/rtl/Flist.ucb_common
   -flist=$DV_ROOT/design/sys/iop/common/rtl/Flist.clib_common
   -flist=$DV_ROOT/design/sys/iop/common/rtl/Flist.dft_common
   -flist=$DV_ROOT/design/sys/iop/analog/bw_iodll/rtl/Flist.dll_common
   -flist=$DV_ROOT/design/sys/iop/analog/bw_clk/rtl/Flist.bw_clk
   -flist=$DV_ROOT/design/sys/iop/srams/rtl/Flist.srams
   -flist=$DV_ROOT/verif/env/cmp/dram.flist
   -config_rtl=RTL_CMP
   -config_rtl=RTL_FLOP_RPTRS
   -config_rtl=RTL_DRAM02
   -config_rtl=RTL_DRAM13
   -config_rtl=RTL_PAD_DDR0
   -config_rtl=RTL_PAD_DDR1
   -config_rtl=RTL_PAD_DDR2
   -config_rtl=RTL_PAD_DDR3
   -env_base=$DV_ROOT/verif/env/cmp
   -model=dram
   -vera_build_args="VFLAGS=-DDRAM"
   -vera_build_args=PAL_OPTS="sys=DRAM"
   -vcs_build_args=+define+BWSIM_SAME_GCLK_RCLK+
   -vcs_build_args=+define+DRAM_SAT+
   -vcs_build_args=+define+MODEL_DRAM+
//   -vcs_build_args="-P /import/datools/vendor/denali/3.100-0008/verilog/pli.tab"
//   -vcs_build_args=/import/datools/vendor/denali/3.100-0008/verilog/denverlib.o
   -vcs_build_args="-P $DV_ROOT/tools/pli/socket/bwsocket_pli.tab"
   -vcs_build_args=$DV_ROOT/tools/pli/utility/libdummy.a
   -vcs_build_args=$DV_ROOT/tools/pli/socket/libbwsocket_pli.a
   -vcs_build_args="-P $DV_ROOT/tools/pli/mem/bwmem_pli.tab"
   -vcs_build_args=$DV_ROOT/tools/pli/mem/libbwmem_pli.a
   -vcs_build_args="-P $DV_ROOT/tools/pli/utility/bwutility_pli.tab"
   -vcs_build_args=$DV_ROOT/tools/pli/utility/libbwutility_pli.a
   -vcs_build_args=-M
   -vcs_build_args=-Mupdate
   -vcs_build_args=-vera
   -drm_disk=[/export/home/bw=30]
   -drm_type=vcs
   -drm_freeprocessor=1
   -vcs_run_args=+DRAM
   -vcs_run_args=+vera_exit_on_error
   -vcs_run_args=+no_slam_init
   -post_process_cmd="regreport -1 > status.log"
   -post_process_cmd="perf > perf.log"
   -asm_diag_root=$DV_ROOT/verif
   -tpt_diag_root=$DV_ROOT/verif
   -spis_diag_root=$DV_ROOT/verif
   -vera_diag_root=$DV_ROOT/verif
   -vera_config_root=$DV_ROOT/verif
   -image_diag_root=$DV_ROOT/verif
   -drm_freeswap=1000
   -drm_freeram=1000
</dram>