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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / config / fc.config
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc.config
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "defaults.config"
36
37// Define a text macro that is specific to the tapeout.
38// Note: This should probably go inside defaults.config
39#include "tapeout_defines.config"
40
41
42// Map the text macro from tapeout_defines.config
43// to a macro that is already used in this config file
44#ifdef ONLY_FOR_TO_1_0
45#define TO_1_0_VECTORS
46#endif
47
48// To provide support for users still using the earlier run_scripts
49#ifdef DTM15_SLAM_TO_1_0
50#define DTM15_SLAM
51#endif // DTM15_SLAM_TO_1_0
52
53#ifdef DTM15_SLAM_DP1_DUMP
54#define DTM15_SLAM_DUMP
55#define DTM15_SLAM_DP1
56#define DTM15_SLAM
57#endif // DTM15_SLAM_DP1_DUMP
58
59#ifdef DTM15_NONSLAM_DP1_DUMP
60#define DTM15_NONSLAM_DUMP
61#define DTM15_NONSLAM_DP1
62#define DTM15_NONSLAM
63#endif // DTM15_NONSLAM_DP1_DUMP
64
65#ifdef DTM15_SLAM_DP2_DUMP
66#define DTM15_SLAM_DUMP
67#define DTM15_SLAM_DP2
68#define DTM15_SLAM
69#endif // DTM15_SLAM_DP2_DUMP
70
71#ifdef DTM15_NONSLAM_DP2_DUMP
72#define DTM15_NONSLAM_DUMP
73#define DTM15_NONSLAM_DP2
74#define DTM15_NONSLAM
75#endif // DTM15_NONSLAM_DP2_DUMP
76
77// Do some global things for test vectors; see also fc_common.config
78#ifdef DTM15_SLAM
79#endif // DTM15_SLAM
80
81#ifdef DTM15_NONSLAM
82#define USE_TAP_DRIVER
83#endif // DTM15_NONSLAM
84
85// added this so all config cpp args for T2 will go here
86// note: only config cpp args go here
87// the rest of the args will have to be declared further down below,
88// in <fc1>,<fc2>,<fc4>,<fc8>
89
90
91#define T2 T2
92// here are the config cpp declarations (3 of them specified for now)
93#ifdef PEU_SYSC_NIU_SYSC
94#define PEU_SYSTEMC_T2 PEU_SYSTEMC_T2
95#define NIU_SYSTEMC_T2 NIU_SYSTEMC_T2
96#else
97#ifdef PEU_SYSC_NIU_RTL
98#define PEU_SYSTEMC_T2 PEU_SYSTEMC_T2
99#undef NIU_SYSTEMC_T2
100#else
101// #define FC_NO_PEU_VERA
102#undef PEU_SYSTEMC_T2
103#undef NIU_SYSTEMC_T2
104#define FC_NO_PEU_VERA FC_NO_PEU_VERA
105#define FC_NO_PEU_T2 FC_NO_PEU_T2
106#define FC_NO_NIU_T2 FC_NO_NIU_T2
107#undef NIU_SYSTEMC_T2
108#endif
109#endif
110#ifndef PEU_SYSTEMC_T2
111#undef FC_NO_PEU_VERA
112#define FC_NO_PEU_VERA
113#undef FC_NO_PEU_T2
114#define FC_NO_PEU_T2
115// if PEU SYSTEMC model is not included, do not include NIU
116#undef FC_NO_NIU_T2
117#define FC_NO_NIU_T2
118#undef NIU_SYSTEMC_T2
119#endif //PEU_SYSTEMC_T2
120
121// Because we pass FC_NO_PEU_VERA to other modules,
122// we need to define it as itself, else cpp will mess it up.
123#ifdef FC_NO_PEU_VERA
124#undef FC_NO_PEU_VERA
125#define FC_NO_PEU_VERA FC_NO_PEU_VERA
126#endif // FC_NO_PEU_VERA
127
128// added this to exclude PEU in T2
129#ifdef FC_NO_PEU_T2
130#undef FC_NO_PEU_T2
131#define FC_NO_PEU_T2 FC_NO_PEU_T2
132#endif // FC_NO_PEU_T2
133
134// added this to exclude NIU in T2
135#ifdef FC_NO_NIU_T2
136#undef FC_NO_NIU_T2
137#define FC_NO_NIU_T2 FC_NO_NIU_T2
138#endif // FC_NO_NIU_T2
139
140// added this to include NIU SYSTEMC model in T2
141#ifdef NIU_SYSTEMC_T2
142#undef NIU_SYSTEMC_T2
143#define NIU_SYSTEMC_T2 NIU_SYSTEMC_T2
144#endif // NIU_SYSTEMC_T2
145
146
147#ifdef LINUX
148#undef LINUX
149#define LINUX LINUX
150#endif // LINUX
151
152#ifdef USE_TAP_DRIVER
153#undef USE_TAP_DRIVER
154#define USE_TAP_DRIVER USE_TAP_DRIVER
155#endif // USE_TAP_DRIVER
156
157#ifdef DRAMX8
158#undef DRAMX8
159#define DRAMX8 DRAMX8
160#endif
161
162#ifdef TO_1_0_VECTORS
163#undef TO_1_0_VECTORS
164#define TO_1_0_VECTORS TO_1_0_VECTORS
165#endif
166
167
168#ifdef FASTER_AXIS
169#define AXIS_NO_FSR
170#endif
171
172//////////////////////////////////////////////////////////////////////////////
173<fc1>
174// for gatesim
175#ifdef GATESIM_CLUSTER
176 -sunv_run
177 -nozeroIn_build
178#include "fc_gate_cluster.config"
179#endif
180#ifdef GATESIM_CLUSTER_IO
181 -sunv_run
182 -nozeroIn_build
183#include "fc_gate_cluster.config"
184#include "fc_gate_io.config"
185#endif
186#ifdef GATESIM_ALL
187 -nosunv_run
188 -nozeroIn_build
189#include "fc_gate_all.config"
190#endif
191
192#ifdef AXIS_DAILY
193#define AXIS_TL
194#define AXIS_BUILD
195#define FC_NO_PEU_VERA FC_NO_PEU_VERA
196 -vcs_run_args=-s
197 -axis_run_args="-user_run_template $DV_ROOT/verif/env/mcu/cmd_tl.i "
198#endif
199#ifdef AXIS_TL
200 -vcs_build_args=+incdir+$DV_ROOT/design/niu/niu_mac_l/hedwig_lite
201#else
202#ifndef GATESIM
203 -flist=$DV_ROOT/verif/env/common/verilog/debug/debug.flist
204#endif
205#endif
206#include "fc_common.config"
207 -model=fc1
208 -config_rtl=FC1_BENCH
209 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
210 -vera_diag_args="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
211 -config_rtl=CORE_0
212 -config_rtl=RTL_NO_SPC1
213 -config_rtl=RTL_NO_SPC2
214 -config_rtl=RTL_NO_SPC3
215 -config_rtl=RTL_NO_SPC4
216 -config_rtl=RTL_NO_SPC5
217 -config_rtl=RTL_NO_SPC6
218 -config_rtl=RTL_NO_SPC7
219 -sas_run_args=-DSP0
220 -sunv_args=-define=RTL_NO_SPC1
221 -sunv_args=-define=RTL_NO_SPC2
222 -sunv_args=-define=RTL_NO_SPC3
223 -sunv_args=-define=RTL_NO_SPC4
224 -sunv_args=-define=RTL_NO_SPC5
225 -sunv_args=-define=RTL_NO_SPC6
226 -sunv_args=-define=RTL_NO_SPC7
227 -vcs_run_args=+ASI_CORE_AVILABLE=ff
228 -vcs_run_args=+ASI_CORE_ENABLE=ff
229 -diaglist_cpp_args=-DALL_THREADS=ff
230#ifdef GATESIM
231 -max_cycle=3000000
232#else
233 -max_cycle=2000000
234#endif
235 -midas_args=-DALL_THREADS=0xff
236 -midas_args=-DMAX_THREADS=8
237 -rtl_timeout=25000
238 -efuse_image_name=efa.dat
239 -efuse_image_root=$SIMS_LAUNCH_DIR
240 -pre_process_cmd="$DV_ROOT/tools/bin/efa_gen $SIMS_LAUNCH_DIR $DV_ROOT -fc1"
241 -post_process_cmd="mv $SIMS_LAUNCH_DIR/efa.dat $SIMS_LAUNCH_DIR/efa_used"
242</fc1>
243
244//////////////////////////////////////////////////////////////////////////////
245
246<fc8>
247// for gatesim
248#ifdef GATESIM_CLUSTER
249 -sunv_run
250 -nozeroIn_build
251#include "fc_gate_cluster.config"
252#endif
253#ifdef GATESIM_CLUSTER_IO
254 -sunv_run
255 -nozeroIn_build
256#include "fc_gate_cluster.config"
257#include "fc_gate_io.config"
258#endif
259#ifdef GATESIM_ALL
260 -nosunv_run
261 -nozeroIn_build
262#include "fc_gate_all.config"
263#endif
264
265#ifdef AXIS_DAILY
266#define AXIS_TL
267#define AXIS_BUILD
268#define AXIS_64BIT
269#define AXIS_NO_IP
270#define FC_NO_PEU_VERA FC_NO_PEU_VERA
271 //-vcs_run_args=-s
272 //-axis_run_args="-user_run_template $DV_ROOT/verif/env/mcu/cmd_tl.i "
273#endif
274#ifdef AXIS_TL
275 -vcs_build_args=+incdir+$DV_ROOT/design/niu/niu_mac_l/hedwig_lite
276#else
277#ifndef GATESIM
278 -flist=$DV_ROOT/verif/env/common/verilog/debug/debug_8core.flist
279#endif
280#endif
281#include "fc_common.config"
282 -model=fc8
283 -config_rtl=FC8_BENCH
284 -config_rtl=CORE_0
285 -config_rtl=CORE_1
286 -config_rtl=CORE_2
287 -config_rtl=CORE_3
288 -config_rtl=CORE_4
289 -config_rtl=CORE_5
290 -config_rtl=CORE_6
291 -config_rtl=CORE_7
292 -sas_run_args=-DSP0
293 -sas_run_args=-DSP1
294 -sas_run_args=-DSP2
295 -sas_run_args=-DSP3
296 -sas_run_args=-DSP4
297 -sas_run_args=-DSP5
298 -sas_run_args=-DSP6
299 -sas_run_args=-DSP7
300 -vcs_run_args=+ASI_CORE_AVILABLE=ffffffffffffffff
301 -vcs_run_args=+ASI_CORE_ENABLE=ffffffffffffffff
302 -diaglist_cpp_args=-DALL_THREADS=ffffffffffffffff
303 -max_cycle=4000000
304 -midas_args=-DALL_THREADS=0xffffffffffffffff
305 -midas_args=-DMAX_THREADS=64
306 -rtl_timeout=40000
307 -efuse_image_name=efa.dat
308 -efuse_image_root=$SIMS_LAUNCH_DIR
309 -pre_process_cmd="$DV_ROOT/tools/bin/efa_gen $SIMS_LAUNCH_DIR $DV_ROOT -fc8"
310 -post_process_cmd="mv $SIMS_LAUNCH_DIR/efa.dat $SIMS_LAUNCH_DIR/efa_used"
311// -vcs_build_args=+define+FBDIMM_NUM_8+
312// -vcs_run_args=+8_FBDIMMS
313</fc8>
314
315//////////////////////////////////////////////////////////////////////////////
316
317<fc4>
318#include "fc_common.config"
319 -model=fc4
320 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
321 -vera_diag_args="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
322 -config_rtl=CORE_0
323 -config_rtl=CORE_1
324 -config_rtl=CORE_2
325 -config_rtl=CORE_3
326 -config_rtl=RTL_NO_SPC4
327 -config_rtl=RTL_NO_SPC5
328 -config_rtl=RTL_NO_SPC6
329 -config_rtl=RTL_NO_SPC7
330 -sas_run_args=-DSP0
331 -sas_run_args=-DSP1
332 -sas_run_args=-DSP2
333 -sas_run_args=-DSP3
334 -sunv_args=-define=RTL_NO_SPC4
335 -sunv_args=-define=RTL_NO_SPC5
336 -sunv_args=-define=RTL_NO_SPC6
337 -sunv_args=-define=RTL_NO_SPC7
338 -vcs_run_args=+ASI_CORE_AVILABLE=ffffffff
339 -vcs_run_args=+ASI_CORE_ENABLE=ffffffff
340 -diaglist_cpp_args=-DALL_THREADS=ffffffff
341 -max_cycle=3000000
342 -rtl_timeout=30000
343 -midas_args=-DALL_THREADS=0xffffffff
344 -midas_args=-DMAX_THREADS=32
345 -efuse_image_name=efa.dat
346 -efuse_image_root=$SIMS_LAUNCH_DIR
347 -pre_process_cmd="$DV_ROOT/tools/bin/efa_gen $SIMS_LAUNCH_DIR $DV_ROOT -fc4"
348 -post_process_cmd="mv $SIMS_LAUNCH_DIR/efa.dat $SIMS_LAUNCH_DIR/efa_used"
349</fc4>
350
351//////////////////////////////////////////////////////////////////////////////
352
353<fc2>
354#ifdef AXIS_DAILY
355#define AXIS_TL
356#define AXIS_BUILD
357#undef AXIS_64BIT
358#undef AXIS_NO_IP
359#define FC_NO_PEU_VERA FC_NO_PEU_VERA
360#endif
361#ifdef AXIS_TL
362 -vcs_build_args=+incdir+$DV_ROOT/design/niu/niu_mac_l/hedwig_lite
363#endif
364
365#include "fc_common.config"
366 -model=fc2
367 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
368 -config_rtl=CORE_0
369 -config_rtl=CORE_1
370 -config_rtl=RTL_NO_SPC2
371 -config_rtl=RTL_NO_SPC3
372 -config_rtl=RTL_NO_SPC4
373 -config_rtl=RTL_NO_SPC5
374 -config_rtl=RTL_NO_SPC6
375 -config_rtl=RTL_NO_SPC7
376 -sas_run_args=-DSP0
377 -sas_run_args=-DSP1
378 -sunv_args=-define=RTL_NO_SPC2
379 -sunv_args=-define=RTL_NO_SPC3
380 -sunv_args=-define=RTL_NO_SPC4
381 -sunv_args=-define=RTL_NO_SPC5
382 -sunv_args=-define=RTL_NO_SPC6
383 -sunv_args=-define=RTL_NO_SPC7
384 -vcs_run_args=+ASI_CORE_AVILABLE=ffff
385 -vcs_run_args=+ASI_CORE_ENABLE=ffff
386 -diaglist_cpp_args=-DALL_THREADS=ffff
387 -max_cycle=3000000
388 -rtl_timeout=30000
389 -midas_args=-DALL_THREADS=0xffff
390 -midas_args=-DMAX_THREADS=16
391 -efuse_image_name=efa.dat
392 -efuse_image_root=$SIMS_LAUNCH_DIR
393 -pre_process_cmd="$DV_ROOT/tools/bin/efa_gen $SIMS_LAUNCH_DIR $DV_ROOT -fc2"
394 -post_process_cmd="mv $SIMS_LAUNCH_DIR/efa.dat $SIMS_LAUNCH_DIR/efa_used"
395</fc2>
Full OpenSPARC design & verification tarball including full HDL.