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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / config / fc_scan_common.config
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_scan_common.config
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifdef GATESIM_ALL
36 -nosunv_run
37 -nozeroIn_build
38
39#include "fc_gate_all.config"
40// #define USE_FULL_FLOP USE_FULL_FLOP
41
42 -vcs_build_args=+define+PEU_DMU_GATESIM
43 -vcs_build_args=+define+CCU_GATESIM
44#endif
45
46#if (defined CORES1)
47 -config_rtl=CORE_0
48 -sunv_args=-define=RTL_NO_SPC1
49 -sunv_args=-define=RTL_NO_SPC2
50 -sunv_args=-define=RTL_NO_SPC3
51 -sunv_args=-define=RTL_NO_SPC4
52 -sunv_args=-define=RTL_NO_SPC5
53 -sunv_args=-define=RTL_NO_SPC6
54 -sunv_args=-define=RTL_NO_SPC7
55 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
56 -vera_diag_args="-DRTL_NO_SPC1 -DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
57#endif
58#if (defined CORES2)
59 -config_rtl=CORE_0
60 -config_rtl=CORE_1
61 -sunv_args=-define=RTL_NO_SPC2
62 -sunv_args=-define=RTL_NO_SPC3
63 -sunv_args=-define=RTL_NO_SPC4
64 -sunv_args=-define=RTL_NO_SPC5
65 -sunv_args=-define=RTL_NO_SPC6
66 -sunv_args=-define=RTL_NO_SPC7
67 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
68 -vera_diag_args="-DRTL_NO_SPC2 -DRTL_NO_SPC3 -DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
69#endif
70#if (defined CORES4)
71 -config_rtl=CORE_0
72 -config_rtl=CORE_1
73 -config_rtl=CORE_2
74 -config_rtl=CORE_3
75 -sunv_args=-define=RTL_NO_SPC4
76 -sunv_args=-define=RTL_NO_SPC5
77 -sunv_args=-define=RTL_NO_SPC6
78 -sunv_args=-define=RTL_NO_SPC7
79 -vera_build_args=RTL_NO_SPC_LIST="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
80 -vera_diag_args="-DRTL_NO_SPC4 -DRTL_NO_SPC5 -DRTL_NO_SPC6 -DRTL_NO_SPC7"
81#endif
82#if (!defined CORES1 && !defined CORES2 && !defined CORES4)
83 -config_rtl=CORE_0
84 -config_rtl=CORE_1
85 -config_rtl=CORE_2
86 -config_rtl=CORE_3
87 -config_rtl=CORE_4
88 -config_rtl=CORE_5
89 -config_rtl=CORE_6
90 -config_rtl=CORE_7
91#endif
92
93 -flist=$DV_ROOT/verif/env/fc_scan/fc_scan_common.flist
94 -post_process_cmd="regreport -1 | tee status.log"
95
96#ifdef FULL_GATE
97 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist
98 -flist=$DV_ROOT/verif/env/fc/fc_rptr.flist
99#endif
100
101// entire model is gates (model is all gates)
102#if (defined USE_GATESIM)
103 -config_rtl=GATESIM
104 -vera_build_args=GATESIM=GATESIM
105 // whatever...
106#else
107 // whatever...
108 // sunv stuff
109#endif
110
111#if (defined USE_DMU_GATES)
112 -config_rtl=DMU_GATES
113 -config_rtl=ASIC_GATES
114 -vera_build_args=DMU_GATES=DMU_GATES
115 -vera_diag_args="-DDMU_GATES"
116 -vera_build_args=ASIC_GATES=ASIC_GATES
117#endif
118#if (defined USE_PEU_GATES)
119 -config_rtl=PEU_GATES
120 -config_rtl=ASIC_GATES
121 -vera_build_args=PEU_GATES=PEU_GATES
122 -vera_diag_args="-DPEU_GATES"
123 -vera_build_args=ASIC_GATES=ASIC_GATES
124#endif
125#if (defined USE_NIU_GATES)
126 -config_rtl=NIU_GATES
127 -config_rtl=ASIC_GATES
128 -vera_build_args=NIU_GATES=NIU_GATES
129 -vera_diag_args="-DNIU_GATES"
130 -vera_build_args=ASIC_GATES=ASIC_GATES
131#endif
132#if (defined USE_CCU_GATES)
133 -config_rtl=CCU_GATES
134 -config_rtl=ASIC_GATES
135 -vera_build_args=CCU_GATES=CCU_GATES
136 -vera_diag_args="-DCCU_GATES"
137 -vera_build_args=ASIC_GATES=ASIC_GATES
138#endif
139
140 -asm_diag_root=$DV_ROOT/verif/diag
141 -config_rtl=FC_SCAN_BENCH
142 -config_rtl=FC_BENCH
143 -config_rtl=RTL_SPARC0
144 -drm_disk=[/export/home/bw=30]
145 -drm_freeprocessor=1.0
146 -drm_freeram=3000
147 -drm_freeswap=1800
148 -drm_type=vcs
149 -env_base=$DV_ROOT/verif/env/fc_scan
150 -hcs_build_args=-comp_options "+hcs+v2k"
151 -hcs_drm_tokens=12
152
153 -fsdbfile=fc_scan_top.fsdb
154 -image_diag_root=$DV_ROOT/verif
155 -pal_use_tgseed
156 // review
157 -max_cycle=400000000
158 // review
159 -rtl_timeout=25000
160
161#if (defined FC_RAW)
162 -flist=$DV_ROOT/verif/env/fc_scan/fc_raw.flist
163#endif
164
165 -sunv_args=-define=SCAN_MODE
166 -sunv_args=-define=LIB
167 -sunv_args=-define=SIM
168 -sunv_args=-define=VCS
169 -sunv_args=-excludepreload
170 -sunv_args=-ignorepartial
171 -sunv_args=-out=cpu.v
172 -sunv_args=-path=SUNV_RTL_PATH
173 -sunv_args=-perlinclude=SUNV_PATH/include
174 -sunv_args=-preload=SUNVLIBS_SUNV
175 -sunv_args=-showCompiledOutCode=off
176 -sunv_args=-topcell=cpu
177 -sunv_args=-unusednet='unused$:unused\[[0-9]+\]$'
178 -sunv_args=-version
179 -sunv_args=-warn=2000
180 -sunv_args=-excludecell=\^ccu\$
181 -sunv_args=-excludecell=\^n2_rng_cust\$
182 -sunv_use_nonprim
183
184 // KDW 8-18-05 -vcs_build_args=+define+FSR_NOATPG
185 -vcs_build_args=+define+SCAN_MODE
186 -vcs_build_args="-Xstrict=0x1 -syslib -lpthread"
187 -vcs_build_args="-notice"
188 -vcs_build_args=+define+LIB
189 -vcs_build_args=+define+SIM
190 -vcs_build_args=+define+TOP=tb_top
191 -vcs_build_args=+define+X4+
192 -vcs_build_args=+nospecify
193 -vcs_build_args=+notimingcheck
194 -vcs_build_args=+optconfigfile+$DV_ROOT/verif/env/fc_scan/exclude.v
195#if (!defined GATESIM)
196#if (!defined NO_RAD)
197 -vcs_build_args=+rad
198#endif
199#endif
200#ifdef PATCH_713R35
201 -vcs_build_args=+optconfigfile+$DV_ROOT/verif/env/fc_scan/tresh
202 -vcs_build_args=+rad
203// -vcs_build_args=+memopt
204// -vcs_build_args=-comp64
205 -vcs_build_args=-Xman=4
206#endif
207
208 -vcs_build_args=+v2k
209 -vcs_build_args=-Mupdate
210 //-vcs_build_args=-lstdc++
211 -vcs_build_args=SUNVLIBS_OTHER
212
213 -vcs_run_args=+0in_checker_finish_delay+3000
214 -vcs_run_args=+skt_timeout=50000
215 -vcs_run_args=+vcs+flush+log
216
217
218#if (!defined FC_RAW)
219 -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/monitor/monitor_pli.tab"
220 -vcs_build_args=$DV_ROOT/verif/env/common/pli/monitor/libmonitor_pli.a
221 -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/socket/socket_pli.tab"
222 -vcs_build_args=$DV_ROOT/verif/env/common/pli/socket/libsocket_pli.a
223
224 // vera stuff
225 -vcs_run_args=+vera_disable_final_report
226 -vcs_run_args=+vera_exit_on_error
227 -vcs_use_vera
228 // never in common --> -vera_build_args=VERA_SYS_DEFS="-DFC_SCAN_BENCH -DNCURTL -DFC_BENCH"
229 -vera_diag_args="-DFC_SCAN_BENCH -DFC_BENCH"
230 -vera_config_root=$DV_ROOT/verif
231 -vera_diag_root=$DV_ROOT/verif/diag
232 -vera_vcon_file=fc_scan_top.vcon
233 // vera stuff end
234#endif
235
236#ifdef NOSUNV
237 -flist=$DV_ROOT/verif/env/fc/remaining.flist
238#endif
239
240#ifdef PEU_DMU_GATESIM
241 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.peu+dmu_gate
242#endif
243#ifdef CCU_GATESIM
244 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccu_gate
245#endif
246
247#ifdef SUNV_EXCLUDE_IO
248 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.io_gate
249 -sunv_args=-excludecell=\^fsr
250 -sunv_args=-excludecell=\^esr
251 -sunv_args=-excludecell=\^psr
252 -sunv_args=-excludecell=\^mio
253 -sunv_args=-excludecell=\^mio
254 -sunv_args=-excludecell=\^n2_pcm_main_blk
255#endif
256
257#ifdef SUNV_EXCLUDE_CLK_GL_CUST
258 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.clk_gl_cust_gate
259 -sunv_args=-excludecell=\^n2_clk_gl_cust\$
260 -sunv_args=-excludecell=\^n2_clk_gl_cmp_tree\$
261 -sunv_args=-excludecell=\^n2_clk_gl_dr_tree\$
262 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_top\$
263 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_ccu_m0
264 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_rst_m0
265 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_tcu_m0
266 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_17s1
267 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_8s2
268 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_4s4
269 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_1
270 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_0
271 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_0
272 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_1
273 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s4_2
274 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1t_s1_1
275 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_0
276 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_1
277 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_2
278 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s4_3
279 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s1_0
280 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_0
281 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2b_s2_1
282 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_0
283 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_0
284 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s2_1
285 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_0
286 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_1
287 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_3
288 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3t_s1_2
289 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_0
290 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_1
291 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_3
292 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c3b_s1_2
293 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_0
294 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c1b_s1_1
295 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_c2t_s1_1
296 -sunv_args=-excludecell=\^n2_clk_gl_cc_stage_align
297 -sunv_args=-excludecell=\^n2_clk_gl_cc_stg_mcu_dr
298#endif
299
300
301#ifdef SUNV_EXCLUDE_CPU
302 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.cpu_gate
303 -sunv_args=-excludecell=\^cpu
304#endif
305
306#ifdef SUNV_EXCLUDE_MCU
307 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.mcu_gate
308 -sunv_args=-excludecell=\^mcu
309#endif
310
311
312#ifdef SUNV_EXCLUDE_NIU
313 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.niu_gate
314 -sunv_args=-excludecell=\^niu
315 -sunv_args=-excludecell=\^mac
316 -sunv_args=-excludecell=\^rtx
317 -sunv_args=-excludecell=\^rdp
318 -sunv_args=-excludecell=\^tds
319#endif
320#ifdef SUNV_EXCLUDE_TCU
321 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.tcu_gate
322 -sunv_args=-excludecell=\^tcu
323#endif
324#ifdef SUNV_EXCLUDE_RST
325 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.rst_gate
326 -sunv_args=-excludecell=\^rst
327#endif
328#ifdef SUNV_EXCLUDE_EFU
329 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.efu_gate
330 -sunv_args=-excludecell=\^efu
331#endif
332#ifdef SUNV_EXCLUDE_SII_SIO
333 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.sii+sio_gate
334 -sunv_args=-excludecell=\^sii\$
335 -sunv_args=-excludecell=\^sii_ilc_ctl\$
336 -sunv_args=-excludecell=\^sii_ild_dp\$
337 -sunv_args=-excludecell=\^sii_inc_ctl\$
338 -sunv_args=-excludecell=\^sii_ipcc_ctl\$
339 -sunv_args=-excludecell=\^sii_ipcc_dp\$
340 -sunv_args=-excludecell=\^sii_ipcs_ctl\$
341 -sunv_args=-excludecell=\^sii_mb0_ctl\$
342 -sunv_args=-excludecell=\^sii_mb1_ctl\$
343 -sunv_args=-excludecell=\^sii_stgsio_dp\$
344 -sunv_args=-excludecell=\^sio\$
345 -sunv_args=-excludecell=\^sio_mb0_ctl\$
346 -sunv_args=-excludecell=\^sio_mb1_ctl\$
347 -sunv_args=-excludecell=\^sio_mbist_ctl\$
348 -sunv_args=-excludecell=\^sio_olc_ctl\$
349 -sunv_args=-excludecell=\^sio_old_dp\$
350 -sunv_args=-excludecell=\^sio_old_rf_cust\$
351 -sunv_args=-excludecell=\^sio_opcc_ctl\$
352 -sunv_args=-excludecell=\^sio_opcs_ctl\$
353 -sunv_args=-excludecell=\^sio_opd_data_rf_cust\$
354 -sunv_args=-excludecell=\^sio_opd_hdr_rf_cust\$
355 -sunv_args=-excludecell=\^sio_opdc_dp\$
356 -sunv_args=-excludecell=\^sio_opds_dp\$
357 -sunv_args=-excludecell=\^sio_stg1_dp\$
358 -sunv_args=-excludecell=\^sio_stg2_dp\$
359#endif
360#ifdef SUNV_EXCLUDE_SPC
361 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.spc_gate
362 // exclude spc
363 -sunv_args=-excludecell=\^spc\$
364 -sunv_args=-excludecell=\^spc_msf0_dp\$
365 -sunv_args=-excludecell=\^spc_msf1_dp\$
366 -sunv_args=-excludecell=\^spc_lb_ctl\$
367 -sunv_args=-excludecell=\^clkgen_spc_cmp\$
368 -sunv_args=-excludecell=\^dmo_dp\$
369 -sunv_args=-excludecell=\^gkt\$
370 -sunv_args=-excludecell=\^fgu\$
371 -sunv_args=-excludecell=\^ifu_ibu\$
372 -sunv_args=-excludecell=\^ifu_ftu\$
373 -sunv_args=-excludecell=\^ifu_cmu\$
374 -sunv_args=-excludecell=\^dec\$
375 -sunv_args=-excludecell=\^pku\$
376 -sunv_args=-excludecell=\^exu\$
377 -sunv_args=-excludecell=\^tlu\$
378 -sunv_args=-excludecell=\^lsu\$
379 -sunv_args=-excludecell=\^spu\$
380 -sunv_args=-excludecell=\^mmu\$
381 -sunv_args=-excludecell=\^pmu\$
382 -sunv_args=-excludecell=\^spc_mb0_ctl\$
383 -sunv_args=-excludecell=\^spc_mb1_ctl\$
384 -sunv_args=-excludecell=\^spc_mb2_ctl\$
385#endif
386#ifdef SUNV_EXCLUDE_CCX
387 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ccx_gate
388 // exclude ccx
389 -sunv_args=-excludecell=\^ccx\$
390 -sunv_args=-excludecell=\^cpx\$
391 -sunv_args=-excludecell=\^pcx\$
392#endif
393#ifdef SUNV_EXCLUDE_L2
394 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.l2_gate
395 // exclude l2t
396 -sunv_args=-excludecell=\^l2t\$
397 -sunv_args=-excludecell=\^l2t_arb_ctl\$
398 -sunv_args=-excludecell=\^l2t_arbadr_dp\$
399 -sunv_args=-excludecell=\^l2t_arbdat_dp\$
400 -sunv_args=-excludecell=\^l2t_arbdec_dp\$
401 -sunv_args=-excludecell=\^l2t_csr_ctl\$
402 -sunv_args=-excludecell=\^l2t_csreg_ctl\$
403 -sunv_args=-excludecell=\^l2t_decc_dp\$
404 -sunv_args=-excludecell=\^l2t_deccck_ctl\$
405 -sunv_args=-excludecell=\^l2t_dir_ctl\$
406 -sunv_args=-excludecell=\^l2t_dirbuf_ctl\$
407 -sunv_args=-excludecell=\^l2t_dirin_dp\$
408 -sunv_args=-excludecell=\^l2t_dirlbf_dp\$
409 -sunv_args=-excludecell=\^l2t_dirout_dp\$
410 -sunv_args=-excludecell=\^l2t_dirrep_ctl\$
411 -sunv_args=-excludecell=\^l2t_dirtop_ctl\$
412 -sunv_args=-excludecell=\^l2t_dirvec_ctl\$
413 -sunv_args=-excludecell=\^l2t_dirvec_dp\$
414 -sunv_args=-excludecell=\^l2t_dmo_dp\$
415 -sunv_args=-excludecell=\^l2t_dmorpt_dp\$
416 -sunv_args=-excludecell=\^l2t_ecc24b_dp\$
417 -sunv_args=-excludecell=\^l2t_ecc30b_dp\$
418 -sunv_args=-excludecell=\^l2t_ecc39_dp\$
419 -sunv_args=-excludecell=\^l2t_ecc39a_dp\$
420 -sunv_args=-excludecell=\^l2t_evctag_dp\$
421 -sunv_args=-excludecell=\^l2t_ffrpt_dp\$
422 -sunv_args=-excludecell=\^l2t_filbuf_ctl\$
423 -sunv_args=-excludecell=\^l2t_iqu_ctl\$
424 -sunv_args=-excludecell=\^l2t_ique_dp\$
425 -sunv_args=-excludecell=\^l2t_l2brep_dp\$
426 -sunv_args=-excludecell=\^l2t_l2drpt_dp\$
427 -sunv_args=-excludecell=\^l2t_mb0_ctl\$
428 -sunv_args=-excludecell=\^l2t_mb2_ctl\$
429 -sunv_args=-excludecell=\^l2t_mbist_ctl\$
430 -sunv_args=-excludecell=\^l2t_misbuf_ctl\$
431 -sunv_args=-excludecell=\^l2t_mrep16x8_dp\$
432 -sunv_args=-excludecell=\^l2t_mrep2x64_dp\$
433 -sunv_args=-excludecell=\^l2t_mrep32x3_dp\$
434 -sunv_args=-excludecell=\^l2t_mrep4x6_dp\$
435 -sunv_args=-excludecell=\^l2t_mrep8x16_dp\$
436 -sunv_args=-excludecell=\^l2t_oqu_ctl\$
437 -sunv_args=-excludecell=\^l2t_oque_dp\$
438 -sunv_args=-excludecell=\^l2t_pgen32b_dp\$
439 -sunv_args=-excludecell=\^l2t_rdmarpt_dp\$
440 -sunv_args=-excludecell=\^l2t_rdmat_ctl\$
441 -sunv_args=-excludecell=\^l2t_rep_dp\$
442 -sunv_args=-excludecell=\^l2t_ret_dp\$
443 -sunv_args=-excludecell=\^l2t_shdwscn_dp\$
444 -sunv_args=-excludecell=\^l2t_snp_ctl\$
445 -sunv_args=-excludecell=\^l2t_snpd_dp\$
446 -sunv_args=-excludecell=\^l2t_tag_ctl\$
447 -sunv_args=-excludecell=\^l2t_tagd_dp\$
448 -sunv_args=-excludecell=\^l2t_tagdp_ctl\$
449 -sunv_args=-excludecell=\^l2t_taghdr_ctl\$
450 -sunv_args=-excludecell=\^l2t_tagl_dp\$
451 -sunv_args=-excludecell=\^l2t_usaloc_dp\$
452 -sunv_args=-excludecell=\^l2t_vlddir_dp\$
453 -sunv_args=-excludecell=\^l2t_vuad_ctl\$
454 -sunv_args=-excludecell=\^l2t_vuad_dp\$
455 -sunv_args=-excludecell=\^l2t_vuaddp_ctl\$
456 -sunv_args=-excludecell=\^l2t_vuadio_dp\$
457 -sunv_args=-excludecell=\^l2t_vuadpm_dp\$
458 -sunv_args=-excludecell=\^l2t_wbuf_ctl\$
459 -sunv_args=-excludecell=\^l2t_wbufrpt_dp\$
460 // exclude l2b
461 -sunv_args=-excludecell=\^l2b
462#endif
463#ifdef SUNV_EXCLUDE_DB
464 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.db_gate
465 // exclude db0
466 -sunv_args=-excludecell=\^db0\$
467 -sunv_args=-excludecell=\^db0_red_dp\$
468 -sunv_args=-excludecell=\^db0_reduct_ctl\$
469 -sunv_args=-excludecell=\^db0_rtc_dp\$
470 // exclude db1
471 -sunv_args=-excludecell=\^db1\$
472 -sunv_args=-excludecell=\^db1_csr_ctl\$
473 -sunv_args=-excludecell=\^db1_dbgprt_dp\$
474 -sunv_args=-excludecell=\^db1_ucbbusin4_ctl\$
475 -sunv_args=-excludecell=\^db1_ucbbusout4_ctl\$
476 -sunv_args=-excludecell=\^db1_ucbflow_ctl\$
477#endif
478#ifdef SUNV_EXCLUDE_NCU
479 -flist=$DV_ROOT/verif/env/fc/fc_gl.flist.ncu_gate
480 -sunv_args=-excludecell=\^ncu\$
481 -sunv_args=-excludecell=\^ncu_c2ibuf32_ctl\$
482 -sunv_args=-excludecell=\^ncu_c2ibuf4_ctl\$
483 -sunv_args=-excludecell=\^ncu_c2ibufpio_ctl\$
484 -sunv_args=-excludecell=\^ncu_c2ifc_ctl\$
485 -sunv_args=-excludecell=\^ncu_c2ifcd_ctl\$
486 -sunv_args=-excludecell=\^ncu_c2ifd_ctl\$
487 -sunv_args=-excludecell=\^ncu_c2isc_ctl\$
488 -sunv_args=-excludecell=\^ncu_c2iscd_ctl\$
489 -sunv_args=-excludecell=\^ncu_c2isd_ctl\$
490 -sunv_args=-excludecell=\^ncu_ctrl_ctl\$
491 -sunv_args=-excludecell=\^ncu_eccchk11_ctl\$
492 -sunv_args=-excludecell=\^ncu_eccchk16_ctl\$
493 -sunv_args=-excludecell=\^ncu_eccchk6_ctl\$
494 -sunv_args=-excludecell=\^ncu_eccgen11_ctl\$
495 -sunv_args=-excludecell=\^ncu_eccgen6_ctl\$
496 -sunv_args=-excludecell=\^ncu_fcd_ctl\$
497 -sunv_args=-excludecell=\^ncu_i2cbuf32_ctl\$
498 -sunv_args=-excludecell=\^ncu_i2cbuf32_ni_ctl\$
499 -sunv_args=-excludecell=\^ncu_i2cbuf4_ctl\$
500 -sunv_args=-excludecell=\^ncu_i2cbuf4_ni_ctl\$
501 -sunv_args=-excludecell=\^ncu_i2cbufsii_ctl\$
502 -sunv_args=-excludecell=\^ncu_i2cbuftcu_ctl\$
503 -sunv_args=-excludecell=\^ncu_i2cfc_ctl\$
504 -sunv_args=-excludecell=\^ncu_i2cfcd_ctl\$
505 -sunv_args=-excludecell=\^ncu_i2cfd_ctl\$
506 -sunv_args=-excludecell=\^ncu_i2csc_ctl\$
507 -sunv_args=-excludecell=\^ncu_i2cscd_ctl\$
508 -sunv_args=-excludecell=\^ncu_i2csd_ctl\$
509 -sunv_args=-excludecell=\^ncu_mb0_ctl\$
510 -sunv_args=-excludecell=\^ncu_mb1_ctl\$
511 -sunv_args=-excludecell=\^ncu_scd_ctl\$
512 -sunv_args=-excludecell=\^ncu_ssiflow_ctl\$
513 -sunv_args=-excludecell=\^ncu_ssisif_ctl\$
514 -sunv_args=-excludecell=\^ncu_ssisrg64_ctl\$
515 -sunv_args=-excludecell=\^ncu_ssisrg8_ctl\$
516 -sunv_args=-excludecell=\^ncu_ssitop_ctl\$
517 -sunv_args=-excludecell=\^ncu_ssiui4_ctl\$
518 -sunv_args=-excludecell=\^ncu_ssiuif_ctl\$
519 -sunv_args=-excludecell=\^ncu_ssiuo4_ctl\$
520 -sunv_args=-excludecell=\^ncu_ucbbusin8_ctl\$
521 //
522#endif
523
524 -vlint_args=+define+TOP=tb_top
525 -vlint_args=-binary
526 -vlint_args=-depth 999
527 -vlint_args=-turn_unspecified_off
528 -vlint_args=SUNVLIBS_OTHER
529 -vlint_args=-vlint
530 -vlint_args=-vr $DV_ROOT/verif/env/config/vlint.rc
531 -vlint_top=tb_top
532
533 -vcs_cm_config=$DV_ROOT/verif/env/fc_scan/fc_scan.cm_config
534 -wait_cycle_to_kill=15
535
536 -zeroIn_build_args=+define+EMBED_SIMS_BUILD_ARGS
537 -zeroIn_build_args=+define+FC_NO_PEUSAT_CODE
538 -zeroIn_build_args=+define+CPU=tb_top.cpu
539 -zeroIn_build_args=+define+ESR=tb_top.cpu.esr
540 -zeroIn_build_args=+define+MAC=tb_top.cpu.mac
541 -zeroIn_build_args=+define+RDP=tb_top.cpu.rdp
542 -zeroIn_build_args=+define+RTX=tb_top.cpu.rtx
543 -zeroIn_build_args=+define+TDS=tb_top.cpu.tds
544 -zeroIn_build_args=+define+TOP=tb_top
545 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/coverage/0in_coverages.v
546 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v
547 -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/fc_scan/fc_scan_zeroIn_cfg.v
548 -zeroIn_build_args=-d cpu
549 -zeroIn_build_args=+error+command-19
550 -zeroIn_build_args=+error+command-46
551 -zeroIn_build_args=+error+command-6
552 -zeroIn_build_args=+error+command-7
553 -zeroIn_build_args=-exit_on_directive_errors
554 -zeroIn_build_args=-incr
555#ifdef AXIS_BUILD
556 -zeroIn_build_args=-sim axis
557#else
558 -zeroIn_build_args=-sim vcs
559#ifndef NOFASTMOD
560 -zeroIn_build_args=-fastmod
561#endif
562#ifndef ZEROINCOV
563 -zeroIn_build_args="-fastsim turbo"
564#else
565 // This arg creates a 0in_coverage_bitmap.txt in the 0in build dir
566 -zeroIn_dbg_args=+0in_debug+display_stats_in_binary+coverage_bit_map
567#endif
568#endif
569 -zeroIn_build_args=SUNVLIBS_OTHER
570
571 //-vcs_build_args=+applylearn+$DV_ROOT/verif/env/fc/pli_learn_all.tab
572 //-zeroIn_build_args=-fastmod
573 SUNVFORCEOPTS
Full OpenSPARC design & verification tarball including full HDL.