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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fpga.config | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // This config file builds all FPGA models | |
36 | ////////////////////////////////////////////////////////////////////////////// | |
37 | <fpga_1c8t> | |
38 | ||
39 | -model=fpga_1c8t | |
40 | ||
41 | #ifdef GATESIM | |
42 | -flist=$DV_ROOT/design/fpga/gate/fpga_gate_master.flist | |
43 | -vcs_build_args=-Marchive=100 | |
44 | ||
45 | #else | |
46 | -flist=$DV_ROOT/design/fpga/rtl/fpga_rtl.flist | |
47 | #endif | |
48 | ||
49 | -novera_build | |
50 | -nontb_lib | |
51 | ||
52 | -vcs_build_args=+v2k | |
53 | -vcs_build_args=+vcs+initmem+0 | |
54 | -vcs_build_args=-nohsopt | |
55 | ||
56 | -fast_boot | |
57 | -nosas | |
58 | -tg_seed=1 | |
59 | ||
60 | -asm_diag_root=$DV_ROOT/verif/diag/assembly | |
61 | -image_diag_root=$DV_ROOT/verif/diag | |
62 | -midas_args=-tsbtagfmt=tagtarget | |
63 | -midas_args=-cpp_args=-traditional-cpp | |
64 | -midas_args=-allow_tsb_conflict | |
65 | -midas_args=-DL2_REG_PROG | |
66 | -midas_args=-DCMP_THREAD_START=0x1 | |
67 | -midas_args=-DPART_0_BASE=0 | |
68 | -midas_args=-DPART_1_BASE=0x20000000 | |
69 | -midas_args=-DPART_2_BASE=0x30000000 | |
70 | -midas_args=-DMAIN_BASE_DATA_RA=0x21000000 | |
71 | -midas_args=-DMAIN_BASE_BSS_RA=0x18030000 | |
72 | -midas_args=-DMAIN_BASE_TEXT_RA=0x18000000 | |
73 | -midas_args=-DKERNEL_BASE_TEXT_RA=0x01834000 | |
74 | -midas_args=-DUSER_HEAP_DATA_RA=0x28020000 | |
75 | -midas_args=-DKERNEL_BASE_DATA_RA=0x01c34000 | |
76 | -midas_args=-DPART_0_LINK_AREA_BASE_ADDR=0x2d000000 | |
77 | -midas_args=-DMAIN_BASE_DATA_VA=0x2a000000 | |
78 | ||
79 | -vcs_run_args=+GOOD_TRAP=0000083400 | |
80 | -novera_run | |
81 | -post_process_cmd="regreport -1 | tee status.log" | |
82 | ||
83 | ||
84 | ||
85 | </fpga_1c8t> | |
86 | ////////////////////////////////////////////////////////////////////////////// |