Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / config / niu.config

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: niu.config
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#include "defaults.config"
//------------------------------------------------------------

<niu>
#ifdef AXIS_BUILD
    -config_rtl=AXIS
    -sunv_args=-keepSectionSym=AXIS_SMEM
    -sunv_args=-keepSectionSym=EMUL_COSIM
    -vcs_build_args=-P $VERA_HOME/lib/vera_pli.tab
    -vcs_build_args=$VERA_HOME/lib/libSysSciTask.a
    -vcs_build_args="-pl -lsocket -pl -lnsl -pl -lintl -pl -ldl"
    -vcs_build_args=+v2000
// use axis_build_args to exclude modules    -vcs_build_args=+dutexcl+fflp_flow_fifo
   -vcs_build_args=+dutexcl+fflp_flow_fifo
   -vcs_build_args=+dutexcl+niu_smx_regfl
   -vcs_build_args=+dutexcl+fflp_hdr_fifo
//   -vcs_build_args=+dutexcl+delay_n
//   -vcs_build_args=+dutexcl+delay_n_w_stalling
//   -vcs_build_args=+dutexcl+dmu_common_simple_fifo
    -vcs_build_args=+define+AXIS
    -axis_build_args="-scope n2_ccm  -map_udp"
//    -axis_build_args="-vms_excl delay_n+delay_n_w_stalling+niu_smx_regfl+dmu_common_simple_fifo+fflp_hdr_fifo+fflp_flow_fifo "
    -vcs_build_args=+define+DISABLE_ERR_MON
#endif
    -asm_diag_root=$DV_ROOT/verif/diag
        -vera_diag_root=$DV_ROOT/verif/diag
        -vera_config_root=$DV_ROOT/verif
        -image_diag_root=$DV_ROOT/verif
        -wait_cycle_to_kill=10
        -post_process_cmd="regreport -1 > status.log"
    -model=niu
        -flist=$DV_ROOT/verif/env/niu/niu.flist
        -flist=$DV_ROOT/verif/env/niu/niu_tb.flist
// Since TI's SERDES model doesn't work right now bypass and use noserdes mode
// as default for AXIS_BUILD
#ifdef AXIS_BUILD
	-flist=$DV_ROOT/verif/env/niu/eser_dummy.flist
#else
        -flist=$DV_ROOT/verif/env/niu/eser_rtl.flist
        -flist=$DV_ROOT/verif/env/niu/eser_tb.flist
#endif
        -config_rtl=niu
        -env_base=$DV_ROOT/verif/env/niu
    -drm_disk=[/export/home/bw=30]
        -drm_type=vcs
        -drm_freeram=500
        -drm_freeprocessor=1.0
    SUNVFORCEOPTS
    -sunv_args=-topcell=cpu
        -sunv_args=-define=sim
        -sunv_use_nonprim
        -sunv_nonprim_list=$DV_ROOT/verif/env/niu/nonprimitive.list
        -sunv_args=-excludecell=rdp
        -sunv_args=-excludecell=rtx
        -sunv_args=-excludecell=tds
        -sunv_args=-excludecell=mac
        -sunv_args=-excludecell=esr
        -sunv_args=-excludepreload
        -sunv_args=-out=cpu.v
        -sunv_args=-path=SUNV_RTL_PATH
        -sunv_args=-path=SUNVMACROS
        -sunv_args=-preload=SUNVLIBS_SUNV
        -sunv_args=-perlinclude=SUNVPERLINC
    -vlint_top=niu
        -vlint_args=+define+TOP=niu
        -vlint_args=-turn_unspecified_off
        -vlint_args=-binary
        -vlint_args=-vlint
        -vlint_args=-depth 999
        -vlint_args=-vr $DV_ROOT/verif/env/config/asic_vlint.rc
        -vlint_args=-turn_unspecified_off
        -vlint_args=+define+N2_NIU
        -vlint_args=+define+LIB
        -vlint_args=+turnoff+synopsys+translate_off+turnon+synopsys+translate_on
	-vlint_args=-merge_bus_report
	-vlint_args=SUNVLIBS_OTHER
    -illust_run
    -illust_args=-b -c $DV_ROOT/verif/env/config/filter_vlint.rc
    -zeroIn_build_args=-d cpu
	-zeroIn_build_args=+define+TOP=tb_top
#ifdef AXIS_BUILD
   -zeroIn_build_args=-sim axis
#else
            -zeroIn_build_args=-sim vcs
#endif
	    -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/common/verilog/checkers/0in_checkers.v
            -zeroIn_build_args=+define+CPU=tb_top.cpu
            -zeroIn_build_args=+define+MAC=tb_top.cpu.mac
            -zeroIn_build_args=+define+RDP=tb_top.cpu.rdp
            -zeroIn_build_args=+define+TDS=tb_top.cpu.tds
            -zeroIn_build_args=+define+RTX=tb_top.cpu.rtx
            -zeroIn_build_args=+define+ESR=tb_top.cpu.esr
            -zeroIn_build_args=+define+VERA_SHELL_TOP=niu_top_shell
            -zeroIn_build_args=-ctrl $DV_ROOT/verif/env/niu/niu_zeroIn_cfg.v
	    -zeroIn_build_args=-v SUNVLIB
	    -zeroIn_build_args=SUNVLIBS_OTHER
	    -zeroIn_build_args=-rcd
            -zeroIn_build_args=+define+X_GUARD
   	    -zeroIn_build_args=+define+LIB
   	    -zeroIn_build_args=+define+N2_NIU
	    -zeroIn_build_args=-exit_on_directive_errors
            -zeroIn_build_args=+error+command-19
            -zeroIn_build_args=+error+command-46
            -zeroIn_build_args=+error+command-6
            -zeroIn_build_args=+error+command-7
#ifdef AXIS_BUILD
   // Remove   -axis_build_args=" -model_type axis_sw_vcs "
   -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.tab"
   -vcs_build_args=" -P $DV_ROOT/verif/model/verilog/niu/sparse_mem_model/pli/mempli.tab "
   -vcs_build_args=" +vc vera/mempli.a"

   -vcs_build_args=" +vc vera/mal.o"
   -vcs_build_args=" $DV_ROOT/verif/env/common/pli/niu_pli/pgRandom.o"
   -vcs_build_args=" -pl -R/import/freetools/local/gcc/3.3.2/lib "
   -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libstdc++.so"
   -vcs_build_args=" /import/freetools/local/gcc/3.3.2/lib/libgcc_s.so "
//these four packet gen files are order sensitive!! sims reverses the order from what is shown here
//to what gets passed to the linker, and libnet.a must be at the end of the link order
   -vcs_build_args=" +vc vera/libnet.a "
   -vcs_build_args=" +vc vera/pgVera.a"
   -vcs_build_args=" +vc vera/pgVeraWrap.o "
   -vcs_build_args=" +vc vera/genCpacket.o  "
   -vcs_build_args=" $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o "
   -vcs_build_args="+tran  +tran_force"
        -vcs_build_args=+define+MAC0 +define+MAC1 +define+MAC2 +define+MAC3 +define+RXC +define+N2_NIU
        -vcs_build_args="+ignUnusedTf+SysPreInit_Data"
#else

    -vcs_build_args=-Mupdate 
            -vcs_build_args=+v2k
            -vcs_build_args=-vera
            -vcs_build_args="-Xstrict=0x1 -syslib -lpthread "
	    -vcs_build_args="-Xstrict=0x1 -syslib -lpthread "
            VCS_BUILD_WITH_GPP
            -vcs_build_args="-lstdc++"
            -vcs_build_args=+define+MAC0 +define+MAC1 +define+MAC2 +define+MAC3 +define+RXC +define+N2_NIU
            -vcs_build_args=" -P $DV_ROOT/verif/model/verilog/niu/sparse_mem_model/pli/mempli.tab "
            -vcs_build_args=" +vc vera/mal.o"
            -vcs_build_args=" +vc vera/pgVeraWrap.o"
            -vcs_build_args=" +vc vera/genCpacket.o"
            -vcs_build_args=" +vc vera/libnet.a"
            -vcs_build_args=" +vc vera/pgVera.a"
            -vcs_build_args=" +vc vera/pgRandom.o"
            -vcs_build_args=vera/mempli.a
            -vcs_build_args="-P $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.tab"
            -vcs_build_args=" $DV_ROOT/verif/env/common/pli/niu_pli/get_plus_args.o -cc gcc"

#endif
            -vcs_build_args=+define+LIB
            -vcs_build_args=+define+INITLATZERO
	    -vcs_build_args=SUNVLIBS_OTHER
    -vcs_cm_config=$DV_ROOT/verif/env/niu/niu.cm_config
    -sas_run_args=-DSP0
        -sas_run_args=-DMEM_TEST
        -sas_run_args=-DINTR_TEST
        -sas_run_args=-DMEM_DEBUG
        -sas_run_args=-DNIAGARA
    -vcs_run_args=+SRDS_REG_SLAM
// Default AXIS_BUILD to no serdes
#ifdef AXIS_BUILD
#else
    -vcs_run_args=+wserdes
#endif
    -vcs_run_args=+vera_disable_final_report
    -vcs_run_args=+vera_exit_on_error 
#ifdef AXIS_BUILD
    -vera_build_args=N2_AXIS=N2_AXIS
#endif
    -vera_build_args=NEPTUNE_MODE=N2
    -vera_build_args=NEPTUNE_ENV=CDMSPP
</niu>