projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: axis_ccx_mon.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module axis_cmp_mon ( | |
| 36 | clk, | |
| 37 | reset96, | |
| 38 | spc_pcx_req_pq, | |
| 39 | pcx_spc_grant_px, | |
| 40 | spc_pcx_atom_pq, | |
| 41 | spc_pcx_data_pa, | |
| 42 | cpx_spc_data_cx2, | |
| 43 | ||
| 44 | CLK_CNT, | |
| 45 | core_mask, | |
| 46 | core_id, | |
| 47 | en_status, | |
| 48 | pcx_cpx_en, | |
| 49 | pcx_cpx_short, | |
| 50 | pcx_cpx_io, | |
| 51 | watch_dog_finish | |
| 52 | ); | |
| 53 | ||
| 54 | ||
| 55 | input clk; | |
| 56 | input reset96; | |
| 57 | input [ 8:0] spc_pcx_req_pq; | |
| 58 | input [ 8:0] pcx_spc_grant_px; | |
| 59 | input [ 8:0] spc_pcx_atom_pq; | |
| 60 | input [129:0] spc_pcx_data_pa; | |
| 61 | input [145:0] cpx_spc_data_cx2; | |
| 62 | input [ 39:0] CLK_CNT; | |
| 63 | input [ 7:0] core_mask; | |
| 64 | input [ 2:0] core_id; | |
| 65 | input en_status; | |
| 66 | input pcx_cpx_en; | |
| 67 | input pcx_cpx_short; | |
| 68 | input pcx_cpx_io; | |
| 69 | ||
| 70 | output watch_dog_finish; | |
| 71 | ||
| 72 | ||
| 73 | ||
| 74 | reg [15:0] WDOG0, WDOG1, WDOG2, WDOG3, WDOG4,WDOG5,WDOG6,WDOG7; | |
| 75 | reg WDOG_IDLE0, WDOG_IDLE1, WDOG_IDLE2, WDOG_IDLE3 , WDOG_IDLE4, WDOG_IDLE5, WDOG_IDLE6, WDOG_IDLE7; | |
| 76 | ||
| 77 | reg REQ_CY; | |
| 78 | reg ERROR_BANK; | |
| 79 | reg [1:0] REQ_OUTSTANDING0; | |
| 80 | reg [1:0] REQ_OUTSTANDING1; | |
| 81 | reg [1:0] REQ_OUTSTANDING2; | |
| 82 | reg [1:0] REQ_OUTSTANDING3; | |
| 83 | reg [1:0] REQ_OUTSTANDING4; | |
| 84 | reg [1:0] REQ_OUTSTANDING5; | |
| 85 | reg [1:0] REQ_OUTSTANDING6; | |
| 86 | reg [1:0] REQ_OUTSTANDING7; | |
| 87 | reg [1:0] REQ_OUTSTANDING8; | |
| 88 | reg [63:0] CONSOLE_DATA; | |
| 89 | ||
| 90 | reg [3:0] HYP_WATCH_CNT; | |
| 91 | reg [1:0] HYP_WATCH_ITER; | |
| 92 | ||
| 93 | reg [2:0] core_id_r; | |
| 94 | reg [8:0] tlu_early_ttype_g_r; | |
| 95 | reg [1:0] true_trap_tid_g_r; | |
| 96 | reg [2:0] trp_lvl_r; | |
| 97 | reg [ 48:0] tlu_restore_pc_w1_r; | |
| 98 | reg [129:0] spc_pcx_data_pa_r; | |
| 99 | reg [145:0] cpx_spc_data_cx2_r; | |
| 100 | ||
| 101 | ||
| 102 | /******************************************************************************************************************* | |
| 103 | * This logic makes sure threads are not inactive for more than 8K cycles. | |
| 104 | *******************************************************************************************************************/ | |
| 105 | wire wdog_fwdv = (spc_pcx_data_pa[122:119] == 4'h6); | |
| 106 | ||
| 107 | `ifdef CMP_IOBDG | |
| 108 | wire wdog_clk = (CLK_CNT > 190000); | |
| 109 | `else | |
| 110 | wire wdog_clk = (CLK_CNT > 20000); | |
| 111 | `endif | |
| 112 | ||
| 113 | wire wdog_reqv0 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b000) & ~wdog_fwdv & wdog_clk & core_mask[0]; | |
| 114 | wire wdog_reqv1 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b001) & ~wdog_fwdv & wdog_clk & core_mask[1]; | |
| 115 | wire wdog_reqv2 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b010) & ~wdog_fwdv & wdog_clk & core_mask[2]; | |
| 116 | wire wdog_reqv3 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b011) & ~wdog_fwdv & wdog_clk & core_mask[3]; | |
| 117 | wire wdog_reqv4 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b100) & ~wdog_fwdv & wdog_clk & core_mask[4]; | |
| 118 | wire wdog_reqv5 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b101) & ~wdog_fwdv & wdog_clk & core_mask[5]; | |
| 119 | wire wdog_reqv6 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b110) & ~wdog_fwdv & wdog_clk & core_mask[6]; | |
| 120 | wire wdog_reqv7 = spc_pcx_data_pa[129] & (spc_pcx_data_pa[119:117] == 3'b111) & ~wdog_fwdv & wdog_clk & core_mask[7]; | |
| 121 | ||
| 122 | wire wdog_intv0 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b00) & core_mask[0]; | |
| 123 | wire wdog_intv1 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b01) & core_mask[1]; | |
| 124 | wire wdog_intv2 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b10) & core_mask[2]; | |
| 125 | wire wdog_intv3 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b11) & core_mask[3]; | |
| 126 | wire wdog_intv4 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b11) & core_mask[4]; | |
| 127 | wire wdog_intv5 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b11) & core_mask[5]; | |
| 128 | wire wdog_intv6 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b11) & core_mask[6]; | |
| 129 | wire wdog_intv7 = (cpx_spc_data_cx2[145:141] == 5'h17) & ~cpx_spc_data_cx2[137] & (cpx_spc_data_cx2[9:8] == 2'b11) & core_mask[7]; | |
| 130 | ||
| 131 | wire [15:0] wdog0p = wdog_reqv0 ? 16'hFFFF : | |
| 132 | (WDOG0 == 16'h0000) ? 16'h0000 : | |
| 133 | WDOG_IDLE0 ? WDOG0 : ((WDOG0 - 1'b1) & 16'hFFFF); | |
| 134 | wire [15:0] wdog1p = wdog_reqv1 ? 16'hFFFF : | |
| 135 | (WDOG1 == 16'h0000) ? 16'h0000 : | |
| 136 | WDOG_IDLE1 ? WDOG1 : ((WDOG1 - 1'b1) & 16'hFFFF); | |
| 137 | wire [15:0] wdog2p = wdog_reqv2 ? 16'hFFFF : | |
| 138 | (WDOG2 == 16'h0000) ? 16'h0000 : | |
| 139 | WDOG_IDLE2 ? WDOG2 : ((WDOG2 - 1'b1) & 16'hFFFF); | |
| 140 | wire [15:0] wdog3p = wdog_reqv3 ? 16'hFFFF : | |
| 141 | (WDOG3 == 16'h0000) ? 16'h0000 : | |
| 142 | WDOG_IDLE3 ? WDOG3 : ((WDOG3 - 1'b1) & 16'hFFFF); | |
| 143 | wire [15:0] wdog4p = wdog_reqv4 ? 16'hFFFF : | |
| 144 | (WDOG4 == 16'h0000) ? 16'h0000 : | |
| 145 | WDOG_IDLE4 ? WDOG4 : ((WDOG4 - 1'b1) & 16'hFFFF); | |
| 146 | wire [15:0] wdog5p = wdog_reqv5 ? 16'hFFFF : | |
| 147 | (WDOG5 == 16'h0000) ? 16'h0000 : | |
| 148 | WDOG_IDLE5 ? WDOG5 : ((WDOG5 - 1'b1) & 16'hFFFF); | |
| 149 | wire [15:0] wdog6p = wdog_reqv6 ? 16'hFFFF : | |
| 150 | (WDOG6 == 16'h0000) ? 16'h0000 : | |
| 151 | WDOG_IDLE6 ? WDOG6 : ((WDOG6 - 1'b1) & 16'hFFFF); | |
| 152 | wire [15:0] wdog7p = wdog_reqv7 ? 16'hFFFF : | |
| 153 | (WDOG7 == 16'h0000) ? 16'h0000 : | |
| 154 | WDOG_IDLE7 ? WDOG7 : ((WDOG7 - 1'b1) & 16'hFFFF); | |
| 155 | ||
| 156 | wire wdog_idle0p = wdog_intv0 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE0; | |
| 157 | wire wdog_idle1p = wdog_intv1 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE1; | |
| 158 | wire wdog_idle2p = wdog_intv2 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE2; | |
| 159 | wire wdog_idle3p = wdog_intv3 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE3; | |
| 160 | wire wdog_idle4p = wdog_intv4 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE4; | |
| 161 | wire wdog_idle5p = wdog_intv5 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE4; | |
| 162 | wire wdog_idle6p = wdog_intv6 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE5; | |
| 163 | wire wdog_idle7p = wdog_intv7 ? (cpx_spc_data_cx2[17:16] == 2'b10) : WDOG_IDLE7; | |
| 164 | ||
| 165 | /******************************************************************************************************************* | |
| 166 | * This logic checks that each core has at most two request outstanding to each bank at the same time. | |
| 167 | *******************************************************************************************************************/ | |
| 168 | wire req_cyP =( | |
| 169 | (spc_pcx_req_pq[8] & ~((REQ_OUTSTANDING8 == 2'b10) & ~pcx_spc_grant_px[8])) | | |
| 170 | (spc_pcx_req_pq[7] & ~((REQ_OUTSTANDING7 == 2'b10) & ~pcx_spc_grant_px[7])) | | |
| 171 | (spc_pcx_req_pq[6] & ~((REQ_OUTSTANDING6 == 2'b10) & ~pcx_spc_grant_px[6])) | | |
| 172 | (spc_pcx_req_pq[5] & ~((REQ_OUTSTANDING5 == 2'b10) & ~pcx_spc_grant_px[5])) | | |
| 173 | (spc_pcx_req_pq[4] & ~((REQ_OUTSTANDING4 == 2'b10) & ~pcx_spc_grant_px[4])) | | |
| 174 | (spc_pcx_req_pq[3] & ~((REQ_OUTSTANDING3 == 2'b10) & ~pcx_spc_grant_px[3])) | | |
| 175 | (spc_pcx_req_pq[2] & ~((REQ_OUTSTANDING2 == 2'b10) & ~pcx_spc_grant_px[2])) | | |
| 176 | (spc_pcx_req_pq[1] & ~((REQ_OUTSTANDING1 == 2'b10) & ~pcx_spc_grant_px[1])) | | |
| 177 | (spc_pcx_req_pq[0] & ~((REQ_OUTSTANDING0 == 2'b10) & ~pcx_spc_grant_px[0]))); | |
| 178 | ||
| 179 | wire [1:0] req_outstanding0p = (spc_pcx_atom_pq[0] & spc_pcx_req_pq[0]) ? 2'b10 : | |
| 180 | ~(pcx_spc_grant_px[0] ^ (spc_pcx_req_pq[0] & req_cyP)) ? REQ_OUTSTANDING0[1:0] : | |
| 181 | pcx_spc_grant_px[0] ? (REQ_OUTSTANDING0[1:0] - 2'h1) : | |
| 182 | (REQ_OUTSTANDING0[1:0] + 2'h1); | |
| 183 | wire [1:0] req_outstanding1p = (spc_pcx_atom_pq[1] & spc_pcx_req_pq[1]) ? 2'b10 : | |
| 184 | ~(pcx_spc_grant_px[1] ^ (spc_pcx_req_pq[1] & req_cyP)) ? REQ_OUTSTANDING1[1:0] : | |
| 185 | pcx_spc_grant_px[1] ? (REQ_OUTSTANDING1[1:0] - 2'h1) : | |
| 186 | (REQ_OUTSTANDING1[1:0] + 2'h1); | |
| 187 | wire [1:0] req_outstanding2p = (spc_pcx_atom_pq[2] & spc_pcx_req_pq[2]) ? 2'b10 : | |
| 188 | ~(pcx_spc_grant_px[2] ^ (spc_pcx_req_pq[2] & req_cyP)) ? REQ_OUTSTANDING2[1:0] : | |
| 189 | pcx_spc_grant_px[2] ? (REQ_OUTSTANDING2[1:0] - 2'h1) : | |
| 190 | (REQ_OUTSTANDING2[1:0] + 2'h1); | |
| 191 | wire [1:0] req_outstanding3p = (spc_pcx_atom_pq[3] & spc_pcx_req_pq[3]) ? 2'b10 : | |
| 192 | ~(pcx_spc_grant_px[3] ^ (spc_pcx_req_pq[3] & req_cyP)) ? REQ_OUTSTANDING3[1:0] : | |
| 193 | pcx_spc_grant_px[3] ? (REQ_OUTSTANDING3[1:0] - 2'h1) : | |
| 194 | (REQ_OUTSTANDING3[1:0] + 2'h1); | |
| 195 | /*{{{ */ | |
| 196 | wire [1:0] req_outstanding4p = (spc_pcx_atom_pq[4] & spc_pcx_req_pq[4]) ? 2'b10 : | |
| 197 | ~(pcx_spc_grant_px[4] ^ (spc_pcx_req_pq[4] & req_cyP)) ? REQ_OUTSTANDING4[1:0] : | |
| 198 | pcx_spc_grant_px[4] ? (REQ_OUTSTANDING4[1:0] - 2'h1) : | |
| 199 | (REQ_OUTSTANDING4[1:0] + 2'h1); | |
| 200 | /*}}} */ | |
| 201 | /*{{{ */ | |
| 202 | wire [1:0] req_outstanding5p = (spc_pcx_atom_pq[5] & spc_pcx_req_pq[5]) ? 2'b10 : | |
| 203 | ~(pcx_spc_grant_px[5] ^ (spc_pcx_req_pq[5] & req_cyP)) ? REQ_OUTSTANDING5[1:0] : | |
| 204 | pcx_spc_grant_px[5] ? (REQ_OUTSTANDING5[1:0] - 2'h1) : | |
| 205 | (REQ_OUTSTANDING5[1:0] + 2'h1); | |
| 206 | /*}}} */ | |
| 207 | /*{{{ */ | |
| 208 | wire [1:0] req_outstanding6p = (spc_pcx_atom_pq[6] & spc_pcx_req_pq[6]) ? 2'b10 : | |
| 209 | ~(pcx_spc_grant_px[6] ^ (spc_pcx_req_pq[6] & req_cyP)) ? REQ_OUTSTANDING6[1:0] : | |
| 210 | pcx_spc_grant_px[6] ? (REQ_OUTSTANDING6[1:0] - 2'h1) : | |
| 211 | (REQ_OUTSTANDING6[1:0] + 2'h1); | |
| 212 | /*}}} */ | |
| 213 | /*{{{ */ | |
| 214 | wire [1:0] req_outstanding7p = (spc_pcx_atom_pq[7] & spc_pcx_req_pq[7]) ? 2'b10 : | |
| 215 | ~(pcx_spc_grant_px[7] ^ (spc_pcx_req_pq[7] & req_cyP)) ? REQ_OUTSTANDING7[1:0] : | |
| 216 | pcx_spc_grant_px[7] ? (REQ_OUTSTANDING7[1:0] - 2'h1) : | |
| 217 | (REQ_OUTSTANDING7[1:0] + 2'h1); | |
| 218 | /*}}} */ | |
| 219 | /*{{{ */ | |
| 220 | wire [1:0] req_outstanding8p = (spc_pcx_atom_pq[8] & spc_pcx_req_pq[8]) ? 2'b10 : | |
| 221 | ~(pcx_spc_grant_px[8] ^ (spc_pcx_req_pq[8] & req_cyP)) ? REQ_OUTSTANDING8[1:0] : | |
| 222 | pcx_spc_grant_px[8] ? (REQ_OUTSTANDING8[1:0] - 2'h1) : | |
| 223 | (REQ_OUTSTANDING8[1:0] + 2'h1); | |
| 224 | /*}}} */ | |
| 225 | ||
| 226 | wire error_bankP = ((&REQ_OUTSTANDING0)|(&REQ_OUTSTANDING1)| | |
| 227 | (&REQ_OUTSTANDING2)|(&REQ_OUTSTANDING3)| | |
| 228 | (&REQ_OUTSTANDING4)|(&REQ_OUTSTANDING5)| | |
| 229 | (&REQ_OUTSTANDING6)|(&REQ_OUTSTANDING7)| | |
| 230 | (&REQ_OUTSTANDING8)); // 0in val -val 0 | |
| 231 | ||
| 232 | ||
| 233 | /******************************************************************************************************************* | |
| 234 | * This is the bus display logic | |
| 235 | *******************************************************************************************************************/ | |
| 236 | wire istor_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100001); | |
| 237 | wire ifill_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b110000); | |
| 238 | wire ifprl_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b101010); | |
| 239 | wire iload_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100000) & ~spc_pcx_data_pa[115]; | |
| 240 | wire ilstm_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100000) & spc_pcx_data_pa[115]; | |
| 241 | wire icasa1_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100010); | |
| 242 | wire icasa2_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100011); | |
| 243 | wire iswap_req = REQ_CY & (spc_pcx_data_pa[129:124] == 6'b100111); | |
| 244 | ||
| 245 | wire error_ack = (cpx_spc_data_cx2[145:141] == 5'b11100); | |
| 246 | wire load_ack = (cpx_spc_data_cx2[145:141] == 5'b10000); | |
| 247 | wire fill_ack = (cpx_spc_data_cx2[145:141] == 5'b10001); | |
| 248 | wire stor_ack = (cpx_spc_data_cx2[145:141] == 5'b10100); | |
| 249 | wire evict = (cpx_spc_data_cx2[145:141] == 5'b10011); | |
| 250 | ||
| 251 | wire hyperv_console = ((istor_req) & ((spc_pcx_data_pa[103:64] == 40'h1f00000000) | | |
| 252 | (spc_pcx_data_pa[103:64] == 40'hfff0c2c000))); | |
| 253 | ||
| 254 | wire guest0_console = ((istor_req) & (spc_pcx_data_pa[103:64] == 40'h1f10002000)); | |
| 255 | wire guest1_console = ((istor_req) & (spc_pcx_data_pa[103:64] == 40'h1f10004000)); | |
| 256 | wire guest2_console = ((istor_req) & (spc_pcx_data_pa[103:64] == 40'h1f10006000)); | |
| 257 | wire guest3_console = ((istor_req) & (spc_pcx_data_pa[103:64] == 40'h1f10008000)); | |
| 258 | ||
| 259 | wire [3:0] hyp_watch_cntP = ~hyperv_console ? HYP_WATCH_CNT : | |
| 260 | (HYP_WATCH_CNT == 0) ? ((spc_pcx_data_pa[7:0] == 8'h57) ? 8'h01 : 8'h0) : | |
| 261 | (HYP_WATCH_CNT == 1) ? ((spc_pcx_data_pa[7:0] == 8'h41) ? 8'h02 : 8'h0) : | |
| 262 | (HYP_WATCH_CNT == 2) ? ((spc_pcx_data_pa[7:0] == 8'h54) ? 8'h03 : 8'h0) : | |
| 263 | (HYP_WATCH_CNT == 3) ? ((spc_pcx_data_pa[7:0] == 8'h43) ? 8'h04 : 8'h0) : | |
| 264 | (HYP_WATCH_CNT == 4) ? ((spc_pcx_data_pa[7:0] == 8'h48) ? 8'h05 : 8'h0) : | |
| 265 | (HYP_WATCH_CNT == 5) ? ((spc_pcx_data_pa[7:0] == 8'h44) ? 8'h06 : 8'h0) : | |
| 266 | (HYP_WATCH_CNT == 6) ? ((spc_pcx_data_pa[7:0] == 8'h4F) ? 8'h07 : 8'h0) : | |
| 267 | (HYP_WATCH_CNT == 7) ? ((spc_pcx_data_pa[7:0] == 8'h47) ? 8'hff : 8'h0) : 8'h00; | |
| 268 | ||
| 269 | wire [1:0] hyp_watch_iterP = (hyperv_console & (HYP_WATCH_CNT == 8'hff)) ? (HYP_WATCH_ITER + 1) : HYP_WATCH_ITER; | |
| 270 | ||
| 271 | assign watch_dog_finish = (HYP_WATCH_ITER == 2'b11); | |
| 272 | ||
| 273 | always @(posedge clk) begin | |
| 274 | ||
| 275 | WDOG0 <= (reset96) ? 16'h0 : wdog0p; | |
| 276 | WDOG1 <= (reset96) ? 16'h0 : wdog1p; | |
| 277 | WDOG2 <= (reset96) ? 16'h0 : wdog2p; | |
| 278 | WDOG3 <= (reset96) ? 16'h0 : wdog3p; | |
| 279 | WDOG4 <= (reset96) ? 16'h0 : wdog3p; | |
| 280 | WDOG5 <= (reset96) ? 16'h0 : wdog3p; | |
| 281 | WDOG6 <= (reset96) ? 16'h0 : wdog3p; | |
| 282 | WDOG7 <= (reset96) ? 16'h0 : wdog3p; | |
| 283 | ||
| 284 | WDOG_IDLE0 <= (reset96) ? 1'b0 : wdog_idle0p; | |
| 285 | WDOG_IDLE1 <= (reset96) ? 1'b0 : wdog_idle1p; | |
| 286 | WDOG_IDLE2 <= (reset96) ? 1'b0 : wdog_idle2p; | |
| 287 | WDOG_IDLE3 <= (reset96) ? 1'b0 : wdog_idle3p; | |
| 288 | WDOG_IDLE4 <= (reset96) ? 1'b0 : wdog_idle4p; | |
| 289 | WDOG_IDLE5 <= (reset96) ? 1'b0 : wdog_idle5p; | |
| 290 | WDOG_IDLE6 <= (reset96) ? 1'b0 : wdog_idle6p; | |
| 291 | WDOG_IDLE7 <= (reset96) ? 1'b0 : wdog_idle7p; | |
| 292 | ||
| 293 | HYP_WATCH_CNT <= (reset96) ? 4'h0 : hyp_watch_cntP; | |
| 294 | HYP_WATCH_ITER <= (reset96) ? 2'b0 : hyp_watch_iterP; | |
| 295 | ||
| 296 | `ifdef AXIS | |
| 297 | begin | |
| 298 | if ((WDOG0 == 16'b1)) begin // axis tbcall_region | |
| 299 | $display(" WATCH_DOG%h_0 %d",core_id_r, $time); | |
| 300 | end | |
| 301 | if ((WDOG1 == 16'b1)) begin // axis tbcall_region | |
| 302 | $display(" WATCH_DOG%h_1 %d",core_id_r, $time); | |
| 303 | end | |
| 304 | if ((WDOG2 == 16'b1)) begin // axis tbcall_region | |
| 305 | $display(" WATCH_DOG%h_2 %d",core_id_r, $time); | |
| 306 | end | |
| 307 | if ((WDOG3 == 16'b1)) begin // axis tbcall_region | |
| 308 | $display(" WATCH_DOG%h_3 %d",core_id_r, $time); | |
| 309 | end | |
| 310 | if ((WDOG4 == 16'b1)) begin // axis tbcall_region | |
| 311 | $display(" WATCH_DOG%h_4 %d",core_id_r, $time); | |
| 312 | end | |
| 313 | if ((WDOG5 == 16'b1)) begin // axis tbcall_region | |
| 314 | $display(" WATCH_DOG%h_5 %d",core_id_r, $time); | |
| 315 | end | |
| 316 | if ((WDOG6 == 16'b1)) begin // axis tbcall_region | |
| 317 | $display(" WATCH_DOG%h_6 %d",core_id_r, $time); | |
| 318 | end | |
| 319 | if ((WDOG7 == 16'b1)) begin // axis tbcall_region | |
| 320 | $display(" WATCH_DOG%h_7 %d",core_id_r, $time); | |
| 321 | end | |
| 322 | end | |
| 323 | `else | |
| 324 | begin | |
| 325 | if ((wdog0p == 16'b1)) begin | |
| 326 | $display(" WATCH_DOG%h_0 %d",core_id, CLK_CNT); | |
| 327 | end | |
| 328 | if ((wdog1p == 16'b1)) begin | |
| 329 | $display(" WATCH_DOG%h_1 %d",core_id, CLK_CNT); | |
| 330 | end | |
| 331 | if ((wdog2p == 16'b1)) begin | |
| 332 | $display(" WATCH_DOG%h_2 %d",core_id, CLK_CNT); | |
| 333 | end | |
| 334 | if ((wdog3p == 16'b1)) begin | |
| 335 | $display(" WATCH_DOG%h_3 %d",core_id, CLK_CNT); | |
| 336 | end | |
| 337 | end | |
| 338 | `endif | |
| 339 | ||
| 340 | begin | |
| 341 | if (wdog_intv0) begin | |
| 342 | $display(" RESUME%h_0 %h %d",core_id, cpx_spc_data_cx2[17:16], CLK_CNT); | |
| 343 | end | |
| 344 | if (wdog_intv1) begin | |
| 345 | $display(" RESUME%h_1 %h %d",core_id, cpx_spc_data_cx2[17:16], CLK_CNT); | |
| 346 | end | |
| 347 | if (wdog_intv2) begin | |
| 348 | $display(" RESUME%h_2 %h %d",core_id, cpx_spc_data_cx2[17:16], CLK_CNT); | |
| 349 | end | |
| 350 | if (wdog_intv3) begin | |
| 351 | $display(" RESUME%h_3 %h %d",core_id, cpx_spc_data_cx2[17:16], CLK_CNT); | |
| 352 | end | |
| 353 | end | |
| 354 | ||
| 355 | REQ_CY <= (reset96) ? 1'b0 : req_cyP; | |
| 356 | ||
| 357 | REQ_OUTSTANDING0 <= (reset96) ? 2'b00 : req_outstanding0p[1:0]; | |
| 358 | REQ_OUTSTANDING1 <= (reset96) ? 2'b00 : req_outstanding1p[1:0]; | |
| 359 | REQ_OUTSTANDING2 <= (reset96) ? 2'b00 : req_outstanding2p[1:0]; | |
| 360 | REQ_OUTSTANDING3 <= (reset96) ? 2'b00 : req_outstanding3p[1:0]; | |
| 361 | REQ_OUTSTANDING4 <= (reset96) ? 2'b00 : req_outstanding4p[1:0]; | |
| 362 | REQ_OUTSTANDING5 <= (reset96) ? 2'b00 : req_outstanding5p[1:0]; | |
| 363 | REQ_OUTSTANDING6 <= (reset96) ? 2'b00 : req_outstanding6p[1:0]; | |
| 364 | REQ_OUTSTANDING7 <= (reset96) ? 2'b00 : req_outstanding7p[1:0]; | |
| 365 | REQ_OUTSTANDING8 <= (reset96) ? 2'b00 : req_outstanding8p[1:0]; | |
| 366 | ||
| 367 | ERROR_BANK <= (reset96) ? 1'b0 : error_bankP; | |
| 368 | ||
| 369 | core_id_r <= core_id; | |
| 370 | spc_pcx_data_pa_r <= spc_pcx_data_pa; | |
| 371 | cpx_spc_data_cx2_r <= cpx_spc_data_cx2; | |
| 372 | ||
| 373 | begin | |
| 374 | if (ERROR_BANK) | |
| 375 | begin // axis tbcall_region | |
| 376 | $display(" ERROR%h: MORE THAN TWO REQUESTS FROM A CORE TO A BANK ON CYCLE %d",core_id_r, $time); | |
| 377 | end | |
| 378 | end | |
| 379 | ||
| 380 | `ifdef AXIS | |
| 381 | if (istor_req & pcx_cpx_en) | |
| 382 | begin // axis tbcall_region | |
| 383 | $display(" STOR%h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 384 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 385 | end | |
| 386 | if (ifill_req & pcx_cpx_en) | |
| 387 | begin // axis tbcall_region | |
| 388 | $display(" FILL%h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 389 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 390 | end | |
| 391 | if (iload_req & pcx_cpx_en) | |
| 392 | begin // axis tbcall_region | |
| 393 | $display(" LOAD%h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 394 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 395 | end | |
| 396 | if (ilstm_req & pcx_cpx_en) | |
| 397 | begin // axis tbcall_region | |
| 398 | $display(" LSTM%h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 399 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 400 | end | |
| 401 | if (ifprl_req & pcx_cpx_en) | |
| 402 | begin // axis tbcall_region | |
| 403 | $display(" FP %h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 404 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 405 | end | |
| 406 | if (icasa1_req & pcx_cpx_en) | |
| 407 | begin // axis tbcall_region | |
| 408 | $display(" CAS1 %h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 409 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 410 | end | |
| 411 | if (icasa2_req & pcx_cpx_en) | |
| 412 | begin // axis tbcall_region | |
| 413 | $display(" CAS2 %h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], | |
| 414 | $time, spc_pcx_data_pa_r[129:104], spc_pcx_data_pa_r[103:64], spc_pcx_data_pa_r[63:0]); | |
| 415 | end | |
| 416 | if (load_ack & pcx_cpx_en) | |
| 417 | begin // axis tbcall_region | |
| 418 | $display(" LACK%h_%h %d %h_%h_%h", core_id_r, cpx_spc_data_cx2_r[136:134], | |
| 419 | $time, cpx_spc_data_cx2_r[145:128], cpx_spc_data_cx2_r[127:64],cpx_spc_data_cx2_r[63:0]); | |
| 420 | end | |
| 421 | if (fill_ack & pcx_cpx_en) | |
| 422 | begin // axis tbcall_region | |
| 423 | $display(" FACK%h_%h %d %h_%h_%h", core_id_r, cpx_spc_data_cx2_r[136:134], | |
| 424 | $time, cpx_spc_data_cx2_r[145:128], cpx_spc_data_cx2_r[127:64],cpx_spc_data_cx2_r[63:0]); | |
| 425 | end | |
| 426 | if (stor_ack & pcx_cpx_en) | |
| 427 | begin // axis tbcall_region | |
| 428 | $display(" SACK%h_%h %d %h_%h_%h", core_id_r, cpx_spc_data_cx2_r[136:134], | |
| 429 | $time, cpx_spc_data_cx2_r[145:128], cpx_spc_data_cx2_r[127:64],cpx_spc_data_cx2_r[63:0]); | |
| 430 | end | |
| 431 | if (evict & pcx_cpx_en) | |
| 432 | begin // axis tbcall_region | |
| 433 | $display(" EVICT%h_0 %h_1 %h_2 %h_3 %d %h_%h_%h", core_id_r, | |
| 434 | core_id_r, | |
| 435 | core_id_r, | |
| 436 | core_id_r, | |
| 437 | $time, cpx_spc_data_cx2_r[145:128], cpx_spc_data_cx2_r[127:64],cpx_spc_data_cx2_r[63:0]); | |
| 438 | end | |
| 439 | if (error_ack & pcx_cpx_en) | |
| 440 | begin // axis tbcall_region | |
| 441 | $display(" EACK%h %d", core_id_r, $time); | |
| 442 | end | |
| 443 | ||
| 444 | `else | |
| 445 | if (istor_req) $display(" STOR%h_%h %d %h", core_id, spc_pcx_data_pa[119:117], CLK_CNT, spc_pcx_data_pa[123:0]); | |
| 446 | if (ifill_req) $display(" FILL%h_%h %d %h", core_id, spc_pcx_data_pa[119:117], CLK_CNT, spc_pcx_data_pa[123:0]); | |
| 447 | if (iload_req) $display(" LOAD%h_%h %d %h", core_id, spc_pcx_data_pa[119:117], CLK_CNT, spc_pcx_data_pa[123:0]); | |
| 448 | if (ilstm_req) $display(" LSTM%h_%h %d %h", core_id, spc_pcx_data_pa[119:117], CLK_CNT, spc_pcx_data_pa[123:0]); | |
| 449 | if (ifprl_req) $display(" FP %h_%h %d %h", core_id, spc_pcx_data_pa[119:117], CLK_CNT, spc_pcx_data_pa[123:0]); | |
| 450 | ||
| 451 | if (load_ack) $display(" LACK%h_%h %d %h", core_id, cpx_spc_data_cx2[136:134], | |
| 452 | CLK_CNT, cpx_spc_data_cx2[145:0]); | |
| 453 | if (fill_ack) $display(" FACK%h_%h %d %h", core_id, cpx_spc_data_cx2[136:134], | |
| 454 | CLK_CNT, cpx_spc_data_cx2[145:0]); | |
| 455 | if (stor_ack) $display(" SACK%h_%h %d %h", core_id, cpx_spc_data_cx2[136:134], | |
| 456 | CLK_CNT, cpx_spc_data_cx2[145:0]); | |
| 457 | ||
| 458 | if (evict ) $display(" EVICT%h_0 %h_1 %h_2 %h_3 %d %h", core_id, | |
| 459 | core_id, | |
| 460 | core_id, | |
| 461 | core_id, | |
| 462 | CLK_CNT, cpx_spc_data_cx2[145:0]); | |
| 463 | ||
| 464 | if (error_ack) $display(" EACK%h %d", core_id, CLK_CNT); | |
| 465 | `endif | |
| 466 | ||
| 467 | `ifdef AXIS | |
| 468 | // if (REQ_CY & pcx_cpx_short) | |
| 469 | if (REQ_CY & pcx_cpx_short || (REQ_CY & spc_pcx_data_pa[103] & pcx_cpx_io)) | |
| 470 | begin // axis tbcall_region | |
| 471 | $display("PCX%h_%h %d %h_%h_%h", core_id_r, spc_pcx_data_pa_r[119:117], $time, spc_pcx_data_pa_r[129:104], | |
| 472 | spc_pcx_data_pa_r[103:64],spc_pcx_data_pa_r[63:0]); | |
| 473 | end | |
| 474 | ||
| 475 | if (cpx_spc_data_cx2[145] & pcx_cpx_short) | |
| 476 | begin // axis tbcall_region | |
| 477 | $display("CPX%h_%h %d %h_%h_%h", core_id_r, cpx_spc_data_cx2_r[136:134], $time, cpx_spc_data_cx2_r[145:128], | |
| 478 | cpx_spc_data_cx2_r[127:64],cpx_spc_data_cx2_r[63:0]); | |
| 479 | end | |
| 480 | `else | |
| 481 | if (REQ_CY & pcx_cpx_short) | |
| 482 | begin // axis tbcall_region | |
| 483 | $display("PCX%h_%h %d %h_%h_%h", core_id, spc_pcx_data_pa_r[119:117], CLK_CNT, spc_pcx_data_pa[129:104], | |
| 484 | spc_pcx_data_pa[103:64],spc_pcx_data_pa[63:0]); | |
| 485 | end | |
| 486 | ||
| 487 | if (cpx_spc_data_cx2[145] & pcx_cpx_short) | |
| 488 | begin // axis tbcall_region | |
| 489 | $display("CPX%h_%h %d %h_%h_%h", core_id, cpx_spc_data_cx2_r[136:134], CLK_CNT, cpx_spc_data_cx2[145:128], | |
| 490 | cpx_spc_data_cx2[127:64],cpx_spc_data_cx2[63:0]); | |
| 491 | end | |
| 492 | `endif | |
| 493 | ||
| 494 | ||
| 495 | `ifdef AXIS | |
| 496 | begin | |
| 497 | CONSOLE_DATA <= spc_pcx_data_pa[63:0]; | |
| 498 | ||
| 499 | if (hyperv_console) | |
| 500 | begin // axis tbcall_region | |
| 501 | $display("%h HYPERVISOR CONSOLE%h_%h %h",CLK_CNT, core_id_r, | |
| 502 | spc_pcx_data_pa_r[119:117], CONSOLE_DATA[7:0]); | |
| 503 | end | |
| 504 | if (guest0_console) | |
| 505 | begin // axis tbcall_region | |
| 506 | $display("%h GUEST0 CONSOLE%h_%h %h",CLK_CNT,core_id_r, | |
| 507 | spc_pcx_data_pa_r[119:117], CONSOLE_DATA[7:0]); | |
| 508 | end | |
| 509 | if (guest1_console) | |
| 510 | begin // axis tbcall_region | |
| 511 | $display("%h GUEST1 CONSOLE%h_%h %h",CLK_CNT,core_id_r, | |
| 512 | spc_pcx_data_pa_r[119:117], CONSOLE_DATA[7:0]); | |
| 513 | end | |
| 514 | if (guest2_console) | |
| 515 | begin // axis tbcall_region | |
| 516 | $display("%h GUEST2 CONSOLE%h_%h %h",CLK_CNT,core_id_r, | |
| 517 | spc_pcx_data_pa_r[119:117], CONSOLE_DATA[7:0]); | |
| 518 | end | |
| 519 | if (guest3_console) | |
| 520 | begin // axis tbcall_region | |
| 521 | $display("%h GUEST3 CONSOLE%h_%h %h",CLK_CNT,core_id_r, | |
| 522 | spc_pcx_data_pa_r[119:117], CONSOLE_DATA[7:0]); | |
| 523 | end | |
| 524 | end | |
| 525 | `else | |
| 526 | begin | |
| 527 | if (hyperv_console) | |
| 528 | begin // axis tbcall_region | |
| 529 | $display("%h HYPERVISOR CONSOLE%h_0 %h",CLK_CNT,core_id, spc_pcx_data_pa[7:0]); | |
| 530 | end | |
| 531 | end | |
| 532 | `endif | |
| 533 | ||
| 534 | end | |
| 535 | ||
| 536 | ||
| 537 | endmodule | |
| 538 | ||
| 539 | module axis_io_mon ( | |
| 540 | clk, | |
| 541 | reset96, | |
| 542 | io_cpx_data_ca, | |
| 543 | io_cpx_req_cq, | |
| 544 | io_pcx_stall_pq, | |
| 545 | cpx_io_grant_cx, | |
| 546 | ||
| 547 | CLK_CNT, | |
| 548 | core_mask, | |
| 549 | core_id, | |
| 550 | en_status, | |
| 551 | pcx_cpx_en, | |
| 552 | pcx_cpx_short, | |
| 553 | pcx_cpx_io, | |
| 554 | watch_dog_finish | |
| 555 | ); | |
| 556 | ||
| 557 | ||
| 558 | input clk; | |
| 559 | input reset96; | |
| 560 | input [145:0] io_cpx_data_ca; | |
| 561 | input [7:0] io_cpx_req_cq; | |
| 562 | input io_pcx_stall_pq; | |
| 563 | input [7:0] cpx_io_grant_cx; | |
| 564 | input [ 39:0] CLK_CNT; | |
| 565 | input [ 7:0] core_mask; | |
| 566 | input [ 2:0] core_id; | |
| 567 | input en_status; | |
| 568 | input pcx_cpx_en; | |
| 569 | input pcx_cpx_short; | |
| 570 | input pcx_cpx_io; | |
| 571 | ||
| 572 | output watch_dog_finish; | |
| 573 | ||
| 574 | reg [7:0] io_cpx_req_cq_r; | |
| 575 | reg [145:0] io_cpx_data_ca_r; | |
| 576 | reg [7:0] io_cpx_req_cq_r1; | |
| 577 | reg [145:0] io_cpx_data_ca_r1; | |
| 578 | ||
| 579 | always @(posedge clk) begin | |
| 580 | io_cpx_req_cq_r <= io_cpx_req_cq; | |
| 581 | io_cpx_data_ca_r <= io_cpx_data_ca; | |
| 582 | ||
| 583 | if (|io_cpx_req_cq_r1 & pcx_cpx_io) | |
| 584 | begin // axis tbcall_region | |
| 585 | $display("IOX%h_%h %d %h_%h_%h", io_cpx_req_cq_r,io_cpx_data_ca_r[136:134], $time, io_cpx_data_ca_r[145:128], | |
| 586 | io_cpx_data_ca_r[127:64],io_cpx_data_ca_r[63:0]); | |
| 587 | end | |
| 588 | end | |
| 589 | always @(negedge clk) begin | |
| 590 | io_cpx_req_cq_r1 <= io_cpx_req_cq_r; | |
| 591 | end | |
| 592 | endmodule | |
| 593 |