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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: axis_modules.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `ifdef AXIS_TL | |
36 | //---------------------------------------------------------- | |
37 | //---------------------------------------------------------- | |
38 | `timescale 1ps/1ps | |
39 | module axis_clock_gen(sclkdiv2,sclk,sysclk); | |
40 | output sclkdiv2; | |
41 | output sclk; | |
42 | output sysclk; | |
43 | ||
44 | `ifdef AXIS_FBDIMM_NO_FSR | |
45 | `ifndef RESET_AXIS_ONLY | |
46 | assign sclkdiv2 = 0; | |
47 | `else | |
48 | assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk44; | |
49 | `endif | |
50 | `else | |
51 | `ifdef FAST_AXIS | |
52 | assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.clk44; | |
53 | `else | |
54 | assign sclkdiv2 = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk44; | |
55 | `endif | |
56 | `endif | |
57 | `ifdef FAST_AXIS | |
58 | assign sysclk=tb_top.cpu.ccu.ccu_pll.clk2424; | |
59 | `else | |
60 | assign sysclk=tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk2424; | |
61 | `endif | |
62 | `ifdef AXIS_TL | |
63 | `ifdef AXIS_FBDIMM_NO_FSR | |
64 | `ifdef FAST_AXIS | |
65 | assign sclk = tb_top.cpu.ccu.ccu_pll.clk33; | |
66 | `else | |
67 | assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk33; | |
68 | `endif | |
69 | `else | |
70 | `ifdef FAST_AXIS | |
71 | assign sclk = tb_top.cpu.ccu.ccu_pll.clk11; | |
72 | `else | |
73 | assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk11; | |
74 | `endif | |
75 | `endif | |
76 | `else | |
77 | `ifdef FAST_AXIS | |
78 | assign sclk = tb_top.cpu.ccu.ccu_pll.clk2424; | |
79 | `else | |
80 | assign sclk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk2424; | |
81 | `endif | |
82 | `endif | |
83 | ||
84 | endmodule | |
85 | ||
86 | module axis_clock_force (mac_clk,peu_clk); | |
87 | input mac_clk; | |
88 | input peu_clk; | |
89 | ||
90 | assign tb_top.cpu.psr_peu_txbclk0 = peu_clk; //ref clk to PEU | |
91 | assign tb_top.cpu.mac.esr_mac_tclk_0 = mac_clk; //ref clk inputs to xMAC | |
92 | assign tb_top.cpu.mac.esr_mac_tclk_1 = mac_clk; | |
93 | assign tb_top.cpu.mac.esr_mac_rclk_0[3] = mac_clk; //ref clk inputs to xMAC | |
94 | assign tb_top.cpu.mac.esr_mac_rclk_0[2] = mac_clk; // req'd for xPCS loopback | |
95 | assign tb_top.cpu.mac.esr_mac_rclk_0[1] = mac_clk; | |
96 | assign tb_top.cpu.mac.esr_mac_rclk_0[0] = mac_clk; | |
97 | assign tb_top.cpu.mac.esr_mac_rclk_1[3] = mac_clk; | |
98 | assign tb_top.cpu.mac.esr_mac_rclk_1[2] = mac_clk; | |
99 | assign tb_top.cpu.mac.esr_mac_rclk_1[1] = mac_clk; | |
100 | assign tb_top.cpu.mac.esr_mac_rclk_1[0] = mac_clk; | |
101 | ||
102 | endmodule | |
103 | ||
104 | module axis_clock_generator (sclk,fbclk,sysclk); | |
105 | ||
106 | output sclk; | |
107 | output fbclk; | |
108 | output sysclk; | |
109 | wire mac_clk,peu_clk; | |
110 | `ifdef FAST_AXIS | |
111 | assign mac_clk = tb_top.cpu.ccu.ccu_pll.n2_core_pll_cust.mac_clk_1; | |
112 | assign peu_clk = tb_top.cpu.ccu.ccu_pll.n2_core_pll_cust.peu_clk_1; | |
113 | `else | |
114 | assign mac_clk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.mac_clk_1; | |
115 | assign peu_clk = tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.peu_clk_1; | |
116 | `endif | |
117 | //assign sclk;=axis_clock_gen.sclk; | |
118 | //assign fbclk;=axis_clock_gen.sclkdiv2; | |
119 | //assign sysclk; //=axis_clock_gen.sysclk; | |
120 | ||
121 | axis_clock_force axis_clock_force (mac_clk,peu_clk); | |
122 | ||
123 | axis_clock_gen axis_clock_gen (fbclk,sclk,sysclk); | |
124 | endmodule | |
125 | `endif | |
126 | ||
127 | module dbuff_pc ( | |
128 | cycle,pc,clk,core,thread | |
129 | ); | |
130 | ||
131 | ||
132 | input [63:0] cycle; | |
133 | input [63:0] pc; | |
134 | input clk; | |
135 | input [2:0] core; | |
136 | input [2:0] thread; | |
137 | ||
138 | ||
139 | `ifdef AXIS_TL | |
140 | reg [63:0] last_pc; | |
141 | reg [111:0] pc_r; | |
142 | reg [17:0] addr; | |
143 | reg we; | |
144 | reg [63:0] inact_cnt; | |
145 | reg [63:0] ptr_0_cycle; | |
146 | reg [2:0] core_r; | |
147 | reg [2:0] thread_r; | |
148 | reg [63:0] cycle_r; | |
149 | ||
150 | ||
151 | wire [17:0] a_adr0 = addr; | |
152 | wire [111:0] a_data0=pc_r; | |
153 | wire a_we=we; | |
154 | wire [7:0] status; | |
155 | ||
156 | `ifdef PALLADIUM | |
157 | // INTERNAL ERROR | |
158 | // | |
159 | reg [112:0] DBUFF [0:262143]; | |
160 | // always @ (a_adr0 or a_data0 or a_we) | |
161 | // begin | |
162 | // if(a_we) | |
163 | // DBUFF[a_adr0] <= a_data0 ; | |
164 | // end | |
165 | // | |
166 | `else // !`ifdef PALLADIUM | |
167 | ||
168 | axis_smem #(18, 112, 1, 0) DBUFF | |
169 | ( | |
170 | {112'bz }, // Data Out | |
171 | {a_data0 }, // Data In | |
172 | {a_adr0 }, // Address | |
173 | {a_we }, // Write Enable : 1'b0 means always read | |
174 | {1'b1 }, // Chip Enable | |
175 | {1'bz }, // Clocks : 1'bz means asynchronous | |
176 | {112'bz } // Mask | |
177 | ); | |
178 | initial addr=18'b0; | |
179 | initial last_pc=48'b0; | |
180 | initial we=1'b0; | |
181 | initial inact_cnt = 64'b1; | |
182 | ||
183 | always @(posedge clk) begin | |
184 | pc_r <= {cycle[63:0],pc[47:0]}; | |
185 | core_r <= core; | |
186 | cycle_r <= cycle; | |
187 | thread_r <= thread; | |
188 | if (pc[47:0] != last_pc[47:0]) begin | |
189 | inact_cnt <= 64'b0; | |
190 | if (!tb_top.pc_trc_mode || (pc[47:0] != last_pc[47:0]+4)) begin | |
191 | last_pc<= pc; | |
192 | addr<=addr+18'b1; | |
193 | we<=1'b1; | |
194 | if (addr == 0) ptr_0_cycle <= cycle; | |
195 | end | |
196 | end else begin | |
197 | we<=1'b0; | |
198 | if ((pc[47:0] != 0) && (pc[47:44] != 4'hf)) inact_cnt <= inact_cnt + 1; | |
199 | end | |
200 | if (inact_cnt == tb_top.thread_wdto) begin // axis tbcall_region | |
201 | $display("INACT%h_%h at cycle %d, t=%d.",core_r,thread_r,cycle_r,$time); | |
202 | if(tb_top.stop_on_wdto) begin | |
203 | axis_top.task_dump_mem; | |
204 | axis_top.task_rcc_off; | |
205 | end | |
206 | end | |
207 | end | |
208 | `endif // !PALLADIUM | |
209 | `endif //AXIS_TL | |
210 | ||
211 | endmodule | |
212 | ||
213 | `ifdef AXIS_TL_ICE | |
214 | `timescale 1ps/1ps | |
215 | module jtag_ice (tms,tdi,tdo,tck,tck_fb); | |
216 | input tdo; | |
217 | input tck_fb; | |
218 | output tms; | |
219 | output tdi; | |
220 | output tck; | |
221 | ||
222 | wire tdo_to_asl; | |
223 | wire tck_fb_to_asl; | |
224 | wire tdi_from_asl; | |
225 | wire tms_from_asl; | |
226 | wire tck_from_asl; | |
227 | ||
228 | ||
229 | reg tms_r,tdi_r,tdo_r,tck_r,tck_r2, tck_r3,tck_r_r; | |
230 | assign tdo_to_asl=tdo; | |
231 | assign tck_fb_to_asl=tck_fb; | |
232 | wire tdi_i=tdi_from_asl; | |
233 | wire tms_i=tms_from_asl; | |
234 | wire tck_i=tck_from_asl; | |
235 | assign tdi=tdi_r; | |
236 | assign tms=tms_r; | |
237 | assign tck=tck_r_r; | |
238 | reg dbg,dbg1; | |
239 | initial dbg=0; | |
240 | ||
241 | `ifndef PALLADIUM | |
242 | `ifdef FAST_AXIS | |
243 | always @(posedge tb_top.cpu.ccu.ccu_pll.clk22) begin | |
244 | `else | |
245 | always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22) begin | |
246 | `endif | |
247 | tms_r=tms_i; | |
248 | tdi_r=tdi_i; | |
249 | tdo_r=tdo; | |
250 | tck_r_r=tck_r3; | |
251 | tck_r3=tck_r2; | |
252 | tck_r2=tck_r; | |
253 | tck_r=tck_i; | |
254 | end | |
255 | always @(posedge tck_r_r) | |
256 | if (dbg & (tms_r | tdi_r | tck_r | tdo_r)) | |
257 | begin // axis tbcall_region | |
258 | $display($time,"dbg:tms,tdi,tck,tdo %b %b %b %b",tms_r,tdi_r,tck_r,tdo_r); | |
259 | end | |
260 | `endif // !PALLADIUM | |
261 | ||
262 | reg tms_r1,tdi_r1,tdo_r1,tck_r1; | |
263 | ||
264 | `ifndef PALLADIUM | |
265 | initial dbg1=0; | |
266 | `ifdef FAST_AXIS | |
267 | always @(posedge tb_top.cpu.ccu.ccu_pll.clk22) begin | |
268 | `else | |
269 | always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22) begin | |
270 | `endif | |
271 | tms_r1=tms; | |
272 | tdi_r1=tdi; | |
273 | tdo_r1=tdo; | |
274 | tck_r1=tck; | |
275 | end | |
276 | always @(tms_r1 or tdi_r1 or tck_r1 or tdo_r1) | |
277 | if (dbg1) | |
278 | begin // axis tbcall_region | |
279 | $display($time,"dbg1: tms,tdi,tck,tdo %b %b %b %b",tms_r1,tdi_r1,tck_r1,tdo_r1); | |
280 | end | |
281 | `endif // !PALLADIUM | |
282 | ||
283 | wire tck_fb_to_asl_a=tck_fb_to_asl; | |
284 | wire tck_fb_to_asl_b=tck_fb_to_asl; | |
285 | ||
286 | `ifndef PALLADIUM | |
287 | axis_asl_use (tdo_to_asl,"d",11,"js1",88); | |
288 | axis_asl_use (tck_fb_to_asl,"d",11,"js1",89); | |
289 | axis_asl_use (tck_fb_to_asl_a,"d",11,"js1",93); | |
290 | axis_asl_use (tck_fb_to_asl_b,"d",11,"js1",97); | |
291 | axis_asl_drive (tms_from_asl,"d",11,"js1",138); | |
292 | axis_asl_drive (tdi_from_asl,"d",11,"js1",96); | |
293 | axis_asl_drive (tck_from_asl,"c",11,"js1",92); | |
294 | `endif // !PALLADIUM | |
295 | endmodule | |
296 | `endif | |
297 | ||
298 | `timescale 1ps/1ps | |
299 | module axis_mcu_errmon (clk, | |
300 | rdpctl_meu_error, | |
301 | rdpctl_mec_error, | |
302 | rdpctl_dac_error, | |
303 | rdpctl_dau_error, | |
304 | rdpctl_dsc_error, | |
305 | rdpctl_dsu_error, | |
306 | rdpctl_dbu_error, | |
307 | rdpctl_meb_error, | |
308 | rdpctl_fbu_error, | |
309 | rdpctl_fbr_error | |
310 | ); | |
311 | parameter INST = 0; // Instance of MCU | |
312 | ||
313 | input clk; | |
314 | input rdpctl_meu_error; | |
315 | input rdpctl_mec_error; | |
316 | input rdpctl_dac_error; | |
317 | input rdpctl_dau_error; | |
318 | input rdpctl_dsc_error; | |
319 | input rdpctl_dsu_error; | |
320 | input rdpctl_dbu_error; | |
321 | input rdpctl_meb_error; | |
322 | input rdpctl_fbu_error; | |
323 | input rdpctl_fbr_error; | |
324 | ||
325 | wire [31:0] rdpctl_err_sts_next; | |
326 | reg [31:0] rdpctl_err_sts_reg; | |
327 | ||
328 | assign rdpctl_err_sts_next[25:16] = {rdpctl_meu_error, rdpctl_mec_error, rdpctl_dac_error, rdpctl_dau_error, | |
329 | rdpctl_dsc_error, rdpctl_dsu_error, rdpctl_dbu_error, rdpctl_meb_error, | |
330 | rdpctl_fbu_error, rdpctl_fbr_error}; | |
331 | ||
332 | initial begin | |
333 | rdpctl_err_sts_reg = 0; | |
334 | end | |
335 | ||
336 | // always @(posedge clk) begin | |
337 | always @(rdpctl_err_sts_next) begin | |
338 | if(rdpctl_err_sts_reg != rdpctl_err_sts_next) begin // axis tbcall_region | |
339 | $display("%d mcu%d rdpctl_err_sts_next <= %08X", $time, INST, rdpctl_err_sts_next); | |
340 | end | |
341 | ||
342 | rdpctl_err_sts_reg <= rdpctl_err_sts_next; | |
343 | end | |
344 | endmodule // axis_mcu_errmon |