[OpenSPARC-T2-DV] / verif / env / fc / axis_siu_mon.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: axis_siu_mon.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
  module axis_siu_mon (
		       clk,
		       reset,

	               niu_sii_hdr_vld,
 	               niu_sii_reqbypass,
 	               niu_sii_datareq,
                       niu_sii_data,
 	               niu_sii_parity,
 	               sii_niu_oqdq,
	               sii_niu_bqdq,

                       niu_sio_dq,
	               sio_niu_hdr_vld,
 	               sio_niu_datareq,
                       sio_niu_data,
                       sio_niu_parity,

                       dmu_sii_hdr_vld,
 	               dmu_sii_reqbypass,
 	               dmu_sii_datareq,
 	               dmu_sii_datareq16,
                       dmu_sii_data,
 	               dmu_sii_parity,
  	               dmu_sii_be_parity,
                       dmu_sii_be,
                       sii_dmu_wrack_vld,
                       sii_dmu_wrack_tag,
	               sii_dmu_wrack_parity,

	               sio_dmu_hdr_vld,
                       sio_dmu_data,
                       sio_dmu_parity
		       );

   input              clk;
   input              reset;
              
   // ================== NIU  =================
   // SII
   input 	 niu_sii_hdr_vld;   // PINDEF:BOT  // Ethernet requesting to send packet to SII
   input 	 niu_sii_reqbypass; // PINDEF:BOT  // Ethernet requesting to send packet to bypass queue of SII
   input 	 niu_sii_datareq;   // PINDEF:BOT  // Ethernet requesting to send packet w/data to SII
   input [127:0] niu_sii_data;	    // PINDEF:BOT  // Packet from Ethernet to SII
   input [7:0] 	 niu_sii_parity;    // PINDEF:BOT  // Packet parity from Ethernet to SII
   input 	 sii_niu_oqdq;      // PINDEF:BOT  // Asserted when SII dqs an NIU entry from Ordered Queue
   input 	 sii_niu_bqdq;      // PINDEF:BOT  // Asserted when SII dqs an NIU entry from Bypass Queue 		

   // SIO
   input        niu_sio_dq;             //PINDEF:BOT  // flow control or credit return signal from NIU to SIO
   input 	sio_niu_hdr_vld;	//PINDEF:BOT  // SIO requesting to send packet to Ethernet
   input 	sio_niu_datareq;	//PINDEF:BOT  // Valid during header phase only - 1=current request is a read data return
   input [127:0] sio_niu_data;		//PINDEF:BOT  // Packet from SIO to Ethernet
   input [7:0]   sio_niu_parity;	//PINDEF:BOT  // Packet parity from SIO to Ethernet
   // ================== NIU  =================
 
   // ================== DMU  =================
   // SII
   input 	 dmu_sii_hdr_vld;   // PINDEF:BOT  // DMU requesting to send packet to SII
   input 	 dmu_sii_reqbypass; // PINDEF:BOT  // DMU requesting to send packet to bypass queue of SII
   input 	 dmu_sii_datareq;   // PINDEF:BOT  // DMU requesting to send packet w/data to SII
   input 	 dmu_sii_datareq16; // PINDEF:BOT  // DMU requesting to send packet w/16B only
   input [127:0] dmu_sii_data;	    // PINDEF:BOT  // Packet from DMU to SII
   input [7:0] 	 dmu_sii_parity;    // PINDEF:BOT  // Packet parity from DMU to SII
   input  	 dmu_sii_be_parity; // PINDEF:BOT  // Packet parity from DMU to SII
   input [15:0]  dmu_sii_be;	    // PINDEF:BOT  // Packet byte enables from DMU to SII
   input        sii_dmu_wrack_vld;
   input[3:0]   sii_dmu_wrack_tag;
   input	 sii_dmu_wrack_parity;


   // SIO
   input 	  sio_dmu_hdr_vld;	//PINDEF:BOT  // SIO requesting to send DMA/Fl/Int packet to DMU
   input [127:0] sio_dmu_data;		//PINDEF:BOT  // Packet from SIO to DMU
   input [7:0]   sio_dmu_parity;	//PINDEF:BOT  // Packet parity from SIO to DMU
   // ================== DMU  =================

   // ================== NIU  =================
   // SII
   reg         niu_sii_hdr_vld_r;   // PINDEF:BOT  // Ethernet requesting to send packet to SII
   reg         niu_sii_reqbypass_r; // PINDEF:BOT  // Ethernet requesting to send packet to bypass queue of SII
   reg         niu_sii_datareq_r;   // PINDEF:BOT  // Ethernet requesting to send packet w/data to SII
   reg [127:0] niu_sii_data_r;	    // PINDEF:BOT  // Packet from Ethernet to SII
   reg [7:0]   niu_sii_parity_r;    // PINDEF:BOT  // Packet parity from Ethernet to SII
   reg         sii_niu_oqdq_r;      // PINDEF:BOT  // Asserted when SII dqs an NIU entry from Ordered Queue
   reg         sii_niu_bqdq_r;      // PINDEF:BOT  // Asserted when SII dqs an NIU entry from Bypass Queue 		
   
   // SIO
   reg         niu_sio_dq_r;             //PINDEF:BOT  // flow control or credit return signal from NIU to SIO
   reg         sio_niu_hdr_vld_r;	//PINDEF:BOT  // SIO requesting to send packet to Ethernet
   reg         sio_niu_datareq_r;	//PINDEF:BOT  // Valid during header phase only - 1=current request is a read data return
   reg [127:0] sio_niu_data_r;		//PINDEF:BOT  // Packet from SIO to Ethernet
   reg [7:0]   sio_niu_parity_r;	//PINDEF:BOT  // Packet parity from SIO to Ethernet
   // ================== NIU  =================
 
   // ================== DMU  =================
   // SII
   reg         dmu_sii_hdr_vld_r;   // PINDEF:BOT  // DMU requesting to send packet to SII
   reg         dmu_sii_reqbypass_r; // PINDEF:BOT  // DMU requesting to send packet to bypass queue of SII
   reg         dmu_sii_datareq_r;   // PINDEF:BOT  // DMU requesting to send packet w/data to SII
   reg         dmu_sii_datareq16_r; // PINDEF:BOT  // DMU requesting to send packet w/16B only
   reg [127:0] dmu_sii_data_r;	    // PINDEF:BOT  // Packet from DMU to SII
   reg [7:0]   dmu_sii_parity_r;    // PINDEF:BOT  // Packet parity from DMU to SII
   reg         dmu_sii_be_parity_r; // PINDEF:BOT  // Packet parity from DMU to SII
   reg [15:0]  dmu_sii_be_r;	    // PINDEF:BOT  // Packet byte enables from DMU to SII
   reg         sii_dmu_wrack_vld_r;
   reg [3:0]   sii_dmu_wrack_tag_r;
   reg         sii_dmu_wrack_parity_r;
   
   // SIO
   reg         sio_dmu_hdr_vld_r;	//PINDEF:BOT  // SIO requesting to send DMA/Fl/Int packet to DMU
   reg [127:0] sio_dmu_data_r;		//PINDEF:BOT  // Packet from SIO to DMU
   reg [7:0]   sio_dmu_parity_r;	//PINDEF:BOT  // Packet parity from SIO to DMU
   // ================== DMU  =================

   // ================== TCU  =================
   // SII
   reg         tcu_sii_vld_r;
   // SIO
   reg         sio_tcu_vld_r;    // assert for jtag read return valid

   // Count data cycles on interface after header cycle
   reg [2:0]   dmu_sii_cntr_r;
   reg [2:0]   niu_sii_cntr_r;
   reg [2:0]   dmu_sio_cntr_r;
   reg [2:0]   niu_sio_cntr_r;
   reg [8:0]   tcu_sii_cntr_r;
   reg [8:0]   tcu_sio_cntr_r;

   wire [2:0]  dmu_sii_cntr;
   wire [2:0]  niu_sii_cntr;
   wire [2:0]  dmu_sio_cntr;
   wire [2:0]  niu_sio_cntr;
   wire [8:0]  tcu_sii_cntr;
   wire [8:0]  tcu_sio_cntr;
   
   // The SIU interfaces for the DMU & NIU are not identical so
   // the logic below is not quite symetrical.
   assign dmu_sii_cntr = (reset) ? 0 :  // Reset to 0
          (dmu_sii_hdr_vld_r && dmu_sii_datareq_r && dmu_sii_datareq16_r) ? 0 : // No data case?
          (dmu_sii_hdr_vld_r && dmu_sii_datareq16_r) ? 1 : // Single xfer cycle
          (dmu_sii_hdr_vld_r && dmu_sii_datareq_r) ? 4 : // Four xfer cycles
          (|dmu_sii_cntr_r) ? (dmu_sii_cntr_r - 1) : // Decrement counter when non-zero
          dmu_sii_cntr_r; // Hold otherwise

   assign niu_sii_cntr = (reset) ? 0 :  // Reset to 0
          (niu_sii_hdr_vld_r && niu_sii_datareq_r) ? 4 : // Four xfer cycle
          (|niu_sii_cntr_r) ? (niu_sii_cntr_r - 1) : // Decrement counter when non-zero
          niu_sii_cntr_r; // Hold otherwise

   assign tcu_sii_cntr = (reset) ? 0 :  // Reset to 0
          (tcu_sii_vld_r) ? 129 : // 128 cycles to shift, one to sample
          (|tcu_sii_cntr_r) ? (tcu_sii_cntr_r - 1) : // Decrement counter when non-zero
          tcu_sii_cntr_r; // Hold otherwise

   assign dmu_sio_cntr = (reset) ? 0 :  // Reset to 0
          (sio_dmu_hdr_vld_r) ? 4 : // Four xfer cycles
          (|dmu_sio_cntr_r) ? (dmu_sio_cntr_r - 1) : // Decrement counter when non-zero
          dmu_sio_cntr_r; // Hold otherwise

   assign niu_sio_cntr = (reset) ? 0 :  // Reset to 0
          (sio_niu_hdr_vld_r && sio_niu_datareq_r) ? 4 : // Four xfer cycle
          (|niu_sio_cntr_r) ? (niu_sio_cntr_r - 1) : // Decrement counter when non-zero
          niu_sio_cntr_r; // Hold otherwise

   assign tcu_sio_cntr = (reset) ? 0 :  // Reset to 0
          (sio_tcu_vld_r) ? 65  : // 64 cycles to assemble data, one to strobe out
          (|tcu_sio_cntr_r) ? (tcu_sio_cntr_r - 1) : // Decrement counter when non-zero
          tcu_sio_cntr_r; // Hold at 0 otherwise

always @(posedge clk) begin
   // Register all inputs, even ones I don't use, may
   // want them some day.
   niu_sii_hdr_vld_r <= (reset) ? 0 : niu_sii_hdr_vld;
   niu_sii_reqbypass_r <= (reset) ? 0 : niu_sii_reqbypass;
   niu_sii_datareq_r <= (reset) ? 0 : niu_sii_datareq;
   niu_sii_data_r <= (reset) ? 0 : niu_sii_data;
   niu_sii_parity_r <= (reset) ? 0 : niu_sii_parity;
   sii_niu_oqdq_r <= (reset) ? 0 : sii_niu_oqdq;
   sii_niu_bqdq_r <= (reset) ? 0 : sii_niu_bqdq;

   niu_sio_dq_r <= (reset) ? 0 : niu_sio_dq;
   sio_niu_hdr_vld_r <= (reset) ? 0 : sio_niu_hdr_vld;
   sio_niu_datareq_r <= (reset) ? 0 : sio_niu_datareq;
   sio_niu_data_r <= (reset) ? 0 : sio_niu_data;
   sio_niu_parity_r <= (reset) ? 0 : sio_niu_parity;
   dmu_sii_hdr_vld_r <= (reset) ? 0 : dmu_sii_hdr_vld;
   dmu_sii_reqbypass_r <= (reset) ? 0 : dmu_sii_reqbypass;
   dmu_sii_datareq_r <= (reset) ? 0 : dmu_sii_datareq;
   dmu_sii_datareq16_r <= (reset) ? 0 : dmu_sii_datareq16;
   dmu_sii_data_r <= (reset) ? 0 : dmu_sii_data;
   dmu_sii_parity_r <= (reset) ? 0 : dmu_sii_parity;
   dmu_sii_be_parity_r <= (reset) ? 0 : dmu_sii_be_parity;
   dmu_sii_be_r <= (reset) ? 0 : dmu_sii_be;
   sii_dmu_wrack_vld_r <= (reset) ? 0 : sii_dmu_wrack_vld;
   sii_dmu_wrack_tag_r <= (reset) ? 0 : sii_dmu_wrack_tag;
   sii_dmu_wrack_parity_r <= (reset) ? 0 : sii_dmu_wrack_parity;
   
   sio_dmu_hdr_vld_r <= (reset) ? 0 : sio_dmu_hdr_vld;
   sio_dmu_data_r <= (reset) ? 0 : sio_dmu_data;
   sio_dmu_parity_r <= (reset) ? 0 : sio_dmu_parity;

   niu_sii_cntr_r <= niu_sii_cntr;
   dmu_sii_cntr_r <= dmu_sii_cntr;
   niu_sio_cntr_r <= niu_sio_cntr;
   dmu_sio_cntr_r <= dmu_sio_cntr;

   tcu_sii_vld_r <= `CPU.tcu_sii_vld;
   sio_tcu_vld_r <= `CPU.sio_tcu_vld;


end // always @ (posedge clk)
   
always @(posedge clk) begin
   // Input, AKA DMA Writes
   if(`TOP.info && dmu_sii_hdr_vld) begin // axis tbcall_region
      $display("%d dmu_sii_hdr  %08x-%08x-%08x-%08x  Byp %x",
               $time,
               dmu_sii_data_r[127:96],dmu_sii_data_r[95:64],
               dmu_sii_data_r[63:32],dmu_sii_data_r[31:0], dmu_sii_reqbypass_r);
   end
   if(`TOP.info && |dmu_sii_cntr) begin // axis tbcall_region
      $display("%d dmu_sii_data %08x-%08x-%08x-%08x  BE %02x",
               $time,
               dmu_sii_data_r[127:96],dmu_sii_data_r[95:64],
               dmu_sii_data_r[63:32],dmu_sii_data_r[31:0], dmu_sii_be_r);
   end

   if(`TOP.info && niu_sii_hdr_vld) begin // axis tbcall_region
      $display("%d niu_sii_hdr  %08x-%08x-%08x-%08x  Byp %x",
               $time,
               niu_sii_data_r[127:96],niu_sii_data_r[95:64],
               niu_sii_data_r[63:32],niu_sii_data_r[31:0], niu_sii_reqbypass_r);
   end
   if(`TOP.info && |niu_sii_cntr) begin // axis tbcall_region
      $display("%d niu_sii_data %08x-%08x-%08x-%08x",
               $time,
               niu_sii_data_r[127:96],niu_sii_data_r[95:64],
               niu_sii_data_r[63:32],niu_sii_data_r[31:0]);
   end
   if(`TOP.info && (tcu_sii_cntr == 1)) begin // axis tbcall_region
      $display("%d tcu_sii_data %08x-%08x-%08x-%08x",
               $time,
               `TOP.cpu.sii.ipcc.tcu_serial_data_l[127:96],
               `TOP.cpu.sii.ipcc.tcu_serial_data_l[95:64],
               `TOP.cpu.sii.ipcc.tcu_serial_data_l[63:32],
               `TOP.cpu.sii.ipcc.tcu_serial_data_l[31:0]);
   end

   // Output, AKA DMA Reads
   if(`TOP.info && sio_dmu_hdr_vld) begin // axis tbcall_region
      $display("%d sio_dmu_hdr  %08x-%08x-%08x-%08x",
               $time,
               sio_dmu_data_r[127:96],sio_dmu_data_r[95:64],
               sio_dmu_data_r[63:32],sio_dmu_data_r[31:0]);
   end
   if(`TOP.info && |dmu_sio_cntr) begin // axis tbcall_region
      $display("%d sio_dmu_data %08x-%08x-%08x-%08x",
               $time,
               sio_dmu_data_r[127:96],sio_dmu_data_r[95:64],
               sio_dmu_data_r[63:32],sio_dmu_data_r[31:0]);
   end

   if(`TOP.info && sio_niu_hdr_vld) begin // axis tbcall_region
      $display("%d sio_niu_hdr  %08x-%08x-%08x-%08x",
               $time,
               sio_niu_data_r[127:96],sio_niu_data_r[95:64],
               sio_niu_data_r[63:32],sio_niu_data_r[31:0]);
   end
   if(`TOP.info && |niu_sio_cntr) begin // axis tbcall_region
      $display("%d sio_niu_data %08x-%08x-%08x-%08x",
               $time,
               sio_niu_data_r[127:96],sio_niu_data_r[95:64],
               sio_niu_data_r[63:32],sio_niu_data_r[31:0]);
   end
   if(`TOP.info && (tcu_sio_cntr == 1)) begin // axis tbcall_region
      $display("%d sio_tcu_data %08x-%08x",
               $time,
               `TOP.cpu.tcu.regs_ctl.next_l2data_reg[63:32],
               `TOP.cpu.tcu.regs_ctl.next_l2data_reg[31:0]);
   end
   
end // always @ (posedge clk)

endmodule // axis_siu_mon
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: axis_siu_mon.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module axis_siu_mon (
	36	clk,
	37	reset,
	38
	39	niu_sii_hdr_vld,
	40	niu_sii_reqbypass,
	41	niu_sii_datareq,
	42	niu_sii_data,
	43	niu_sii_parity,
	44	sii_niu_oqdq,
	45	sii_niu_bqdq,
	46
	47	niu_sio_dq,
	48	sio_niu_hdr_vld,
	49	sio_niu_datareq,
	50	sio_niu_data,
	51	sio_niu_parity,
	52
	53	dmu_sii_hdr_vld,
	54	dmu_sii_reqbypass,
	55	dmu_sii_datareq,
	56	dmu_sii_datareq16,
	57	dmu_sii_data,
	58	dmu_sii_parity,
	59	dmu_sii_be_parity,
	60	dmu_sii_be,
	61	sii_dmu_wrack_vld,
	62	sii_dmu_wrack_tag,
	63	sii_dmu_wrack_parity,
	64
65	sio_dmu_hdr_vld,
66	sio_dmu_data,
67	sio_dmu_parity
68	);
69
70	input clk;
71	input reset;
72
73	// ================== NIU =================
74	// SII
75	input niu_sii_hdr_vld; // PINDEF:BOT // Ethernet requesting to send packet to SII
76	input niu_sii_reqbypass; // PINDEF:BOT // Ethernet requesting to send packet to bypass queue of SII
77	input niu_sii_datareq; // PINDEF:BOT // Ethernet requesting to send packet w/data to SII
78	input [127:0] niu_sii_data; // PINDEF:BOT // Packet from Ethernet to SII
79	input [7:0] niu_sii_parity; // PINDEF:BOT // Packet parity from Ethernet to SII
80	input sii_niu_oqdq; // PINDEF:BOT // Asserted when SII dqs an NIU entry from Ordered Queue
81	input sii_niu_bqdq; // PINDEF:BOT // Asserted when SII dqs an NIU entry from Bypass Queue
82
83	// SIO
84	input niu_sio_dq; //PINDEF:BOT // flow control or credit return signal from NIU to SIO
85	input sio_niu_hdr_vld; //PINDEF:BOT // SIO requesting to send packet to Ethernet
86	input sio_niu_datareq; //PINDEF:BOT // Valid during header phase only - 1=current request is a read data return
87	input [127:0] sio_niu_data; //PINDEF:BOT // Packet from SIO to Ethernet
88	input [7:0] sio_niu_parity; //PINDEF:BOT // Packet parity from SIO to Ethernet
89	// ================== NIU =================
90
91	// ================== DMU =================
92	// SII
93	input dmu_sii_hdr_vld; // PINDEF:BOT // DMU requesting to send packet to SII
94	input dmu_sii_reqbypass; // PINDEF:BOT // DMU requesting to send packet to bypass queue of SII
95	input dmu_sii_datareq; // PINDEF:BOT // DMU requesting to send packet w/data to SII
96	input dmu_sii_datareq16; // PINDEF:BOT // DMU requesting to send packet w/16B only
97	input [127:0] dmu_sii_data; // PINDEF:BOT // Packet from DMU to SII
98	input [7:0] dmu_sii_parity; // PINDEF:BOT // Packet parity from DMU to SII
99	input dmu_sii_be_parity; // PINDEF:BOT // Packet parity from DMU to SII
100	input [15:0] dmu_sii_be; // PINDEF:BOT // Packet byte enables from DMU to SII
101	input sii_dmu_wrack_vld;
102	input[3:0] sii_dmu_wrack_tag;
103	input sii_dmu_wrack_parity;
104
105
106	// SIO
107	input sio_dmu_hdr_vld; //PINDEF:BOT // SIO requesting to send DMA/Fl/Int packet to DMU
108	input [127:0] sio_dmu_data; //PINDEF:BOT // Packet from SIO to DMU
109	input [7:0] sio_dmu_parity; //PINDEF:BOT // Packet parity from SIO to DMU
110	// ================== DMU =================
111
112	// ================== NIU =================
113	// SII
114	reg niu_sii_hdr_vld_r; // PINDEF:BOT // Ethernet requesting to send packet to SII
115	reg niu_sii_reqbypass_r; // PINDEF:BOT // Ethernet requesting to send packet to bypass queue of SII
116	reg niu_sii_datareq_r; // PINDEF:BOT // Ethernet requesting to send packet w/data to SII
117	reg [127:0] niu_sii_data_r; // PINDEF:BOT // Packet from Ethernet to SII
118	reg [7:0] niu_sii_parity_r; // PINDEF:BOT // Packet parity from Ethernet to SII
119	reg sii_niu_oqdq_r; // PINDEF:BOT // Asserted when SII dqs an NIU entry from Ordered Queue
120	reg sii_niu_bqdq_r; // PINDEF:BOT // Asserted when SII dqs an NIU entry from Bypass Queue
121
122	// SIO
123	reg niu_sio_dq_r; //PINDEF:BOT // flow control or credit return signal from NIU to SIO
124	reg sio_niu_hdr_vld_r; //PINDEF:BOT // SIO requesting to send packet to Ethernet
125	reg sio_niu_datareq_r; //PINDEF:BOT // Valid during header phase only - 1=current request is a read data return
126	reg [127:0] sio_niu_data_r; //PINDEF:BOT // Packet from SIO to Ethernet
127	reg [7:0] sio_niu_parity_r; //PINDEF:BOT // Packet parity from SIO to Ethernet
128	// ================== NIU =================
129
130	// ================== DMU =================
131	// SII
132	reg dmu_sii_hdr_vld_r; // PINDEF:BOT // DMU requesting to send packet to SII
133	reg dmu_sii_reqbypass_r; // PINDEF:BOT // DMU requesting to send packet to bypass queue of SII
134	reg dmu_sii_datareq_r; // PINDEF:BOT // DMU requesting to send packet w/data to SII
135	reg dmu_sii_datareq16_r; // PINDEF:BOT // DMU requesting to send packet w/16B only
136	reg [127:0] dmu_sii_data_r; // PINDEF:BOT // Packet from DMU to SII
137	reg [7:0] dmu_sii_parity_r; // PINDEF:BOT // Packet parity from DMU to SII
138	reg dmu_sii_be_parity_r; // PINDEF:BOT // Packet parity from DMU to SII
139	reg [15:0] dmu_sii_be_r; // PINDEF:BOT // Packet byte enables from DMU to SII
140	reg sii_dmu_wrack_vld_r;
141	reg [3:0] sii_dmu_wrack_tag_r;
142	reg sii_dmu_wrack_parity_r;
143
144	// SIO
145	reg sio_dmu_hdr_vld_r; //PINDEF:BOT // SIO requesting to send DMA/Fl/Int packet to DMU
146	reg [127:0] sio_dmu_data_r; //PINDEF:BOT // Packet from SIO to DMU
147	reg [7:0] sio_dmu_parity_r; //PINDEF:BOT // Packet parity from SIO to DMU
148	// ================== DMU =================
149
150	// ================== TCU =================
151	// SII
152	reg tcu_sii_vld_r;
153	// SIO
154	reg sio_tcu_vld_r; // assert for jtag read return valid
155
156	// Count data cycles on interface after header cycle
157	reg [2:0] dmu_sii_cntr_r;
158	reg [2:0] niu_sii_cntr_r;
159	reg [2:0] dmu_sio_cntr_r;
160	reg [2:0] niu_sio_cntr_r;
161	reg [8:0] tcu_sii_cntr_r;
162	reg [8:0] tcu_sio_cntr_r;
163
164	wire [2:0] dmu_sii_cntr;
165	wire [2:0] niu_sii_cntr;
166	wire [2:0] dmu_sio_cntr;
167	wire [2:0] niu_sio_cntr;
168	wire [8:0] tcu_sii_cntr;
169	wire [8:0] tcu_sio_cntr;
170
171	// The SIU interfaces for the DMU & NIU are not identical so
172	// the logic below is not quite symetrical.
173	assign dmu_sii_cntr = (reset) ? 0 : // Reset to 0
174	(dmu_sii_hdr_vld_r && dmu_sii_datareq_r && dmu_sii_datareq16_r) ? 0 : // No data case?
175	(dmu_sii_hdr_vld_r && dmu_sii_datareq16_r) ? 1 : // Single xfer cycle
176	(dmu_sii_hdr_vld_r && dmu_sii_datareq_r) ? 4 : // Four xfer cycles
177	(\|dmu_sii_cntr_r) ? (dmu_sii_cntr_r - 1) : // Decrement counter when non-zero
178	dmu_sii_cntr_r; // Hold otherwise
179
180	assign niu_sii_cntr = (reset) ? 0 : // Reset to 0
181	(niu_sii_hdr_vld_r && niu_sii_datareq_r) ? 4 : // Four xfer cycle
182	(\|niu_sii_cntr_r) ? (niu_sii_cntr_r - 1) : // Decrement counter when non-zero
183	niu_sii_cntr_r; // Hold otherwise
184
185	assign tcu_sii_cntr = (reset) ? 0 : // Reset to 0
186	(tcu_sii_vld_r) ? 129 : // 128 cycles to shift, one to sample
187	(\|tcu_sii_cntr_r) ? (tcu_sii_cntr_r - 1) : // Decrement counter when non-zero
188	tcu_sii_cntr_r; // Hold otherwise
189
190	assign dmu_sio_cntr = (reset) ? 0 : // Reset to 0
191	(sio_dmu_hdr_vld_r) ? 4 : // Four xfer cycles
192	(\|dmu_sio_cntr_r) ? (dmu_sio_cntr_r - 1) : // Decrement counter when non-zero
193	dmu_sio_cntr_r; // Hold otherwise
194
195	assign niu_sio_cntr = (reset) ? 0 : // Reset to 0
196	(sio_niu_hdr_vld_r && sio_niu_datareq_r) ? 4 : // Four xfer cycle
197	(\|niu_sio_cntr_r) ? (niu_sio_cntr_r - 1) : // Decrement counter when non-zero
198	niu_sio_cntr_r; // Hold otherwise
199
200	assign tcu_sio_cntr = (reset) ? 0 : // Reset to 0
201	(sio_tcu_vld_r) ? 65 : // 64 cycles to assemble data, one to strobe out
202	(\|tcu_sio_cntr_r) ? (tcu_sio_cntr_r - 1) : // Decrement counter when non-zero
203	tcu_sio_cntr_r; // Hold at 0 otherwise
204
205	always @(posedge clk) begin
206	// Register all inputs, even ones I don't use, may
207	// want them some day.
208	niu_sii_hdr_vld_r <= (reset) ? 0 : niu_sii_hdr_vld;
209	niu_sii_reqbypass_r <= (reset) ? 0 : niu_sii_reqbypass;
210	niu_sii_datareq_r <= (reset) ? 0 : niu_sii_datareq;
211	niu_sii_data_r <= (reset) ? 0 : niu_sii_data;
212	niu_sii_parity_r <= (reset) ? 0 : niu_sii_parity;
213	sii_niu_oqdq_r <= (reset) ? 0 : sii_niu_oqdq;
214	sii_niu_bqdq_r <= (reset) ? 0 : sii_niu_bqdq;
215
216	niu_sio_dq_r <= (reset) ? 0 : niu_sio_dq;
217	sio_niu_hdr_vld_r <= (reset) ? 0 : sio_niu_hdr_vld;
218	sio_niu_datareq_r <= (reset) ? 0 : sio_niu_datareq;
219	sio_niu_data_r <= (reset) ? 0 : sio_niu_data;
220	sio_niu_parity_r <= (reset) ? 0 : sio_niu_parity;
221	dmu_sii_hdr_vld_r <= (reset) ? 0 : dmu_sii_hdr_vld;
222	dmu_sii_reqbypass_r <= (reset) ? 0 : dmu_sii_reqbypass;
223	dmu_sii_datareq_r <= (reset) ? 0 : dmu_sii_datareq;
224	dmu_sii_datareq16_r <= (reset) ? 0 : dmu_sii_datareq16;
225	dmu_sii_data_r <= (reset) ? 0 : dmu_sii_data;
226	dmu_sii_parity_r <= (reset) ? 0 : dmu_sii_parity;
227	dmu_sii_be_parity_r <= (reset) ? 0 : dmu_sii_be_parity;
228	dmu_sii_be_r <= (reset) ? 0 : dmu_sii_be;
229	sii_dmu_wrack_vld_r <= (reset) ? 0 : sii_dmu_wrack_vld;
230	sii_dmu_wrack_tag_r <= (reset) ? 0 : sii_dmu_wrack_tag;
231	sii_dmu_wrack_parity_r <= (reset) ? 0 : sii_dmu_wrack_parity;
232
233	sio_dmu_hdr_vld_r <= (reset) ? 0 : sio_dmu_hdr_vld;
234	sio_dmu_data_r <= (reset) ? 0 : sio_dmu_data;
235	sio_dmu_parity_r <= (reset) ? 0 : sio_dmu_parity;
236
237	niu_sii_cntr_r <= niu_sii_cntr;
238	dmu_sii_cntr_r <= dmu_sii_cntr;
239	niu_sio_cntr_r <= niu_sio_cntr;
240	dmu_sio_cntr_r <= dmu_sio_cntr;
241
242	tcu_sii_vld_r <= `CPU.tcu_sii_vld;
243	sio_tcu_vld_r <= `CPU.sio_tcu_vld;
244
245
246	end // always @ (posedge clk)
247
248	always @(posedge clk) begin
249	// Input, AKA DMA Writes
250	if(`TOP.info && dmu_sii_hdr_vld) begin // axis tbcall_region
251	$display("%d dmu_sii_hdr %08x-%08x-%08x-%08x Byp %x",
252	$time,
253	dmu_sii_data_r[127:96],dmu_sii_data_r[95:64],
254	dmu_sii_data_r[63:32],dmu_sii_data_r[31:0], dmu_sii_reqbypass_r);
255	end
256	if(`TOP.info && \|dmu_sii_cntr) begin // axis tbcall_region
257	$display("%d dmu_sii_data %08x-%08x-%08x-%08x BE %02x",
258	$time,
259	dmu_sii_data_r[127:96],dmu_sii_data_r[95:64],
260	dmu_sii_data_r[63:32],dmu_sii_data_r[31:0], dmu_sii_be_r);
261	end
262
263	if(`TOP.info && niu_sii_hdr_vld) begin // axis tbcall_region
264	$display("%d niu_sii_hdr %08x-%08x-%08x-%08x Byp %x",
265	$time,
266	niu_sii_data_r[127:96],niu_sii_data_r[95:64],
267	niu_sii_data_r[63:32],niu_sii_data_r[31:0], niu_sii_reqbypass_r);
268	end
269	if(`TOP.info && \|niu_sii_cntr) begin // axis tbcall_region
270	$display("%d niu_sii_data %08x-%08x-%08x-%08x",
271	$time,
272	niu_sii_data_r[127:96],niu_sii_data_r[95:64],
273	niu_sii_data_r[63:32],niu_sii_data_r[31:0]);
274	end
275	if(`TOP.info && (tcu_sii_cntr == 1)) begin // axis tbcall_region
276	$display("%d tcu_sii_data %08x-%08x-%08x-%08x",
277	$time,
278	`TOP.cpu.sii.ipcc.tcu_serial_data_l[127:96],
279	`TOP.cpu.sii.ipcc.tcu_serial_data_l[95:64],
280	`TOP.cpu.sii.ipcc.tcu_serial_data_l[63:32],
281	`TOP.cpu.sii.ipcc.tcu_serial_data_l[31:0]);
282	end
283
284	// Output, AKA DMA Reads
285	if(`TOP.info && sio_dmu_hdr_vld) begin // axis tbcall_region
286	$display("%d sio_dmu_hdr %08x-%08x-%08x-%08x",
287	$time,
288	sio_dmu_data_r[127:96],sio_dmu_data_r[95:64],
289	sio_dmu_data_r[63:32],sio_dmu_data_r[31:0]);
290	end
291	if(`TOP.info && \|dmu_sio_cntr) begin // axis tbcall_region
292	$display("%d sio_dmu_data %08x-%08x-%08x-%08x",
293	$time,
294	sio_dmu_data_r[127:96],sio_dmu_data_r[95:64],
295	sio_dmu_data_r[63:32],sio_dmu_data_r[31:0]);
296	end
297
298	if(`TOP.info && sio_niu_hdr_vld) begin // axis tbcall_region
299	$display("%d sio_niu_hdr %08x-%08x-%08x-%08x",
300	$time,
301	sio_niu_data_r[127:96],sio_niu_data_r[95:64],
302	sio_niu_data_r[63:32],sio_niu_data_r[31:0]);
303	end
304	if(`TOP.info && \|niu_sio_cntr) begin // axis tbcall_region
305	$display("%d sio_niu_data %08x-%08x-%08x-%08x",
306	$time,
307	sio_niu_data_r[127:96],sio_niu_data_r[95:64],
308	sio_niu_data_r[63:32],sio_niu_data_r[31:0]);
309	end
310	if(`TOP.info && (tcu_sio_cntr == 1)) begin // axis tbcall_region
311	$display("%d sio_tcu_data %08x-%08x",
312	$time,
313	`TOP.cpu.tcu.regs_ctl.next_l2data_reg[63:32],
314	`TOP.cpu.tcu.regs_ctl.next_l2data_reg[31:0]);
315	end
316
317	end // always @ (posedge clk)
318
319	endmodule // axis_siu_mon