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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / axis_top.vh
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: axis_top.vh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef AXIS_TL
36`ifdef AXIS_FBDIMM_NO_FSR
37 wire dram_3x_clk;
38`ifdef FAST_AXIS
39 assign dram_3x_clk=tb_top.cpu.ccu.ccu_pll.clk33;
40`else
41 assign dram_3x_clk=tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk33;
42`endif
43
44 wire dram_2x_clk;
45`ifdef FAST_AXIS
46 assign dram_2x_clk=tb_top.cpu.ccu.ccu_pll.clk32;
47`else
48 assign dram_2x_clk=tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk32;
49`endif
50`endif
51
52 reg dbg_en;
53 reg dbg_en1;
54 reg dbg_io;
55 reg tlu_dbg_en;
56 reg tlb_dbg_en;
57 reg stop_on_wdto;
58 reg [63:0] thread_wdto;
59 reg pc_trc_mode;
60 reg repeatablility_check;
61 reg [22:0] dump_pc_size;
62 wire [7:0] cmp_cores =8'h01;
63
64`ifdef AXIS_FBDIMM_NO_FSR
65 //this removes one flop in nb_encode_crc to avoid race on hw
66 wire run_on_axis_hw = 1'b1;
67`else
68 //turn off when run tl model in sw
69 wire run_on_axis_hw = 1'b0;
70`endif
71 initial $export_frcrel(tb_top.run_on_axis_hw);
72
73 initial dbg_en=0;
74 initial dbg_en1=0;
75 initial dbg_io=0;
76 initial tlu_dbg_en=0;
77 initial tlb_dbg_en=0;
78 initial thread_wdto=8192;
79 initial stop_on_wdto=0;
80 initial pc_trc_mode=0;
81 initial repeatablility_check=0;
82 initial dump_pc_size=512;
83 initial $export_frcrel(tb_top.cpu.ccu.csr_blk.pll_div2);
84 initial $export_frcrel(tb_top.cpu.ccu.csr_blk.pll_div4);
85`ifndef FAST_AXIS
86 initial $export_frcrel(tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.saved_div);
87`endif
88 initial $export_frcrel(tb_top.cpu.mcu0.fbdic.fbdic_status_parity_error_en);
89 initial $export_frcrel(tb_top.cpu.mcu1.fbdic.fbdic_status_parity_error_en);
90 initial $export_frcrel(tb_top.cpu.mcu2.fbdic.fbdic_status_parity_error_en);
91 initial $export_frcrel(tb_top.cpu.mcu3.fbdic.fbdic_status_parity_error_en);
92 initial $export_frcrel(tb_top.cpu.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.wmr_vec_mask);
93 initial $export_frcrel(tb_top.cpu.ccu.ccu_serdes_dtm);
94 initial $export_frcrel(tb_top.cpu.SSI_MISO);
95 initial $export_frcrel(tb_top.SSI_EXT_INT_L);
96 initial $export_frcrel(tb_top.cpu.ccu_ncu_vld);
97 initial $export_frcrel(tb_top.cpu.ccu_rst_sync_stable);
98 //initial $export_frcrel(tb_top.cpu.rst.rst_cmp_ctl.mio_rst_pwron_rst_cmp_);
99 //initial $export_frcrel(tb_top.cpu.rst.rst_cmp_ctl.pwron_rst_l);
100`ifndef AXIS_TL_ICE
101 initial $export_frcrel(`CPU.tcu.jtag_ctl.clock_chop_bclk);
102 initial $export_frcrel(`CPU.tcu.jtag_ctl.clock_chop_aclk);
103`endif
104 initial $export_frcrel(`TOP.dbg_en);
105 initial $export_frcrel(`TOP.dbg_io);
106 initial $export_frcrel(`TOP.tlu_dbg_en);
107 initial $export_frcrel(`TOP.tlb_dbg_en);
108 initial $export_frcrel(`TOP.dbg_en1);
109 initial $export_frcrel(`TOP.thread_wdto);
110 initial $export_frcrel(`TOP.stop_on_wdto);
111 initial $export_frcrel(`TOP.pc_trc_mode);
112 initial $export_frcrel(`TOP.repeatablility_check);
113 initial $export_frcrel(`TOP.dump_pc_size);
114 `define AXIS_DRAM `TOP.mcusat_fbdimm.axis_dimm
115 initial $export_frcrel(`AXIS_DRAM.dimm.dram_dump);
116 initial $export_frcrel(`AXIS_DRAM.dimm.dram_addr_dump);
117 initial $export_frcrel(`AXIS_DRAM.data_delay);
118 initial $export_frcrel(tb_top.cpu.ncu.tcu_sck_bypass);
119
120 axis_io_mon axis_io_mon (
121 .clk (`CPU.l2clk),
122 .reset96 (~reset),
123 .io_cpx_data_ca (`CPU.ccx.io_cpx_data_ca),
124 .io_cpx_req_cq (`CPU.ccx.io_cpx_req_cq),
125 .io_pcx_stall_pq (`CPU.ccx.io_pcx_stall_pq),
126 .cpx_io_grant_cx (`CPU.ccx.cpx_io_grant_cx),
127 .CLK_CNT (cycle[39:0]),
128 .core_mask (cmp_cores[ 7: 0]),
129 .core_id (3'b000),
130 .en_status (1'b1),
131 .pcx_cpx_en (dbg_en),
132 .pcx_cpx_short (dbg_en1),
133 .pcx_cpx_io (dbg_io),
134 .watch_dog_finish ()
135 );
136
137 //{{{ 0
138 `ifdef CORE_0
139 axis_cmp_mon core0 (
140 .clk (`CPU.l2clk),
141 .reset96 (~reset),
142 .spc_pcx_req_pq (`CPU.spc0_pcx_req_pq),
143 .pcx_spc_grant_px (`CPU.pcx_spc0_grant_px),
144 .spc_pcx_atom_pq (`CPU.spc0_pcx_atm_pq),
145 .spc_pcx_data_pa (`CPU.spc0_pcx_data_pa),
146 .cpx_spc_data_cx2 (`CPU.cpx_spc0_data_cx2),
147 .CLK_CNT (cycle[39:0]),
148 .core_mask (cmp_cores[ 7: 0]),
149 .core_id (3'b000),
150 .en_status (1'b1),
151 .pcx_cpx_en (dbg_en),
152 .pcx_cpx_short (dbg_en1),
153 .pcx_cpx_io (dbg_io),
154 .watch_dog_finish ()
155 );
156 itlb_wr_c0 itlb_mon_c0(
157 .dbg_in (tlb_dbg_en)
158 );
159 dtlb_wr_c0 dtlb_mon_c0(
160 .dbg_in (tlb_dbg_en)
161 );
162
163 `endif
164 //}}}
165 //{{{ 1
166 `ifdef CORE_1
167 axis_cmp_mon core1 (
168 .clk (`CPU.l2clk),
169 .reset96 (~reset),
170 .spc_pcx_req_pq (`CPU.spc1_pcx_req_pq),
171 .pcx_spc_grant_px (`CPU.pcx_spc1_grant_px),
172 .spc_pcx_atom_pq (`CPU.spc1_pcx_atm_pq),
173 .spc_pcx_data_pa (`CPU.spc1_pcx_data_pa),
174 .cpx_spc_data_cx2 (`CPU.cpx_spc1_data_cx2),
175 .CLK_CNT (cycle[39:0]),
176 .core_mask (cmp_cores[ 7: 0]),
177 .core_id (3'b001),
178 .en_status (1'b1),
179 .pcx_cpx_en (dbg_en),
180 .pcx_cpx_short (dbg_en1),
181 .pcx_cpx_io (dbg_io),
182 .watch_dog_finish ()
183 );
184 itlb_wr_c1 itlb_mon_c1(
185 .dbg_in (tlb_dbg_en)
186 );
187 dtlb_wr_c1 dtlb_mon_c1(
188 .dbg_in (tlb_dbg_en)
189 );
190
191 `endif
192 //}}}
193 //{{{ 2
194 `ifdef CORE_2
195 axis_cmp_mon core2 (
196 .clk (`CPU.l2clk),
197 .reset96 (~reset),
198 .spc_pcx_req_pq (`CPU.spc2_pcx_req_pq),
199 .pcx_spc_grant_px (`CPU.pcx_spc2_grant_px),
200 .spc_pcx_atom_pq (`CPU.spc2_pcx_atm_pq),
201 .spc_pcx_data_pa (`CPU.spc2_pcx_data_pa),
202 .cpx_spc_data_cx2 (`CPU.cpx_spc2_data_cx2),
203 .CLK_CNT (cycle[39:0]),
204 .core_mask (cmp_cores[ 7: 0]),
205 .core_id (3'b010),
206 .en_status (1'b1),
207 .pcx_cpx_en (dbg_en),
208 .pcx_cpx_short (dbg_en1),
209 .pcx_cpx_io (dbg_io),
210 .watch_dog_finish ()
211 );
212 itlb_wr_c2 itlb_mon_c2(
213 .dbg_in (tlb_dbg_en)
214 );
215 dtlb_wr_c2 dtlb_mon_c2(
216 .dbg_in (tlb_dbg_en)
217 );
218
219 `endif
220 //}}}
221 //{{{ 3
222 `ifdef CORE_3
223 axis_cmp_mon core3 (
224 .clk (`CPU.l2clk),
225 .reset96 (~reset),
226 .spc_pcx_req_pq (`CPU.spc3_pcx_req_pq),
227 .pcx_spc_grant_px (`CPU.pcx_spc3_grant_px),
228 .spc_pcx_atom_pq (`CPU.spc3_pcx_atm_pq),
229 .spc_pcx_data_pa (`CPU.spc3_pcx_data_pa),
230 .cpx_spc_data_cx2 (`CPU.cpx_spc3_data_cx2),
231 .CLK_CNT (cycle[39:0]),
232 .core_mask (cmp_cores[ 7: 0]),
233 .core_id (3'b011),
234 .en_status (1'b1),
235 .pcx_cpx_en (dbg_en),
236 .pcx_cpx_short (dbg_en1),
237 .pcx_cpx_io (dbg_io),
238 .watch_dog_finish ()
239 );
240 itlb_wr_c3 itlb_mon_c3(
241 .dbg_in (tlb_dbg_en)
242 );
243 dtlb_wr_c3 dtlb_mon_c3(
244 .dbg_in (tlb_dbg_en)
245 );
246
247 `endif
248 //}}}
249 //{{{ 4
250 `ifdef CORE_4
251 axis_cmp_mon core4 (
252 .clk (`CPU.l2clk),
253 .reset96 (~reset),
254 .spc_pcx_req_pq (`CPU.spc4_pcx_req_pq),
255 .pcx_spc_grant_px (`CPU.pcx_spc4_grant_px),
256 .spc_pcx_atom_pq (`CPU.spc4_pcx_atm_pq),
257 .spc_pcx_data_pa (`CPU.spc4_pcx_data_pa),
258 .cpx_spc_data_cx2 (`CPU.cpx_spc4_data_cx2),
259 .CLK_CNT (cycle[39:0]),
260 .core_mask (cmp_cores[ 7: 0]),
261 .core_id (3'b100),
262 .en_status (1'b1),
263 .pcx_cpx_en (dbg_en),
264 .pcx_cpx_short (dbg_en1),
265 .pcx_cpx_io (dbg_io),
266 .watch_dog_finish ()
267 );
268 itlb_wr_c4 itlb_mon_c4(
269 .dbg_in (tlb_dbg_en)
270 );
271 dtlb_wr_c4 dtlb_mon_c4(
272 .dbg_in (tlb_dbg_en)
273 );
274
275 `endif
276 //}}}
277 //{{{ 5
278 `ifdef CORE_5
279 axis_cmp_mon core5 (
280 .clk (`CPU.l2clk),
281 .reset96 (~reset),
282 .spc_pcx_req_pq (`CPU.spc5_pcx_req_pq),
283 .pcx_spc_grant_px (`CPU.pcx_spc5_grant_px),
284 .spc_pcx_atom_pq (`CPU.spc5_pcx_atm_pq),
285 .spc_pcx_data_pa (`CPU.spc5_pcx_data_pa),
286 .cpx_spc_data_cx2 (`CPU.cpx_spc5_data_cx2),
287 .CLK_CNT (cycle[39:0]),
288 .core_mask (cmp_cores[ 7: 0]),
289 .core_id (3'b101),
290 .en_status (1'b1),
291 .pcx_cpx_en (dbg_en),
292 .pcx_cpx_short (dbg_en1),
293 .pcx_cpx_io (dbg_io),
294 .watch_dog_finish ()
295 );
296 itlb_wr_c5 itlb_mon_c5(
297 .dbg_in (tlb_dbg_en)
298 );
299 dtlb_wr_c5 dtlb_mon_c5(
300 .dbg_in (tlb_dbg_en)
301 );
302
303 `endif
304 //}}}
305 //{{{ 6
306 `ifdef CORE_6
307 axis_cmp_mon core6 (
308 .clk (`CPU.l2clk),
309 .reset96 (~reset),
310 .spc_pcx_req_pq (`CPU.spc6_pcx_req_pq),
311 .pcx_spc_grant_px (`CPU.pcx_spc6_grant_px),
312 .spc_pcx_atom_pq (`CPU.spc6_pcx_atm_pq),
313 .spc_pcx_data_pa (`CPU.spc6_pcx_data_pa),
314 .cpx_spc_data_cx2 (`CPU.cpx_spc6_data_cx2),
315 .CLK_CNT (cycle[39:0]),
316 .core_mask (cmp_cores[ 7: 0]),
317 .core_id (3'b110),
318 .en_status (1'b1),
319 .pcx_cpx_en (dbg_en),
320 .pcx_cpx_short (dbg_en1),
321 .pcx_cpx_io (dbg_io),
322 .watch_dog_finish ()
323 );
324 itlb_wr_c6 itlb_mon_c6(
325 .dbg_in (tlb_dbg_en)
326 );
327 dtlb_wr_c6 dtlb_mon_c6(
328 .dbg_in (tlb_dbg_en)
329 );
330
331 `endif
332 //}}}
333 //{{{ 7
334 `ifdef CORE_7
335 axis_cmp_mon core7 (
336 .clk (`CPU.l2clk),
337 .reset96 (~reset),
338 .spc_pcx_req_pq (`CPU.spc7_pcx_req_pq),
339 .pcx_spc_grant_px (`CPU.pcx_spc7_grant_px),
340 .spc_pcx_atom_pq (`CPU.spc7_pcx_atm_pq),
341 .spc_pcx_data_pa (`CPU.spc7_pcx_data_pa),
342 .cpx_spc_data_cx2 (`CPU.cpx_spc7_data_cx2),
343 .CLK_CNT (cycle[39:0]),
344 .core_mask (cmp_cores[ 7: 0]),
345 .core_id (3'b111),
346 .en_status (1'b1),
347 .pcx_cpx_en (dbg_en),
348 .pcx_cpx_short (dbg_en1),
349 .pcx_cpx_io (dbg_io),
350 .watch_dog_finish ()
351 );
352 itlb_wr_c7 itlb_mon_c7(
353 .dbg_in (tlb_dbg_en)
354 );
355 dtlb_wr_c7 dtlb_mon_c7(
356 .dbg_in (tlb_dbg_en)
357 );
358
359 `endif
360 //}}}
361
362 //{{{ 0
363 `ifdef CORE_0
364 wire [7:0] good_trap_sigs_c0 = {`TOP.axis_trap_top.c0.t7.hit_good_trap,
365 `TOP.axis_trap_top.c0.t6.hit_good_trap,
366 `TOP.axis_trap_top.c0.t5.hit_good_trap,
367 `TOP.axis_trap_top.c0.t4.hit_good_trap,
368 `TOP.axis_trap_top.c0.t3.hit_good_trap,
369 `TOP.axis_trap_top.c0.t2.hit_good_trap,
370 `TOP.axis_trap_top.c0.t1.hit_good_trap,
371 `TOP.axis_trap_top.c0.t0.hit_good_trap} ;
372 `else
373 wire [7:0] good_trap_sigs_c0 = 8'b0;
374 `endif
375 //}}}
376 //{{{ 1
377 `ifdef CORE_1
378 wire [7:0] good_trap_sigs_c1 = {`TOP.axis_trap_top.c1.t7.hit_good_trap,
379 `TOP.axis_trap_top.c1.t6.hit_good_trap,
380 `TOP.axis_trap_top.c1.t5.hit_good_trap,
381 `TOP.axis_trap_top.c1.t4.hit_good_trap,
382 `TOP.axis_trap_top.c1.t3.hit_good_trap,
383 `TOP.axis_trap_top.c1.t2.hit_good_trap,
384 `TOP.axis_trap_top.c1.t1.hit_good_trap,
385 `TOP.axis_trap_top.c1.t0.hit_good_trap} ;
386 `else
387 wire [7:0] good_trap_sigs_c1 = 8'b0;
388 `endif
389 //}}}
390 //{{{ 2
391 `ifdef CORE_2
392 wire [7:0] good_trap_sigs_c2 = {`TOP.axis_trap_top.c2.t7.hit_good_trap,
393 `TOP.axis_trap_top.c2.t6.hit_good_trap,
394 `TOP.axis_trap_top.c2.t5.hit_good_trap,
395 `TOP.axis_trap_top.c2.t4.hit_good_trap,
396 `TOP.axis_trap_top.c2.t3.hit_good_trap,
397 `TOP.axis_trap_top.c2.t2.hit_good_trap,
398 `TOP.axis_trap_top.c2.t1.hit_good_trap,
399 `TOP.axis_trap_top.c2.t0.hit_good_trap} ;
400 `else
401 wire [7:0] good_trap_sigs_c2 = 8'b0;
402 `endif
403 //}}}
404 //{{{ 3
405 `ifdef CORE_3
406 wire [7:0] good_trap_sigs_c3 = {`TOP.axis_trap_top.c3.t7.hit_good_trap,
407 `TOP.axis_trap_top.c3.t6.hit_good_trap,
408 `TOP.axis_trap_top.c3.t5.hit_good_trap,
409 `TOP.axis_trap_top.c3.t4.hit_good_trap,
410 `TOP.axis_trap_top.c3.t3.hit_good_trap,
411 `TOP.axis_trap_top.c3.t2.hit_good_trap,
412 `TOP.axis_trap_top.c3.t1.hit_good_trap,
413 `TOP.axis_trap_top.c3.t0.hit_good_trap} ;
414 `else
415 wire [7:0] good_trap_sigs_c3 = 8'b0;
416 `endif
417 //}}}
418 //{{{ 4
419 `ifdef CORE_4
420 wire [7:0] good_trap_sigs_c4 = {`TOP.axis_trap_top.c4.t7.hit_good_trap,
421 `TOP.axis_trap_top.c4.t6.hit_good_trap,
422 `TOP.axis_trap_top.c4.t5.hit_good_trap,
423 `TOP.axis_trap_top.c4.t4.hit_good_trap,
424 `TOP.axis_trap_top.c4.t3.hit_good_trap,
425 `TOP.axis_trap_top.c4.t2.hit_good_trap,
426 `TOP.axis_trap_top.c4.t1.hit_good_trap,
427 `TOP.axis_trap_top.c4.t0.hit_good_trap} ;
428 `else
429 wire [7:0] good_trap_sigs_c4 = 8'b0;
430 `endif
431 //}}}
432 //{{{ 5
433 `ifdef CORE_5
434 wire [7:0] good_trap_sigs_c5 = {`TOP.axis_trap_top.c5.t7.hit_good_trap,
435 `TOP.axis_trap_top.c5.t6.hit_good_trap,
436 `TOP.axis_trap_top.c5.t5.hit_good_trap,
437 `TOP.axis_trap_top.c5.t4.hit_good_trap,
438 `TOP.axis_trap_top.c5.t3.hit_good_trap,
439 `TOP.axis_trap_top.c5.t2.hit_good_trap,
440 `TOP.axis_trap_top.c5.t1.hit_good_trap,
441 `TOP.axis_trap_top.c5.t0.hit_good_trap} ;
442 `else
443 wire [7:0] good_trap_sigs_c5 = 8'b0;
444 `endif
445 //}}}
446 //{{{ 6
447 `ifdef CORE_6
448 wire [7:0] good_trap_sigs_c6 = {`TOP.axis_trap_top.c6.t7.hit_good_trap,
449 `TOP.axis_trap_top.c6.t6.hit_good_trap,
450 `TOP.axis_trap_top.c6.t5.hit_good_trap,
451 `TOP.axis_trap_top.c6.t4.hit_good_trap,
452 `TOP.axis_trap_top.c6.t3.hit_good_trap,
453 `TOP.axis_trap_top.c6.t2.hit_good_trap,
454 `TOP.axis_trap_top.c6.t1.hit_good_trap,
455 `TOP.axis_trap_top.c6.t0.hit_good_trap} ;
456 `else
457 wire [7:0] good_trap_sigs_c6 = 8'b0;
458 `endif
459 //}}}
460 //{{{ 7
461 `ifdef CORE_7
462 wire [7:0] good_trap_sigs_c7 = {`TOP.axis_trap_top.c7.t7.hit_good_trap,
463 `TOP.axis_trap_top.c7.t6.hit_good_trap,
464 `TOP.axis_trap_top.c7.t5.hit_good_trap,
465 `TOP.axis_trap_top.c7.t4.hit_good_trap,
466 `TOP.axis_trap_top.c7.t3.hit_good_trap,
467 `TOP.axis_trap_top.c7.t2.hit_good_trap,
468 `TOP.axis_trap_top.c7.t1.hit_good_trap,
469 `TOP.axis_trap_top.c7.t0.hit_good_trap} ;
470 `else
471 wire [7:0] good_trap_sigs_c7 = 8'b0;
472 `endif
473 //}}}
474 wire [63:0] good_trap_sigs={ good_trap_sigs_c7, good_trap_sigs_c6, good_trap_sigs_c5, good_trap_sigs_c4,
475 good_trap_sigs_c3, good_trap_sigs_c2, good_trap_sigs_c1, good_trap_sigs_c0};
476 always @(posedge `CPU.l2clk)
477 begin
478 if (((good_trap_sigs & `TOP.verif_args.finish_mask) == `TOP.verif_args.finish_mask) && `TOP.verif_args.finish_mask)
479 begin // axis tbcall_region // {
480 `PR_NORMAL ("tb_top", `NORMAL, "all checked threads (%x) reached Good Trap. returning to cli", `TOP.verif_args.finish_mask);
481 `PR_NORMAL ("tb_top", `NORMAL, "Diag Reached GOOD End! (pre-regreport checking)");
482 `PR_NORMAL ("tb_top", `NORMAL, "regreport will determine if diag has really PASSED");
483 $stop;
484 end //}
485 end
486
487 axis_trap_top axis_trap_top (dump_pc_size);
488
489
490`ifdef AXIS_TL_ICE
491 wire tck_fb;
492 reg tck_fb_r;
493 reg [3:0]tap_state;
494 reg [7:0]tap_instr;
495 reg tap_dbg;
496 initial tap_dbg=1'b1;
497 reg [3:0] tap_state_r;
498 reg [7:0] tap_instr_r;
499 always @(posedge tb_top.SystemClock) begin
500 tap_state = `TCU.jtag_ctl.tap_state;
501 tap_instr = `TCU.jtag_ctl.instr;
502 end
503`ifdef FAST_AXIS
504 always @(posedge tb_top.cpu.ccu.ccu_pll.clk22) begin
505`else
506 always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22) begin
507`endif
508 if (tap_state_r != tap_state) begin
509 if (tap_dbg) begin // axis tbcall_region
510 $display("%t TAP state changed to %x", $time, tap_state);
511 end
512 tap_state_r <= tap_state;
513 end
514 if (tap_instr_r != tap_instr) begin
515 if (tap_dbg) begin // axis tbcall_region
516 $display("%t TAP instruction changed to %x", $time, tap_instr);
517 end
518 tap_instr_r <= tap_instr;
519 end
520 end
521`ifdef FAST_AXIS
522 always @(posedge tb_top.cpu.ccu.ccu_pll.clk22)
523`else
524 always @(posedge tb_top.cpu.ccu.ccu_pll.x1.imaginary_vco_gen.pll_core.clk22)
525`endif
526 tck_fb_r=`CPU.tcu.jtag_ctl.tcu_jtag_tap_ctl.l1tck;
527 assign tck_fb=tck_fb_r;
528 assign TRST=reset;
529
530 jtag_ice jtag_ice(TMS,TDI,TDO,TCK,tck_fb);
531 initial $export_frcrel(tb_top.tap_dbg);
532 initial $export_frcrel(tb_top.jtag_ice.dbg);
533 initial $export_frcrel(tb_top.jtag_ice.dbg1);
534 initial $export_frcrel(tb_top.jtag_ice.tck_fb);
535
536`endif // `ifdef AXIS_TL_ICE
537
538// SIU to DMU/NIU monitor - 12/15/2005
539axis_siu_mon axis_siu_mon(
540 .clk (`CPU.gl_io_out_c3b0),
541 .reset (~reset),
542
543 .niu_sii_hdr_vld (`CPU.niu_sii_hdr_vld),
544 .niu_sii_reqbypass (`CPU.niu_sii_reqbypass),
545 .niu_sii_datareq (`CPU.niu_sii_datareq),
546 .niu_sii_data (`CPU.niu_sii_data),
547 .niu_sii_parity (`CPU.niu_sii_parity),
548 .sii_niu_oqdq (`CPU.sii_niu_oqdq),
549 .sii_niu_bqdq (`CPU.sii_niu_bqdq),
550
551 .niu_sio_dq (`CPU.niu_sio_dq),
552 .sio_niu_hdr_vld (`CPU.sio_niu_hdr_vld),
553 .sio_niu_datareq (`CPU.sio_niu_datareq),
554 .sio_niu_data (`CPU.sio_niu_data),
555 .sio_niu_parity (`CPU.sio_niu_parity),
556
557 .dmu_sii_hdr_vld (`CPU.dmu_sii_hdr_vld),
558 .dmu_sii_reqbypass (`CPU.dmu_sii_reqbypass),
559 .dmu_sii_datareq (`CPU.dmu_sii_datareq),
560 .dmu_sii_datareq16 (`CPU.dmu_sii_datareq16),
561 .dmu_sii_data (`CPU.dmu_sii_data),
562 .dmu_sii_parity (`CPU.dmu_sii_parity),
563 .dmu_sii_be_parity (`CPU.dmu_sii_be_parity),
564 .dmu_sii_be (`CPU.dmu_sii_be),
565 .sii_dmu_wrack_vld (`CPU.sii_dmu_wrack_vld),
566 .sii_dmu_wrack_tag (`CPU.sii_dmu_wrack_tag),
567 .sii_dmu_wrack_parity (`CPU.sii_dmu_wrack_parity),
568
569 .sio_dmu_hdr_vld (`CPU.sio_dmu_hdr_vld),
570 .sio_dmu_data (`CPU.sio_dmu_data),
571 .sio_dmu_parity (`CPU.sio_dmu_parity)
572 );
573
574// MCU Error monitors. These simply print a message anytime the
575// DRAM_ERROR_STATUS_REG (0x84-0000-0280) changes. - 1/19/2006
576axis_mcu_errmon #(0) axis_mcu0_errmon(
577 .clk (`MCU0.rdpctl.l1clk),
578 .rdpctl_meu_error (`MCU0.rdpctl.rdpctl_meu_error),
579 .rdpctl_mec_error (`MCU0.rdpctl.rdpctl_mec_error),
580 .rdpctl_dac_error (`MCU0.rdpctl.rdpctl_dac_error),
581 .rdpctl_dau_error (`MCU0.rdpctl.rdpctl_dau_error),
582 .rdpctl_dsc_error (`MCU0.rdpctl.rdpctl_dsc_error),
583 .rdpctl_dsu_error (`MCU0.rdpctl.rdpctl_dsu_error),
584 .rdpctl_dbu_error (`MCU0.rdpctl.rdpctl_dbu_error),
585 .rdpctl_meb_error (`MCU0.rdpctl.rdpctl_meb_error),
586 .rdpctl_fbu_error (`MCU0.rdpctl.rdpctl_fbu_error),
587 .rdpctl_fbr_error (`MCU0.rdpctl.rdpctl_fbr_error)
588 );
589
590axis_mcu_errmon #(1) axis_mcu1_errmon(
591 .clk (`MCU1.rdpctl.l1clk),
592 .rdpctl_meu_error (`MCU1.rdpctl.rdpctl_meu_error),
593 .rdpctl_mec_error (`MCU1.rdpctl.rdpctl_mec_error),
594 .rdpctl_dac_error (`MCU1.rdpctl.rdpctl_dac_error),
595 .rdpctl_dau_error (`MCU1.rdpctl.rdpctl_dau_error),
596 .rdpctl_dsc_error (`MCU1.rdpctl.rdpctl_dsc_error),
597 .rdpctl_dsu_error (`MCU1.rdpctl.rdpctl_dsu_error),
598 .rdpctl_dbu_error (`MCU1.rdpctl.rdpctl_dbu_error),
599 .rdpctl_meb_error (`MCU1.rdpctl.rdpctl_meb_error),
600 .rdpctl_fbu_error (`MCU1.rdpctl.rdpctl_fbu_error),
601 .rdpctl_fbr_error (`MCU1.rdpctl.rdpctl_fbr_error)
602 );
603axis_mcu_errmon #(2) axis_mcu2_errmon(
604 .clk (`MCU2.rdpctl.l1clk),
605 .rdpctl_meu_error (`MCU2.rdpctl.rdpctl_meu_error),
606 .rdpctl_mec_error (`MCU2.rdpctl.rdpctl_mec_error),
607 .rdpctl_dac_error (`MCU2.rdpctl.rdpctl_dac_error),
608 .rdpctl_dau_error (`MCU2.rdpctl.rdpctl_dau_error),
609 .rdpctl_dsc_error (`MCU2.rdpctl.rdpctl_dsc_error),
610 .rdpctl_dsu_error (`MCU2.rdpctl.rdpctl_dsu_error),
611 .rdpctl_dbu_error (`MCU2.rdpctl.rdpctl_dbu_error),
612 .rdpctl_meb_error (`MCU2.rdpctl.rdpctl_meb_error),
613 .rdpctl_fbu_error (`MCU2.rdpctl.rdpctl_fbu_error),
614 .rdpctl_fbr_error (`MCU2.rdpctl.rdpctl_fbr_error)
615 );
616axis_mcu_errmon #(3) axis_mcu3_errmon(
617 .clk (`MCU3.rdpctl.l1clk),
618 .rdpctl_meu_error (`MCU3.rdpctl.rdpctl_meu_error),
619 .rdpctl_mec_error (`MCU3.rdpctl.rdpctl_mec_error),
620 .rdpctl_dac_error (`MCU3.rdpctl.rdpctl_dac_error),
621 .rdpctl_dau_error (`MCU3.rdpctl.rdpctl_dau_error),
622 .rdpctl_dsc_error (`MCU3.rdpctl.rdpctl_dsc_error),
623 .rdpctl_dsu_error (`MCU3.rdpctl.rdpctl_dsu_error),
624 .rdpctl_dbu_error (`MCU3.rdpctl.rdpctl_dbu_error),
625 .rdpctl_meb_error (`MCU3.rdpctl.rdpctl_meb_error),
626 .rdpctl_fbu_error (`MCU3.rdpctl.rdpctl_fbu_error),
627 .rdpctl_fbr_error (`MCU3.rdpctl.rdpctl_fbr_error)
628 );
629
630`endif // `ifdef AXIS_TL
631
632`ifndef AXIS_TL
633`ifdef AXIS_FBDIMM_NO_FSR
634reg ref_dram_3x_clk_reg;
635integer ref_dram_3x_clk_period;
636integer time1_r2, time2_r2;
637
638// ---- Clock Generator for FBD Channel clock ; dr_clk X 3 (linkclk) -----
639initial
640begin
641 ref_dram_3x_clk_reg=0;
642 @ (posedge `CCU.ccu_rst_sync_stable);
643 @ (posedge sysclk);
644 time1_r2=$realtime;
645 @ (posedge sysclk);
646 time2_r2=$realtime;
647 if ($test$plusargs("DTM_ENABLED"))
648 ref_dram_3x_clk_period=(time2_r2-time1_r2)/(3);
649 else
650 ref_dram_3x_clk_period=(time2_r2-time1_r2)/(3*2);
651 forever begin #(ref_dram_3x_clk_period/2) ref_dram_3x_clk_reg = ~ref_dram_3x_clk_reg; end
652end
653
654 assign dram_3x_clk = ref_dram_3x_clk_reg ;
655
656reg ref_dram_2x_clk_reg;
657integer ref_dram_2x_clk_period;
658integer time1_r3, time2_r3;
659
660// ---- Clock Generator for FBD Channel clock ; dr_clk X 2 (linkclk) -----
661initial
662begin
663 ref_dram_2x_clk_reg=0;
664 @ (posedge `CCU.ccu_rst_sync_stable);
665 @ (posedge sysclk);
666 time1_r3=$realtime;
667 @ (posedge sysclk);
668 time2_r3=$realtime;
669 if ($test$plusargs("DTM_ENABLED"))
670 ref_dram_2x_clk_period=(time2_r3-time1_r3)/(2);
671 else
672 ref_dram_2x_clk_period=(time2_r3-time1_r3)/(2*2);
673 forever begin #(ref_dram_2x_clk_period/2) ref_dram_2x_clk_reg = ~ref_dram_2x_clk_reg; end
674end
675
676 assign dram_2x_clk = ref_dram_2x_clk_reg ;
677`endif
678`endif //not AXIS_TL
679
Full OpenSPARC design & verification tarball including full HDL.