Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / fc / fc.flist

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fc.flist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
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// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
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// ========== Copyright Header End ============================================

// Testbench Files for ccm Bench

// ******************************************************************
// NIU Env files for FC Testbench
// ******************************************************************
// +incdir+$DV_ROOT/verif/env/niu/verilog
// ../../../verif/env/niu/verilog/neptune_defines.h
// NIU .v files moved to fc_niu.flist and included in fc_common.config for axis_tl builds
//../../../verif/model/verilog/niu/niu_enet_models/phy_clock_doubler_env.v
//../../../verif/model/verilog/niu/niu_enet_models/port_clk.v
//../../../verif/model/verilog/niu/niu_enet_models/rgmii_mux.v
//../../../verif/model/verilog/niu/niu_enet_models/unh_checker.v
//../../../verif/model/verilog/niu/niu_enet_models/xaui_decode.v
//../../../verif/model/verilog/niu/niu_enet_models/xgmii_if.v
//../../../verif/model/verilog/niu/niu_enet_models/xgmii_rx_decoder.v
//../../../verif/model/verilog/niu/niu_enet_models/xgmii_tx_encoder.v
//../../../verif/model/verilog/niu/niu_enet_models/xgmii_tx_encoder_top.v
//../../../verif/model/verilog/niu/niu_enet_models/bw_calc.v
// ******************************************************************
fc.vh
+incdir++
+incdir+../common/verilog/checkers+
+incdir+../common/coverage+
+incdir+./vera/include
+incdir+$DV_ROOT/verif/env/mcu
fc_top.v
trig_event.v
$DV_ROOT/verif/env/fc/system_reset.v
-v $DV_ROOT/verif/env/fc/fc_fast_bisi.v
verif_args.v
-v force_random_redundancy_bits.v
//-v ../../../verif/model/verilog/mem/denali/denali_ddrII.v
//-v ../../../verif/model/verilog/mem/denali/ddrII_soma.v
-v $DV_ROOT/verif/env/mcu/amb_dram_err_inject.v
$DV_ROOT/verif/env/mcu/cmp_mem.v
$DV_ROOT/verif/env/mcu/mcu_mem_config.v
$DV_ROOT/verif/env/mcu/mcusat_fbdimm.v
$DV_ROOT/verif/env/mcu/fbdimm_ch_mem.v
-v $DV_ROOT/verif/env/mcu/ccu_pll_config.v
-v ../../../verif/env/tcu/tcu_mon.v
-v ../../../verif/env/tcu/ccu_mon.v
//+incdir+../../../design/cpu/rtl+
+incdir+../../../verif/env/tcu+
$DV_ROOT/verif/env/common/verilog/monitors/global_monitor.v
-v $DV_ROOT/verif/env/common/verilog/monitors/mcusat_cov_mon.v
-v $DV_ROOT/verif/env/common/verilog/monitors/n2_int.v
-v $DV_ROOT/verif/env/common/verilog/monitors/n2_int_latency.v
-v $DV_ROOT/verif/env/common/verilog/monitors/iommu_demap.v
-y $DV_ROOT/verif/env/fc
-v $DV_ROOT/verif/env/common/verilog/misc/l2_scrub.v