Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / fc / fc.flist.des_v_rtl

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: fc.flist.des_v_rtl
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================

//
//=============== design_v rtl list for nosunv compile ======
//
$DV_ROOT/design/sys/iop/cpu/rtl/cpu.v
//
// $DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
// $DV_ROOT/design/sys/iop/db0/rtl/db0.v
// $DV_ROOT/design/sys/iop/db1/rtl/db1.v
// $DV_ROOT/design/sys/iop/efu/rtl/efu.v
// $DV_ROOT/design/sys/iop/l2b/rtl/l2b.v
// $DV_ROOT/design/sys/iop/mcu/rtl/mcu.v
// $DV_ROOT/design/sys/iop/ncu/rtl/ncu.v
// $DV_ROOT/design/sys/iop/rst/rtl/rst.v
// $DV_ROOT/design/sys/iop/sii/rtl/sii.v
// $DV_ROOT/design/sys/iop/sio/rtl/sio.v
// $DV_ROOT/design/sys/iop/tcu/rtl/tcu.v
//
// -v $DV_ROOT/design/sys/iop/l2t/rtl/l2t.v
// -v $DV_ROOT/design/sys/iop/spc/rtl/spc.v


-v $DV_ROOT/design/sys/iop/mio/rtl/mio.v
-v $DV_ROOT/libs/rtl/n2_efuhdr1_ctl.v
-v $DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl/n2_l2d_sp_512kb_cust.v
-v $DV_ROOT/libs/tisram/soc/n2_efa_sp_256b_cust_l/n2_efa_sp_256b_cust/rtl/n2_efa_sp_256b_cust.v
-v $DV_ROOT/libs/tisram/soc/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl/n2_l2t_sp_28kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
-v $DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_16x160_cust_l/n2_l2t_dp_16x160_cust/rtl/n2_l2t_dp_16x160_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_32x128_cust_l/n2_l2t_dp_32x128_cust/rtl/n2_l2t_dp_32x128_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_32x40_cust_l/n2_com_cm_32x40_cust/rtl/n2_com_cm_32x40_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_8x40_cust_l/n2_com_cm_8x40_cust/rtl/n2_com_cm_8x40_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_32x160_cust_l/n2_l2t_dp_32x160_cust/rtl/n2_l2t_dp_32x160_cust.v
-v $DV_ROOT/libs/n2sram/async/n2_mcu_32x72async_dp_cust_l/n2_mcu_32x72async_dp_cust/rtl/n2_mcu_32x72async_dp_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72_cust_l/n2_com_dp_64x72_cust/rtl/n2_com_dp_64x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x144s_cust_l/n2_com_dp_32x144s_cust/rtl/n2_com_dp_32x144s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x144_cust_l/n2_com_dp_32x144_cust/rtl/n2_com_dp_32x144_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x32_cust_l/n2_com_dp_32x32_cust/rtl/n2_com_dp_32x32_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_128x16s_cust_l/n2_com_dp_128x16s_cust/rtl/n2_com_dp_128x16s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x82_cust_l/n2_com_dp_32x82_cust/rtl/n2_com_dp_32x82_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x80_cust_l/n2_com_dp_64x80_cust/rtl/n2_com_dp_64x80_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x72_cust_l/n2_com_dp_16x72_cust/rtl/n2_com_dp_16x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x34_cust_l/n2_com_dp_32x34_cust/rtl/n2_com_dp_32x34_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72s_cust_l/n2_com_dp_64x72s_cust/rtl/n2_com_dp_64x72s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x32s_cust_l/n2_com_dp_16x32s_cust/rtl/n2_com_dp_16x32s_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_64x64_cust_l/n2_com_cm_64x64_cust/rtl/n2_com_cm_64x64_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_arf_dp_16x128_cust_l/n2_arf_dp_16x128_cust/rtl/n2_arf_dp_16x128_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_mam_mp_160x66_cust_l/n2_mam_mp_160x66_cust/rtl/n2_mam_mp_160x66_cust.v
-v $DV_ROOT/libs/clk/n2_clk_gl_cust_l/n2_clk_gl_cust/rtl/n2_clk_gl_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr1_cust_l/n2_clk_clstr_hdr1_cust/rtl/n2_clk_clstr_hdr1_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_cmp_cust/rtl/n2_clk_db0_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_io_cust/rtl/n2_clk_db0_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_cmp_cust/rtl/n2_clk_db1_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_io_cust/rtl/n2_clk_db1_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_cmp_cust/rtl/n2_clk_efu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_io_cust/rtl/n2_clk_efu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2b_cmp_cust/rtl/n2_clk_l2b_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2t_cmp_cust/rtl/n2_clk_l2t_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_cmp_cust/rtl/n2_clk_mcu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_dr_cust/rtl/n2_clk_mcu_dr_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_io_cust/rtl/n2_clk_mcu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_io_cust/rtl/n2_clk_ncu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_cmp_cust/rtl/n2_clk_ncu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_cmp_cust/rtl/n2_clk_rst_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_io_cust/rtl/n2_clk_rst_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_cmp_cust/rtl/n2_clk_sii_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_io_cust/rtl/n2_clk_sii_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_cmp_cust/rtl/n2_clk_sio_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_io_cust/rtl/n2_clk_sio_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clkchp_4sel_32x_cust_l/n2_clk_clkchp_4sel_32x_cust/rtl/n2_clk_clkchp_4sel_32x_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_cmp_cust/rtl/n2_clk_tcu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_io_cust/rtl/n2_clk_tcu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_cmp_cust/rtl/n2_clk_mio_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_io_cust/rtl/n2_clk_mio_io_cust.v

//
$DV_ROOT/libs/analog/n2_pcmb_cust_l/n2_pcmb_cust/rtl/n2_pcmb_cust.v
$DV_ROOT/libs/analog/n2_pcma_cust_l/n2_pcma_cust/rtl/n2_pcma_cust.v
$DV_ROOT/libs/analog/n2_tmpd_cust_l/n2_tmpd_cust/rtl/n2_tmpd_cust.v
$DV_ROOT/libs/analog/n2_revid_cust_l/n2_revid_cust/rtl/n2_revid_cust.v
$DV_ROOT/libs/analog/n2_esd_core_cust_l/n2_esd_core_cust/rtl/n2_esd_core_cust.v
$DV_ROOT/libs/analog/n2_esd_vpp_cust_l/n2_esd_vpp_cust/rtl/n2_esd_vpp_cust.v
//
$DV_ROOT/libs/clk/rtl/clkgen_efu_io.v
$DV_ROOT/libs/clk/rtl/clkgen_mcu_io.v
$DV_ROOT/libs/clk/rtl/clkgen_rst_io.v
$DV_ROOT/libs/clk/rtl/clkgen_sii_io.v
$DV_ROOT/libs/clk/rtl/clkgen_ncu_io.v
$DV_ROOT/libs/clk/rtl/clkgen_sio_io.v
$DV_ROOT/libs/clk/rtl/clkgen_db0_io.v
$DV_ROOT/libs/clk/rtl/clkgen_db1_io.v
$DV_ROOT/libs/clk/rtl/clkgen_tcu_io.v
$DV_ROOT/libs/clk/rtl/clkgen_mio_io.v
$DV_ROOT/libs/clk/rtl/clkgen_efu_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_l2b_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_l2t_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_db0_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_db1_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_sii_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_mcu_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_rst_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_ncu_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_ccx_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_tcu_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_sio_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_spc_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_mio_cmp.v
$DV_ROOT/libs/clk/rtl/clkgen_mcu_dr.v

///////