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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / fc.vh
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc.vh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef INC_FC_DEFINE
36
37`else
38
39`define INC_FC_DEFINE
40
41// common defines
42`include "defines.vh"
43
44`define BAD_END bad_end
45
46`define CORE_0
47
48`define TOP_MOD tb_top
49`define TOP tb_top
50`define CPU `TOP.cpu
51
52`define PROBES0 `TOP.intf0
53`define PROBES1 `TOP.intf1
54`define PROBES2 `TOP.intf2
55`define PROBES3 `TOP.intf3
56`define PROBES4 `TOP.intf4
57`define PROBES5 `TOP.intf5
58`define PROBES6 `TOP.intf6
59`define PROBES7 `TOP.intf7
60
61`define SPC0 `CPU.spc0
62`define SPC1 `CPU.spc1
63`define SPC2 `CPU.spc2
64`define SPC3 `CPU.spc3
65`define SPC4 `CPU.spc4
66`define SPC5 `CPU.spc5
67`define SPC6 `CPU.spc6
68`define SPC7 `CPU.spc7
69`define CCX `CPU.ccx
70
71`define MCU0 `CPU.mcu0
72`define MCU1 `CPU.mcu1
73`define MCU2 `CPU.mcu2
74`define MCU3 `CPU.mcu3
75
76`define DMU `CPU.dmu
77`define ILU `DMU.ilu
78`define PEU `CPU.peu
79
80`define NIU `CPU.niu
81
82`define NCU `CPU.ncu // Non-cacheable unit
83`define SII `CPU.sii // sii unit
84`define SIO `CPU.sio // sio unit
85
86`define TCU `CPU.tcu // Test control unit
87`define CCU `CPU.ccu // Clock control unit
88`define RST `CPU.rst // Reset logic unit
89`define EFU `CPU.efu // Electronic fuse unit
90
91`define DBG0 `CPU.dbg0
92`define DBG1 `CPU.dbg1
93
94// PCI Express DMA Endpoint model for Axis simulation.
95`define DMAEPT `TOP.ept
96
97//----------------------------------------------------------
98
99//dram
100`define DRAMPATH0 `TOP.mcusat_dram.mem0
101`define DRAMPATH1 `TOP.mcusat_dram.mem1
102`define DRAMPATH2 `TOP.mcusat_dram.mem2
103`define DRAMPATH3 `TOP.mcusat_dram.mem3
104
105`define DRIF_PATH0 `CPU.mcu0.drif
106`define DRIF_PATH1 `CPU.mcu1.drif
107`define DRIF_PATH2 `CPU.mcu2.drif
108`define DRIF_PATH3 `CPU.mcu3.drif
109
110`define TOP_MEMORY `CPU
111`define TOP_DESIGN `CPU
112
113//dram
114`define FBD_CH_PATH0 `TOP.mcusat_fbdimm.fbdimm_mem0
115`define FBD_CH_PATH1 `TOP.mcusat_fbdimm.fbdimm_mem1
116`define FBD_CH_PATH2 `TOP.mcusat_fbdimm.fbdimm_mem2
117`define FBD_CH_PATH3 `TOP.mcusat_fbdimm.fbdimm_mem3
118`define FBD_CH_PATH4 `TOP.mcusat_fbdimm.fbdimm_mem4
119`define FBD_CH_PATH5 `TOP.mcusat_fbdimm.fbdimm_mem5
120`define FBD_CH_PATH6 `TOP.mcusat_fbdimm.fbdimm_mem6
121`define FBD_CH_PATH7 `TOP.mcusat_fbdimm.fbdimm_mem7
122
123`define DIMMPATH0 fbdimm0.fbdimm_DIMMx4
124`define DIMMPATH1 fbdimm1.fbdimm_DIMMx4
125`define DIMMPATH2 fbdimm2.fbdimm_DIMMx4
126`define DIMMPATH3 fbdimm3.fbdimm_DIMMx4
127`define DIMMPATH4 fbdimm4.fbdimm_DIMMx4
128`define DIMMPATH5 fbdimm5.fbdimm_DIMMx4
129`define DIMMPATH6 fbdimm6.fbdimm_DIMMx4
130`define DIMMPATH7 fbdimm7.fbdimm_DIMMx4
131
132`ifdef RANK_DIMM
133`else
134`define RANK_DIMMPATH0 fbdimm0.fbdimm_DIMMx4_rank2
135`define RANK_DIMMPATH1 fbdimm1.fbdimm_DIMMx4_rank2
136`define RANK_DIMMPATH2 fbdimm2.fbdimm_DIMMx4_rank2
137`define RANK_DIMMPATH3 fbdimm3.fbdimm_DIMMx4_rank2
138`define RANK_DIMMPATH4 fbdimm4.fbdimm_DIMMx4_rank2
139`define RANK_DIMMPATH5 fbdimm5.fbdimm_DIMMx4_rank2
140`define RANK_DIMMPATH6 fbdimm6.fbdimm_DIMMx4_rank2
141`define RANK_DIMMPATH7 fbdimm7.fbdimm_DIMMx4_rank2
142`endif
143
144`define MONTCU `TOP.tcu_mon // Verilog DUT monitors
145`define MONCCU `TOP.ccu_mon // Verilog DUT monitors
146`define MONRST `TOP.rst_mon // Verilog DUT monitors
147
148
149`define TCK_HALF_PERIOD 25_000 // ps., 20Mhz == 50000ps
150`define SYS_HALF_PERIOD 2_500 // ps., 200Mhz == 5000ps
151
152`define IO_ASI_ADDR 8'h90
153
154
155`define NCU_C2ISC `CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_c2isc_ctl
156`define NCU_I2CSD `CPU.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csd_ctl
157`define NCU_I2CSC `CPU.ncu.ncu_scd_ctl.ncu_i2cscd_ctl.ncu_i2csc_ctl
158`define NCU_C2IFC `CPU.ncu.ncu_fcd_ctl.ncu_c2ifcd_ctl.ncu_c2ifc_ctl
159`define NCU_I2CFC `CPU.ncu.ncu_fcd_ctl.ncu_i2cfcd_ctl.ncu_i2cfc_ctl
160
161`ifdef NCU_GATE
162`define FUSE_STAT_63 `NCU.ncu_scd_ctl__n40067
163`define FUSE_STAT_62 `NCU.ncu_scd_ctl__n40066
164`define FUSE_STAT_61 `NCU.ncu_scd_ctl__n40068
165`define FUSE_STAT_60 `NCU.ncu_scd_ctl__n40069
166`define FUSE_STAT_59 `NCU.ncu_scd_ctl__n40070
167`define FUSE_STAT_58 `NCU.ncu_scd_ctl__n40072
168`define FUSE_STAT_57 `NCU.ncu_scd_ctl__n40073
169`define FUSE_STAT_56 `NCU.ncu_scd_ctl__n40074
170`define FUSE_STAT_55 `NCU.ncu_scd_ctl__n40075
171`define FUSE_STAT_54 `NCU.ncu_scd_ctl__n40076
172`define FUSE_STAT_53 `NCU.ncu_scd_ctl__n40077
173`define FUSE_STAT_52 `NCU.ncu_scd_ctl__n40078
174`define FUSE_STAT_51 `NCU.ncu_scd_ctl__n40079
175`define FUSE_STAT_50 `NCU.ncu_scd_ctl__n40080
176`define FUSE_STAT_49 `NCU.ncu_scd_ctl__n40081
177`define FUSE_STAT_48 `NCU.ncu_scd_ctl__n40083
178`define FUSE_STAT_47 `NCU.ncu_scd_ctl__n40084
179`define FUSE_STAT_46 `NCU.ncu_scd_ctl__n40085
180`define FUSE_STAT_45 `NCU.ncu_scd_ctl__n40086
181`define FUSE_STAT_44 `NCU.ncu_scd_ctl__n40087
182`define FUSE_STAT_43 `NCU.ncu_scd_ctl__n40088
183`define FUSE_STAT_42 `NCU.ncu_scd_ctl__n40089
184`define FUSE_STAT_41 `NCU.ncu_scd_ctl__n40090
185`define FUSE_STAT_40 `NCU.ncu_scd_ctl__n40091
186`define FUSE_STAT_39 `NCU.ncu_scd_ctl__n40092
187`define FUSE_STAT_38 `NCU.ncu_scd_ctl__n40094
188`define FUSE_STAT_37 `NCU.ncu_scd_ctl__n40095
189`define FUSE_STAT_36 `NCU.ncu_scd_ctl__n40096
190`define FUSE_STAT_35 `NCU.ncu_scd_ctl__n40097
191`define FUSE_STAT_34 `NCU.ncu_scd_ctl__n40098
192`define FUSE_STAT_33 `NCU.ncu_scd_ctl__n40099
193`define FUSE_STAT_32 `NCU.ncu_scd_ctl__n40100
194`define FUSE_STAT_31 `NCU.ncu_scd_ctl__n40101
195`define FUSE_STAT_30 `NCU.ncu_scd_ctl__n40102
196`define FUSE_STAT_29 `NCU.ncu_scd_ctl__n40103
197`define FUSE_STAT_28 `NCU.ncu_scd_ctl__n40105
198`define FUSE_STAT_27 `NCU.ncu_scd_ctl__n40106
199`define FUSE_STAT_26 `NCU.ncu_scd_ctl__n40107
200`define FUSE_STAT_25 `NCU.ncu_scd_ctl__n40108
201`define FUSE_STAT_24 `NCU.ncu_scd_ctl__n40109
202`define FUSE_STAT_23 `NCU.ncu_scd_ctl__n40110
203`define FUSE_STAT_22 `NCU.ncu_scd_ctl__n40111
204`define FUSE_STAT_21 `NCU.ncu_scd_ctl__n40112
205`define FUSE_STAT_20 `NCU.ncu_scd_ctl__n40113
206`define FUSE_STAT_19 `NCU.ncu_scd_ctl__n40114
207`define FUSE_STAT_18 `NCU.ncu_scd_ctl__n40116
208`define FUSE_STAT_17 `NCU.ncu_scd_ctl__n40117
209`define FUSE_STAT_16 `NCU.ncu_scd_ctl__n40118
210`define FUSE_STAT_15 `NCU.ncu_scd_ctl__n40119
211`define FUSE_STAT_14 `NCU.ncu_scd_ctl__n40120
212`define FUSE_STAT_13 `NCU.ncu_scd_ctl__n40121
213`define FUSE_STAT_12 `NCU.ncu_scd_ctl__n40122
214`define FUSE_STAT_11 `NCU.ncu_scd_ctl__n40123
215`define FUSE_STAT_10 `NCU.ncu_scd_ctl__n40124
216`define FUSE_STAT_9 `NCU.ncu_scd_ctl__n40062
217`define FUSE_STAT_8 `NCU.ncu_scd_ctl__n40061
218`define FUSE_STAT_7 `NCU.ncu_scd_ctl__n40063
219`define FUSE_STAT_6 `NCU.ncu_scd_ctl__n40064
220`define FUSE_STAT_5 `NCU.ncu_scd_ctl__n40065
221`define FUSE_STAT_4 `NCU.ncu_scd_ctl__n40071
222`define FUSE_STAT_3 `NCU.ncu_scd_ctl__n40082
223`define FUSE_STAT_2 `NCU.ncu_scd_ctl__n40093
224`define FUSE_STAT_1 `NCU.ncu_scd_ctl__n40104
225`define FUSE_STAT_0 `NCU.ncu_scd_ctl__n40115
226`endif // NCU_GATE
227
228`ifdef EFU_GATE
229`define SHFT_DATA_0 `EFU.u_efa_stdc__tck_shft_data_ff_0_
230`define SHFT_DATA_1 `EFU.u_efa_stdc__tck_shft_data_ff_1_
231`define SHFT_DATA_2 `EFU.u_efa_stdc__tck_shft_data_ff_2_
232`define SHFT_DATA_3 `EFU.u_efa_stdc__tck_shft_data_ff_3_
233`define SHFT_DATA_4 `EFU.u_efa_stdc__tck_shft_data_ff_4_
234`define SHFT_DATA_5 `EFU.u_efa_stdc__tck_shft_data_ff_5_
235`define SHFT_DATA_6 `EFU.u_efa_stdc__tck_shft_data_ff_6_
236`define SHFT_DATA_7 `EFU.u_efa_stdc__tck_shft_data_ff_7_
237`define SHFT_DATA_8 `EFU.u_efa_stdc__tck_shft_data_ff_8_
238`define SHFT_DATA_9 `EFU.u_efa_stdc__tck_shft_data_ff_9_
239`define SHFT_DATA_10 `EFU.u_efa_stdc__tck_shft_data_ff_10_
240`define SHFT_DATA_11 `EFU.u_efa_stdc__tck_shft_data_ff_11_
241`define SHFT_DATA_12 `EFU.u_efa_stdc__tck_shft_data_ff_12_
242`define SHFT_DATA_13 `EFU.u_efa_stdc__tck_shft_data_ff_13_
243`define SHFT_DATA_14 `EFU.u_efa_stdc__tck_shft_data_ff_14_
244`define SHFT_DATA_15 `EFU.u_efa_stdc__tck_shft_data_ff_15_
245`define SHFT_DATA_16 `EFU.u_efa_stdc__tck_shft_data_ff_16_
246`define SHFT_DATA_17 `EFU.u_efa_stdc__tck_shft_data_ff_17_
247`define SHFT_DATA_18 `EFU.u_efa_stdc__tck_shft_data_ff_18_
248`define SHFT_DATA_19 `EFU.u_efa_stdc__tck_shft_data_ff_19_
249`define SHFT_DATA_20 `EFU.u_efa_stdc__tck_shft_data_ff_20_
250`define SHFT_DATA_21 `EFU.u_efa_stdc__tck_shft_data_ff_21_
251`define SHFT_DATA_22 `EFU.u_efa_stdc__tck_shft_data_ff_22_
252`define SHFT_DATA_23 `EFU.u_efa_stdc__tck_shft_data_ff_23_
253`define SHFT_DATA_24 `EFU.u_efa_stdc__tck_shft_data_ff_24_
254`define SHFT_DATA_25 `EFU.u_efa_stdc__tck_shft_data_ff_25_
255`define SHFT_DATA_26 `EFU.u_efa_stdc__tck_shft_data_ff_26_
256`define SHFT_DATA_27 `EFU.u_efa_stdc__tck_shft_data_ff_27_
257`define SHFT_DATA_28 `EFU.u_efa_stdc__tck_shft_data_ff_28_
258`define SHFT_DATA_29 `EFU.u_efa_stdc__tck_shft_data_ff_29_
259`define SHFT_DATA_30 `EFU.u_efa_stdc__tck_shft_data_ff_30_
260`endif // EFU_GATE
261//
262//---------------------------
263//
264
265
266//----------------------------------------------------------
267// END OF FILE
268//----------------------------------------------------------
269//
270`endif // !`ifdef INC_FC_DEFINE
Full OpenSPARC design & verification tarball including full HDL.