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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / fc_niu_slam.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_niu_slam.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35 reg sel_gmii;
36 integer speed0,speed1;
37
38 integer speed;
39 integer mac_port;
40 reg speed_10G;
41 reg [8*60:1] arg,arg0,arg1;
42
43
44
45 initial
46 begin
47 arg = "GET_MAC_PORTS=";
48
49 if ($test$plusargs("GET_MAC_PORTS="))
50 mac_port = $util_get_plus_args_num(arg);
51 $display("mc_core : Ethernet Port is %0d \n",mac_port);
52
53 end
54
55 initial
56 begin
57 /* Check MAC_SPEED0 */
58
59 arg0 = "MAC_SPEED0=";
60 if ($test$plusargs("MAC_SPEED0="))
61 speed0 = $util_get_plus_args_num(arg0);
62 else speed0 = 10000;
63
64 /* Check MAC_SPEED1 */
65
66 arg1 = "MAC_SPEED1=";
67 if ($test$plusargs("MAC_SPEED1="))
68 speed1 = $util_get_plus_args_num(arg1);
69 else speed1 = 10000;
70
71
72 if ((speed0 == 10000) ||(speed1 == 10000))
73 begin
74 $display("mc_core : Ethernet Speed 10G\n");
75 speed_10G = 1;
76 end
77 else
78 begin
79 $display("mac_core : Ethernet Speed0 Speed1 %0d, %0d\n",speed0, speed1);
80 speed_10G = 0;
81 end
82
83
84 /* Check PCS_SERDES */
85
86 if ($test$plusargs("PCS_SERDES"))
87 begin
88 $display("mac_core : Ethernet SerDes Mode\n");
89 sel_gmii = 0;
90 end
91 else
92 begin
93 $display("mac_core : Ethernet RGMII Mode\n");
94 sel_gmii = 1;
95 end
96
97 if ($test$plusargs ("NO_SRDS_REG_SLAM"))
98 begin
99 end
100 else // Default SERDES SLAMing
101 begin
102`ifdef NIU_SYSTEMC_T2
103`else
104 if(speed_10G == 1)
105 begin
106 force `ESR.cfgtx0_0 = 24'h00_0001;
107 force `ESR.cfgtx1_0 = 24'h00_0001;
108 force `ESR.cfgtx2_0 = 24'h00_0001;
109 force `ESR.cfgtx3_0 = 24'h00_0001;
110 force `ESR.cfgrx0_0 = 28'h008_5001;
111 force `ESR.cfgrx1_0 = 28'h008_5001;
112 force `ESR.cfgrx2_0 = 28'h008_5001;
113 force `ESR.cfgrx3_0 = 28'h008_5001;
114 force `ESR.cfgpll_0 = 12'h003;
115 force `ESR.testcfg_0 = 16'h0000;
116
117 force `ESR.cfgtx0_1 = 24'h00_0001;
118 force `ESR.cfgtx1_1 = 24'h00_0001;
119 force `ESR.cfgtx2_1 = 24'h00_0001;
120 force `ESR.cfgtx3_1 = 24'h00_0001;
121 force `ESR.cfgrx0_1 = 28'h008_5001;
122 force `ESR.cfgrx1_1 = 28'h008_5001;
123 force `ESR.cfgrx2_1 = 28'h008_5001;
124 force `ESR.cfgrx3_1 = 28'h008_5001;
125 force `ESR.cfgpll_1 = 12'h003;
126 force `ESR.testcfg_1 = 16'h0000;
127 end
128 else
129 begin
130 force `ESR.cfgtx0_0 = 20'h0_0021;
131 force `ESR.cfgtx1_0 = 20'h0_0000;
132 force `ESR.cfgtx2_0 = 20'h0_0000;
133 force `ESR.cfgtx3_0 = 20'h0_0000;
134 force `ESR.cfgrx0_0 = 28'h000_5021;
135 force `ESR.cfgrx1_0 = 28'h000_0000;
136 force `ESR.cfgrx2_0 = 28'h000_0000;
137 force `ESR.cfgrx3_0 = 28'h000_0000;
138 force `ESR.cfgpll_0 = 12'h00b;
139 force `ESR.testcfg_0 = 16'h0000;
140
141 force `ESR.cfgtx0_1 = 20'h0_0021;
142 force `ESR.cfgtx1_1 = 20'h0_0000;
143 force `ESR.cfgtx2_1 = 20'h0_0000;
144 force `ESR.cfgtx3_1 = 20'h0_0000;
145 force `ESR.cfgrx0_1 = 28'h008_5021;
146 force `ESR.cfgrx1_1 = 28'h008_0000;
147 force `ESR.cfgrx2_1 = 28'h008_0000;
148 force `ESR.cfgrx3_1 = 28'h008_0000;
149 force `ESR.cfgpll_1 = 12'h00b;
150 force `ESR.testcfg_1 = 16'h0000;
151
152 end
153`endif // NIU_SYSTEMC_T2
154 end
155 end
156
157assign refclk_enet_n = ~refclk_enet;
158assign refclk_enet = speed_10G ? enet_clk : m0_rx_clk ;
159
160// These are derived clks that
161// needed an initial state
162
163`ifdef NIU_SYSTEMC_T2
164`else
165
166initial
167 begin
168`ifdef NIU_GATE
169 force tb_top.cpu.rdp.debug_niu_clk_divby2 = 1'b0;
170 force tb_top.cpu.rdp.debug_niu_clk_divby4 = 1'b0;
171 force tb_top.cpu.rdp.debug_niu_clk_divby8 = 1'b0;
172 #1;
173 release tb_top.cpu.rdp.debug_niu_clk_divby2;
174 release tb_top.cpu.rdp.debug_niu_clk_divby4;
175 release tb_top.cpu.rdp.debug_niu_clk_divby8;
176`else
177 if($test$plusargs("NIU_CLK_DIV")) begin
178 tb_top.cpu.rdp.debug.niu_clk_divby2 = 0;
179 tb_top.cpu.rdp.debug.niu_clk_divby4 = 0;
180 tb_top.cpu.rdp.debug.niu_clk_divby8 = 0;
181 end
182`endif
183 end
184
185`endif // NIU_SYSTEMC_T2
186
187
Full OpenSPARC design & verification tarball including full HDL.