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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_pcie_stuff.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | wire [7:0] RX_N; | |
36 | wire [7:0] RX_P; | |
37 | wire [7:0] TX_N; | |
38 | wire [7:0] TX_P; | |
39 | wire PEX_RESET_L; | |
40 | reg PCIE_Clock_250; | |
41 | ||
42 | `ifndef FC_NO_PEUSAT_CODE | |
43 | // ******************************************************************************** | |
44 | // PEU and Denali logic. | |
45 | // ******************************************************************************** | |
46 | wire DEN_CLK_TX; | |
47 | wire DEN_CLK_RX; | |
48 | wire DEN_RESET; | |
49 | wire [7:0] RCV_DET_LANES; | |
50 | ||
51 | // denali root monitor Clocks and Reset | |
52 | wire denali_root_monitor_CLK_TX; | |
53 | wire denali_root_monitor_CLK_RX; | |
54 | wire denali_root_monitor_RESET = PEX_RESET_L; | |
55 | ||
56 | denali_pcie_device #( 8 ) pcieA ( | |
57 | .TX ( RX_P ), | |
58 | .TX_ ( RX_N ), | |
59 | .RX ( TX_P ), | |
60 | .RX_ ( TX_N ), | |
61 | .CLK_TX ( DEN_CLK_TX ), | |
62 | .CLK_RX ( DEN_CLK_RX ), | |
63 | // AT, 1/26/06: In DTM mode, Denali reset need to be driven by TB, not N2. | |
64 | // AT- .PERST_ ( PEX_RESET_L ) | |
65 | `ifndef DTM_ENABLED | |
66 | .PERST_ ( PEX_RESET_L ) | |
67 | `else | |
68 | .PERST_ ( ~DEN_RESET) | |
69 | `endif | |
70 | ); | |
71 | defparam pcieA.interface_soma = "$DV_ROOT/verif/env/ilu_peu/soma_fastlink.soma"; | |
72 | ||
73 | ||
74 | // Denali Root Complex monitor: for compliance check purpose | |
75 | denali_pcie_root_complex_monitor #(8) pcie_root_monitor | |
76 | ( | |
77 | .TX (TX_P), | |
78 | .TX_ (TX_N), | |
79 | .RX (RX_P), | |
80 | .RX_ (RX_N), | |
81 | .CLK_TX (denali_root_monitor_CLK_TX), | |
82 | .CLK_RX (denali_root_monitor_CLK_RX), | |
83 | .PERST_ (denali_root_monitor_RESET) | |
84 | ); | |
85 | ||
86 | defparam pcie_root_monitor.interface_soma = "$DV_ROOT/verif/env/ilu_peu/soma_fastlink_root_monitor.soma"; | |
87 | ||
88 | //Use ELEC_IDLE_LANES to force the | |
89 | // RX lanes to simulate electrical idle condition | |
90 | // This is driven by the Vera task linkdown(), so is not needed in the endpoint model | |
91 | wire [7:0] ELEC_IDLE_LANES; | |
92 | ||
93 | always @( ELEC_IDLE_LANES ) begin | |
94 | if( ELEC_IDLE_LANES[0] ) begin | |
95 | force RX_P[0] = 0; | |
96 | force RX_N[0] = 0; end | |
97 | else begin | |
98 | release RX_P[0]; | |
99 | release RX_N[0]; end | |
100 | if( ELEC_IDLE_LANES[1] ) begin | |
101 | force RX_P[1] = 0; | |
102 | force RX_N[1] = 0; end | |
103 | else begin | |
104 | release RX_P[1]; | |
105 | release RX_N[1]; end | |
106 | if( ELEC_IDLE_LANES[2] ) begin | |
107 | force RX_P[2] = 0; | |
108 | force RX_N[2] = 0; end | |
109 | else begin | |
110 | release RX_P[2]; | |
111 | release RX_N[2]; end | |
112 | if( ELEC_IDLE_LANES[3] ) begin | |
113 | force RX_P[3] = 0; | |
114 | force RX_N[3] = 0; end | |
115 | else begin | |
116 | release RX_P[3]; | |
117 | release RX_N[3]; end | |
118 | if( ELEC_IDLE_LANES[4] ) begin | |
119 | force RX_P[4] = 0; | |
120 | force RX_N[4] = 0; end | |
121 | else begin | |
122 | release RX_P[4]; | |
123 | release RX_N[4]; end | |
124 | if( ELEC_IDLE_LANES[5] ) begin | |
125 | force RX_P[5] = 0; | |
126 | force RX_N[5] = 0; end | |
127 | else begin | |
128 | release RX_P[5]; | |
129 | release RX_N[5]; end | |
130 | if( ELEC_IDLE_LANES[6] ) begin | |
131 | force RX_P[6] = 0; | |
132 | force RX_N[6] = 0; end | |
133 | else begin | |
134 | release RX_P[6]; | |
135 | release RX_N[6]; end | |
136 | if( ELEC_IDLE_LANES[7] ) begin | |
137 | force RX_P[7] = 0; | |
138 | force RX_N[7] = 0; end | |
139 | else begin | |
140 | release RX_P[7]; | |
141 | release RX_N[7]; end | |
142 | end | |
143 | ||
144 | `else | |
145 | // PCI-E DMA endpoint | |
146 | ||
147 | // added this ifndef | |
148 | `ifndef FC_NO_PEU_T2 | |
149 | ept ept (); | |
150 | `endif | |
151 | ||
152 | `ifdef BUILD_USE_BOBO | |
153 | // Task to be called from Vera for backdoor writes | |
154 | task bobo_write_64bit; | |
155 | input [39:0] pa; | |
156 | input [63:0] data64; | |
157 | ||
158 | begin | |
159 | ept.pci_dma.dma.e3.buffer.ram0.memory_array[pa[11:3]] = data64[7:0]; | |
160 | ept.pci_dma.dma.e3.buffer.ram1.memory_array[pa[11:3]] = data64[15:8]; | |
161 | ept.pci_dma.dma.e3.buffer.ram2.memory_array[pa[11:3]] = data64[23:16]; | |
162 | ept.pci_dma.dma.e3.buffer.ram3.memory_array[pa[11:3]] = data64[31:24]; | |
163 | ept.pci_dma.dma.e3.buffer.ram4.memory_array[pa[11:3]] = data64[39:32]; | |
164 | ept.pci_dma.dma.e3.buffer.ram5.memory_array[pa[11:3]] = data64[47:40]; | |
165 | ept.pci_dma.dma.e3.buffer.ram6.memory_array[pa[11:3]] = data64[55:48]; | |
166 | ept.pci_dma.dma.e3.buffer.ram7.memory_array[pa[11:3]] = data64[63:56]; | |
167 | `PR_INFO ("ept", `MON_INFO, "bobo_write_64bit {pa[11:3],3'b000} = %h, data64 = %h\n", {pa[11:3],3'b000}, data64); | |
168 | end | |
169 | endtask // bobo_write_64bit | |
170 | `endif // BUILD_USE_BOBO | |
171 | ||
172 | `endif // !`ifndef FC_NO_PEUSAT_CODE | |
173 | ||
174 | `ifdef PALLADIUM | |
175 | // The following code is not used in the FC design. | |
176 | `elsif AXIS_TL | |
177 | `else | |
178 | initial begin | |
179 | PCIE_Clock_250 = 0; | |
180 | ||
181 | forever begin | |
182 | # 2000 | |
183 | PCIE_Clock_250 = 1; | |
184 | # 2000 | |
185 | PCIE_Clock_250 = 0; | |
186 | end | |
187 | end | |
188 | `endif //PALLADIUM | |
189 | ||
190 | integer delay_ref = delay_250; // = 250MHz default reference clock | |
191 | reg PCIE_Ref_Clock; // Reference clock can be 100,125,250 MHz | |
192 | ||
193 | //Choose a serdes reference clock | |
194 | `ifdef PALLADIUM | |
195 | // The following block is not used in the FC design | |
196 | ||
197 | `elsif AXIS_TL | |
198 | `else | |
199 | initial begin | |
200 | PCIE_Ref_Clock = 0; | |
201 | if ($test$plusargs("PCIE_REF_CLK_100")) begin | |
202 | delay_ref = 100; | |
203 | end | |
204 | else if ($test$plusargs("PCIE_REF_CLK_104")) begin // DTM mode only | |
205 | delay_ref = 104; | |
206 | end | |
207 | else if ($test$plusargs("PCIE_REF_CLK_125")) begin | |
208 | delay_ref = 125; | |
209 | end | |
210 | else if ($test$plusargs("PCIE_REF_CLK_250")) begin | |
211 | delay_ref = 250; | |
212 | end | |
213 | else begin | |
214 | delay_ref = 250; | |
215 | end | |
216 | ||
217 | /* Changed for DTM 104 MHz fix | |
218 | if ($test$plusargs("PCIE_REF_CLK_100")) begin | |
219 | delay_ref = delay_100; | |
220 | end | |
221 | else if ($test$plusargs("PCIE_REF_CLK_125")) begin | |
222 | delay_ref = delay_125; | |
223 | end | |
224 | else if ($test$plusargs("PCIE_REF_CLK_250")) begin | |
225 | delay_ref = delay_250; | |
226 | end | |
227 | else begin | |
228 | delay_ref = delay_250; | |
229 | end | |
230 | */ | |
231 | ||
232 | forever begin | |
233 | /* AT-, DTM: Per email on 4/4/06: | |
234 | # delay_ref | |
235 | PCIE_Ref_Clock = 1; | |
236 | # delay_ref | |
237 | PCIE_Ref_Clock = 0; | |
238 | */ | |
239 | ||
240 | // AT+, DTM: Per MkS emial on 4/4/06 | |
241 | if( delay_ref == 100 )begin | |
242 | # delay_100 | |
243 | PCIE_Ref_Clock = 1; | |
244 | # delay_100 | |
245 | PCIE_Ref_Clock = 0; | |
246 | end | |
247 | ||
248 | if( delay_ref == 104 )begin // DTM mode only | |
249 | # delay_104 | |
250 | PCIE_Ref_Clock = 1; | |
251 | # delay_104 | |
252 | PCIE_Ref_Clock = 0; | |
253 | end | |
254 | ||
255 | if( delay_ref == 125 )begin | |
256 | # delay_125 | |
257 | PCIE_Ref_Clock = 1; | |
258 | # delay_125 | |
259 | PCIE_Ref_Clock = 0; | |
260 | end | |
261 | ||
262 | if( delay_ref == 250 )begin | |
263 | # delay_250 | |
264 | PCIE_Ref_Clock = 1; | |
265 | # delay_250 | |
266 | PCIE_Ref_Clock = 0; | |
267 | end | |
268 | end | |
269 | ||
270 | end | |
271 | `endif |