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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fc_zeroIn_cfg.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cmp_zeroin_ctl; | |
36 | ||
37 | // set global default clock | |
38 | // 0in set_clock l2clk -default -module cpu | |
39 | // 0in set_clock drl2clk -default -module mcu | |
40 | // 0in set_clock iol2clk -posedge -default -module dmu | |
41 | ||
42 | ||
43 | // set default checker action to finish simulation when a checker fires | |
44 | // 0in set_checker_action -finish -severity 0 | |
45 | ||
46 | // make sure a checker which fires causes a fail | |
47 | // 0in checker_firing_keyword -name "ERROR - failing assertion!" -severity 0 | |
48 | // 0in checker_firing_keyword -name "WARNING - assertion fired!" -severity 1 | |
49 | // 0in checker_firing_keyword -name "INFO - assertion fired!" -severity 2 | |
50 | ||
51 | ||
52 | //--------------------------------------------------------------------------- | |
53 | // during flush reset, disable checkers | |
54 | //--------------------------------------------------------------------------- | |
55 | // LOOK HERE -> you can not do -module *. You can not do -name w/o -type. | |
56 | // for all -> x0in disable_checker ~tb_top.flush_reset_complete -name cpu.* -type * | |
57 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.dmu* -type * | |
58 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.ncu* -type * | |
59 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.peu* -type * | |
60 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.si* -type * | |
61 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.l2* -type * | |
62 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.spc* -type * | |
63 | ||
64 | ||
65 | //--------------------------------------------------------------------------- | |
66 | // PEU checkers | |
67 | //--------------------------------------------------------------------------- | |
68 | ||
69 | // x0in default_reset -sync -infer -module dmu | |
70 | ||
71 | // get dmu reset signals after they are sync'd | |
72 | wire dmu_rst_asserted = (tb_top.cpu.dmu.por_ !== 1'b1 || | |
73 | tb_top.cpu.dmu.wmr_ !== 1'b1 ); | |
74 | ||
75 | // 0in default_reset dmu_rst_asserted -sync -module dmu | |
76 | ||
77 | // get peu reset signals after they are sync'd | |
78 | wire peu_rst_asserted = (tb_top.cpu.peu.rst_por_sync_ !== 1'b1 || | |
79 | tb_top.cpu.peu.rst_wmr_sync_ !== 1'b1 ); | |
80 | ||
81 | // 0in default_reset peu_rst_asserted -sync -module peu | |
82 | ||
83 | // Disable PEU checkers until the clocks have stabilized | |
84 | ||
85 | ||
86 | // This module does not specify clock in it's checkers | |
87 | // 0-in infers l2clk which causes false firings | |
88 | // 0in set_clock clk -module pcie_common_dcs_ism | |
89 | ||
90 | // 0in set_clock clk -module pcie_common_srq | |
91 | ||
92 | ||
93 | // From peu sat | |
94 | // 0in set_clock l1clk -default -module dmu_ilu | |
95 | // 0in set_clock `PEU.peu_ptl.l2t_clk -default -module peu | |
96 | // 0in set_clock l2t_clk -default -module ptl | |
97 | // 0in set_clock clk -default -module ptl_itl_ihp | |
98 | // x0in set_clock pc_clk -default -module peu | |
99 | ||
100 | ||
101 | // these checkers are not getting mapped correctly to 0-in. | |
102 | ||
103 | // | |
104 | // x0in exclude_checker -name cpu.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_addr_decode.mapped_after_valid | |
105 | // x0in exclude_checker -name cpu.peu.peu_ptl.ctb.tlr.csr.ptl_ctb_tlr_addr_decode.daemon_csrbus_done_high | |
106 | ||
107 | // DH, 07/11/05: Disable this fifo check since it doesn't seem to be working correctly | |
108 | // x0in exclude_checker -name cpu.peu.peu_ptl.ihb.ptl_ihb_async_ram_chk | |
109 | ||
110 | // DH, 07/12/05: Disable this scoreboard check since it doesn't seem to be working correctly | |
111 | // x0in exclude_checker -name cpu.dmu.dsn.dmu_dsn_ctl.dsn_ncu_sii_scbd | |
112 | ||
113 | // x0in exclude_checker -name cpu.peu.peu_ptl.itl.ifc.state_4 | |
114 | ||
115 | // x0in exclude_checker -name cpu.peu.peu_ptl.etl.hcs.fifo_request.enq_deq | |
116 | ||
117 | //--------------------------------------------------------------------------- | |
118 | // NIU checkers | |
119 | //--------------------------------------------------------------------------- | |
120 | // disable NIU checkers till reset is deasserted | |
121 | // | |
122 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.rtx* | |
123 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.tds* | |
124 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.rdp* | |
125 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.mac* | |
126 | // 0in disable_checker ~tb_top.flush_reset_complete -name cpu.esr* | |
127 | ||
128 | // 0in exclude_checker -name cpu.mac.mac_core.mac_2ports.xmac_2pcs_core_port0.xpcs.xpcs_rx.req_ack | |
129 | // 0in exclude_checker -name cpu.mac.mac_core.mac_2ports.xmac_2pcs_core_port1.xpcs.xpcs_rx.req_ack | |
130 | ||
131 | // 0in exclude_checker -name cpu.rtx.rxc.ipp_top_0.ipp0.ipp_unload_ctl_1ke_0.c_unload_st_1 | |
132 | // 0in exclude_checker -name cpu.rtx.rxc.ipp_top_0.ipp1.ipp_unload_ctl_1ke_0.c_unload_st_1 | |
133 | ||
134 | //--------------------------------------------------------------------------- | |
135 | // MCU checkers | |
136 | //------------------------------------- -------------------------------------- | |
137 | // disable MCU checkers since the fsr* will drive x for some time | |
138 | // after the clocks are running. | |
139 | reg fsr_clk_stable = 1'b0; | |
140 | ||
141 | initial fork | |
142 | repeat (50) @ (posedge `TOP.fbl2clk); | |
143 | fsr_clk_stable = 1'b1; | |
144 | join | |
145 | ||
146 | // 0in disable_checker fsr_clk_stable -name cpu.mcu* | |
147 | ||
148 | //========================================================================= | |
149 | //black box certain heirachy | |
150 | //========================================================================= | |
151 | //0in exclude_hier -module fc_l2_csr_probe | |
152 | //0in exclude_hier -module fc_mcu_csr_probe | |
153 | //0in exclude_hier -module trig_event | |
154 | ||
155 | //Option to exclude rst_chkr | |
156 | `ifdef EXCLUDE_RST_CHKR | |
157 | //0in exclude_checker -group rst_chkr | |
158 | `endif | |
159 | ||
160 | endmodule |