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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / vcd_scope.vh
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: vcd_scope.vh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35if ($test$plusargs("DUMP_LIMIT")) begin // {
36
37`ifndef GATESIM
38
39 if ($test$plusargs("DUMP_PINS")) begin // {
40 `PR_NORMAL ("dump_scope",`NORMAL,"DUMP_PINS plusarg detected");
41 // ANALOG //
42 $dumpvars(1,tb_top.cpu.VDD_PLL_CMP_REG);
43 $dumpvars(1,tb_top.cpu.VDD_RNG_HV);
44 $dumpvars(1,tb_top.cpu.VDD_SENSE);
45 $dumpvars(1,tb_top.cpu.VSS_SENSE);
46 $dumpvars(1,tb_top.cpu.VDDO_PCM);
47 $dumpvars(1,tb_top.cpu.DIODE_TOP);
48 $dumpvars(1,tb_top.cpu.DIODE_BOT);
49 $dumpvars(1,tb_top.cpu.RNG_ANLG_CHAR_OUT);
50 $dumpvars(1,tb_top.cpu.PLL_CHAR_OUT); // should be PLL_CMP_CHAR_OUT[1:0]
51 $dumpvars(1,tb_top.cpu.PLL_TESTMODE);
52 $dumpvars(1,tb_top.cpu.VREG_SELBG_L);
53
54
55 // BISI //
56 $dumpvars(1,tb_top.cpu.tcu_bisx_done);
57 $dumpvars(1,tb_top.cpu.tcu.mbist_done);
58
59 // CLOCKS //
60 $dumpvars(1,tb_top.cpu.PLL_CMP_CLK_P);
61 $dumpvars(1,tb_top.cpu.PLL_CMP_CLK_N);
62 $dumpvars(1,tb_top.cpu.FBDIMM1_REFCLK_P);
63 $dumpvars(1,tb_top.cpu.FBDIMM1_REFCLK_N);
64 $dumpvars(1,tb_top.cpu.FBDIMM2_REFCLK_P);
65 $dumpvars(1,tb_top.cpu.FBDIMM2_REFCLK_N);
66 $dumpvars(1,tb_top.cpu.FBDIMM3_REFCLK_P);
67 $dumpvars(1,tb_top.cpu.FBDIMM3_REFCLK_N);
68 $dumpvars(1,tb_top.cpu.PEX_REFCLK_P);
69 $dumpvars(1,tb_top.cpu.PEX_REFCLK_N);
70`ifndef FC_NO_NIU_T2
71 $dumpvars(1,tb_top.cpu.XAUI0_REFCLK_P);
72 $dumpvars(1,tb_top.cpu.XAUI0_REFCLK_N);
73`endif
74 $dumpvars(1,tb_top.cpu.tcu.gclk);
75 $dumpvars(1,tb_top.cpu.ccu.cmp_pll_clk);
76 $dumpvars(1,tb_top.cpu.ccu.dr_pll_clk);
77 $dumpvars(1,tb_top.cpu.efu.iol2clk);
78 $dumpvars(1,tb_top.cpu.l2clk);
79
80 // DEBUG //
81 $dumpvars(1,tb_top.cpu.DBG_DQ);
82 $dumpvars(1,tb_top.cpu.dbg1_mio_drv_en_muxtest_inp);
83 $dumpvars(1,tb_top.cpu.dbg1_mio_drv_en_muxtestpll_inp);
84 // tb_top.cpu.DBG_DQ[165:160]) ----> SOC Observability FSM state //
85 // tb_top.cpu.DBG_DQ[159]) ----> SCAN_OUT31 //
86 // tb_top.cpu.DBG_DQ[158]) ----> SCAN_IN31 //
87 // tb_top.cpu.DBG_DQ[157]) ----> PLL_CMP_CHAR_IN //
88 // tb_top.cpu.DBG_DQ[156:151]) ----> PLL_CMP_DIV2[5:0] //
89 // tb_top.cpu.DBG_DQ[150]) ----> PLL_CMP_TRST_L //
90 // tb_top.cpu.DBG_DQ[149]) ----> PLL_CMP_CLAMP_FLTR //
91 // tb_top.cpu.DBG_DQ[148:147]) //
92 // tb_top.cpu.DBG_DQ[146:140]) ----> PLL_CMP_DIV4[6:0] //
93 // tb_top.cpu.DBG_DQ[139]) ----> PLL_EXT_DR_CLK //
94 // tb_top.cpu.DBG_DQ[138]) ----> PLL_EXT_CMP_CLK //
95 // tb_top.cpu.DBG_DQ[137]) ----> AC_TESTMODE //
96 // tb_top.cpu.DBG_DQ[136]) ----> AC_TESTTRIG //
97 // tb_top.cpu.DBG_DQ[135]) ----> ACLK //
98 // tb_top.cpu.DBG_DQ[134]) ----> BCLK //
99 // tb_top.cpu.DBG_DQ[133:103]) ----> SCAN_IN[30:0] //
100 // tb_top.cpu.DBG_DQ[102:85]); //
101 // tb_top.cpu.DBG_DQ[84]) ----> PEU_CLK_EXT //
102 // tb_top.cpu.DBG_DQ[83]); //
103 // tb_top.cpu.DBG_DQ[82:77]) ----> NIU_CLK_EXT[5:0] //
104 // tb_top.cpu.DBG_DQ[76:75]); //
105 // tb_top.cpu.DBG_DQ[74]) ----> SCAN_ENABLE //
106 // tb_top.cpu.DBG_DQ[73:43]) ----> SCAN_OUT[30:0] //
107 // tb_top.cpu.DBG_DQ[42]) ----> DMO_SYNC //
108 // tb_top.cpu.DBG_DQ[41:2]) ----> DMO_DATA[39:0] //
109 // tb_top.cpu.DBG_DQ[1]) ----> MBIST_DONE //
110 // tb_top.cpu.DBG_DQ[0]) ----> MBIST_FAIL //
111 $dumpvars(1,tb_top.cpu.DBG_CK0);
112 $dumpvars(1,tb_top.cpu.TRIGIN);
113 $dumpvars(1,tb_top.cpu.TRIGOUT);
114 $dumpvars(1,tb_top.cpu.tcu_sck_bypass);
115 $dumpvars(1,tb_top.cpu.tcu.mbist_ctl.bisx_counter);
116 $dumpvars(1,tb_top.cpu.tcu_rst_clk_stop);
117 $dumpvars(1,tb_top.cpu.tcu_rst_io_clk_stop);
118 $dumpvars(1,tb_top.cpu.tcu_efu_read_start);
119 $dumpvars(1,tb_top.cpu.tcu.tcu_mbist_start);
120 $dumpvars(1,tb_top.cpu.ncu.coreavail);
121
122
123 // FBDIMM //
124 $dumpvars(1,tb_top.cpu.FBDIMM0A_TX_P);
125 $dumpvars(1,tb_top.cpu.FBDIMM0A_TX_N);
126 $dumpvars(1,tb_top.cpu.FBDIMM0B_TX_P);
127 $dumpvars(1,tb_top.cpu.FBDIMM0B_TX_N);
128 $dumpvars(1,tb_top.cpu.FBDIMM1A_TX_P);
129 $dumpvars(1,tb_top.cpu.FBDIMM1A_TX_N);
130 $dumpvars(1,tb_top.cpu.FBDIMM1B_TX_P);
131 $dumpvars(1,tb_top.cpu.FBDIMM1B_TX_N);
132 $dumpvars(1,tb_top.cpu.FBDIMM2A_TX_P);
133 $dumpvars(1,tb_top.cpu.FBDIMM2A_TX_N);
134 $dumpvars(1,tb_top.cpu.FBDIMM2B_TX_P);
135 $dumpvars(1,tb_top.cpu.FBDIMM2B_TX_N);
136 $dumpvars(1,tb_top.cpu.FBDIMM3A_TX_P);
137 $dumpvars(1,tb_top.cpu.FBDIMM3A_TX_N);
138 $dumpvars(1,tb_top.cpu.FBDIMM3B_TX_P);
139 $dumpvars(1,tb_top.cpu.FBDIMM3B_TX_N);
140 $dumpvars(1,tb_top.cpu.FBDIMM0A_RX_P);
141 $dumpvars(1,tb_top.cpu.FBDIMM0A_RX_N);
142 $dumpvars(1,tb_top.cpu.FBDIMM0B_RX_P);
143 $dumpvars(1,tb_top.cpu.FBDIMM0B_RX_N);
144 $dumpvars(1,tb_top.cpu.FBDIMM1A_RX_P);
145 $dumpvars(1,tb_top.cpu.FBDIMM1A_RX_N);
146 $dumpvars(1,tb_top.cpu.FBDIMM1B_RX_P);
147 $dumpvars(1,tb_top.cpu.FBDIMM1B_RX_N);
148 $dumpvars(1,tb_top.cpu.FBDIMM2A_RX_P);
149 $dumpvars(1,tb_top.cpu.FBDIMM2A_RX_N);
150 $dumpvars(1,tb_top.cpu.FBDIMM2B_RX_P);
151 $dumpvars(1,tb_top.cpu.FBDIMM2B_RX_N);
152 $dumpvars(1,tb_top.cpu.FBDIMM3A_RX_P);
153 $dumpvars(1,tb_top.cpu.FBDIMM3A_RX_N);
154 $dumpvars(1,tb_top.cpu.FBDIMM3B_RX_P);
155 $dumpvars(1,tb_top.cpu.FBDIMM3B_RX_N);
156 $dumpvars(1,tb_top.cpu.FBDIMM0A_AMUX);
157 $dumpvars(1,tb_top.cpu.FBDIMM0B_AMUX);
158 $dumpvars(1,tb_top.cpu.FBDIMM1A_AMUX);
159 $dumpvars(1,tb_top.cpu.FBDIMM1B_AMUX);
160 $dumpvars(1,tb_top.cpu.FBDIMM2A_AMUX);
161 $dumpvars(1,tb_top.cpu.FBDIMM2B_AMUX);
162 $dumpvars(1,tb_top.cpu.FBDIMM3A_AMUX);
163 $dumpvars(1,tb_top.cpu.FBDIMM3B_AMUX);
164 $dumpvars(1,tb_top.cpu.mcu0_fsr0_data);
165 $dumpvars(1,tb_top.cpu.fsr0_mcu0_data);
166 $dumpvars(1,tb_top.cpu.mcu1_fsr2_data);
167 $dumpvars(1,tb_top.cpu.fsr2_mcu1_data);
168 $dumpvars(1,tb_top.cpu.mcu2_fsr4_data);
169 $dumpvars(1,tb_top.cpu.fsr4_mcu2_data);
170 $dumpvars(1,tb_top.cpu.mcu3_fsr6_data);
171 $dumpvars(1,tb_top.cpu.fsr6_mcu3_data);
172
173 // FLUSH-RESETS //
174 $dumpvars(1,tb_top.cpu.tcu.rst_tcu_flush_init_req);
175 $dumpvars(1,tb_top.cpu.tcu.tcu_rst_flush_init_ack);
176 $dumpvars(1,tb_top.cpu.tcu.rst_tcu_flush_stop_req);
177 $dumpvars(1,tb_top.cpu.tcu.tcu_rst_flush_stop_ack);
178 $dumpvars(1,tb_top.cpu.tcu.sigmux_ctl.clock_stop_active);
179 $dumpvars(1,tb_top.cpu.tcu_se_scancollar_in);
180 // $dumpvars(1,tb_top.cpu.rst.rst_fsm_ctl.rst_soc_run);
181 $dumpvars(1,tb_top.cpu.rst_ncu_unpark_thread);
182
183 // JTAG //
184 $dumpvars(1,tb_top.cpu.TCK);
185 $dumpvars(1,tb_top.cpu.TMS);
186 $dumpvars(1,tb_top.cpu.TDI);
187 $dumpvars(1,tb_top.cpu.TDO);
188 $dumpvars(1,tb_top.cpu.tcu.jtag_ctl.tap_state);
189 $dumpvars(1,tb_top.cpu.tcu.jtag_ctl.instr);
190 $dumpvars(1,tb_top.cpu.tcu.jtag_creg_addr);
191 $dumpvars(1,tb_top.cpu.tcu.jtag_ctl.jtag_creg_data);
192
193 // MISC. //
194 $dumpvars(1,tb_top.cpu.PMI);
195 $dumpvars(1,tb_top.cpu.PMO);
196 $dumpvars(1,tb_top.cpu.PGRM_EN);
197 $dumpvars(1,tb_top.cpu.VPP);
198 $dumpvars(1,tb_top.cpu.BURNIN);
199
200 // PCIE //
201 $dumpvars(1,tb_top.cpu.PEX_TX_P);
202 $dumpvars(1,tb_top.cpu.PEX_TX_N);
203 $dumpvars(1,tb_top.cpu.PEX_RX_P);
204 $dumpvars(1,tb_top.cpu.PEX_RX_N);
205 $dumpvars(1,tb_top.cpu.PEX_AMUX);
206// added this
207`ifndef FC_NO_PEU_T2
208`ifndef PEU_SYSTEMC_MODEL
209 $dumpvars(1,tb_top.cpu.peu.peu_mio_pipe_txdata);
210 $dumpvars(1,tb_top.cpu.peu.peu_mio_pipe_txdatak);
211`endif
212`endif
213 // RESETS //
214 $dumpvars(1,tb_top.cpu.PWRON_RST_L);
215 $dumpvars(1,tb_top.cpu.PB_RST_L);
216 $dumpvars(1,tb_top.cpu.BUTTON_XIR_L);
217 $dumpvars(1,tb_top.cpu.PEX_RESET_L);
218 $dumpvars(1,tb_top.cpu.TRST_L);
219 // $dumpvars(1,tb_top.cpu.sigmux_ctl.por_one);
220 // $dumpvars(1,tb_top.cpu.sigmux_ctl.por_two);
221 // $dumpvars(1,tb_top.cpu.sigmux_ctl.wmr_one);
222 // $dumpvars(1,tb_top.cpu.sigmux_ctl.wmr_two);
223 $dumpvars(1,tb_top.cpu.tcu.sigmux_ctl.jtag_por_active);
224 $dumpvars(1,tb_top.cpu.rst_l2_por_);
225 $dumpvars(1,tb_top.cpu.rst_l2_wmr_);
226 // $dumpvars(1,tb_top.cpu.sio.rst_por_);
227 // $dumpvars(1,tb_top.cpu.l2b0.rst_por_);
228 // $dumpvars(1,tb_top.cpu.l2b1.rst_por_);
229 // $dumpvars(1,tb_top.cpu.l2b2.rst_por_);
230 // $dumpvars(1,tb_top.cpu.l2b3.rst_por_);
231 // $dumpvars(1,tb_top.cpu.l2b4.rst_por_);
232 // $dumpvars(1,tb_top.cpu.l2b5.rst_por_);
233 // $dumpvars(1,tb_top.cpu.l2b6.rst_por_);
234 // $dumpvars(1,tb_top.cpu.l2b7.rst_por_);
235 // $dumpvars(1,tb_top.rst_por_);
236 // $dumpvars(1,tb_top.cpu.sio.rst_wmr_);
237 // $dumpvars(1,tb_top.cpu.l2b0.rst_wmr_);
238 // $dumpvars(1,tb_top.cpu.l2b1.rst_wmr_);
239 // $dumpvars(1,tb_top.cpu.l2b2.rst_wmr_);
240 // $dumpvars(1,tb_top.cpu.l2b3.rst_wmr_);
241 // $dumpvars(1,tb_top.cpu.l2b4.rst_wmr_);
242 // $dumpvars(1,tb_top.cpu.l2b5.rst_wmr_);
243 // $dumpvars(1,tb_top.cpu.l2b6.rst_wmr_);
244 // $dumpvars(1,tb_top.cpu.l2b7.rst_wmr_);
245 // $dumpvars(1,tb_top.rst_wmr_);
246 // $dumpvars(1,tb_top.cpu.rst.rst_dmu_peu_por_);
247 // $dumpvars(1,tb_top.cpu.rst.rst_dmu_peu_wmr_);
248 // $dumpvars(1,tb_top.cpu.rst.rst_niu_);
249 // $dumpvars(1,tb_top.cpu.rst_niu_wmr_);
250 $dumpvars(1,tb_top.cpu.rst.rst_mio_rst_state);
251 $dumpvars(1,tb_top.cpu.rst_ccu_pll_);
252 $dumpvars(1,tb_top.cpu.rst_ccu_);
253 $dumpvars(1,tb_top.cpu.tcu_efu_read_start);
254 $dumpvars(1,tb_top.cpu.efu.sbc_efa_word_addr);
255 $dumpvars(1,tb_top.cpu.tcu_rst_efu_done);
256 $dumpvars(1,tb_top.cpu.tcu_bisx_done);
257 $dumpvars(1,tb_top.cpu.ccu_serdes_dtm);
258 $dumpvars(1,tb_top.cpu.tcu.cycle_count);
259
260 // SSI //
261 $dumpvars(1,tb_top.cpu.SSI_SCK);
262 $dumpvars(1,tb_top.cpu.SSI_MOSI);
263 $dumpvars(1,tb_top.cpu.SSI_MISO);
264 $dumpvars(1,tb_top.cpu.SSI_EXT_INT_L);
265 $dumpvars(1,tb_top.cpu.SSI_SYNC_L);
266 $dumpvars(1,tb_top.cpu.ncu.ncu_ssitop_ctl.ncu_ssisif_ctl.ssi_sm);
267 $dumpvars(1,tb_top.cpu.ncu.ncu_ssitop_ctl.ncu_ssisif_ctl.ssi_sm_rst_l);
268
269 // STCI //
270 $dumpvars(1,tb_top.cpu.STCICLK);
271 $dumpvars(1,tb_top.cpu.STCICFG);
272 $dumpvars(1,tb_top.cpu.STCID);
273 $dumpvars(1,tb_top.cpu.STCIQ);
274
275 // TEST CONTROLS //
276 $dumpvars(1,tb_top.cpu.TESTCLKT);
277 $dumpvars(1,tb_top.cpu.TESTCLKR);
278 $dumpvars(1,tb_top.cpu.TESTMODE);
279 $dumpvars(1,tb_top.cpu.DIVIDER_BYPASS);
280 $dumpvars(1,tb_top.cpu.PLL_CMP_BYPASS);
281 // $dumpvars(1,tb_top.cpu.PLL_DR_BYPASS);
282 $dumpvars(1,tb_top.cpu.PWR_THRTTL_0);
283 $dumpvars(1,tb_top.cpu.PWR_THRTTL_1);
284 // $dumpvars(1,tb_top.cpu.SPARE);
285
286`ifndef FC_NO_NIU_T2
287 // XAUI //
288 $dumpvars(1,tb_top.cpu.XAUI_MDINT1_L);
289 $dumpvars(1,tb_top.cpu.XAUI_MDINT0_L);
290 $dumpvars(1,tb_top.cpu.XAUI0_TX_P);
291 $dumpvars(1,tb_top.cpu.XAUI0_TX_N);
292 $dumpvars(1,tb_top.cpu.XAUI0_RX_P);
293 $dumpvars(1,tb_top.cpu.XAUI0_RX_N);
294 $dumpvars(1,tb_top.cpu.XAUI1_TX_P);
295 $dumpvars(1,tb_top.cpu.XAUI1_TX_N);
296 $dumpvars(1,tb_top.cpu.XAUI1_RX_P);
297 $dumpvars(1,tb_top.cpu.XAUI1_RX_N);
298 $dumpvars(1,tb_top.cpu.XAUI0_AMUX);
299 $dumpvars(1,tb_top.cpu.XAUI0_LINK_LED);
300 $dumpvars(1,tb_top.cpu.XAUI0_ACT_LED);
301 $dumpvars(1,tb_top.cpu.XAUI1_AMUX);
302 $dumpvars(1,tb_top.cpu.XAUI1_LINK_LED);
303 $dumpvars(1,tb_top.cpu.XAUI1_ACT_LED);
304 $dumpvars(1,tb_top.cpu.XAUI_MDC);
305 $dumpvars(1,tb_top.cpu.XAUI_MDIO);
306 $dumpvars(1,tb_top.cpu.mdoe);
307`endif
308 end //}
309
310`endif
311
312end
Full OpenSPARC design & verification tarball including full HDL.