Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / vera / classes / asmToVeraIntf.vr
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: asmToVeraIntf.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36#include "globals.vri"
37#include "std_display_defines.vri"
38#include "std_display_class.vrh"
39#include "baseUtilsClass.vrh"
40#include "sparcBenchUtils.vrh"
41#include "utilsClass.vrh"
42#include "memArray.vrh"
43#include "baseAsmToVeraIntf.vrh"
44#include "generic_ev_packet.vrh"
45
46#include "pcg_defines.vri"
47//#include "pcg_types.vri"
48// added this to remove NIU for OpenSparc T2
49#ifndef FC_NO_NIU_T2
50#include "pack_db.vrh"
51#include "flow_db.vrh"
52#include "flow_db_tasks.vrh"
53#include "pg_top_pp.vrh"
54#include "pc_top_pp.vrh"
55#include "niu_tx_descp.vrh"
56#include "pcg_token.vrh"
57
58#ifndef FC_NO_PEU_VERA
59#include "Testbench.vrh"
60#endif
61#include "niu_tx_descp.vrh"
62#include "niu_tx_port.vrh"
63#include "pio_driver.vrh"
64#include "mac_pio_class.vrh"
65#include "bmac_util.vrh"
66#include "fflp_util.vrh"
67#include "niu_rxdmc.vrh"
68#include "pktConfig.vrh"
69#endif
70
71// #include <VeraListProgram.vrh>
72#include <ListMacros.vrh>
73
74//ras
75
76#include "ios_injerr.vrh"
77#include "ios_err_packet.vrh"
78#ifndef FC_NO_NIU_T2
79#include "sioniu_err_mon.vrh"
80#endif
81#include "siodmu_err_mon.vrh"
82#ifndef GATESIM
83#include "ios_err_interrupt.vrh"
84#endif
85
86// for JTAG - L2 access
87#include "tcu_siu_packet.vrh"
88extern tcu_siu_packet tcu_siu_pkt;
89extern reg [39:0] jtagDoneMemAddr;
90extern event e_StartJtag;
91
92
93// THE INTENT OF THIS FILE IS TO BE A BRIDGE TO OTHER CLASSES THAT
94// ACTUALLY DO THE TESTING. THIS FILE IS NOT THE PLACE TO TEST ANYTHING.
95// THE CODE IN HERE SHOULD BE MINIMAL AND SHOULD SIMPLY MAKE A ZERO TIME
96// CALL INTO THE CLASS THAT DOES THE REAL WORK.
97
98#ifndef FC_NO_NIU_T2
99extern CpktConfig pktConfig;
100extern RxDMAChannel rx_dma[32];
101extern CRDMC rdmc;
102#endif
103// extern class BaseAsmToVeraIntf;
104extern integer config_mb;
105extern integer config0_mb;
106extern integer config1_mb;
107extern integer flow_mb;
108//extern pg pack_gen[16];
109
110#ifndef FC_NO_PEU_VERA
111extern event e_StartPEUTest;
112extern integer asm2peu_mbox;
113#endif
114
115extern ios_ras_inj ras_injector;
116// extern ios_err_packet err_pkt;
117
118#ifndef GATESIM
119extern ios_err_interrupt_mon ras_interrupt;
120#endif
121
122#include "ssi.vrh"
123extern SSI bootrom;
124
125ExternVeraList(ios_err_packet);
126
127extern integer generic_ev_mbox; // mailbox for generic asm-to-vera user event 'generic_ev'
128
129
130
131class AsmToVeraIntf extends BaseAsmToVeraIntf {
132
133integer inj_result;
134integer p0_dma_chnl[];
135integer p1_dma_chnl[];
136
137
138#ifndef FC_NO_NIU_T2
139CMacTxPort MacTxPort[2];
140flow_desc flow_p0[];
141flow_desc flow_p1[];
142#endif
143 task new();
144
145 // generic user event
146 task generic_ev(
147 string arg1_str,
148 reg [63:0] arg2_64bits,
149 reg [63:0] arg3_64bits
150 );
151 // trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector) hex, w/no 64'h
152 // trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector, src, wait)
153 task intp(reg [5:0] tid = 0,
154 reg [63:0] type = 0,
155 reg [63:0] vec = 0,
156 integer src = 16, // 0-16 are ccx ports. 16 = NCU
157 integer wait = 0);
158
159 // dump actual RAM contents
160 // trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> dump_mem(addr, amount)
161 task dump_mem(reg [63:0] addr=0,
162 integer amount = 8);
163
164 // trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> extint(wait/delay)
165 task extint(integer wait = 0, integer width = 0);
166
167 task warmrst(integer wait = 0);
168
169 // SPC BFM will do a store. Pick correct port w/ BFM!!!
170 // trig_pc_d(1,...) -> store(cpu/ccxPort, addr, data)
171 task store(reg [7:0] ccxPortMask = 0,
172 reg [63:0] addr=0,
173 reg [63:0] data=0);
174
175task IosErrInj (string errtype, bit [15:0] ctag, bit [39:0] pa);
176task IosRandErrInj (string errtype, integer num_errs, integer weight);
177
178task jtagRdWrL2 (
179 reg [63:0] paAddr,
180 reg [63:0] data,
181 reg [63:0] jtagDoneAddrMem,
182 reg rdwr // =0 asm->VERA, =1 VERA->asm
183);
184
185
186#ifndef FC_NO_NIU_T2
187task pktGenConfig (
188 integer mac_port,
189 integer frame_type,
190 integer frame_class,
191 integer data_length,
192 (integer tx_multi_port = 0, integer data_length_p1 = -1)
193);
194
195task NIU_AddTxChannels (
196 integer mac_port,
197 integer dma_no,
198 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
199);
200
201task NIU_SetTxMaxBurst (
202 integer mac_port,
203 integer dma_no,
204 integer SetTxMaxBurst_Data,
205 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
206);
207
208task NIU_TxDMAActivate (
209 integer mac_port,
210 integer dma_activelist,
211 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
212);
213
214task NIU_InitTxDma (
215 integer mac_port,
216 integer dma_no,
217 bit Xlate,
218 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
219);
220
221task NIU_EXIT_chk (
222 integer mac_port
223);
224
225task NIU_SetTxRingKick (
226 integer mac_port,
227 integer dma_no,
228 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
229);
230
231task TxPktGen (
232 integer mac_port,
233 integer dmaport,
234 integer numofpacket,
235 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
236);
237
238task TxPktGen_int (
239 integer mac_port,
240 integer dmaport,
241 integer numofpacket,
242 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0)
243);
244
245task NIU_InitRxDma (
246 integer RxDmaChnlNo,
247 integer RxDescRingLen,
248 bit [39:0] RxRingStartAddr,
249 bit [63:0] RbrConfData,
250 integer RxInitKick,
251 bit Xlate,
252 (bit [15:0] rx_multi_dma = 16'h0)
253);
254
255task NIU_RxPktConf (
256 integer RxPktCnt,
257 (integer iport = 0)
258);
259
260task NIU_RxGenPkt (
261 integer mac_port,
262 integer RxDmaChnlNo,
263 integer RxPktCnt,
264 integer RxPktLen,
265 (integer rx_multi_PORT = 0, bit [15:0] rx_multi_DMA = 16'h0)
266);
267
268task NIU_internalrx (
269 integer mac_port,
270 integer RxDmaChnlNo,
271 integer RxPktCnt,
272 integer RxPktLen,
273 (integer rx_multi_port = 0, bit [15:0] rx_multi_dma = 16'h0)
274);
275#endif
276
277
278task marker(
279 string what,
280 reg [5:0] fromTid,
281 reg [63:0] pc
282);
283 // trig_pc_d(1,expr(@VA(.MAIN.lable) -> L2ErrTrapCount(register with trap count)
284 //task for fc random error injection in data array of L2
285 task L2ErrTrapCount(reg [8:0] count=0);
286
287task reset_now(
288 string what
289);
290
291#ifndef FC_NO_PEU_VERA
292task set_StartPEUTest ();
293task EnablePCIeEgCmd (string cmdType,
294 bit [63:0] addr,
295 bit [31:0] txLen,
296 bit [31:0] startData,
297 string err);
298
299task EnablePCIeIgCmd (string cmdType,
300 bit [63:0] StartAddr,
301 bit [63:0] EndAddr,
302 string txLen,
303 bit [31:0] NumCmds,
304 string err);
305#endif
306
307
308
309}
310
311
312task AsmToVeraIntf::new() {
313 probe_if.gOutOfBoot <= 64'h0;
314 random_rst_if.POR_from_UserEvent <= 0;
315 random_rst_if.PB_RST_from_UserEvent <= 0;
316}
317
318// generic user event
319task AsmToVeraIntf::generic_ev(string arg1_str,
320 reg [63:0] arg2_64bits,
321 reg [63:0] arg3_64bits)
322{
323 Generic_ev_packet pkt = new();
324 pkt.arg1_str = arg1_str;
325 pkt.arg2_64bits = arg2_64bits;
326 pkt.arg3_64bits = arg3_64bits;
327 mailbox_put (generic_ev_mbox, pkt);
328}
329// trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector) hex, w/no 64'h
330// trig_pc_d(kind, 64'h1234567812345678) -> intp(tid, type, vector, src, wait)
331task AsmToVeraIntf::intp(reg [5:0] tid = 0,
332 reg [63:0] type = 0,
333 reg [63:0] vec = 0,
334 integer src = DEV_NCU, // 0-16 are ccx ports. 16 = NCU
335 integer wait = 0)
336{
337
338 error("AsmToVeraIntf::intp is not coded yet for NCU RTL!!!\n");
339
340 fork {
341 repeat (wait) @(posedge CLOCK);
342 gUtil.sendIntr(tid,type,vec,src);
343 }
344 join none
345}
346
347// dump actual RAM contents
348// trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> dump_mem(addr, amount)
349task AsmToVeraIntf::dump_mem(reg [63:0] addr=0,
350 integer amount = 8)
351{
352 gMem.dumpMem(addr,amount);
353}
354
355// trig_pc_d(1,expr(@VA(.MAIN.T1_ext_intr_200), 16, 16)) -> extint(wait/delay)
356task AsmToVeraIntf::extint(integer wait = 0, integer width = 0)
357{
358// error("AsmToVeraIntf::extint is not coded yet\n");
359 bootrom.pulse_ssi_int_l(wait, width);
360}
361
362task AsmToVeraIntf::warmrst(integer wait = 0)
363{
364 error("AsmToVeraIntf::warmrst is not coded yet\n");
365}
366
367
368// SPC BFM will do a store. Pick correct port w/ BFM!!!
369// trig_pc_d(1,...) -> store(cpu/ccxPort, addr, data)
370task AsmToVeraIntf::store(reg [7:0] ccxPortMask = 0,
371 reg [63:0] addr=0,
372 reg [63:0] data=0)
373{
374 error("AsmToVeraIntf::store is not coded yet\n");
375}
376
377// ***********************************************************************************
378// JTAG Read/Write L2 Task
379// ***********************************************************************************
380task AsmToVeraIntf::jtagRdWrL2 (reg [63:0] paAddr=0,
381 reg [63:0] data=0,
382 reg [63:0] jtagDoneAddrMem=0,
383 reg rdwr=0) // rd=0 asm->VERA, wr=1 VERA->asm
384{
385 reg [63:0] header;
386
387 printf ("\n In jtagRdWr... setting StartJtag\n");
388 if (rdwr) { // VERA -> asm
389 header = {24'h820000, paAddr[39:0]}; // write operation
390 // save to share packet
391 tcu_siu_pkt.header = header;
392 tcu_siu_pkt.payload = data;
393 tcu_siu_pkt.type = JTAG_WR;
394 }
395 else { // asm -> VERA
396 header = {24'h810000, paAddr[39:0]}; // read operation
397 // save to share packet
398 tcu_siu_pkt.header = header;
399 tcu_siu_pkt.payload = data;
400 tcu_siu_pkt.type = JTAG_RD;
401 }
402 jtagDoneMemAddr = jtagDoneAddrMem[39:0]; // only 40 bits of PA are used
403 trigger (ON, e_StartJtag);
404}
405
406#ifndef FC_NO_NIU_T2
407// ***********************************************************************************
408// NIU Tx Tasks
409// ***********************************************************************************
410task AsmToVeraIntf::pktGenConfig (integer mac_port,
411 integer frame_type,
412 integer frame_class,
413 integer data_length,
414 (integer tx_multi_port = 0, integer data_length_p1 = -1))
415{
416//integer data_length;
417integer pkt_length;
418integer byte_incr;
419integer mark_bit;
420flow_desc flow0;
421flow_desc flow1;
422//TxPacketGenConfig config;
423TxPacketGenConfig config0;
424TxPacketGenConfig config1;
425
426if (tx_multi_port == 0)
427 {
428 if (mac_port == 0)
429 {
430 PR_INFO("fc_niu_asm_event", MON_INFO,
431 psprintf("KHH-TX Debug : Configuring TX PKTGEN for Port %0d", mac_port));
432 flow0= new;
433
434 flow0.frame.frame_type = frame_type; // 072105 flow0.frame.frame_type = 2;
435 flow0.frame.frame_class = frame_class; // 072105 flow0.frame.frame_class = CL_IP;
436 flow0.frame.type = -1;
437 flow0.frame.class_mask = 0;
438 flow0.frame.class_funct = CLF_SRC;
439 flow0.frame.data_type = DAT_SEQ|DAT_LEN_EXACT ;
440 flow0.frame.data_seed = 0;
441
442 flow0.src_node.l2_addr = 48'h00_a5_5a_a5_5a_a5; // flow0.src_node.l2_addr = 48'haaaa_1111_0000;
443 flow0.src_node.tci = random(); // flow0.src_node.tci = 16'hcb00;
444 flow0.src_node.ip_addr = random(); // IPv4 address of this substation // flow0.src_node.ip_addr = 32'hcccc_0000;
445 flow0.src_node.ipv6_addr = random();
446 // flow0.src_node.src_port = 20'h00001;
447
448
449
450 flow0.dst_node.l2_addr = 48'h00_55_55_55_55_55; // flow0.dst_node.l2_addr = 48'hdddd_bbbb_0000;
451 flow0.dst_node.tci = random(); // flow0.dst_node.tci = 16'hcb00;
452 flow0.dst_node.ip_addr = random(); // flow0.dst_node.ip_addr = 32'h8888_0000;
453 flow0.dst_node.ipv6_addr = random();
454 // flow0.dst_node.src_port = 20'h00001;
455
456 flow0.tup.src_tcp_udp_port = random(); // Source TCP/UDP Port // flow0.tup.src_tcp_udp_port = 16'h1234;
457 flow0.tup.dst_tcp_udp_port = random(); // Destination TCP/UDP Port // flow0.tup.dst_tcp_udp_port = 16'hABCD;
458
459 flow0.rx_param.rcv_isn = 32'h1357_abef; // flow0.rx_param.rcv_isn = 32'hA5A5_F5F5;
460
461 flow0.fl_state.tcp_flags = 6'b00_0010;
462
463 flow0.flow_no = 0;
464
465 flow0.partial_chksum = 1;
466
467 flow0.psu_hdr[0] = 8'hdc;
468 flow0.psu_hdr[1] = 8'h92;
469
470
471// if (get_plus_arg (CHECK, "TX_PKT_LEN"))
472// data_length = get_plus_arg (NUM, "TX_PKT_LEN");
473// else
474// data_length = 52; //MAQ: 020905 data_length = 64;
475
476 if( get_plus_arg (CHECK, "TX_PKT_SIZE_SWEEP")) {
477 byte_incr = get_plus_arg (NUM, "TX_PKT_INCR");
478 } else byte_incr = 0;
479
480 config0 = new();
481 config0.mac_id = mac_port;
482 config0.flow = flow0;
483
484 if (get_plus_arg (CHECK, "TX_INT_MARK"))
485 mark_bit = get_plus_arg (NUM, "TX_INT_MARK");
486 else
487 mark_bit = 0;
488
489 config0.mark_bit = mark_bit;
490
491//072005 pkt_length = data_length;
492//072005 if(pkt_length > 1500)
493//072005 pkt_length = data_length ;
494//072005 config.data_length = pkt_length;
495
496 config0.data_length = data_length;
497 if (get_plus_arg (CHECK, "TX_GATHER"))
498 config0.g_mode = 1;
499 else
500 config0.g_mode = 0;
501
502 mailbox_put (config0_mb, config0);
503 }
504 else if (mac_port == 1)
505 {
506 PR_INFO("fc_niu_asm_event", MON_INFO,
507 psprintf("KHH-TX Debug : Configuring TX PKTGEN for Port %0d", mac_port));
508 flow1= new;
509
510 flow1.frame.frame_type = frame_type; // 072105 flow1.frame.frame_type = 2;
511 flow1.frame.frame_class = frame_class; // 072105 flow1.frame.frame_class = CL_IP;
512 flow1.frame.type = -1;
513 flow1.frame.class_mask = 0;
514 flow1.frame.class_funct = CLF_SRC;
515 flow1.frame.data_type = DAT_SEQ|DAT_LEN_EXACT ;
516 flow1.frame.data_seed = 0;
517
518 flow1.src_node.l2_addr = 48'h00_b5_b6_b7_b8_b9; // flow1.src_node.l2_addr = 48'haaaa_1111_0000;
519 flow1.src_node.tci = random(); // flow1.src_node.tci = 16'hcb00;
520 flow1.src_node.ip_addr = random(); // IPv4 address of this substation // flow1.src_node.ip_addr = 32'hcccc_0000;
521 flow1.src_node.ipv6_addr = random();
522 // flow1.src_node.src_port = 20'h00001;
523
524 flow1.dst_node.l2_addr = 48'h00_65_66_67_68_69; // flow1.dst_node.l2_addr = 48'hdddd_bbbb_0000;
525 flow1.dst_node.tci = random(); // flow1.dst_node.tci = 16'hcb00;
526 flow1.dst_node.ip_addr = random(); // flow1.dst_node.ip_addr = 32'h8888_0000;
527 flow1.dst_node.ipv6_addr = random();
528 // flow1.dst_node.src_port = 20'h00001;
529
530 flow1.tup.src_tcp_udp_port = random(); // Source TCP/UDP Port // flow1.tup.src_tcp_udp_port = 16'h1234;
531 flow1.tup.dst_tcp_udp_port = random(); // Destination TCP/UDP Port // flow1.tup.dst_tcp_udp_port = 16'hABCD;
532
533 flow1.rx_param.rcv_isn = 32'h1213_1415; // flow1.rx_param.rcv_isn = 32'hA5A5_F5F5;
534
535 flow1.fl_state.tcp_flags = 6'b00_0010;
536
537 flow1.flow_no = 0;
538
539 flow1.partial_chksum = 1;
540
541 flow1.psu_hdr[0] = 8'hab;
542 flow1.psu_hdr[1] = 8'hcd;
543
544
545// if (get_plus_arg (CHECK, "TX_PKT_LEN"))
546// data_length = get_plus_arg (NUM, "TX_PKT_LEN");
547// else
548// data_length = 52; //MAQ: 020905 data_length = 64;
549
550 if( get_plus_arg (CHECK, "TX_PKT_SIZE_SWEEP")) {
551 byte_incr = get_plus_arg (NUM, "TX_PKT_INCR");
552 } else byte_incr = 0;
553
554 config1 = new();
555 config1.mac_id = mac_port;
556 config1.flow = flow1;
557
558 if (get_plus_arg (CHECK, "TX_INT_MARK"))
559 mark_bit = get_plus_arg (NUM, "TX_INT_MARK");
560 else
561 mark_bit = 0;
562
563 config1.mark_bit = mark_bit;
564
565//072005 pkt_length = data_length;
566//072005 if(pkt_length > 1500)
567//072005 pkt_length = data_length ;
568//072005 config.data_length = pkt_length;
569
570 config1.data_length = data_length;
571 if (get_plus_arg (CHECK, "TX_GATHER"))
572 config1.g_mode = 1;
573 else
574 config1.g_mode = 0;
575
576 mailbox_put (config1_mb, config1);
577 }
578 else
579 {
580 PR_ERROR("fc_niu_asm_event", MON_ERROR,
581 psprintf("pktGenConfig: Unexpected TX Port Value %0d", mac_port));
582 }
583 }
584else
585 {
586 mac_port = 0;
587 PR_INFO("fc_niu_asm_event", MON_INFO,
588 psprintf("KHH-TX Debug : Configuring TX PKTGEN for Port %0d", mac_port));
589 flow0= new;
590
591 flow0.frame.frame_type = frame_type; // 072105 flow0.frame.frame_type = 2;
592 flow0.frame.frame_class = frame_class; // 072105 flow0.frame.frame_class = CL_IP;
593 flow0.frame.type = -1;
594 flow0.frame.class_mask = 0;
595 flow0.frame.class_funct = CLF_SRC;
596 flow0.frame.data_type = DAT_SEQ|DAT_LEN_EXACT ;
597 flow0.frame.data_seed = 0;
598
599 flow0.src_node.l2_addr = 48'h00_a5_5a_a5_5a_a5; // flow0.src_node.l2_addr = 48'haaaa_1111_0000;
600 flow0.src_node.tci = random(); // flow0.src_node.tci = 16'hcb00;
601 flow0.src_node.ip_addr = random(); // IPv4 address of this substation // flow0.src_node.ip_addr = 32'hcccc_0000;
602 flow0.src_node.ipv6_addr = random();
603 // flow0.src_node.src_port = 20'h00001;
604
605 flow0.dst_node.l2_addr = 48'h00_55_55_55_55_55; // flow0.dst_node.l2_addr = 48'hdddd_bbbb_0000;
606 flow0.dst_node.tci = random(); // flow0.dst_node.tci = 16'hcb00;
607 flow0.dst_node.ip_addr = random(); // flow0.dst_node.ip_addr = 32'h8888_0000;
608 flow0.dst_node.ipv6_addr = random();
609 // flow0.dst_node.src_port = 20'h00001;
610
611 flow0.tup.src_tcp_udp_port = random(); // Source TCP/UDP Port // flow0.tup.src_tcp_udp_port = 16'h1234;
612 flow0.tup.dst_tcp_udp_port = random(); // Destination TCP/UDP Port // flow0.tup.dst_tcp_udp_port = 16'hABCD;
613
614 flow0.rx_param.rcv_isn = 32'h1357_abef; // flow0.rx_param.rcv_isn = 32'hA5A5_F5F5;
615
616 flow0.fl_state.tcp_flags = 6'b00_0010;
617
618 flow0.flow_no = 0;
619
620 flow0.partial_chksum = 1;
621
622 flow0.psu_hdr[0] = 8'hdc;
623 flow0.psu_hdr[1] = 8'h92;
624
625
626// if (get_plus_arg (CHECK, "TX_PKT_LEN"))
627// data_length = get_plus_arg (NUM, "TX_PKT_LEN");
628// else
629// data_length = 52; //MAQ: 020905 data_length = 64;
630
631 if( get_plus_arg (CHECK, "TX_PKT_SIZE_SWEEP")) {
632 byte_incr = get_plus_arg (NUM, "TX_PKT_INCR");
633 } else byte_incr = 0;
634
635 config0 = new();
636 config0.mac_id = mac_port;
637 config0.flow = flow0;
638
639 if (get_plus_arg (CHECK, "TX_INT_MARK"))
640 mark_bit = get_plus_arg (NUM, "TX_INT_MARK");
641 else
642 mark_bit = 0;
643
644 config0.mark_bit = mark_bit;
645
646//072005 pkt_length = data_length;
647//072005 if(pkt_length > 1500)
648//072005 pkt_length = data_length ;
649//072005 config.data_length = pkt_length;
650
651 config0.data_length = data_length;
652 if (get_plus_arg (CHECK, "TX_GATHER"))
653 config0.g_mode = 1;
654 else
655 config0.g_mode = 0;
656
657 mailbox_put (config0_mb, config0);
658
659 mac_port = 1;
660
661 PR_INFO("fc_niu_asm_event", MON_INFO,
662 psprintf("KHH-TX Debug : Configuring TX PKTGEN for Port %0d", mac_port));
663 flow1= new;
664
665 flow1.frame.frame_type = frame_type; // 072105 flow1.frame.frame_type = 2;
666 flow1.frame.frame_class = frame_class; // 072105 flow1.frame.frame_class = CL_IP;
667 flow1.frame.type = -1;
668 flow1.frame.class_mask = 0;
669 flow1.frame.class_funct = CLF_SRC;
670 flow1.frame.data_type = DAT_SEQ|DAT_LEN_EXACT ;
671 flow1.frame.data_seed = 0;
672
673 flow1.src_node.l2_addr = 48'h00_b5_b6_b7_b8_b9; // flow1.src_node.l2_addr = 48'haaaa_1111_0000;
674 flow1.src_node.tci = random(); // flow1.src_node.tci = 16'hcb00;
675 flow1.src_node.ip_addr = random(); // IPv4 address of this substation // flow1.src_node.ip_addr = 32'hcccc_0000;
676 flow1.src_node.ipv6_addr = random();
677 // flow1.src_node.src_port = 20'h00001;
678
679 flow1.dst_node.l2_addr = 48'h00_65_66_67_68_69; // flow1.dst_node.l2_addr = 48'hdddd_bbbb_0000;
680 flow1.dst_node.tci = random(); // flow1.dst_node.tci = 16'hcb00;
681 flow1.dst_node.ip_addr = random(); // flow1.dst_node.ip_addr = 32'h8888_0000;
682 flow1.dst_node.ipv6_addr = random();
683 // flow1.dst_node.src_port = 20'h00001;
684
685 flow1.tup.src_tcp_udp_port = random(); // Source TCP/UDP Port // flow1.tup.src_tcp_udp_port = 16'h1234;
686 flow1.tup.dst_tcp_udp_port = random(); // Destination TCP/UDP Port // flow1.tup.dst_tcp_udp_port = 16'hABCD;
687
688 flow1.rx_param.rcv_isn = 32'h1213_1415; // flow1.rx_param.rcv_isn = 32'hA5A5_F5F5;
689
690 flow1.fl_state.tcp_flags = 6'b00_0010;
691
692 flow1.flow_no = 0;
693
694 flow1.partial_chksum = 1;
695
696 flow1.psu_hdr[0] = 8'hab;
697 flow1.psu_hdr[1] = 8'hcd;
698
699
700// if (get_plus_arg (CHECK, "TX_PKT_LEN"))
701// data_length = get_plus_arg (NUM, "TX_PKT_LEN");
702// else
703// data_length = 52; //MAQ: 020905 data_length = 64;
704
705 if( get_plus_arg (CHECK, "TX_PKT_SIZE_SWEEP")) {
706 byte_incr = get_plus_arg (NUM, "TX_PKT_INCR");
707 } else byte_incr = 0;
708
709 config1 = new();
710 config1.mac_id = mac_port;
711 config1.flow = flow1;
712
713 if (get_plus_arg (CHECK, "TX_INT_MARK"))
714 mark_bit = get_plus_arg (NUM, "TX_INT_MARK");
715 else
716 mark_bit = 0;
717
718 config1.mark_bit = mark_bit;
719
720//072005 pkt_length = data_length;
721//072005 if(pkt_length > 1500)
722//072005 pkt_length = data_length ;
723//072005 config.data_length = pkt_length;
724
725 if (data_length_p1 == -1)
726 {
727 data_length_p1 = 80;
728 }
729 config1.data_length = data_length_p1;
730 if (get_plus_arg (CHECK, "TX_GATHER"))
731 config1.g_mode = 1;
732 else
733 config1.g_mode = 0;
734
735 mailbox_put (config1_mb, config1);
736 }
737}
738
739// ***********************************************************************************
740task AsmToVeraIntf::NIU_SetTxRingKick (integer mac_port, integer dma_no,
741 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
742{
743
744 PR_INFO("fc_niu_asm_event", MON_INFO,
745 psprintf("KHH-TX Debug : B4 FOR NIU_SetTxRingKick, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
746 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
747 {
748 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
749 }
750 PR_INFO("fc_niu_asm_event", MON_INFO,
751 psprintf("KHH-TX Debug : AF FOR NIU_SetTxRingKick, NIU_TX_MULTI_PORT = %0d & NIU_TX_MULTI_DMA_P0 = %h MODE", tx_multi_port, tx_multi_dma_p0));
752 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
753 {
754 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
755 }
756 PR_INFO("fc_niu_asm_event", MON_INFO,
757 psprintf("KHH-TX Debug : AF FOR NIU_SetTxRingKick, NIU_TX_MULTI_PORT = %0d & NIU_TX_MULTI_DMA_P1 = %h MODE", tx_multi_port, tx_multi_dma_p1));
758
759 if (tx_multi_dma_p1[15:0] & tx_multi_dma_p0[15:0])
760 {
761 PR_ERROR("fc_niu_asm_event", MON_ERROR,
762 psprintf("NIU_SetTxRingKick: Same DMA assigned to multiple ports: TX_MULTI_DMA_P0 = 0x%h, TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
763 }
764
765 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
766 {
767 PR_INFO("fc_niu_asm_event", MON_INFO,
768 psprintf("MAQ-Debug : B4 setTxRingKick ring_current_addr = %h", MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr));
769 MacTxPort[mac_port].dma[dma_no].setTxRingKick(MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr);
770 PR_INFO("fc_niu_asm_event", MON_INFO,
771 "MAQ-Debug : After setTxRingKick");
772 }
773 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
774 {
775 PR_INFO("fc_niu_asm_event", MON_INFO,
776 psprintf("KHH-TX Debug : FOR NIU_SetTxRingKick, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h, MAC_PORT = %0d, DMA_NO = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1, mac_port, dma_no));
777 PR_INFO("fc_niu_asm_event", MON_INFO,
778 psprintf("KHH-Debug : P0 TX_DMA0 setTxRingKick ring_current_addr = %h", MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr));
779 MacTxPort[mac_port].dma[dma_no].setTxRingKick(MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr);
780 }
781 else if (tx_multi_port == 1 && (tx_multi_dma_p1[15:0] == 16'h0 || tx_multi_dma_p0[15:0] == 16'h0))
782 {
783 PR_ERROR("fc_niu_asm_event", MON_ERROR,
784 psprintf("NIU_SetTxRingKick: For NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_dma_p0, tx_multi_dma_p1));
785 }
786 else if (tx_multi_port == 1 && tx_multi_dma_p1[15:0] > 16'h0 && tx_multi_dma_p0[15:0] > 16'h0)
787 {
788 PR_INFO("fc_niu_asm_event", MON_INFO,
789 psprintf("KHH-TX Debug : FOR NIU_SetTxRingKick, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h, MAC_PORT = %0d & DMA_NO = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1, mac_port, dma_no));
790 PR_INFO("fc_niu_asm_event", MON_INFO,
791 psprintf("KHH-Debug : P0 TX_DMA0 setTxRingKick ring_current_addr = %h", MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr));
792 MacTxPort[mac_port].dma[dma_no].setTxRingKick(MacTxPort[mac_port].dma[dma_no].desc_ring.ring_current_addr);
793 }
794 else
795 {
796 PR_ERROR("fc_niu_asm_event", MON_ERROR,
797 psprintf("NIU_SetTxRingKick: Invalid combination for NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
798 }
799}
800
801// ***********************************************************************************
802task AsmToVeraIntf::NIU_AddTxChannels (integer mac_port, integer dma_no,
803 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
804{
805
806 PR_INFO("fc_niu_asm_event", MON_INFO,
807 psprintf("KHH-TX Debug : FOR NIU_AddTxChannels, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
808 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
809 {
810 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
811 }
812 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
813 {
814 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
815 }
816/*
817 if (tx_multi_dma_p1[15:0] & tx_multi_dma_p0[15:0])
818 {
819 printf("ERROR : NIU_AddTxChannels, FOR TX_MULTI_DMA_P0 = %h, same dma assigned to multiple ports.\n", tx_multi_dma_p0);
820 printf("ERROR : NIU_AddTxChannels, FOR TX_MULTI_DMA_P1 = %h, same dma assigned to multiple ports.\n", tx_multi_dma_p1);
821 }
822 else
823 {
824 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
825 {
826 printf("KHH-TX Debug : FOR NIU_AddTxChannels, MAC_PORT = %d & DMA_NO = %d.\n", mac_port, dma_no);
827 MacTxPort[mac_port].add_channels(dma_no);
828 }
829 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
830 {
831 printf("KHH-TX Debug : FOR NIU_AddTxChannels, NIU_TX_MULTI_PORT = %d & NIU_TX_MULTI_DMA_P0 = %h MODE.\n", tx_multi_port, tx_multi_dma_p0);
832 printf("KHH-TX Debug : FOR NIU_AddTxChannels, NIU_TX_MULTI_PORT = %d & NIU_TX_MULTI_DMA_P1 = %h MODE.\n", tx_multi_port, tx_multi_dma_p1);
833 if (mac_port == 0)
834 {
835 if (tx_multi_dma_p0[0] == 1'b1)
836 {
837 MacTxPort[mac_port].add_channels(0);
838 }
839 if (tx_multi_dma_p0[1] == 1'b1)
840 {
841 MacTxPort[mac_port].add_channels(1);
842 }
843 if (tx_multi_dma_p0[2] == 1'b1)
844 {
845 MacTxPort[mac_port].add_channels(2);
846 }
847 if (tx_multi_dma_p0[3] == 1'b1)
848 {
849 MacTxPort[mac_port].add_channels(3);
850 }
851 if (tx_multi_dma_p0[4] == 1'b1)
852 {
853 MacTxPort[mac_port].add_channels(4);
854 }
855 if (tx_multi_dma_p0[5] == 1'b1)
856 {
857 MacTxPort[mac_port].add_channels(5);
858 }
859 if (tx_multi_dma_p0[6] == 1'b1)
860 {
861 MacTxPort[mac_port].add_channels(6);
862 }
863 if (tx_multi_dma_p0[7] == 1'b1)
864 {
865 MacTxPort[mac_port].add_channels(7);
866 }
867 if (tx_multi_dma_p0[8] == 1'b1)
868 {
869 MacTxPort[mac_port].add_channels(8);
870 }
871 if (tx_multi_dma_p0[9] == 1'b1)
872 {
873 MacTxPort[mac_port].add_channels(9);
874 }
875 if (tx_multi_dma_p0[10] == 1'b1)
876 {
877 MacTxPort[mac_port].add_channels(10);
878 }
879 if (tx_multi_dma_p0[11] == 1'b1)
880 {
881 MacTxPort[mac_port].add_channels(11);
882 }
883 if (tx_multi_dma_p0[12] == 1'b1)
884 {
885 MacTxPort[mac_port].add_channels(12);
886 }
887 if (tx_multi_dma_p0[13] == 1'b1)
888 {
889 MacTxPort[mac_port].add_channels(13);
890 }
891 if (tx_multi_dma_p0[14] == 1'b1)
892 {
893 MacTxPort[mac_port].add_channels(14);
894 }
895 if (tx_multi_dma_p0[15] == 1'b1)
896 {
897 MacTxPort[mac_port].add_channels(15);
898 }
899 }
900 else if (mac_port == 1)
901 {
902 if (tx_multi_dma_p1[0] == 1'b1)
903 {
904 MacTxPort[mac_port].add_channels(0);
905 }
906 if (tx_multi_dma_p1[1] == 1'b1)
907 {
908 MacTxPort[mac_port].add_channels(1);
909 }
910 if (tx_multi_dma_p1[2] == 1'b1)
911 {
912 MacTxPort[mac_port].add_channels(2);
913 }
914 if (tx_multi_dma_p1[3] == 1'b1)
915 {
916 MacTxPort[mac_port].add_channels(3);
917 }
918 if (tx_multi_dma_p1[4] == 1'b1)
919 {
920 MacTxPort[mac_port].add_channels(4);
921 }
922 if (tx_multi_dma_p1[5] == 1'b1)
923 {
924 MacTxPort[mac_port].add_channels(5);
925 }
926 if (tx_multi_dma_p1[6] == 1'b1)
927 {
928 MacTxPort[mac_port].add_channels(6);
929 }
930 if (tx_multi_dma_p1[7] == 1'b1)
931 {
932 MacTxPort[mac_port].add_channels(7);
933 }
934 if (tx_multi_dma_p1[8] == 1'b1)
935 {
936 MacTxPort[mac_port].add_channels(8);
937 }
938 if (tx_multi_dma_p1[9] == 1'b1)
939 {
940 MacTxPort[mac_port].add_channels(9);
941 }
942 if (tx_multi_dma_p1[10] == 1'b1)
943 {
944 MacTxPort[mac_port].add_channels(10);
945 }
946 if (tx_multi_dma_p1[11] == 1'b1)
947 {
948 MacTxPort[mac_port].add_channels(11);
949 }
950 if (tx_multi_dma_p1[12] == 1'b1)
951 {
952 MacTxPort[mac_port].add_channels(12);
953 }
954 if (tx_multi_dma_p1[13] == 1'b1)
955 {
956 MacTxPort[mac_port].add_channels(13);
957 }
958 if (tx_multi_dma_p1[14] == 1'b1)
959 {
960 MacTxPort[mac_port].add_channels(14);
961 }
962 if (tx_multi_dma_p1[15] == 1'b1)
963 {
964 MacTxPort[mac_port].add_channels(15);
965 }
966 }
967 else
968 {
969 printf("KHH-TX ERROR : FOR NIU_AddTxChannels, Unexpected TX Port Value %d.\n", mac_port);
970 }
971 }
972 else if (tx_multi_port == 1 && (tx_multi_dma_p0[15:0] == 16'h0 || tx_multi_dma_p1[15:0] == 16'h0))
973 {
974 printf("KHH-TX ERROR : FOR NIU_AddTxChannels, FOR NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = %h.\n", tx_multi_dma_p0);
975 printf("KHH-TX ERROR : FOR NIU_AddTxChannels, FOR NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P1 = %h.\n", tx_multi_dma_p1);
976 }
977 else if (tx_multi_port == 1 && tx_multi_dma_p0[15:0] > 16'h0 && tx_multi_dma_p1[15:0] > 16'h0)
978 {
979 printf("KHH-TX Debug : FOR NIU_AddTxChannels, NIU_TX_MULTI_PORT = %d & NIU_TX_MULTI_DMA_P0 = %h MODE.\n", tx_multi_port, tx_multi_dma_p0);
980 printf("KHH-TX Debug : FOR NIU_AddTxChannels, NIU_TX_MULTI_PORT = %d & NIU_TX_MULTI_DMA_P1 = %h MODE.\n", tx_multi_port, tx_multi_dma_p1);
981 mac_port = 0;
982 if (tx_multi_dma_p0[0] == 1'b1)
983 {
984 printf("KHH-TX Debug : FOR DMA0 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
985 MacTxPort[mac_port].add_channels(0);
986 }
987 if (tx_multi_dma_p0[1] == 1'b1)
988 {
989 printf("KHH-TX Debug : FOR DMA1 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
990 MacTxPort[mac_port].add_channels(1);
991 }
992 if (tx_multi_dma_p0[2] == 1'b1)
993 {
994 printf("KHH-TX Debug : FOR DMA2 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
995 MacTxPort[mac_port].add_channels(2);
996 }
997 if (tx_multi_dma_p0[3] == 1'b1)
998 {
999 printf("KHH-TX Debug : FOR DMA3 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1000 MacTxPort[mac_port].add_channels(3);
1001 }
1002 if (tx_multi_dma_p0[4] == 1'b1)
1003 {
1004 printf("KHH-TX Debug : FOR DMA4 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1005 MacTxPort[mac_port].add_channels(4);
1006 }
1007 if (tx_multi_dma_p0[5] == 1'b1)
1008 {
1009 printf("KHH-TX Debug : FOR DMA5 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1010 MacTxPort[mac_port].add_channels(5);
1011 }
1012 if (tx_multi_dma_p0[6] == 1'b1)
1013 {
1014 printf("KHH-TX Debug : FOR DMA6 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1015 MacTxPort[mac_port].add_channels(6);
1016 }
1017 if (tx_multi_dma_p0[7] == 1'b1)
1018 {
1019 printf("KHH-TX Debug : FOR DMA7 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1020 MacTxPort[mac_port].add_channels(7);
1021 }
1022 if (tx_multi_dma_p0[8] == 1'b1)
1023 {
1024 printf("KHH-TX Debug : FOR DMA8 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1025 MacTxPort[mac_port].add_channels(8);
1026 }
1027 if (tx_multi_dma_p0[9] == 1'b1)
1028 {
1029 printf("KHH-TX Debug : FOR DMA9 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1030 MacTxPort[mac_port].add_channels(9);
1031 }
1032 if (tx_multi_dma_p0[10] == 1'b1)
1033 {
1034 printf("KHH-TX Debug : FOR DMA10 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1035 MacTxPort[mac_port].add_channels(10);
1036 }
1037 if (tx_multi_dma_p0[11] == 1'b1)
1038 {
1039 printf("KHH-TX Debug : FOR DMA11 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1040 MacTxPort[mac_port].add_channels(11);
1041 }
1042 if (tx_multi_dma_p0[12] == 1'b1)
1043 {
1044 printf("KHH-TX Debug : FOR DMA12 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1045 MacTxPort[mac_port].add_channels(12);
1046 }
1047 if (tx_multi_dma_p0[13] == 1'b1)
1048 {
1049 printf("KHH-TX Debug : FOR DMA13 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1050 MacTxPort[mac_port].add_channels(13);
1051 }
1052 if (tx_multi_dma_p0[14] == 1'b1)
1053 {
1054 printf("KHH-TX Debug : FOR DMA14 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1055 MacTxPort[mac_port].add_channels(14);
1056 }
1057 if (tx_multi_dma_p0[15] == 1'b1)
1058 {
1059 printf("KHH-TX Debug : FOR DMA15 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1060 MacTxPort[mac_port].add_channels(15);
1061 }
1062 mac_port = 1;
1063 if (tx_multi_dma_p1[0] == 1'b1)
1064 {
1065 printf("KHH-TX Debug : FOR DMA0 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1066 MacTxPort[mac_port].add_channels(0);
1067 }
1068 if (tx_multi_dma_p1[1] == 1'b1)
1069 {
1070 printf("KHH-TX Debug : FOR DMA1 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1071 MacTxPort[mac_port].add_channels(1);
1072 }
1073 if (tx_multi_dma_p1[2] == 1'b1)
1074 {
1075 printf("KHH-TX Debug : FOR DMA2 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1076 MacTxPort[mac_port].add_channels(2);
1077 }
1078 if (tx_multi_dma_p1[3] == 1'b1)
1079 {
1080 printf("KHH-TX Debug : FOR DMA3 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1081 MacTxPort[mac_port].add_channels(3);
1082 }
1083 if (tx_multi_dma_p1[4] == 1'b1)
1084 {
1085 printf("KHH-TX Debug : FOR DMA4 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1086 MacTxPort[mac_port].add_channels(4);
1087 }
1088 if (tx_multi_dma_p1[5] == 1'b1)
1089 {
1090 printf("KHH-TX Debug : FOR DMA5 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1091 MacTxPort[mac_port].add_channels(5);
1092 }
1093 if (tx_multi_dma_p1[6] == 1'b1)
1094 {
1095 printf("KHH-TX Debug : FOR DMA6 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1096 MacTxPort[mac_port].add_channels(6);
1097 }
1098 if (tx_multi_dma_p1[7] == 1'b1)
1099 {
1100 printf("KHH-TX Debug : FOR DMA7 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1101 MacTxPort[mac_port].add_channels(7);
1102 }
1103 if (tx_multi_dma_p1[8] == 1'b1)
1104 {
1105 printf("KHH-TX Debug : FOR DMA8 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1106 MacTxPort[mac_port].add_channels(8);
1107 }
1108 if (tx_multi_dma_p1[9] == 1'b1)
1109 {
1110 printf("KHH-TX Debug : FOR DMA9 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1111 MacTxPort[mac_port].add_channels(9);
1112 }
1113 if (tx_multi_dma_p1[10] == 1'b1)
1114 {
1115 printf("KHH-TX Debug : FOR DMA10 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1116 MacTxPort[mac_port].add_channels(10);
1117 }
1118 if (tx_multi_dma_p1[11] == 1'b1)
1119 {
1120 printf("KHH-TX Debug : FOR DMA11 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1121 MacTxPort[mac_port].add_channels(11);
1122 }
1123 if (tx_multi_dma_p1[12] == 1'b1)
1124 {
1125 printf("KHH-TX Debug : FOR DMA12 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1126 MacTxPort[mac_port].add_channels(12);
1127 }
1128 if (tx_multi_dma_p1[13] == 1'b1)
1129 {
1130 printf("KHH-TX Debug : FOR DMA13 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1131 MacTxPort[mac_port].add_channels(13);
1132 }
1133 if (tx_multi_dma_p1[14] == 1'b1)
1134 {
1135 printf("KHH-TX Debug : FOR DMA14 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1136 MacTxPort[mac_port].add_channels(14);
1137 }
1138 if (tx_multi_dma_p1[15] == 1'b1)
1139 {
1140 printf("KHH-TX Debug : FOR DMA15 NIU_AddTxChannels FOR PORT %d.\n", mac_port);
1141 MacTxPort[mac_port].add_channels(15);
1142 }
1143 }
1144 else
1145 {
1146 printf("KHH-TX ERROR : FOR NIU_AddTxChannels, INVALID COMBINATION FOR NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = %h.\n",tx_multi_port, tx_multi_dma_p0);
1147 printf("KHH-TX ERROR : FOR NIU_AddTxChannels, INVALID COMBINATION FOR NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P1 = %h.\n",tx_multi_port, tx_multi_dma_p1);
1148 }
1149 }
1150*/
1151}
1152
1153// ***********************************************************************************
1154task AsmToVeraIntf::NIU_SetTxMaxBurst (integer mac_port, integer dma_no, integer SetTxMaxBurst_Data,
1155 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
1156{
1157integer mac_id = mac_port;
1158
1159 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
1160 {
1161 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
1162 }
1163 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
1164 {
1165 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
1166 }
1167
1168 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
1169 {
1170 PR_INFO("fc_niu_asm_event", MON_INFO,
1171 psprintf("KHH-TX Debug : FOR NIU_SetTxMaxBurst, MAC_ID = %0d & DMA_NO = %0d", mac_id, dma_no));
1172 MacTxPort[mac_id].dma[dma_no].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1173 }
1174 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
1175 {
1176 PR_INFO("fc_niu_asm_event", MON_INFO,
1177 psprintf("KHH-TX Debug : FOR NIU_SetTxMaxBurst, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1178 if (mac_id == 0)
1179 {
1180 if (tx_multi_dma_p0[0] == 1'b1)
1181 {
1182 MacTxPort[mac_id].dma[0].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1183 }
1184 if (tx_multi_dma_p0[1] == 1'b1)
1185 {
1186 MacTxPort[mac_id].dma[1].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1187 }
1188 if (tx_multi_dma_p0[2] == 1'b1)
1189 {
1190 MacTxPort[mac_id].dma[2].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1191 }
1192 if (tx_multi_dma_p0[3] == 1'b1)
1193 {
1194 MacTxPort[mac_id].dma[3].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1195 }
1196 if (tx_multi_dma_p0[4] == 1'b1)
1197 {
1198 MacTxPort[mac_id].dma[4].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1199 }
1200 if (tx_multi_dma_p0[5] == 1'b1)
1201 {
1202 MacTxPort[mac_id].dma[5].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1203 }
1204 if (tx_multi_dma_p0[6] == 1'b1)
1205 {
1206 MacTxPort[mac_id].dma[6].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1207 }
1208 if (tx_multi_dma_p0[7] == 1'b1)
1209 {
1210 MacTxPort[mac_id].dma[7].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1211 }
1212 if (tx_multi_dma_p0[8] == 1'b1)
1213 {
1214 MacTxPort[mac_id].dma[8].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1215 }
1216 if (tx_multi_dma_p0[9] == 1'b1)
1217 {
1218 MacTxPort[mac_id].dma[9].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1219 }
1220 if (tx_multi_dma_p0[10] == 1'b1)
1221 {
1222 MacTxPort[mac_id].dma[10].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1223 }
1224 if (tx_multi_dma_p0[11] == 1'b1)
1225 {
1226 MacTxPort[mac_id].dma[11].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1227 }
1228 if (tx_multi_dma_p0[12] == 1'b1)
1229 {
1230 MacTxPort[mac_id].dma[12].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1231 }
1232 if (tx_multi_dma_p0[13] == 1'b1)
1233 {
1234 MacTxPort[mac_id].dma[13].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1235 }
1236 if (tx_multi_dma_p0[14] == 1'b1)
1237 {
1238 MacTxPort[mac_id].dma[14].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1239 }
1240 if (tx_multi_dma_p0[15] == 1'b1)
1241 {
1242 MacTxPort[mac_id].dma[15].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1243 }
1244 }
1245 else if (mac_id == 1)
1246 {
1247 if (tx_multi_dma_p1[0] == 1'b1)
1248 {
1249 MacTxPort[mac_id].dma[0].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1250 }
1251 if (tx_multi_dma_p1[1] == 1'b1)
1252 {
1253 MacTxPort[mac_id].dma[1].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1254 }
1255 if (tx_multi_dma_p1[2] == 1'b1)
1256 {
1257 MacTxPort[mac_id].dma[2].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1258 }
1259 if (tx_multi_dma_p1[3] == 1'b1)
1260 {
1261 MacTxPort[mac_id].dma[3].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1262 }
1263 if (tx_multi_dma_p1[4] == 1'b1)
1264 {
1265 MacTxPort[mac_id].dma[4].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1266 }
1267 if (tx_multi_dma_p1[5] == 1'b1)
1268 {
1269 MacTxPort[mac_id].dma[5].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1270 }
1271 if (tx_multi_dma_p1[6] == 1'b1)
1272 {
1273 MacTxPort[mac_id].dma[6].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1274 }
1275 if (tx_multi_dma_p1[7] == 1'b1)
1276 {
1277 MacTxPort[mac_id].dma[7].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1278 }
1279 if (tx_multi_dma_p1[8] == 1'b1)
1280 {
1281 MacTxPort[mac_id].dma[8].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1282 }
1283 if (tx_multi_dma_p1[9] == 1'b1)
1284 {
1285 MacTxPort[mac_id].dma[9].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1286 }
1287 if (tx_multi_dma_p1[10] == 1'b1)
1288 {
1289 MacTxPort[mac_id].dma[10].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1290 }
1291 if (tx_multi_dma_p1[11] == 1'b1)
1292 {
1293 MacTxPort[mac_id].dma[11].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1294 }
1295 if (tx_multi_dma_p1[12] == 1'b1)
1296 {
1297 MacTxPort[mac_id].dma[12].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1298 }
1299 if (tx_multi_dma_p1[13] == 1'b1)
1300 {
1301 MacTxPort[mac_id].dma[13].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1302 }
1303 if (tx_multi_dma_p1[14] == 1'b1)
1304 {
1305 MacTxPort[mac_id].dma[14].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1306 }
1307 if (tx_multi_dma_p1[15] == 1'b1)
1308 {
1309 MacTxPort[mac_id].dma[15].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1310 }
1311 }
1312 else
1313 {
1314 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1315 psprintf("NIU_SetTxMaxBurst: Unexpected TX Port Value %0d", mac_port));
1316 }
1317 }
1318 else if (tx_multi_port == 1 && (tx_multi_dma_p0[15:0] == 16'h0 || tx_multi_dma_p1[15:0] == 16'h0))
1319 {
1320 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1321 psprintf("NIU_SetTxMaxBurst: NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_dma_p0, tx_multi_dma_p1));
1322 }
1323 else if (tx_multi_port == 1 && tx_multi_dma_p0[15:0] > 16'h0 && tx_multi_dma_p1[15:0] > 16'h0)
1324 {
1325 if (tx_multi_dma_p1[15:0] & tx_multi_dma_p0[15:0])
1326 {
1327 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1328 psprintf("NIU_SetTxMaxBurst: Same DMA assigned to multiple ports: TX_MULTI_DMA_P0 = 0x%h, TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
1329 }
1330 else
1331 {
1332 PR_INFO("fc_niu_asm_event", MON_INFO,
1333 psprintf("KHH-TX Debug : FOR NIU_SetTxMaxBurst, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1334 mac_id = 0;
1335 if (tx_multi_dma_p0[0] == 1'b1)
1336 {
1337 MacTxPort[mac_id].dma[0].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1338 }
1339 if (tx_multi_dma_p0[1] == 1'b1)
1340 {
1341 MacTxPort[mac_id].dma[1].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1342 }
1343 if (tx_multi_dma_p0[2] == 1'b1)
1344 {
1345 MacTxPort[mac_id].dma[2].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1346 }
1347 if (tx_multi_dma_p0[3] == 1'b1)
1348 {
1349 MacTxPort[mac_id].dma[3].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1350 }
1351 if (tx_multi_dma_p0[4] == 1'b1)
1352 {
1353 MacTxPort[mac_id].dma[4].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1354 }
1355 if (tx_multi_dma_p0[5] == 1'b1)
1356 {
1357 MacTxPort[mac_id].dma[5].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1358 }
1359 if (tx_multi_dma_p0[6] == 1'b1)
1360 {
1361 MacTxPort[mac_id].dma[6].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1362 }
1363 if (tx_multi_dma_p0[7] == 1'b1)
1364 {
1365 MacTxPort[mac_id].dma[7].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1366 }
1367 if (tx_multi_dma_p0[8] == 1'b1)
1368 {
1369 MacTxPort[mac_id].dma[8].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1370 }
1371 if (tx_multi_dma_p0[9] == 1'b1)
1372 {
1373 MacTxPort[mac_id].dma[9].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1374 }
1375 if (tx_multi_dma_p0[10] == 1'b1)
1376 {
1377 MacTxPort[mac_id].dma[10].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1378 }
1379 if (tx_multi_dma_p0[11] == 1'b1)
1380 {
1381 MacTxPort[mac_id].dma[11].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1382 }
1383 if (tx_multi_dma_p0[12] == 1'b1)
1384 {
1385 MacTxPort[mac_id].dma[12].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1386 }
1387 if (tx_multi_dma_p0[13] == 1'b1)
1388 {
1389 MacTxPort[mac_id].dma[13].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1390 }
1391 if (tx_multi_dma_p0[14] == 1'b1)
1392 {
1393 MacTxPort[mac_id].dma[14].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1394 }
1395 if (tx_multi_dma_p0[15] == 1'b1)
1396 {
1397 MacTxPort[mac_id].dma[15].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1398 }
1399 mac_id = 1;
1400 if (tx_multi_dma_p1[0] == 1'b1)
1401 {
1402 MacTxPort[mac_id].dma[0].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1403 }
1404 if (tx_multi_dma_p1[1] == 1'b1)
1405 {
1406 MacTxPort[mac_id].dma[1].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1407 }
1408 if (tx_multi_dma_p1[2] == 1'b1)
1409 {
1410 MacTxPort[mac_id].dma[2].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1411 }
1412 if (tx_multi_dma_p1[3] == 1'b1)
1413 {
1414 MacTxPort[mac_id].dma[3].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1415 }
1416 if (tx_multi_dma_p1[4] == 1'b1)
1417 {
1418 MacTxPort[mac_id].dma[4].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1419 }
1420 if (tx_multi_dma_p1[5] == 1'b1)
1421 {
1422 MacTxPort[mac_id].dma[5].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1423 }
1424 if (tx_multi_dma_p1[6] == 1'b1)
1425 {
1426 MacTxPort[mac_id].dma[6].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1427 }
1428 if (tx_multi_dma_p1[7] == 1'b1)
1429 {
1430 MacTxPort[mac_id].dma[7].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1431 }
1432 if (tx_multi_dma_p1[8] == 1'b1)
1433 {
1434 MacTxPort[mac_id].dma[8].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1435 }
1436 if (tx_multi_dma_p1[9] == 1'b1)
1437 {
1438 MacTxPort[mac_id].dma[9].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1439 }
1440 if (tx_multi_dma_p1[10] == 1'b1)
1441 {
1442 MacTxPort[mac_id].dma[10].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1443 }
1444 if (tx_multi_dma_p1[11] == 1'b1)
1445 {
1446 MacTxPort[mac_id].dma[11].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1447 }
1448 if (tx_multi_dma_p1[12] == 1'b1)
1449 {
1450 MacTxPort[mac_id].dma[12].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1451 }
1452 if (tx_multi_dma_p1[13] == 1'b1)
1453 {
1454 MacTxPort[mac_id].dma[13].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1455 }
1456 if (tx_multi_dma_p1[14] == 1'b1)
1457 {
1458 MacTxPort[mac_id].dma[14].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1459 }
1460 if (tx_multi_dma_p1[15] == 1'b1)
1461 {
1462 MacTxPort[mac_id].dma[15].SetTxMaxBurst(SetTxMaxBurst_Data); // MacTxPort[mac_id].dma[j].SetTxMaxBurst(32'd500);
1463 }
1464 }
1465 }
1466 else
1467 {
1468 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1469 psprintf("NIU_SetTxMaxBurst: Invalid combination for NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1470 }
1471}
1472
1473// ***********************************************************************************
1474task AsmToVeraIntf::NIU_TxDMAActivate (integer mac_port, integer dma_activelist,
1475 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
1476/*@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1477 MacTxPort[mac_id].SetActive(dma_activelist);
1478
1479 dma_activelist is a 32 bit parameter which each bit signifies a dma value as shown below:
1480
1481 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1482 dma15 dma14 dma13 dma12 dma11 dma10 dma9 dma8 dma7 dma6 dma5 dma4 dma3 dma2 dma1 dma0
1483@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@*/
1484{
1485integer mac_id = mac_port;
1486integer tx_multi_dma_p0_list = 0;
1487integer tx_multi_dma_p1_list = 0;
1488bit [31:0] dma_no = 32'h0;
1489
1490integer mac_id_0 = 0;
1491integer mac_id_1 = 0;
1492
1493 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
1494 {
1495 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
1496 }
1497 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
1498 {
1499 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
1500 }
1501
1502dma_no = dma_activelist;
1503
1504 PR_INFO("fc_niu_asm_event", MON_INFO,
1505 psprintf("KHH-TX Debug : FOR NIU_TxDMAActivate, MAC_ID = %0d DMA_ACTIVELIST = %0d DMA_NO = %0d", mac_id, dma_activelist, dma_no));
1506
1507
1508tx_multi_dma_p0_list = {16'h0,tx_multi_dma_p0[15:0]};
1509tx_multi_dma_p1_list = {16'h0,tx_multi_dma_p1[15:0]};
1510
1511 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
1512 {
1513 MacTxPort[mac_id] = new(mac_id);
1514 if (dma_no[0])
1515 {
1516 MacTxPort[mac_id].add_channels(0);
1517 }
1518 else if (dma_no[1])
1519 {
1520 MacTxPort[mac_id].add_channels(1);
1521 }
1522 else if (dma_no[2])
1523 {
1524 MacTxPort[mac_id].add_channels(2);
1525 }
1526 else if (dma_no[3])
1527 {
1528 MacTxPort[mac_id].add_channels(3);
1529 }
1530 else if (dma_no[4])
1531 {
1532 MacTxPort[mac_id].add_channels(4);
1533 }
1534 else if (dma_no[5])
1535 {
1536 MacTxPort[mac_id].add_channels(5);
1537 }
1538 else if (dma_no[6])
1539 {
1540 MacTxPort[mac_id].add_channels(6);
1541 }
1542 else if (dma_no[7])
1543 {
1544 MacTxPort[mac_id].add_channels(7);
1545 }
1546 else if (dma_no[8])
1547 {
1548 MacTxPort[mac_id].add_channels(8);
1549 }
1550 else if (dma_no[9])
1551 {
1552 MacTxPort[mac_id].add_channels(9);
1553 }
1554 else if (dma_no[10])
1555 {
1556 MacTxPort[mac_id].add_channels(10);
1557 }
1558 else if (dma_no[11])
1559 {
1560 MacTxPort[mac_id].add_channels(11);
1561 }
1562 else if (dma_no[12])
1563 {
1564 MacTxPort[mac_id].add_channels(12);
1565 }
1566 else if (dma_no[13])
1567 {
1568 MacTxPort[mac_id].add_channels(13);
1569 }
1570 else if (dma_no[14])
1571 {
1572 MacTxPort[mac_id].add_channels(14);
1573 }
1574 else if (dma_no[15])
1575 {
1576 MacTxPort[mac_id].add_channels(15);
1577 }
1578 else
1579 {
1580 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1581 psprintf("NIU_TxDMAActivate: Unexpected DMA value of 0x%h", dma_no));
1582 }
1583
1584 MacTxPort[mac_id].SetActive(dma_activelist);
1585 }
1586 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
1587 {
1588 PR_INFO("fc_niu_asm_event", MON_INFO,
1589 psprintf("KHH-TX Debug : FOR NIU_TxDMAActivate, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1590 if (mac_id == 0)
1591 {
1592 MacTxPort[mac_id] = new(mac_id);
1593
1594 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1595 //@@ Add requested dma channels for port 0 @@
1596 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1597 if (tx_multi_dma_p0[0] == 1'b1)
1598 {
1599 MacTxPort[mac_id].add_channels(0);
1600 }
1601 if (tx_multi_dma_p0[1] == 1'b1)
1602 {
1603 MacTxPort[mac_id].add_channels(1);
1604 }
1605 if (tx_multi_dma_p0[2] == 1'b1)
1606 {
1607 MacTxPort[mac_id].add_channels(2);
1608 }
1609 if (tx_multi_dma_p0[3] == 1'b1)
1610 {
1611 MacTxPort[mac_id].add_channels(3);
1612 }
1613 if (tx_multi_dma_p0[4] == 1'b1)
1614 {
1615 MacTxPort[mac_id].add_channels(4);
1616 }
1617 if (tx_multi_dma_p0[5] == 1'b1)
1618 {
1619 MacTxPort[mac_id].add_channels(5);
1620 }
1621 if (tx_multi_dma_p0[6] == 1'b1)
1622 {
1623 MacTxPort[mac_id].add_channels(6);
1624 }
1625 if (tx_multi_dma_p0[7] == 1'b1)
1626 {
1627 MacTxPort[mac_id].add_channels(7);
1628 }
1629 if (tx_multi_dma_p0[8] == 1'b1)
1630 {
1631 MacTxPort[mac_id].add_channels(8);
1632 }
1633 if (tx_multi_dma_p0[9] == 1'b1)
1634 {
1635 MacTxPort[mac_id].add_channels(9);
1636 }
1637 if (tx_multi_dma_p0[10] == 1'b1)
1638 {
1639 MacTxPort[mac_id].add_channels(10);
1640 }
1641 if (tx_multi_dma_p0[11] == 1'b1)
1642 {
1643 MacTxPort[mac_id].add_channels(11);
1644 }
1645 if (tx_multi_dma_p0[12] == 1'b1)
1646 {
1647 MacTxPort[mac_id].add_channels(12);
1648 }
1649 if (tx_multi_dma_p0[13] == 1'b1)
1650 {
1651 MacTxPort[mac_id].add_channels(13);
1652 }
1653 if (tx_multi_dma_p0[14] == 1'b1)
1654 {
1655 MacTxPort[mac_id].add_channels(14);
1656 }
1657 if (tx_multi_dma_p0[15] == 1'b1)
1658 {
1659 MacTxPort[mac_id].add_channels(15);
1660 }
1661 MacTxPort[mac_id].SetActive(tx_multi_dma_p0_list);
1662 }
1663 else if (mac_id == 1)
1664 {
1665 MacTxPort[mac_id] = new(mac_id);
1666
1667 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1668 //@@ Add requested dma channels for port 1 @@
1669 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1670 if (tx_multi_dma_p1[0] == 1'b1)
1671 {
1672 MacTxPort[mac_id].add_channels(0);
1673 }
1674 if (tx_multi_dma_p1[1] == 1'b1)
1675 {
1676 MacTxPort[mac_id].add_channels(1);
1677 }
1678 if (tx_multi_dma_p1[2] == 1'b1)
1679 {
1680 MacTxPort[mac_id].add_channels(2);
1681 }
1682 if (tx_multi_dma_p1[3] == 1'b1)
1683 {
1684 MacTxPort[mac_id].add_channels(3);
1685 }
1686 if (tx_multi_dma_p1[4] == 1'b1)
1687 {
1688 MacTxPort[mac_id].add_channels(4);
1689 }
1690 if (tx_multi_dma_p1[5] == 1'b1)
1691 {
1692 MacTxPort[mac_id].add_channels(5);
1693 }
1694 if (tx_multi_dma_p1[6] == 1'b1)
1695 {
1696 MacTxPort[mac_id].add_channels(6);
1697 }
1698 if (tx_multi_dma_p1[7] == 1'b1)
1699 {
1700 MacTxPort[mac_id].add_channels(7);
1701 }
1702 if (tx_multi_dma_p1[8] == 1'b1)
1703 {
1704 MacTxPort[mac_id].add_channels(8);
1705 }
1706 if (tx_multi_dma_p1[9] == 1'b1)
1707 {
1708 MacTxPort[mac_id].add_channels(9);
1709 }
1710 if (tx_multi_dma_p1[10] == 1'b1)
1711 {
1712 MacTxPort[mac_id].add_channels(10);
1713 }
1714 if (tx_multi_dma_p1[11] == 1'b1)
1715 {
1716 MacTxPort[mac_id].add_channels(11);
1717 }
1718 if (tx_multi_dma_p1[12] == 1'b1)
1719 {
1720 MacTxPort[mac_id].add_channels(12);
1721 }
1722 if (tx_multi_dma_p1[13] == 1'b1)
1723 {
1724 MacTxPort[mac_id].add_channels(13);
1725 }
1726 if (tx_multi_dma_p1[14] == 1'b1)
1727 {
1728 MacTxPort[mac_id].add_channels(14);
1729 }
1730 if (tx_multi_dma_p1[15] == 1'b1)
1731 {
1732 MacTxPort[mac_id].add_channels(15);
1733 }
1734 MacTxPort[mac_id].SetActive(tx_multi_dma_p1_list);
1735 }
1736 else
1737 {
1738 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1739 psprintf("NIU_TxDMAActivate: Unexpected TX Port Value %0d", mac_port));
1740 }
1741 }
1742 else if (tx_multi_port == 1 && (tx_multi_dma_p0[15:0] == 16'h0 || tx_multi_dma_p1[15:0] == 16'h0))
1743 {
1744 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1745 psprintf("NIU_TxDMAActivate: NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
1746 }
1747 else if (tx_multi_port == 1 && tx_multi_dma_p0[15:0] > 16'h0 && tx_multi_dma_p1[15:0] > 16'h0)
1748 {
1749 PR_INFO("fc_niu_asm_event", MON_INFO,
1750 psprintf("KHH-TX Debug : FOR NIU_TxDMAActivate, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1751
1752 if (tx_multi_dma_p1[15:0] & tx_multi_dma_p0[15:0])
1753 {
1754 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1755 psprintf("NIU_TxDMAActivate: Same DMA assigned to multiple ports: TX_MULTI_DMA_P0 = 0x%h, TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
1756 }
1757 else
1758 {
1759
1760// KHOSROW 1<<tx_multi_dma_p0
1761// Shifting method should be implemented when we get a chance
1762
1763 mac_id_0 = 0;
1764 MacTxPort[mac_id_0] = new(mac_id_0);
1765
1766 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1767 //@@ Add requested dma channels for port 0 @@
1768 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1769 if (tx_multi_dma_p0[0] == 1'b1)
1770 {
1771 MacTxPort[mac_id_0].add_channels(0);
1772 }
1773 if (tx_multi_dma_p0[1] == 1'b1)
1774 {
1775 MacTxPort[mac_id_0].add_channels(1);
1776 }
1777 if (tx_multi_dma_p0[2] == 1'b1)
1778 {
1779 MacTxPort[mac_id_0].add_channels(2);
1780 }
1781 if (tx_multi_dma_p0[3] == 1'b1)
1782 {
1783 MacTxPort[mac_id_0].add_channels(3);
1784 }
1785 if (tx_multi_dma_p0[4] == 1'b1)
1786 {
1787 MacTxPort[mac_id_0].add_channels(4);
1788 }
1789 if (tx_multi_dma_p0[5] == 1'b1)
1790 {
1791 MacTxPort[mac_id_0].add_channels(5);
1792 }
1793 if (tx_multi_dma_p0[6] == 1'b1)
1794 {
1795 MacTxPort[mac_id_0].add_channels(6);
1796 }
1797 if (tx_multi_dma_p0[7] == 1'b1)
1798 {
1799 MacTxPort[mac_id_0].add_channels(7);
1800 }
1801 if (tx_multi_dma_p0[8] == 1'b1)
1802 {
1803 MacTxPort[mac_id_0].add_channels(8);
1804 }
1805 if (tx_multi_dma_p0[9] == 1'b1)
1806 {
1807 MacTxPort[mac_id_0].add_channels(9);
1808 }
1809 if (tx_multi_dma_p0[10] == 1'b1)
1810 {
1811 MacTxPort[mac_id_0].add_channels(10);
1812 }
1813 if (tx_multi_dma_p0[11] == 1'b1)
1814 {
1815 MacTxPort[mac_id_0].add_channels(11);
1816 }
1817 if (tx_multi_dma_p0[12] == 1'b1)
1818 {
1819 MacTxPort[mac_id_0].add_channels(12);
1820 }
1821 if (tx_multi_dma_p0[13] == 1'b1)
1822 {
1823 MacTxPort[mac_id_0].add_channels(13);
1824 }
1825 if (tx_multi_dma_p0[14] == 1'b1)
1826 {
1827 MacTxPort[mac_id_0].add_channels(14);
1828 }
1829 if (tx_multi_dma_p0[15] == 1'b1)
1830 {
1831 MacTxPort[mac_id_0].add_channels(15);
1832 }
1833 MacTxPort[mac_id_0].SetActive(tx_multi_dma_p0_list);
1834 mac_id_1 = 1;
1835 MacTxPort[mac_id_1] = new(mac_id_1);
1836
1837 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1838 //@@ Add requested dma channels for port 1 @@
1839 //@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
1840 if (tx_multi_dma_p1[0] == 1'b1)
1841 {
1842 MacTxPort[mac_id_1].add_channels(0);
1843 }
1844 if (tx_multi_dma_p1[1] == 1'b1)
1845 {
1846 MacTxPort[mac_id_1].add_channels(1);
1847 }
1848 if (tx_multi_dma_p1[2] == 1'b1)
1849 {
1850 MacTxPort[mac_id_1].add_channels(2);
1851 }
1852 if (tx_multi_dma_p1[3] == 1'b1)
1853 {
1854 MacTxPort[mac_id_1].add_channels(3);
1855 }
1856 if (tx_multi_dma_p1[4] == 1'b1)
1857 {
1858 MacTxPort[mac_id_1].add_channels(4);
1859 }
1860 if (tx_multi_dma_p1[5] == 1'b1)
1861 {
1862 MacTxPort[mac_id_1].add_channels(5);
1863 }
1864 if (tx_multi_dma_p1[6] == 1'b1)
1865 {
1866 MacTxPort[mac_id_1].add_channels(6);
1867 }
1868 if (tx_multi_dma_p1[7] == 1'b1)
1869 {
1870 MacTxPort[mac_id_1].add_channels(7);
1871 }
1872 if (tx_multi_dma_p1[8] == 1'b1)
1873 {
1874 MacTxPort[mac_id_1].add_channels(8);
1875 }
1876 if (tx_multi_dma_p1[9] == 1'b1)
1877 {
1878 MacTxPort[mac_id_1].add_channels(9);
1879 }
1880 if (tx_multi_dma_p1[10] == 1'b1)
1881 {
1882 MacTxPort[mac_id_1].add_channels(10);
1883 }
1884 if (tx_multi_dma_p1[11] == 1'b1)
1885 {
1886 MacTxPort[mac_id_1].add_channels(11);
1887 }
1888 if (tx_multi_dma_p1[12] == 1'b1)
1889 {
1890 MacTxPort[mac_id_1].add_channels(12);
1891 }
1892 if (tx_multi_dma_p1[13] == 1'b1)
1893 {
1894 MacTxPort[mac_id_1].add_channels(13);
1895 }
1896 if (tx_multi_dma_p1[14] == 1'b1)
1897 {
1898 MacTxPort[mac_id_1].add_channels(14);
1899 }
1900 if (tx_multi_dma_p1[15] == 1'b1)
1901 {
1902 MacTxPort[mac_id_1].add_channels(15);
1903 }
1904 MacTxPort[mac_id_1].SetActive(tx_multi_dma_p1_list);
1905 }
1906 }
1907 else
1908 {
1909 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1910 psprintf("NIU_TxDMAActivate: Invalid combination for NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h",tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1911 }
1912}
1913
1914// ***********************************************************************************
1915task AsmToVeraIntf::NIU_InitTxDma (integer mac_port, integer dma_no, bit Xlate,
1916 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
1917{
1918bit [39:0] rng_st_addr;
1919integer mac_id = mac_port;
1920bit[12:0] length;
1921bit [5:0] rand_num;
1922bit [63:0] config_data;
1923
1924 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
1925 {
1926 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
1927 }
1928 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
1929 {
1930 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
1931 }
1932
1933 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
1934 {
1935 PR_INFO("fc_niu_asm_event", MON_INFO,
1936 psprintf("KHH-TX Debug : FOR NIU_InitTxDma, MAC_ID = %0d & DMA_NO = %0d", mac_id, dma_no));
1937 MacTxPort[mac_id].dma[dma_no].xlate_on = Xlate;
1938 MacTxPort[mac_id].dma[dma_no].InitTXDMA(256,rng_st_addr); // 20 is ring-size, changed to 32
1939 }
1940 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
1941 {
1942 PR_INFO("fc_niu_asm_event", MON_INFO,
1943 psprintf("KHH-TX Debug : FOR NIU_InitTxDma, NIU_TX_MULTI_PORT = %0d, MAC_PORT = %0d, DMA_NO = %0h, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, mac_port, dma_no, tx_multi_dma_p0, tx_multi_dma_p1));
1944 MacTxPort[mac_id].dma[dma_no].xlate_on = Xlate;
1945 MacTxPort[mac_id].dma[dma_no].InitTXDMA(256,rng_st_addr); // 20 is ring-size, changed to 32
1946 }
1947 else if (tx_multi_port == 1 && (tx_multi_dma_p0[15:0] == 16'h0 || tx_multi_dma_p1[15:0] == 16'h0))
1948 {
1949 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1950 psprintf("NIU_InitTxDma: NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_dma_p0, tx_multi_dma_p1));
1951 }
1952 else if (tx_multi_port == 1 && tx_multi_dma_p0[15:0] > 16'h0 && tx_multi_dma_p1[15:0] > 16'h0)
1953 {
1954 if (tx_multi_dma_p1[15:0] & tx_multi_dma_p0[15:0])
1955 {
1956 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1957 psprintf("NIU_InitTxDma: Same DMA assigned to multiple ports: TX_MULTI_DMA_P0 = 0x%h, TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
1958 }
1959 else
1960 {
1961 PR_INFO("fc_niu_asm_event", MON_INFO,
1962 psprintf("KHH-TX Debug : FOR NIU_InitTxDma, NIU_TX_MULTI_PORT = %0d, MAC_PORT = %0d, DMA_NO = %0h, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, mac_port, dma_no, tx_multi_dma_p0, tx_multi_dma_p1));
1963 MacTxPort[mac_id].dma[dma_no].xlate_on = Xlate;
1964 MacTxPort[mac_id].dma[dma_no].InitTXDMA(256,rng_st_addr); // 20 is ring-size, changed to 32
1965 }
1966 }
1967 else
1968 {
1969 PR_ERROR("fc_niu_asm_event", MON_ERROR,
1970 psprintf("NIU_InitTxDma: Invalid combination for NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
1971 }
1972
1973
1974/*
1975length = 13'h0fff;
1976rand_num = random()%64;
1977
1978 MacTxPort[mac_id].dma[dma_no].SetTxLPValid(64'h3);
1979 MacTxPort[mac_id].dma[dma_no].SetTxLPMask1(64'h0);
1980 MacTxPort[mac_id].dma[dma_no].SetTxLPMask2(64'h0);
1981 MacTxPort[mac_id].dma[dma_no].ring_start_addr = 44'h000 + dma_no*44'h0_0001_0000;
1982 MacTxPort[mac_id].dma[dma_no].ring_current_addr = 44'h000 + dma_no*44'h0_0001_0000;
1983
1984 if (get_plus_arg (CHECK, "TX_GATHER"))
1985 MacTxPort[mac_id].dma[dma_no].gather_mode = 1;
1986 else
1987 MacTxPort[mac_id].dma[dma_no].gather_mode = 0;
1988
1989
1990 config_data = {3'h0,length,4'h0,4'h0,MacTxPort[mac_id].dma[dma_no].ring_start_addr[39:6],rand_num};
1991// config_data = {16'h0FFF,4'h0,MacTxPort[mac_id].dma[0].ring_start_addr[43:0]};
1992 MacTxPort[mac_id].dma[dma_no].setTxRingConfig(config_data);
1993*/
1994}
1995
1996// ***********************************************************************************
1997task AsmToVeraIntf::NIU_EXIT_chk (integer mac_port)
1998{
1999integer mac_id = mac_port; // port 0 hardcoded; MAQ
2000
2001 MacTxPort[mac_id].check_exit_status();
2002}
2003
2004// ***********************************************************************************
2005task AsmToVeraIntf::TxPktGen (integer mac_port, integer dmaport, integer numofpacket,
2006 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
2007{
2008
2009 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
2010 {
2011 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
2012 }
2013 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
2014 {
2015 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
2016 }
2017 fork
2018 {
2019 TxPktGen_int(mac_port, dmaport, numofpacket,
2020 tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1);
2021 }
2022 join none
2023}
2024
2025// ***********************************************************************************
2026task AsmToVeraIntf::TxPktGen_int (integer mac_port, integer dmaport, integer numofpacket,
2027 (integer tx_multi_port = 0, bit [15:0] tx_multi_dma_p0 = 16'h0, bit [15:0] tx_multi_dma_p1 = 16'h0))
2028{
2029
2030//static TxPacketGenConfig PktGenConfig;
2031static TxPacketGenConfig PktGenConfig0;
2032static TxPacketGenConfig PktGenConfig1;
2033//TxPacketGenConfig config;
2034TxPacketGenConfig config0;
2035TxPacketGenConfig config1;
2036integer i, j;
2037
2038bit interrupt_last_packet = 1'b0;
2039
2040integer mac_id = mac_port;
2041
2042 PR_INFO("fc_niu_asm_event", MON_INFO,
2043 psprintf("TxPktGen_int: mac_port = %0d, dmaport = %0d, numofpacket = %0d, tx_multi_port = %0d, tx_multi_dma_p0 = %0d, tx_multi_dma_p1 = %0d", mac_port, dmaport, numofpacket, tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
2044
2045PktGenConfig0 = new;
2046PktGenConfig1 = new;
2047
2048 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P0="))
2049 {
2050 tx_multi_dma_p0 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P0=");
2051 }
2052 if (get_plus_arg (CHECK, "NIU_TX_MULTI_DMA_P1="))
2053 {
2054 tx_multi_dma_p1 = get_plus_arg( HNUM, "NIU_TX_MULTI_DMA_P1=");
2055 }
2056
2057 if (get_plus_arg (CHECK, "NIU_TX_MARK_LAST_PACKET_FOR_INTERRUPT"))
2058 {
2059 interrupt_last_packet = 1'b1;
2060 }
2061
2062// printf("MAQ-Debug : After Initia desc_ring.ring_current_addr = %h \n", MacTxPort[mac_id].dma[dmaport].desc_ring.ring_current_addr);
2063// printf("MAQ-Debug : After Initia dma.ring_current_addr = %h \n", MacTxPort[mac_id].dma[dmaport].ring_current_addr);
2064
2065//if (mailbox_get(NO_WAIT, config_mb, config))
2066// PktGenConfig = config;
2067
2068// for (i=0; i<numofpacket; i++){
2069// MacTxPort[mac_id].dma[dmaport].gen_txpacket(i, PktGenConfig);
2070// printf("MAQ-Debug : Inloop desc_ring.ring_current_addr = %h \n", MacTxPort[mac_id].dma[dmaport].desc_ring.ring_current_addr);
2071// printf("MAQ-Debug : Inloop dma.ring_current_addr = %h \n", MacTxPort[mac_id].dma[dmaport].ring_current_addr);
2072// }
2073
2074 if (tx_multi_port == 0 && tx_multi_dma_p0 == 16'h0 && tx_multi_dma_p1 == 16'h0)
2075 {
2076 if (mac_id == 0)
2077 {
2078 if (mailbox_get(NO_WAIT, config0_mb, config0))
2079 PktGenConfig0 = config0;
2080
2081 for (i=0; i<numofpacket; i++){
2082 if (interrupt_last_packet && i == numofpacket-1)
2083 PktGenConfig0.mark_bit = 1;
2084 PR_INFO("fc_niu_asm_event", MON_INFO,
2085 psprintf("KHH-TX Debug : FOR TxPktGen_int, FOR PORT0 I = %0d, MARK_BIT = %0d", i, PktGenConfig0.mark_bit));
2086 MacTxPort[mac_id].dma[dmaport].gen_txpacket(i, PktGenConfig0);
2087 }
2088 }
2089 else if (mac_id == 1)
2090 {
2091 if (mailbox_get(NO_WAIT, config1_mb, config1))
2092 PktGenConfig1 = config1;
2093
2094 for (i=0; i<numofpacket; i++){
2095 if (interrupt_last_packet && i == numofpacket-1)
2096 PktGenConfig1.mark_bit = 1;
2097 PR_INFO("fc_niu_asm_event", MON_INFO,
2098 psprintf("KHH-TX Debug : FOR TxPktGen_int, FOR PORT1 I = %0d, MARK_BIT = %0d", i, PktGenConfig1.mark_bit));
2099 MacTxPort[mac_id].dma[dmaport].gen_txpacket(i, PktGenConfig1);
2100 }
2101 }
2102 else
2103 {
2104 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2105 psprintf("TxPktGen_int: Invalid MAC port = %0d", mac_id));
2106 }
2107 }
2108 else if (tx_multi_port == 0 && (tx_multi_dma_p0 > 16'h0 || tx_multi_dma_p1 > 16'h0))
2109 {
2110 PR_INFO("fc_niu_asm_event", MON_INFO,
2111 psprintf("KHH-TX Debug : FOR TxPktGen_int, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
2112 if (mac_id == 0)
2113 {
2114 if (mailbox_get(NO_WAIT, config0_mb, config0))
2115 PktGenConfig0 = config0;
2116
2117 for (i=0; i<numofpacket; i++)
2118 {
2119 j = 0;
2120 if (tx_multi_dma_p0[0] == 1'b1)
2121 {
2122 MacTxPort[mac_id].dma[0].gen_txpacket(i, PktGenConfig0);
2123 PR_INFO("fc_niu_asm_event", MON_INFO,
2124 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[0]));
2125 j = j + 1;
2126 }
2127 if (tx_multi_dma_p0[1] == 1'b1)
2128 {
2129 MacTxPort[mac_id].dma[1].gen_txpacket(i, PktGenConfig0);
2130 PR_INFO("fc_niu_asm_event", MON_INFO,
2131 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[1]));
2132 j = j + 1;
2133 }
2134 if (tx_multi_dma_p0[2] == 1'b1)
2135 {
2136 MacTxPort[mac_id].dma[2].gen_txpacket(i, PktGenConfig0);
2137 PR_INFO("fc_niu_asm_event", MON_INFO,
2138 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[2]));
2139 j = j + 1;
2140 }
2141 if (tx_multi_dma_p0[3] == 1'b1)
2142 {
2143 MacTxPort[mac_id].dma[3].gen_txpacket(i, PktGenConfig0);
2144 PR_INFO("fc_niu_asm_event", MON_INFO,
2145 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[3]));
2146 j = j + 1;
2147 }
2148 if (tx_multi_dma_p0[4] == 1'b1)
2149 {
2150 MacTxPort[mac_id].dma[4].gen_txpacket(i, PktGenConfig0);
2151 PR_INFO("fc_niu_asm_event", MON_INFO,
2152 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[4]));
2153 j = j + 1;
2154 }
2155 if (tx_multi_dma_p0[5] == 1'b1)
2156 {
2157 MacTxPort[mac_id].dma[5].gen_txpacket(i, PktGenConfig0);
2158 PR_INFO("fc_niu_asm_event", MON_INFO,
2159 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[5]));
2160 j = j + 1;
2161 }
2162 if (tx_multi_dma_p0[6] == 1'b1)
2163 {
2164 MacTxPort[mac_id].dma[6].gen_txpacket(i, PktGenConfig0);
2165 PR_INFO("fc_niu_asm_event", MON_INFO,
2166 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[6]));
2167 j = j + 1;
2168 }
2169 if (tx_multi_dma_p0[7] == 1'b1)
2170 {
2171 MacTxPort[mac_id].dma[7].gen_txpacket(i, PktGenConfig0);
2172 PR_INFO("fc_niu_asm_event", MON_INFO,
2173 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[7]));
2174 j = j + 1;
2175 }
2176 if (tx_multi_dma_p0[8] == 1'b1)
2177 {
2178 MacTxPort[mac_id].dma[8].gen_txpacket(i, PktGenConfig0);
2179 PR_INFO("fc_niu_asm_event", MON_INFO,
2180 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[8]));
2181 j = j + 1;
2182 }
2183 if (tx_multi_dma_p0[9] == 1'b1)
2184 {
2185 MacTxPort[mac_id].dma[9].gen_txpacket(i, PktGenConfig0);
2186 PR_INFO("fc_niu_asm_event", MON_INFO,
2187 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[9]));
2188 j = j + 1;
2189 }
2190 if (tx_multi_dma_p0[10] == 1'b1)
2191 {
2192 MacTxPort[mac_id].dma[10].gen_txpacket(i, PktGenConfig0);
2193 PR_INFO("fc_niu_asm_event", MON_INFO,
2194 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[10]));
2195 j = j + 1;
2196 }
2197 if (tx_multi_dma_p0[11] == 1'b1)
2198 {
2199 MacTxPort[mac_id].dma[11].gen_txpacket(i, PktGenConfig0);
2200 PR_INFO("fc_niu_asm_event", MON_INFO,
2201 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[11]));
2202 j = j + 1;
2203 }
2204 if (tx_multi_dma_p0[12] == 1'b1)
2205 {
2206 MacTxPort[mac_id].dma[12].gen_txpacket(i, PktGenConfig0);
2207 PR_INFO("fc_niu_asm_event", MON_INFO,
2208 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[12]));
2209 j = j + 1;
2210 }
2211 if (tx_multi_dma_p0[13] == 1'b1)
2212 {
2213 MacTxPort[mac_id].dma[13].gen_txpacket(i, PktGenConfig0);
2214 PR_INFO("fc_niu_asm_event", MON_INFO,
2215 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[13]));
2216 j = j + 1;
2217 }
2218 if (tx_multi_dma_p0[14] == 1'b1)
2219 {
2220 MacTxPort[mac_id].dma[14].gen_txpacket(i, PktGenConfig0);
2221 PR_INFO("fc_niu_asm_event", MON_INFO,
2222 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[14]));
2223 j = j + 1;
2224 }
2225 if (tx_multi_dma_p0[15] == 1'b1)
2226 {
2227 MacTxPort[mac_id].dma[15].gen_txpacket(i, PktGenConfig0);
2228 PR_INFO("fc_niu_asm_event", MON_INFO,
2229 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p0[15]));
2230 j = j + 1;
2231 }
2232
2233 if (j>1)
2234 {
2235 i = i + (j-1);
2236 }
2237 }
2238 }
2239 else if (mac_id == 1)
2240 {
2241 if (mailbox_get(NO_WAIT, config1_mb, config1))
2242 PktGenConfig1 = config1;
2243
2244 for (i=0; i<numofpacket; i++)
2245 {
2246 j = 0;
2247 if (tx_multi_dma_p1[0] == 1'b1)
2248 {
2249 MacTxPort[mac_id].dma[0].gen_txpacket(i, PktGenConfig1);
2250 PR_INFO("fc_niu_asm_event", MON_INFO,
2251 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[0]));
2252 j = j + 1;
2253 }
2254 if (tx_multi_dma_p1[1] == 1'b1)
2255 {
2256 MacTxPort[mac_id].dma[1].gen_txpacket(i, PktGenConfig1);
2257 PR_INFO("fc_niu_asm_event", MON_INFO,
2258 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[1]));
2259 j = j + 1;
2260 }
2261 if (tx_multi_dma_p1[2] == 1'b1)
2262 {
2263 MacTxPort[mac_id].dma[2].gen_txpacket(i, PktGenConfig1);
2264 PR_INFO("fc_niu_asm_event", MON_INFO,
2265 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[2]));
2266 j = j + 1;
2267 }
2268 if (tx_multi_dma_p1[3] == 1'b1)
2269 {
2270 MacTxPort[mac_id].dma[3].gen_txpacket(i, PktGenConfig1);
2271 PR_INFO("fc_niu_asm_event", MON_INFO,
2272 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[3]));
2273 j = j + 1;
2274 }
2275 if (tx_multi_dma_p1[4] == 1'b1)
2276 {
2277 MacTxPort[mac_id].dma[4].gen_txpacket(i, PktGenConfig1);
2278 PR_INFO("fc_niu_asm_event", MON_INFO,
2279 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[4]));
2280 j = j + 1;
2281 }
2282 if (tx_multi_dma_p1[5] == 1'b1)
2283 {
2284 MacTxPort[mac_id].dma[5].gen_txpacket(i, PktGenConfig1);
2285 PR_INFO("fc_niu_asm_event", MON_INFO,
2286 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[5]));
2287 j = j + 1;
2288 }
2289 if (tx_multi_dma_p1[6] == 1'b1)
2290 {
2291 MacTxPort[mac_id].dma[6].gen_txpacket(i, PktGenConfig1);
2292 PR_INFO("fc_niu_asm_event", MON_INFO,
2293 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[6]));
2294 j = j + 1;
2295 }
2296 if (tx_multi_dma_p1[7] == 1'b1)
2297 {
2298 MacTxPort[mac_id].dma[7].gen_txpacket(i, PktGenConfig1);
2299 PR_INFO("fc_niu_asm_event", MON_INFO,
2300 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[7]));
2301 j = j + 1;
2302 }
2303 if (tx_multi_dma_p1[8] == 1'b1)
2304 {
2305 MacTxPort[mac_id].dma[8].gen_txpacket(i, PktGenConfig1);
2306 PR_INFO("fc_niu_asm_event", MON_INFO,
2307 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[8]));
2308 j = j + 1;
2309 }
2310 if (tx_multi_dma_p1[9] == 1'b1)
2311 {
2312 MacTxPort[mac_id].dma[9].gen_txpacket(i, PktGenConfig1);
2313 PR_INFO("fc_niu_asm_event", MON_INFO,
2314 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[9]));
2315 j = j + 1;
2316 }
2317 if (tx_multi_dma_p1[10] == 1'b1)
2318 {
2319 MacTxPort[mac_id].dma[10].gen_txpacket(i, PktGenConfig1);
2320 PR_INFO("fc_niu_asm_event", MON_INFO,
2321 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[10]));
2322 j = j + 1;
2323 }
2324 if (tx_multi_dma_p1[11] == 1'b1)
2325 {
2326 MacTxPort[mac_id].dma[11].gen_txpacket(i, PktGenConfig1);
2327 PR_INFO("fc_niu_asm_event", MON_INFO,
2328 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[11]));
2329 j = j + 1;
2330 }
2331 if (tx_multi_dma_p1[12] == 1'b1)
2332 {
2333 MacTxPort[mac_id].dma[12].gen_txpacket(i, PktGenConfig1);
2334 PR_INFO("fc_niu_asm_event", MON_INFO,
2335 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[12]));
2336 j = j + 1;
2337 }
2338 if (tx_multi_dma_p1[13] == 1'b1)
2339 {
2340 MacTxPort[mac_id].dma[13].gen_txpacket(i, PktGenConfig1);
2341 PR_INFO("fc_niu_asm_event", MON_INFO,
2342 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[13]));
2343 j = j + 1;
2344 }
2345 if (tx_multi_dma_p1[14] == 1'b1)
2346 {
2347 MacTxPort[mac_id].dma[14].gen_txpacket(i, PktGenConfig1);
2348 PR_INFO("fc_niu_asm_event", MON_INFO,
2349 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[14]));
2350 j = j + 1;
2351 }
2352 if (tx_multi_dma_p1[15] == 1'b1)
2353 {
2354 MacTxPort[mac_id].dma[15].gen_txpacket(i, PktGenConfig1);
2355 PR_INFO("fc_niu_asm_event", MON_INFO,
2356 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = %0d", numofpacket,i,mac_id,tx_multi_dma_p1[15]));
2357 j = j + 1;
2358 }
2359
2360 if (j>1)
2361 {
2362 i = i + (j-1);
2363 }
2364 }
2365 }
2366 else
2367 {
2368 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2369 psprintf("TxPktGen_int: Unexpected TX Port Value %0d", mac_id));
2370 }
2371 }
2372 else if (tx_multi_port == 1 && (tx_multi_dma_p0[15:0] == 16'h0 && tx_multi_dma_p1[15:0] == 16'h0))
2373 {
2374 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2375 psprintf("TxPktGen_int: For NIU_TX_MULTI_PORT, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_dma_p0, tx_multi_dma_p1));
2376 }
2377 else if (tx_multi_port == 1 && tx_multi_dma_p0[15:0] > 16'h0 && tx_multi_dma_p1[15:0] > 16'h0)
2378 {
2379 PR_INFO("fc_niu_asm_event", MON_INFO,
2380 psprintf("KHH-TX Debug : FOR TxPktGen_int, NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = %h, NIU_TX_MULTI_DMA_P1 = %h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
2381 mac_id = 0;
2382 if (mailbox_get(NO_WAIT, config0_mb, config0))
2383 PktGenConfig0 = config0;
2384
2385 for (i=0; i<numofpacket/2; i++)
2386 {
2387 j = 0;
2388 if (tx_multi_dma_p0[0] == 1'b1)
2389 {
2390 MacTxPort[mac_id].dma[0].gen_txpacket(i, PktGenConfig0);
2391 PR_INFO("fc_niu_asm_event", MON_INFO,
2392 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 0", numofpacket,i,mac_id));
2393 j = j + 1;
2394 }
2395 if (tx_multi_dma_p0[1] == 1'b1)
2396 {
2397 MacTxPort[mac_id].dma[1].gen_txpacket(i, PktGenConfig0);
2398 PR_INFO("fc_niu_asm_event", MON_INFO,
2399 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 1", numofpacket,i,mac_id));
2400 j = j + 1;
2401 }
2402 if (tx_multi_dma_p0[2] == 1'b1)
2403 {
2404 MacTxPort[mac_id].dma[2].gen_txpacket(i, PktGenConfig0);
2405 PR_INFO("fc_niu_asm_event", MON_INFO,
2406 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 2", numofpacket,i,mac_id));
2407 j = j + 1;
2408 }
2409 if (tx_multi_dma_p0[3] == 1'b1)
2410 {
2411 MacTxPort[mac_id].dma[3].gen_txpacket(i, PktGenConfig0);
2412 PR_INFO("fc_niu_asm_event", MON_INFO,
2413 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 3", numofpacket,i,mac_id));
2414 j = j + 1;
2415 }
2416 if (tx_multi_dma_p0[4] == 1'b1)
2417 {
2418 MacTxPort[mac_id].dma[4].gen_txpacket(i, PktGenConfig0);
2419 PR_INFO("fc_niu_asm_event", MON_INFO,
2420 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 4", numofpacket,i,mac_id));
2421 j = j + 1;
2422 }
2423 if (tx_multi_dma_p0[5] == 1'b1)
2424 {
2425 MacTxPort[mac_id].dma[5].gen_txpacket(i, PktGenConfig0);
2426 PR_INFO("fc_niu_asm_event", MON_INFO,
2427 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 5", numofpacket,i,mac_id));
2428 j = j + 1;
2429 }
2430 if (tx_multi_dma_p0[6] == 1'b1)
2431 {
2432 MacTxPort[mac_id].dma[6].gen_txpacket(i, PktGenConfig0);
2433 PR_INFO("fc_niu_asm_event", MON_INFO,
2434 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 6", numofpacket,i,mac_id));
2435 j = j + 1;
2436 }
2437 if (tx_multi_dma_p0[7] == 1'b1)
2438 {
2439 MacTxPort[mac_id].dma[7].gen_txpacket(i, PktGenConfig0);
2440 PR_INFO("fc_niu_asm_event", MON_INFO,
2441 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 7", numofpacket,i,mac_id));
2442 j = j + 1;
2443 }
2444 if (tx_multi_dma_p0[8] == 1'b1)
2445 {
2446 MacTxPort[mac_id].dma[0].gen_txpacket(i, PktGenConfig0);
2447 PR_INFO("fc_niu_asm_event", MON_INFO,
2448 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 8", numofpacket,i,mac_id));
2449 j = j + 1;
2450 }
2451 if (tx_multi_dma_p0[9] == 1'b1)
2452 {
2453 MacTxPort[mac_id].dma[1].gen_txpacket(i, PktGenConfig0);
2454 PR_INFO("fc_niu_asm_event", MON_INFO,
2455 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 9", numofpacket,i,mac_id));
2456 j = j + 1;
2457 }
2458 if (tx_multi_dma_p0[10] == 1'b1)
2459 {
2460 MacTxPort[mac_id].dma[2].gen_txpacket(i, PktGenConfig0);
2461 PR_INFO("fc_niu_asm_event", MON_INFO,
2462 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 10", numofpacket,i,mac_id));
2463 j = j + 1;
2464 }
2465 if (tx_multi_dma_p0[11] == 1'b1)
2466 {
2467 MacTxPort[mac_id].dma[3].gen_txpacket(i, PktGenConfig0);
2468 PR_INFO("fc_niu_asm_event", MON_INFO,
2469 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 11", numofpacket,i,mac_id));
2470 j = j + 1;
2471 }
2472 if (tx_multi_dma_p0[12] == 1'b1)
2473 {
2474 MacTxPort[mac_id].dma[4].gen_txpacket(i, PktGenConfig0);
2475 PR_INFO("fc_niu_asm_event", MON_INFO,
2476 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 12", numofpacket,i,mac_id));
2477 j = j + 1;
2478 }
2479 if (tx_multi_dma_p0[13] == 1'b1)
2480 {
2481 MacTxPort[mac_id].dma[5].gen_txpacket(i, PktGenConfig0);
2482 PR_INFO("fc_niu_asm_event", MON_INFO,
2483 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 13", numofpacket,i,mac_id));
2484 j = j + 1;
2485 }
2486 if (tx_multi_dma_p0[14] == 1'b1)
2487 {
2488 MacTxPort[mac_id].dma[6].gen_txpacket(i, PktGenConfig0);
2489 PR_INFO("fc_niu_asm_event", MON_INFO,
2490 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 14", numofpacket,i,mac_id));
2491 j = j + 1;
2492 }
2493 if (tx_multi_dma_p0[15] == 1'b1)
2494 {
2495 MacTxPort[mac_id].dma[7].gen_txpacket(i, PktGenConfig0);
2496 PR_INFO("fc_niu_asm_event", MON_INFO,
2497 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 15", numofpacket,i,mac_id));
2498 j = j + 1;
2499 }
2500
2501 if (j>1)
2502 {
2503 i = i + (j-1);
2504 }
2505 }
2506 mac_id = 1;
2507 if (mailbox_get(NO_WAIT, config1_mb, config1))
2508 PktGenConfig1 = config1;
2509
2510// for (i=0; i<numofpacket/2; i++)
2511 for (i=numofpacket/2; i<numofpacket; i++)
2512 {
2513 j = 0;
2514 if (tx_multi_dma_p1[0] == 1'b1)
2515 {
2516 MacTxPort[mac_id].dma[0].gen_txpacket(i, PktGenConfig1);
2517 PR_INFO("fc_niu_asm_event", MON_INFO,
2518 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 0", numofpacket,i,mac_id));
2519 j = j + 1;
2520 }
2521 if (tx_multi_dma_p1[1] == 1'b1)
2522 {
2523 MacTxPort[mac_id].dma[1].gen_txpacket(i, PktGenConfig1);
2524 PR_INFO("fc_niu_asm_event", MON_INFO,
2525 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 1", numofpacket,i,mac_id));
2526 j = j + 1;
2527 }
2528 if (tx_multi_dma_p1[2] == 1'b1)
2529 {
2530 MacTxPort[mac_id].dma[2].gen_txpacket(i, PktGenConfig1);
2531 PR_INFO("fc_niu_asm_event", MON_INFO,
2532 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 2", numofpacket,i,mac_id));
2533 j = j + 1;
2534 }
2535 if (tx_multi_dma_p1[3] == 1'b1)
2536 {
2537 MacTxPort[mac_id].dma[3].gen_txpacket(i, PktGenConfig1);
2538 PR_INFO("fc_niu_asm_event", MON_INFO,
2539 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 3", numofpacket,i,mac_id));
2540 j = j + 1;
2541 }
2542 if (tx_multi_dma_p1[4] == 1'b1)
2543 {
2544 MacTxPort[mac_id].dma[4].gen_txpacket(i, PktGenConfig1);
2545 PR_INFO("fc_niu_asm_event", MON_INFO,
2546 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 4", numofpacket,i,mac_id));
2547 j = j + 1;
2548 }
2549 if (tx_multi_dma_p1[5] == 1'b1)
2550 {
2551 MacTxPort[mac_id].dma[5].gen_txpacket(i, PktGenConfig1);
2552 PR_INFO("fc_niu_asm_event", MON_INFO,
2553 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 5", numofpacket,i,mac_id));
2554 j = j + 1;
2555 }
2556 if (tx_multi_dma_p1[6] == 1'b1)
2557 {
2558 MacTxPort[mac_id].dma[6].gen_txpacket(i, PktGenConfig1);
2559 PR_INFO("fc_niu_asm_event", MON_INFO,
2560 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 6", numofpacket,i,mac_id));
2561 j = j + 1;
2562 }
2563 if (tx_multi_dma_p1[7] == 1'b1)
2564 {
2565 MacTxPort[mac_id].dma[7].gen_txpacket(i, PktGenConfig1);
2566 PR_INFO("fc_niu_asm_event", MON_INFO,
2567 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 7", numofpacket,i,mac_id));
2568 j = j + 1;
2569 }
2570 if (tx_multi_dma_p1[8] == 1'b1)
2571 {
2572 PR_INFO("fc_niu_asm_event", MON_INFO,
2573 psprintf("KHH-TX Debug : B4 FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 8", numofpacket,i,mac_id));
2574 MacTxPort[mac_id].dma[8].gen_txpacket(i, PktGenConfig1);
2575 PR_INFO("fc_niu_asm_event", MON_INFO,
2576 psprintf("KHH-TX Debug : AF FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 8", numofpacket,i,mac_id));
2577 j = j + 1;
2578 }
2579 if (tx_multi_dma_p1[9] == 1'b1)
2580 {
2581 MacTxPort[mac_id].dma[9].gen_txpacket(i, PktGenConfig1);
2582 PR_INFO("fc_niu_asm_event", MON_INFO,
2583 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 9", numofpacket,i,mac_id));
2584 j = j + 1;
2585 }
2586 if (tx_multi_dma_p1[10] == 1'b1)
2587 {
2588 MacTxPort[mac_id].dma[10].gen_txpacket(i, PktGenConfig1);
2589 PR_INFO("fc_niu_asm_event", MON_INFO,
2590 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 10", numofpacket,i,mac_id));
2591 j = j + 1;
2592 }
2593 if (tx_multi_dma_p1[11] == 1'b1)
2594 {
2595 MacTxPort[mac_id].dma[11].gen_txpacket(i, PktGenConfig1);
2596 PR_INFO("fc_niu_asm_event", MON_INFO,
2597 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 11", numofpacket,i,mac_id));
2598 j = j + 1;
2599 }
2600 if (tx_multi_dma_p1[12] == 1'b1)
2601 {
2602 MacTxPort[mac_id].dma[12].gen_txpacket(i, PktGenConfig1);
2603 PR_INFO("fc_niu_asm_event", MON_INFO,
2604 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 12", numofpacket,i,mac_id));
2605 j = j + 1;
2606 }
2607 if (tx_multi_dma_p1[13] == 1'b1)
2608 {
2609 MacTxPort[mac_id].dma[13].gen_txpacket(i, PktGenConfig1);
2610 PR_INFO("fc_niu_asm_event", MON_INFO,
2611 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 13", numofpacket,i,mac_id));
2612 j = j + 1;
2613 }
2614 if (tx_multi_dma_p1[14] == 1'b1)
2615 {
2616 MacTxPort[mac_id].dma[14].gen_txpacket(i, PktGenConfig1);
2617 PR_INFO("fc_niu_asm_event", MON_INFO,
2618 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 14", numofpacket,i,mac_id));
2619 j = j + 1;
2620 }
2621 if (tx_multi_dma_p1[15] == 1'b1)
2622 {
2623 MacTxPort[mac_id].dma[15].gen_txpacket(i, PktGenConfig1);
2624 PR_INFO("fc_niu_asm_event", MON_INFO,
2625 psprintf("KHH-TX Debug : FOR PKT_CNT = %0d, SENT PKT = %0d TO TX_PORT = %0d TO DMA = 15", numofpacket,i,mac_id));
2626 j = j + 1;
2627 }
2628
2629 if (j>1)
2630 {
2631 i = i + (j-1);
2632 }
2633 }
2634 }
2635 else
2636 {
2637 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2638 psprintf("TxPktGen_int: Invalid combination for NIU_TX_MULTI_PORT = %0d, NIU_TX_MULTI_DMA_P0 = 0x%h, NIU_TX_MULTI_DMA_P1 = 0x%h", tx_multi_port, tx_multi_dma_p0, tx_multi_dma_p1));
2639 }
2640}
2641
2642// ***********************************************************************************
2643// NIU Rx Tasks
2644// ***********************************************************************************
2645task AsmToVeraIntf::NIU_InitRxDma (integer RxDmaChnlNo,
2646 integer RxDescRingLen,
2647 bit [39:0] RxRingStartAddr,
2648 bit [63:0] RbrConfData,
2649 integer RxInitKick,
2650 bit Xlate,
2651 (bit [15:0] rx_multi_dma= 16'h0))
2652{
2653 bit [39:0] ring_start_address;
2654 bit [15:0] initial_kick;
2655 bit [15:0] desc_ring_length;
2656 bit [63:0] rbr_config_B_data;
2657 integer dma_chnl;
2658// bit xlate = 1;
2659
2660 // One single function to initialize the whole RXDMA channel
2661 // This function should be called for each RXDMA channel you want to initialize
2662 dma_chnl = RxDmaChnlNo;
2663 desc_ring_length = RxDescRingLen;
2664 ring_start_address = RxRingStartAddr;
2665 initial_kick = RxInitKick;
2666 rbr_config_B_data = RbrConfData;
2667 fork
2668 {
2669 rdmc.InitRXDMA(dma_chnl, desc_ring_length, ring_start_address, rbr_config_B_data, initial_kick, Xlate);
2670 }
2671 join none
2672 PR_INFO("fc_niu_asm_event", MON_INFO,
2673 "MAQ-DEBUG: NIU_InitRxDma Done");
2674
2675}
2676
2677// ***********************************************************************************
2678task AsmToVeraIntf::NIU_RxPktConf (integer RxPktCnt, (integer iport = 0))
2679{
2680integer n;
2681 bit [12:0] ii = 12'h0;
2682 bit [7:0] DA_L = 8'h0;
2683
2684/*
2685 for(n = 0; n< RxPktCnt; n++) {
2686
2687 flow[n] = new;
2688 flow[n].src_node.l2_addr = 48'hde_f0_72_94_38_15;
2689 flow[n].src_node.tos = 8'hf5;
2690 flow[n].src_node.tci = 16'hcb00;
2691 flow[n].src_node.ip_addr = 32'hcccc_0000;
2692 flow[n].src_node.src_port = 20'h00001;
2693
2694 flow[n].dst_node.l2_addr = 48'h12_34_56_78_9a_bc;
2695 flow[n].dst_node.tci = 16'hcb00;
2696 flow[n].dst_node.ip_addr = 32'h8888_0000;
2697 flow[n].dst_node.src_port = 20'h00001;
2698
2699 flow[n].tup.src_tcp_udp_port = 16'h1234;
2700 flow[n].tup.dst_tcp_udp_port = 16'hABCD;
2701 flow[n].frame.frame_type = 5'b00010;
2702 flow[n].frame.frame_class = CL_IP;
2703 flow[n].frame.type = -1;
2704 flow[n].frame.class_mask = 0;
2705 flow[n].frame.class_funct = CLF_SRC;
2706 flow[n].frame.data_type = DAT_SEQ |DAT_LEN_EXACT;
2707 flow[n].frame.data_seed = 128;
2708 flow[n].rx_param.rcv_isn = 32'hA5A5_F5F5;
2709 flow[n].fl_state.tcp_flags = 6'b00_0010;
2710 flow[n].flow_no = 0;
2711 }
2712 printf("MAQ-DEBUG: NIU_RxPktConf Done Time: %0d.\n", {get_time(HI),get_time(LO)});
2713
2714// mailbox_put (flow_mb, rxflow);
2715*/
2716 DA_L = 8'h0;
2717 if (iport === 0)
2718 {
2719 for(n = 0; n< RxPktCnt; n++) {
2720
2721 flow_p0[n] = new;
2722 flow_p0[n].frame.frame_type = 5'b00010;
2723 flow_p0[n].frame.frame_class = CL_IP;
2724 flow_p0[n].src_node.l2_addr = 48'hde_f0_72_a0_a0_a0;
2725 flow_p0[n].src_node.tos = 8'hf5;
2726 flow_p0[n].src_node.tci = {ii[3:0],ii};
2727 flow_p0[n].src_node.ip_addr = 32'hcccc_a0a0;
2728 flow_p0[n].src_node.src_port = 20'h000a0;
2729
2730 flow_p0[n].dst_node.l2_addr = {40'h12_34_56_a0_a0,DA_L};
2731 flow_p0[n].dst_node.tci = 16'hcb00;
2732 flow_p0[n].dst_node.ip_addr = 32'h8888_b0b0;
2733 flow_p0[n].dst_node.src_port = 20'h000b0;
2734
2735 flow_p0[n].tup.src_tcp_udp_port = 16'h12a0;
2736 flow_p0[n].tup.dst_tcp_udp_port = 16'habb0;
2737 flow_p0[n].frame.type = -1;
2738 flow_p0[n].frame.class_mask = 0;
2739 flow_p0[n].frame.class_funct = CLF_SRC;
2740 flow_p0[n].frame.data_type = DAT_SEQ |DAT_LEN_EXACT;
2741 flow_p0[n].frame.data_seed = 128;
2742 flow_p0[n].rx_param.rcv_isn = 32'hA5A5_a0a0;
2743 flow_p0[n].fl_state.tcp_flags = 6'b00_0010;
2744 flow_p0[n].flow_no = 0;
2745 ii = ii +1;
2746 if (DA_L == 8'h07)
2747 {
2748 DA_L = 8'h00;
2749 }
2750 else
2751 {
2752 DA_L = DA_L + 1;
2753 }
2754 }
2755 PR_INFO("fc_niu_asm_event", MON_INFO,
2756 psprintf("MAQ-DEBUG: NIU_RxPktConf Done for IPORT %0d", iport));
2757 }
2758 else if (iport === 1)
2759 {
2760 for(n = 0; n< RxPktCnt; n++) {
2761
2762 flow_p1[n] = new;
2763 flow_p1[n].frame.frame_type = 5'b00010;
2764 flow_p1[n].frame.frame_class = CL_IP;
2765 flow_p1[n].src_node.l2_addr = 48'hde_f0_72_a1_a1_a1;
2766 flow_p1[n].src_node.tos = 8'hf5;
2767 flow_p1[n].src_node.tci = {ii[3:0],ii};
2768 flow_p1[n].src_node.ip_addr = 32'hcccc_a1a1;
2769 flow_p1[n].src_node.src_port = 20'h000a1;
2770
2771 flow_p1[n].dst_node.l2_addr = 48'h12_34_56_b1_b1_b1;
2772 flow_p1[n].dst_node.tci = 16'hcb00;
2773 flow_p1[n].dst_node.ip_addr = 32'h8888_b1b1;
2774 flow_p1[n].dst_node.src_port = 20'h000b1;
2775
2776 flow_p1[n].tup.src_tcp_udp_port = 16'h12a1;
2777 flow_p1[n].tup.dst_tcp_udp_port = 16'habb1;
2778 flow_p1[n].frame.type = -1;
2779 flow_p1[n].frame.class_mask = 0;
2780 flow_p1[n].frame.class_funct = CLF_SRC;
2781 flow_p1[n].frame.data_type = DAT_SEQ |DAT_LEN_EXACT;
2782 flow_p1[n].frame.data_seed = 128;
2783 flow_p1[n].rx_param.rcv_isn = 32'hA5A5_a1a1;
2784 flow_p1[n].fl_state.tcp_flags = 6'b00_0010;
2785 flow_p1[n].flow_no = 0;
2786 ii = ii +1;
2787 }
2788 PR_INFO("fc_niu_asm_event", MON_INFO,
2789 psprintf("MAQ-DEBUG: NIU_RxPktConf Done for IPORT %0d", iport));
2790 }
2791 else
2792 {
2793 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2794 psprintf("NIU_RxPktConf does not support MAC port %0d", iport));
2795 }
2796
2797}
2798
2799// ***********************************************************************************
2800task AsmToVeraIntf::NIU_RxGenPkt (integer mac_port,
2801 integer RxDmaChnlNo,
2802 integer RxPktCnt,
2803 integer RxPktLen,
2804 (integer rx_multi_PORT=0,
2805 bit [15:0] rx_multi_DMA= 16'h0))
2806{
2807integer portid;
2808integer chnlid;
2809integer pktcnt;
2810integer pktlen;
2811integer rx_multi_port;
2812bit [15:0] rx_multi_dma;
2813
2814portid = mac_port;
2815chnlid = RxDmaChnlNo;
2816pktcnt = RxPktCnt;
2817pktlen = RxPktLen;
2818rx_multi_port = rx_multi_PORT;
2819rx_multi_dma = rx_multi_DMA;
2820
2821 fork
2822 {
2823 NIU_internalrx(portid, chnlid, pktcnt, pktlen, rx_multi_port, rx_multi_dma);
2824 }
2825 join none
2826}
2827task AsmToVeraIntf::NIU_internalrx(integer mac_port,
2828 integer RxDmaChnlNo,
2829 integer RxPktCnt,
2830 integer RxPktLen,
2831 (integer rx_multi_port=0,
2832 bit [15:0] rx_multi_dma= 16'h0))
2833{
2834shadow integer n;
2835integer data_length;
2836shadow integer no_of_pkts;
2837integer last_packet;
2838integer sweep;
2839shadow integer mac_id;
2840integer dma_chnl;
2841bit[47:0] mac_addr;
2842
2843 PR_INFO("fc_niu_asm_event", MON_INFO,
2844 psprintf("KH-DEBUG: NIU_internalrx MAC_PORT = %0d, MULTI_PORT = %0d, MULTI_DMA = 0x%h", mac_port, rx_multi_port, rx_multi_dma));
2845
2846 sweep = 0;
2847 mac_id = mac_port;
2848 dma_chnl = RxDmaChnlNo;
2849 data_length = RxPktLen;
2850
2851 if (rx_multi_port == 1'b1)
2852 {
2853 no_of_pkts = RxPktCnt/2;
2854 PR_INFO("fc_niu_asm_event", MON_INFO,
2855 psprintf("KH-DEBUG: NIU_internalrx MULTI-PORT NO_OF_PKTS = %0d", no_of_pkts));
2856 }
2857 else
2858 {
2859 no_of_pkts = RxPktCnt;
2860 PR_INFO("fc_niu_asm_event", MON_INFO,
2861 psprintf("KH-DEBUG: NIU_internalrx SINGLE-PORT NO_OF_PKTS = %0d", no_of_pkts));
2862 }
2863/*
2864 for(n = 0; n< no_of_pkts; n++) {
2865 if ( mac_id ==0 | mac_id==1 ) {
2866 case(n%4) {
2867 0:{ mac_addr = 48'h0100_FFFF_0001;
2868 flow[n].dst_node.l2_addr = mac_addr;
2869 }
2870 1:{ mac_addr = 48'h1111_FFFF_0003;
2871 flow[n].dst_node.l2_addr = mac_addr;
2872 }
2873 2:{ mac_addr = 48'h2722_FFFF_0005;
2874 flow[n].dst_node.l2_addr = mac_addr;
2875 }
2876 3:{ mac_addr = 48'h3333_FFFF_0007;
2877 flow[n].dst_node.l2_addr = mac_addr;
2878 }
2879 default :{ mac_addr = 48'h2722_FFFF_0005;
2880 }
2881 }
2882 }
2883 }
2884
2885 for(n = 0; n< no_of_pkts; n++) {
2886 printf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d, Time: %0d.\n",
2887 mac_id,n,data_length, {get_time(HI),get_time(LO)});
2888 // Generate and send the packet
2889 last_packet = (n==(no_of_pkts-1));
2890 pktConfig.gen_rxPacket(flow[n], data_length,dma_chnl,mac_id,last_packet);
2891
2892 case (sweep){
2893 1: data_length = data_length + 1;
2894 2: data_length = data_length + 2;
2895 3: data_length = data_length + 3;
2896 4: data_length = data_length + 4;
2897 default : data_length = data_length;
2898 }
2899 }
2900 printf("MAQ-DEBUG: NIU_RxGenPkt Done Time: %0d.\n", {get_time(HI),get_time(LO)});
2901*/
2902 if (rx_multi_port == 0 && mac_id == 0 && rx_multi_dma == 16'h0)
2903 {
2904 for(n = 0; n< no_of_pkts; n++) {
2905 case(n%4) {
2906 0:{ mac_addr = 48'h0100_FFFF_0001;
2907 flow_p0[n].dst_node.l2_addr = mac_addr;
2908 }
2909 1:{ mac_addr = 48'h1111_FFFF_0003;
2910 flow_p0[n].dst_node.l2_addr = mac_addr;
2911 }
2912 2:{ mac_addr = 48'h2722_FFFF_0005;
2913 flow_p0[n].dst_node.l2_addr = mac_addr;
2914 }
2915 3:{ mac_addr = 48'h3333_FFFF_0007;
2916 flow_p0[n].dst_node.l2_addr = mac_addr;
2917 }
2918 default :{ mac_addr = 48'h2722_FFFF_0005;
2919 }
2920 }
2921 }
2922
2923 for(n = 0; n< no_of_pkts; n++) {
2924 PR_INFO("fc_niu_asm_event", MON_INFO,
2925 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
2926 mac_id, n, data_length));
2927 // Generate and send the packet
2928 last_packet = (n==(no_of_pkts-1));
2929 pktConfig.gen_rxPacket(flow_p0[n], data_length,dma_chnl,mac_id,last_packet);
2930
2931 case (sweep){
2932 1: data_length = data_length + 1;
2933 2: data_length = data_length + 2;
2934 3: data_length = data_length + 3;
2935 4: data_length = data_length + 4;
2936 default : data_length = data_length;
2937 }
2938 }
2939 PR_INFO("fc_niu_asm_event", MON_INFO,
2940 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d", mac_id));
2941 }
2942 else if (rx_multi_port == 0 && mac_id == 0 && rx_multi_dma[7:0] > 0)
2943 {
2944 for(n = 0; n< no_of_pkts; n++) {
2945 case (rx_multi_dma[7:0])
2946 {
2947 8'h0:{
2948 PR_ERROR("fc_niu_asm_event", MON_ERROR,
2949 psprintf("NIU_RxGenPkt: Expected MULTI_DMA[3:0] = 'h%h to be greater than 8'h0", rx_multi_dma[3:0]));
2950 }
2951 8'h1:{
2952 mac_addr = 48'h1234_56a0_a000;
2953 flow_p0[n].dst_node.l2_addr = mac_addr;
2954 p0_dma_chnl[n] = 0;
2955 }
2956 8'h2:{
2957 mac_addr = 48'h1234_56a0_a001;
2958 flow_p0[n].dst_node.l2_addr = mac_addr;
2959 p0_dma_chnl[n] = 1;
2960 }
2961 8'h3:{
2962 mac_addr = 48'h1234_56a0_a000;
2963 flow_p0[n].dst_node.l2_addr = mac_addr;
2964 p0_dma_chnl[n] = 0;
2965
2966 n++;
2967 if (n<no_of_pkts)
2968 {
2969 mac_addr = 48'h1234_56a0_a001;
2970 flow_p0[n].dst_node.l2_addr = mac_addr;
2971 p0_dma_chnl[n] = 1;
2972 }
2973 }
2974 8'h4:{
2975 mac_addr = 48'h1234_56a0_a002;
2976 flow_p0[n].dst_node.l2_addr = mac_addr;
2977 p0_dma_chnl[n] = 2;
2978 }
2979 8'h5:{
2980 mac_addr = 48'h1234_56a0_a000;
2981 flow_p0[n].dst_node.l2_addr = mac_addr;
2982 p0_dma_chnl[n] = 0;
2983
2984 n++;
2985 if (n<no_of_pkts)
2986 {
2987 mac_addr = 48'h1234_56a0_a002;
2988 flow_p0[n].dst_node.l2_addr = mac_addr;
2989 p0_dma_chnl[n] = 2;
2990 }
2991 }
2992 8'h6:{
2993 mac_addr = 48'h1234_56a0_a001;
2994 flow_p0[n].dst_node.l2_addr = mac_addr;
2995 p0_dma_chnl[n] = 1;
2996
2997 n++;
2998 if (n<no_of_pkts)
2999 {
3000 mac_addr = 48'h1234_56a0_a002;
3001 flow_p0[n].dst_node.l2_addr = mac_addr;
3002 p0_dma_chnl[n] = 2;
3003 }
3004 }
3005 8'h7:{
3006 mac_addr = 48'h1234_56a0_a000;
3007 flow_p0[n].dst_node.l2_addr = mac_addr;
3008 p0_dma_chnl[n] = 0;
3009
3010 n++;
3011 if (n<no_of_pkts)
3012 {
3013 mac_addr = 48'h1234_56a0_a001;
3014 flow_p0[n].dst_node.l2_addr = mac_addr;
3015 p0_dma_chnl[n] = 1;
3016 }
3017
3018 n++;
3019 if (n<no_of_pkts)
3020 {
3021 mac_addr = 48'h1234_56a0_a002;
3022 flow_p0[n].dst_node.l2_addr = mac_addr;
3023 p0_dma_chnl[n] = 2;
3024 }
3025 }
3026 8'h8:{
3027 mac_addr = 48'h1234_56a0_a003;
3028 flow_p0[n].dst_node.l2_addr = mac_addr;
3029 p0_dma_chnl[n] = 3;
3030 }
3031 8'h9:{
3032 mac_addr = 48'h1234_56a0_a000;
3033 flow_p0[n].dst_node.l2_addr = mac_addr;
3034 p0_dma_chnl[n] = 0;
3035
3036 n++;
3037 if (n<no_of_pkts)
3038 {
3039 mac_addr = 48'h1234_56a0_a003;
3040 flow_p0[n].dst_node.l2_addr = mac_addr;
3041 p0_dma_chnl[n] = 3;
3042 }
3043 }
3044 8'ha:{
3045 mac_addr = 48'h1234_56a0_a001;
3046 flow_p0[n].dst_node.l2_addr = mac_addr;
3047 p0_dma_chnl[n] = 1;
3048
3049 n++;
3050 if (n<no_of_pkts)
3051 {
3052 mac_addr = 48'h1234_56a0_a003;
3053 flow_p0[n].dst_node.l2_addr = mac_addr;
3054 p0_dma_chnl[n] = 3;
3055 }
3056 }
3057 8'hb:{
3058 mac_addr = 48'h1234_56a0_a000;
3059 flow_p0[n].dst_node.l2_addr = mac_addr;
3060 p0_dma_chnl[n] = 0;
3061
3062 n++;
3063 if (n<no_of_pkts)
3064 {
3065 mac_addr = 48'h1234_56a0_a001;
3066 flow_p0[n].dst_node.l2_addr = mac_addr;
3067 p0_dma_chnl[n] = 1;
3068 }
3069
3070 n++;
3071 if (n<no_of_pkts)
3072 {
3073 mac_addr = 48'h1234_56a0_a003;
3074 flow_p0[n].dst_node.l2_addr = mac_addr;
3075 p0_dma_chnl[n] = 3;
3076 }
3077 }
3078 8'hc:{
3079 mac_addr = 48'h1234_56a0_a002;
3080 flow_p0[n].dst_node.l2_addr = mac_addr;
3081 p0_dma_chnl[n] = 2;
3082
3083 n++;
3084 if (n<no_of_pkts)
3085 {
3086 mac_addr = 48'h1234_56a0_a003;
3087 flow_p0[n].dst_node.l2_addr = mac_addr;
3088 p0_dma_chnl[n] = 3;
3089 }
3090 }
3091 8'hd:{
3092 mac_addr = 48'h1234_56a0_a000;
3093 flow_p0[n].dst_node.l2_addr = mac_addr;
3094 p0_dma_chnl[n] = 0;
3095
3096 n++;
3097 if (n<no_of_pkts)
3098 {
3099 mac_addr = 48'h1234_56a0_a002;
3100 flow_p0[n].dst_node.l2_addr = mac_addr;
3101 p0_dma_chnl[n] = 2;
3102 }
3103
3104 n++;
3105 if (n<no_of_pkts)
3106 {
3107 mac_addr = 48'h1234_56a0_a003;
3108 flow_p0[n].dst_node.l2_addr = mac_addr;
3109 p0_dma_chnl[n] = 3;
3110 }
3111 }
3112 8'he:{
3113 mac_addr = 48'h1234_56a0_a001;
3114 flow_p0[n].dst_node.l2_addr = mac_addr;
3115 p0_dma_chnl[n] = 1;
3116
3117 n++;
3118 if (n<no_of_pkts)
3119 {
3120 mac_addr = 48'h1234_56a0_a002;
3121 flow_p0[n].dst_node.l2_addr = mac_addr;
3122 p0_dma_chnl[n] = 2;
3123 }
3124
3125 n++;
3126 if (n<no_of_pkts)
3127 {
3128 mac_addr = 48'h1234_56a0_a003;
3129 flow_p0[n].dst_node.l2_addr = mac_addr;
3130 p0_dma_chnl[n] = 3;
3131 }
3132 }
3133 8'hf:{
3134 mac_addr = 48'h1234_56a0_a000;
3135 flow_p0[n].dst_node.l2_addr = mac_addr;
3136 p0_dma_chnl[n] = 0;
3137
3138 n++;
3139 if (n<no_of_pkts)
3140 {
3141 mac_addr = 48'h1234_56a0_a001;
3142 flow_p0[n].dst_node.l2_addr = mac_addr;
3143 p0_dma_chnl[n] = 1;
3144 }
3145
3146 n++;
3147 if (n<no_of_pkts)
3148 {
3149 mac_addr = 48'h1234_56a0_a002;
3150 flow_p0[n].dst_node.l2_addr = mac_addr;
3151 p0_dma_chnl[n] = 2;
3152 }
3153
3154 n++;
3155 if (n<no_of_pkts)
3156 {
3157 mac_addr = 48'h1234_56a0_a003;
3158 flow_p0[n].dst_node.l2_addr = mac_addr;
3159 p0_dma_chnl[n] = 3;
3160 }
3161 }
3162 8'h10:{
3163 mac_addr = 48'h1234_56a0_a004;
3164 flow_p0[n].dst_node.l2_addr = mac_addr;
3165 p0_dma_chnl[n] = 4;
3166 }
3167 8'h20:{
3168 mac_addr = 48'h1234_56a0_a005;
3169 flow_p0[n].dst_node.l2_addr = mac_addr;
3170 p0_dma_chnl[n] = 5;
3171 }
3172 8'h40:{
3173 mac_addr = 48'h1234_56a0_a006;
3174 flow_p0[n].dst_node.l2_addr = mac_addr;
3175 p0_dma_chnl[n] = 6;
3176 }
3177 8'h80:{
3178 mac_addr = 48'h1234_56a0_a007;
3179 flow_p0[n].dst_node.l2_addr = mac_addr;
3180 p0_dma_chnl[n] = 7;
3181 }
3182 8'ha0:{
3183 mac_addr = 48'h1234_56a0_a005;
3184 flow_p0[n].dst_node.l2_addr = mac_addr;
3185 p0_dma_chnl[n] = 5;
3186
3187 n++;
3188 if (n<no_of_pkts)
3189 {
3190 mac_addr = 48'h1234_56a0_a007;
3191 flow_p0[n].dst_node.l2_addr = mac_addr;
3192 p0_dma_chnl[n] = 7;
3193 }
3194 }
3195 8'hb0:{
3196 mac_addr = 48'h1234_56a0_a004;
3197 flow_p0[n].dst_node.l2_addr = mac_addr;
3198 p0_dma_chnl[n] = 4;
3199
3200 n++;
3201 if (n<no_of_pkts)
3202 {
3203 mac_addr = 48'h1234_56a0_a005;
3204 flow_p0[n].dst_node.l2_addr = mac_addr;
3205 p0_dma_chnl[n] = 5;
3206 }
3207
3208 n++;
3209 if (n<no_of_pkts)
3210 {
3211 mac_addr = 48'h1234_56a0_a007;
3212 flow_p0[n].dst_node.l2_addr = mac_addr;
3213 p0_dma_chnl[n] = 7;
3214 }
3215 }
3216 8'hc0:{
3217 mac_addr = 48'h1234_56a0_a006;
3218 flow_p0[n].dst_node.l2_addr = mac_addr;
3219 p0_dma_chnl[n] = 6;
3220
3221 n++;
3222 if (n<no_of_pkts)
3223 {
3224 mac_addr = 48'h1234_56a0_a007;
3225 flow_p0[n].dst_node.l2_addr = mac_addr;
3226 p0_dma_chnl[n] = 7;
3227 }
3228 }
3229 8'hd0:{
3230 mac_addr = 48'h1234_56a0_a004;
3231 flow_p0[n].dst_node.l2_addr = mac_addr;
3232 p0_dma_chnl[n] = 4;
3233
3234 n++;
3235 if (n<no_of_pkts)
3236 {
3237 mac_addr = 48'h1234_56a0_a006;
3238 flow_p0[n].dst_node.l2_addr = mac_addr;
3239 p0_dma_chnl[n] = 6;
3240 }
3241
3242 n++;
3243 if (n<no_of_pkts)
3244 {
3245 mac_addr = 48'h1234_56a0_a007;
3246 flow_p0[n].dst_node.l2_addr = mac_addr;
3247 p0_dma_chnl[n] = 7;
3248 }
3249 }
3250 8'he0:{
3251 mac_addr = 48'h1234_56a0_a005;
3252 flow_p0[n].dst_node.l2_addr = mac_addr;
3253 p0_dma_chnl[n] = 5;
3254
3255 n++;
3256 if (n<no_of_pkts)
3257 {
3258 mac_addr = 48'h1234_56a0_a006;
3259 flow_p0[n].dst_node.l2_addr = mac_addr;
3260 p0_dma_chnl[n] = 6;
3261 }
3262
3263 n++;
3264 if (n<no_of_pkts)
3265 {
3266 mac_addr = 48'h1234_56a0_a007;
3267 flow_p0[n].dst_node.l2_addr = mac_addr;
3268 p0_dma_chnl[n] = 7;
3269 }
3270 }
3271 8'hf0:{
3272 mac_addr = 48'h1234_56a0_a004;
3273 flow_p0[n].dst_node.l2_addr = mac_addr;
3274 p0_dma_chnl[n] = 4;
3275
3276 n++;
3277 if (n<no_of_pkts)
3278 {
3279 mac_addr = 48'h1234_56a0_a005;
3280 flow_p0[n].dst_node.l2_addr = mac_addr;
3281 p0_dma_chnl[n] = 5;
3282 }
3283
3284 n++;
3285 if (n<no_of_pkts)
3286 {
3287 mac_addr = 48'h1234_56a0_a006;
3288 flow_p0[n].dst_node.l2_addr = mac_addr;
3289 p0_dma_chnl[n] = 6;
3290 }
3291
3292 n++;
3293 if (n<no_of_pkts)
3294 {
3295 mac_addr = 48'h1234_56a0_a007;
3296 flow_p0[n].dst_node.l2_addr = mac_addr;
3297 p0_dma_chnl[n] = 7;
3298 }
3299 }
3300 default :{ mac_addr = 48'h2722_FFFF_0005;
3301 PR_ERROR("fc_niu_asm_event", MON_ERROR,
3302 psprintf("NIU_RxGenPkt: UN-Expected MULTI_DMA[7:0] = 0x%h assignment for MAC_ID = %0d", rx_multi_dma[7:0], mac_id));
3303 }
3304 }
3305 }
3306
3307 for(n = 0; n< no_of_pkts; n++) {
3308 PR_INFO("fc_niu_asm_event", MON_INFO,
3309 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
3310 mac_id,n,data_length));
3311 // Generate and send the packet
3312 last_packet = (n==(no_of_pkts-1));
3313 pktConfig.gen_rxPacket(flow_p0[n], data_length,p0_dma_chnl[n],mac_id,last_packet);
3314
3315 case (sweep){
3316 1: data_length = data_length + 1;
3317 2: data_length = data_length + 2;
3318 3: data_length = data_length + 3;
3319 4: data_length = data_length + 4;
3320 default : data_length = data_length;
3321 }
3322 }
3323 PR_INFO("fc_niu_asm_event", MON_INFO,
3324 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d",mac_id));
3325 }
3326 else if (rx_multi_port == 0 && mac_id == 1 && rx_multi_dma[15:8] > 0)
3327 {
3328 for(n = 0; n< no_of_pkts; n++) {
3329 case (rx_multi_dma[15:8])
3330 {
3331 8'h0:{
3332 PR_ERROR("fc_niu_asm_event", MON_ERROR,
3333 psprintf("NIU_RxGenPkt: Expected MULTI_DMA[15:8] = 'h%h to be greater than 8'h0",rx_multi_dma[15:8]));
3334 }
3335 8'h1:{
3336 mac_addr = 48'h1234_56b0_b000;
3337 flow_p1[n].dst_node.l2_addr = mac_addr;
3338 p1_dma_chnl[n] = 7;
3339 }
3340 8'h2:{
3341 mac_addr = 48'h1234_56b0_b001;
3342 flow_p1[n].dst_node.l2_addr = mac_addr;
3343 p1_dma_chnl[n] = 6;
3344 }
3345 8'h3:{
3346 mac_addr = 48'h1234_56b0_b000;
3347 flow_p1[n].dst_node.l2_addr = mac_addr;
3348 p1_dma_chnl[n] = 7;
3349
3350 n++;
3351 if (n<no_of_pkts)
3352 {
3353 mac_addr = 48'h1234_56b0_b001;
3354 flow_p1[n].dst_node.l2_addr = mac_addr;
3355 p1_dma_chnl[n] = 6;
3356 }
3357 }
3358 8'h4:{
3359 mac_addr = 48'h1234_56b0_b002;
3360 flow_p1[n].dst_node.l2_addr = mac_addr;
3361 p1_dma_chnl[n] = 5;
3362 }
3363 8'h5:{
3364 mac_addr = 48'h1234_56b0_b000;
3365 flow_p1[n].dst_node.l2_addr = mac_addr;
3366 p1_dma_chnl[n] = 7;
3367
3368 n++;
3369 if (n<no_of_pkts)
3370 {
3371 mac_addr = 48'h1234_56b0_b002;
3372 flow_p1[n].dst_node.l2_addr = mac_addr;
3373 p1_dma_chnl[n] = 5;
3374 }
3375 }
3376 8'h6:{
3377 mac_addr = 48'h1234_56b0_b001;
3378 flow_p1[n].dst_node.l2_addr = mac_addr;
3379 p1_dma_chnl[n] = 6;
3380
3381 n++;
3382 if (n<no_of_pkts)
3383 {
3384 mac_addr = 48'h1234_56b0_b002;
3385 flow_p1[n].dst_node.l2_addr = mac_addr;
3386 p1_dma_chnl[n] = 5;
3387 }
3388 }
3389 8'h7:{
3390 mac_addr = 48'h1234_56b0_b000;
3391 flow_p1[n].dst_node.l2_addr = mac_addr;
3392 p1_dma_chnl[n] = 7;
3393
3394 n++;
3395 if (n<no_of_pkts)
3396 {
3397 mac_addr = 48'h1234_56b0_b001;
3398 flow_p1[n].dst_node.l2_addr = mac_addr;
3399 p1_dma_chnl[n] = 6;
3400 }
3401
3402 n++;
3403 if (n<no_of_pkts)
3404 {
3405 mac_addr = 48'h1234_56b0_b002;
3406 flow_p1[n].dst_node.l2_addr = mac_addr;
3407 p1_dma_chnl[n] = 5;
3408 }
3409 }
3410 8'h8:{
3411 mac_addr = 48'h1234_56b0_b003;
3412 flow_p1[n].dst_node.l2_addr = mac_addr;
3413 p1_dma_chnl[n] = 4;
3414 }
3415 8'h9:{
3416 mac_addr = 48'h1234_56b0_b000;
3417 flow_p1[n].dst_node.l2_addr = mac_addr;
3418 p1_dma_chnl[n] = 7;
3419
3420 n++;
3421 if (n<no_of_pkts)
3422 {
3423 mac_addr = 48'h1234_56b0_b003;
3424 flow_p1[n].dst_node.l2_addr = mac_addr;
3425 p1_dma_chnl[n] = 4;
3426 }
3427 }
3428 8'ha:{
3429 mac_addr = 48'h1234_56b0_b001;
3430 flow_p1[n].dst_node.l2_addr = mac_addr;
3431 p1_dma_chnl[n] = 6;
3432
3433 n++;
3434 if (n<no_of_pkts)
3435 {
3436 mac_addr = 48'h1234_56b0_b003;
3437 flow_p1[n].dst_node.l2_addr = mac_addr;
3438 p1_dma_chnl[n] = 4;
3439 }
3440 }
3441 8'hb:{
3442 mac_addr = 48'h1234_56b0_b000;
3443 flow_p1[n].dst_node.l2_addr = mac_addr;
3444 p1_dma_chnl[n] = 7;
3445
3446 n++;
3447 if (n<no_of_pkts)
3448 {
3449 mac_addr = 48'h1234_56b0_b001;
3450 flow_p1[n].dst_node.l2_addr = mac_addr;
3451 p1_dma_chnl[n] = 6;
3452 }
3453
3454 n++;
3455 if (n<no_of_pkts)
3456 {
3457 mac_addr = 48'h1234_56b0_b003;
3458 flow_p1[n].dst_node.l2_addr = mac_addr;
3459 p1_dma_chnl[n] = 4;
3460 }
3461 }
3462 8'hc:{
3463 mac_addr = 48'h1234_56b0_b002;
3464 flow_p1[n].dst_node.l2_addr = mac_addr;
3465 p1_dma_chnl[n] = 5;
3466
3467 n++;
3468 if (n<no_of_pkts)
3469 {
3470 mac_addr = 48'h1234_56b0_b003;
3471 flow_p1[n].dst_node.l2_addr = mac_addr;
3472 p1_dma_chnl[n] = 4;
3473 }
3474 }
3475 8'hd:{
3476 mac_addr = 48'h1234_56b0_b000;
3477 flow_p1[n].dst_node.l2_addr = mac_addr;
3478 p1_dma_chnl[n] = 7;
3479
3480 n++;
3481 if (n<no_of_pkts)
3482 {
3483 mac_addr = 48'h1234_56b0_b002;
3484 flow_p1[n].dst_node.l2_addr = mac_addr;
3485 p1_dma_chnl[n] = 5;
3486 }
3487
3488 n++;
3489 if (n<no_of_pkts)
3490 {
3491 mac_addr = 48'h1234_56b0_b003;
3492 flow_p1[n].dst_node.l2_addr = mac_addr;
3493 p1_dma_chnl[n] = 4;
3494 }
3495 }
3496 8'he:{
3497 mac_addr = 48'h1234_56b0_b001;
3498 flow_p1[n].dst_node.l2_addr = mac_addr;
3499 p1_dma_chnl[n] = 6;
3500
3501 n++;
3502 if (n<no_of_pkts)
3503 {
3504 mac_addr = 48'h1234_56b0_b002;
3505 flow_p1[n].dst_node.l2_addr = mac_addr;
3506 p1_dma_chnl[n] = 5;
3507 }
3508
3509 n++;
3510 if (n<no_of_pkts)
3511 {
3512 mac_addr = 48'h1234_56b0_b003;
3513 flow_p1[n].dst_node.l2_addr = mac_addr;
3514 p1_dma_chnl[n] = 4;
3515 }
3516 }
3517 8'hf:{
3518 mac_addr = 48'h1234_56b0_b000;
3519 flow_p1[n].dst_node.l2_addr = mac_addr;
3520 p1_dma_chnl[n] = 7;
3521
3522 n++;
3523 if (n<no_of_pkts)
3524 {
3525 mac_addr = 48'h1234_56b0_b001;
3526 flow_p1[n].dst_node.l2_addr = mac_addr;
3527 p1_dma_chnl[n] = 6;
3528 }
3529
3530 n++;
3531 if (n<no_of_pkts)
3532 {
3533 mac_addr = 48'h1234_56b0_b002;
3534 flow_p1[n].dst_node.l2_addr = mac_addr;
3535 p1_dma_chnl[n] = 5;
3536 }
3537
3538 n++;
3539 if (n<no_of_pkts)
3540 {
3541 mac_addr = 48'h1234_56b0_b003;
3542 flow_p1[n].dst_node.l2_addr = mac_addr;
3543 p1_dma_chnl[n] = 4;
3544 }
3545 }
3546 8'h10:{
3547 mac_addr = 48'h1234_56b0_b004;
3548 flow_p1[n].dst_node.l2_addr = mac_addr;
3549 p1_dma_chnl[n] = 3;
3550 }
3551 8'h20:{
3552 mac_addr = 48'h1234_56b0_b005;
3553 flow_p1[n].dst_node.l2_addr = mac_addr;
3554 p1_dma_chnl[n] = 2;
3555 }
3556 8'h40:{
3557 mac_addr = 48'h1234_56b0_b006;
3558 flow_p1[n].dst_node.l2_addr = mac_addr;
3559 p1_dma_chnl[n] = 1;
3560 }
3561 8'h80:{
3562 mac_addr = 48'h1234_56b0_b007;
3563 flow_p1[n].dst_node.l2_addr = mac_addr;
3564 p1_dma_chnl[n] = 0;
3565 }
3566 8'ha0:{
3567 mac_addr = 48'h1234_56b0_b005;
3568 flow_p1[n].dst_node.l2_addr = mac_addr;
3569 p1_dma_chnl[n] = 2;
3570
3571 n++;
3572 if (n<no_of_pkts)
3573 {
3574 mac_addr = 48'h1234_56b0_b007;
3575 flow_p1[n].dst_node.l2_addr = mac_addr;
3576 p1_dma_chnl[n] = 0;
3577 }
3578 }
3579 8'hb0:{
3580 mac_addr = 48'h1234_56b0_b004;
3581 flow_p1[n].dst_node.l2_addr = mac_addr;
3582 p1_dma_chnl[n] = 3;
3583
3584 n++;
3585 if (n<no_of_pkts)
3586 {
3587 mac_addr = 48'h1234_56b0_b005;
3588 flow_p1[n].dst_node.l2_addr = mac_addr;
3589 p1_dma_chnl[n] = 2;
3590 }
3591
3592 n++;
3593 if (n<no_of_pkts)
3594 {
3595 mac_addr = 48'h1234_56b0_b007;
3596 flow_p1[n].dst_node.l2_addr = mac_addr;
3597 p1_dma_chnl[n] = 0;
3598 }
3599 }
3600 8'hc0:{
3601 mac_addr = 48'h1234_56b0_b006;
3602 flow_p1[n].dst_node.l2_addr = mac_addr;
3603 p1_dma_chnl[n] = 1;
3604
3605 n++;
3606 if (n<no_of_pkts)
3607 {
3608 mac_addr = 48'h1234_56b0_b007;
3609 flow_p1[n].dst_node.l2_addr = mac_addr;
3610 p1_dma_chnl[n] = 0;
3611 }
3612 }
3613 8'hd0:{
3614 mac_addr = 48'h1234_56b0_b004;
3615 flow_p1[n].dst_node.l2_addr = mac_addr;
3616 p1_dma_chnl[n] = 3;
3617
3618 n++;
3619 if (n<no_of_pkts)
3620 {
3621 mac_addr = 48'h1234_56b0_b006;
3622 flow_p1[n].dst_node.l2_addr = mac_addr;
3623 p1_dma_chnl[n] = 1;
3624 }
3625
3626 n++;
3627 if (n<no_of_pkts)
3628 {
3629 mac_addr = 48'h1234_56b0_b007;
3630 flow_p1[n].dst_node.l2_addr = mac_addr;
3631 p1_dma_chnl[n] = 0;
3632 }
3633 }
3634 8'he0:{
3635 mac_addr = 48'h1234_56b0_b005;
3636 flow_p1[n].dst_node.l2_addr = mac_addr;
3637 p1_dma_chnl[n] = 2;
3638
3639 n++;
3640 if (n<no_of_pkts)
3641 {
3642 mac_addr = 48'h1234_56b0_b006;
3643 flow_p1[n].dst_node.l2_addr = mac_addr;
3644 p1_dma_chnl[n] = 1;
3645 }
3646
3647 n++;
3648 if (n<no_of_pkts)
3649 {
3650 mac_addr = 48'h1234_56b0_b007;
3651 flow_p1[n].dst_node.l2_addr = mac_addr;
3652 p1_dma_chnl[n] = 0;
3653 }
3654 }
3655 8'hf0:{
3656 mac_addr = 48'h1234_56b0_b004;
3657 flow_p1[n].dst_node.l2_addr = mac_addr;
3658 p1_dma_chnl[n] = 3;
3659
3660 n++;
3661 if (n<no_of_pkts)
3662 {
3663 mac_addr = 48'h1234_56b0_b005;
3664 flow_p1[n].dst_node.l2_addr = mac_addr;
3665 p1_dma_chnl[n] = 2;
3666 }
3667
3668 n++;
3669 if (n<no_of_pkts)
3670 {
3671 mac_addr = 48'h1234_56b0_b006;
3672 flow_p1[n].dst_node.l2_addr = mac_addr;
3673 p1_dma_chnl[n] = 1;
3674 }
3675
3676 n++;
3677 if (n<no_of_pkts)
3678 {
3679 mac_addr = 48'h1234_56b0_b007;
3680 flow_p1[n].dst_node.l2_addr = mac_addr;
3681 p1_dma_chnl[n] = 0;
3682 }
3683 }
3684 default :
3685 {
3686 PR_ERROR("fc_niu_asm_event", MON_ERROR,
3687 psprintf("NIU_RxGenPkt: UN-Expected MULTI_DMA[15:8] = 0x%h assignment for MAC_ID = %0d",rx_multi_dma[15:8],mac_id));
3688 }
3689 }
3690 }
3691
3692 for(n = 0; n< no_of_pkts; n++) {
3693 PR_INFO("fc_niu_asm_event", MON_INFO,
3694 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
3695 mac_id,n,data_length));
3696 // Generate and send the packet
3697 last_packet = (n==(no_of_pkts-1));
3698 pktConfig.gen_rxPacket(flow_p1[n], data_length,p1_dma_chnl[n],mac_id,last_packet);
3699
3700 case (sweep){
3701 1: data_length = data_length + 1;
3702 2: data_length = data_length + 2;
3703 3: data_length = data_length + 3;
3704 4: data_length = data_length + 4;
3705 default : data_length = data_length;
3706 }
3707 }
3708 PR_INFO("fc_niu_asm_event", MON_INFO,
3709 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d", mac_id));
3710 }
3711 else if (rx_multi_port == 0 && mac_id == 1 && rx_multi_dma == 16'h0)
3712//else if (rx_multi_port == 0 && mac_id == 1)
3713 {
3714 for(n = 0; n< no_of_pkts; n++) {
3715 case(n%4) {
3716 0:{ mac_addr = 48'h0100_FFFF_0001;
3717 flow_p1[n].dst_node.l2_addr = mac_addr;
3718 }
3719 1:{ mac_addr = 48'h1111_FFFF_0003;
3720 flow_p1[n].dst_node.l2_addr = mac_addr;
3721 }
3722 2:{ mac_addr = 48'h2722_FFFF_0005;
3723 flow_p1[n].dst_node.l2_addr = mac_addr;
3724 }
3725 3:{ mac_addr = 48'h3333_FFFF_0007;
3726 flow_p1[n].dst_node.l2_addr = mac_addr;
3727 }
3728 default :{ mac_addr = 48'h2722_FFFF_0005;
3729 }
3730 }
3731 }
3732
3733 for(n = 0; n< no_of_pkts; n++) {
3734 PR_INFO("fc_niu_asm_event", MON_INFO,
3735 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
3736 mac_id,n,data_length));
3737 // Generate and send the packet
3738 last_packet = (n==(no_of_pkts-1));
3739 pktConfig.gen_rxPacket(flow_p1[n], data_length,dma_chnl,mac_id,last_packet);
3740
3741 case (sweep){
3742 1: data_length = data_length + 1;
3743 2: data_length = data_length + 2;
3744 3: data_length = data_length + 3;
3745 4: data_length = data_length + 4;
3746 default : data_length = data_length;
3747 }
3748 }
3749 PR_INFO("fc_niu_asm_event", MON_INFO,
3750 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d", mac_id));
3751 }
3752 else if (rx_multi_port == 1 && (rx_multi_dma[3:0] > 0 || rx_multi_dma[7:4] > 0))
3753//else if (rx_multi_port == 1)
3754 {
3755 PR_INFO("fc_niu_asm_event", MON_INFO,
3756 "KH-DEBUG: NIU_RxGenPkt Sending Packets to both IPORT 0 & IPORT 1");
3757 PR_INFO("fc_niu_asm_event", MON_INFO,
3758 psprintf("KH-DEBUG: B4FORK MULTI_PORT = %0d, MULTI_DMA =%h", rx_multi_port, rx_multi_dma));
3759 fork
3760 {
3761 mac_id = 0;
3762 PR_INFO("fc_niu_asm_event", MON_INFO,
3763 "KH-DEBUG: NIU_RxGenPkt START Sending Packets to both IPORT 0 in MULTI_PORT MODE");
3764 PR_INFO("fc_niu_asm_event", MON_INFO,
3765 psprintf("KH-DEBUG: MULTI_PORT = %0d, MULTI_DMA =%h", rx_multi_port,rx_multi_dma));
3766 for(n = 0; n< no_of_pkts; n++) {
3767 case (rx_multi_dma[3:0])
3768 {
3769 4'h0:{
3770 PR_ERROR("fc_niu_asm_event", MON_ERROR,
3771 psprintf("NIU_RxGenPkt: Expected MULTI_DMA[3:0] = 'h%h to be greater than 4'h0",rx_multi_dma[3:0]));
3772 }
3773 4'h1:{
3774 mac_addr = 48'h1234_56a0_a000;
3775 flow_p0[n].dst_node.l2_addr = mac_addr;
3776 p0_dma_chnl[n] = 0;
3777 PR_INFO("fc_niu_asm_event", MON_INFO,
3778 psprintf("KHH-INFO-10: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3779 }
3780 4'h2:{
3781 mac_addr = 48'h1234_56a0_a001;
3782 flow_p0[n].dst_node.l2_addr = mac_addr;
3783 p0_dma_chnl[n] = 2;
3784 PR_INFO("fc_niu_asm_event", MON_INFO,
3785 psprintf("KHH-INFO-20: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3786 }
3787 4'h3:{
3788 mac_addr = 48'h1234_56a0_a000;
3789 flow_p0[n].dst_node.l2_addr = mac_addr;
3790 p0_dma_chnl[n] = 0;
3791 PR_INFO("fc_niu_asm_event", MON_INFO,
3792 psprintf("KHH-INFO-30: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3793
3794 n++;
3795 if (n<no_of_pkts)
3796 {
3797 mac_addr = 48'h1234_56a0_a001;
3798 flow_p0[n].dst_node.l2_addr = mac_addr;
3799 p0_dma_chnl[n] = 2;
3800 PR_INFO("fc_niu_asm_event", MON_INFO,
3801 psprintf("KHH-INFO-31: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3802 }
3803 }
3804 4'h4:{
3805 mac_addr = 48'h1234_56a0_a002;
3806 flow_p0[n].dst_node.l2_addr = mac_addr;
3807 p0_dma_chnl[n] = 4;
3808 PR_INFO("fc_niu_asm_event", MON_INFO,
3809 psprintf("KHH-INFO-40: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3810 }
3811 4'h5:{
3812 mac_addr = 48'h1234_56a0_a000;
3813 flow_p0[n].dst_node.l2_addr = mac_addr;
3814 p0_dma_chnl[n] = 0;
3815 PR_INFO("fc_niu_asm_event", MON_INFO,
3816 psprintf("KHH-INFO-50: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3817
3818 n++;
3819 if (n<no_of_pkts)
3820 {
3821 mac_addr = 48'h1234_56a0_a002;
3822 flow_p0[n].dst_node.l2_addr = mac_addr;
3823 p0_dma_chnl[n] = 4;
3824 PR_INFO("fc_niu_asm_event", MON_INFO,
3825 psprintf("KHH-INFO-51: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3826 }
3827 }
3828 4'h6:{
3829 mac_addr = 48'h1234_56a0_a001;
3830 flow_p0[n].dst_node.l2_addr = mac_addr;
3831 p0_dma_chnl[n] = 2;
3832 PR_INFO("fc_niu_asm_event", MON_INFO,
3833 psprintf("KHH-INFO-60: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3834
3835 n++;
3836 if (n<no_of_pkts)
3837 {
3838 mac_addr = 48'h1234_56a0_a002;
3839 flow_p0[n].dst_node.l2_addr = mac_addr;
3840 p0_dma_chnl[n] = 4;
3841 PR_INFO("fc_niu_asm_event", MON_INFO,
3842 psprintf("KHH-INFO-61: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3843 }
3844 }
3845 4'h7:{
3846 mac_addr = 48'h1234_56a0_a000;
3847 flow_p0[n].dst_node.l2_addr = mac_addr;
3848 p0_dma_chnl[n] = 0;
3849 PR_INFO("fc_niu_asm_event", MON_INFO,
3850 psprintf("KHH-INFO-70: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3851
3852 n++;
3853 if (n<no_of_pkts)
3854 {
3855 mac_addr = 48'h1234_56a0_a001;
3856 flow_p0[n].dst_node.l2_addr = mac_addr;
3857 p0_dma_chnl[n] = 2;
3858 PR_INFO("fc_niu_asm_event", MON_INFO,
3859 psprintf("KHH-INFO-71: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3860 }
3861
3862 n++;
3863 if (n<no_of_pkts)
3864 {
3865 mac_addr = 48'h1234_56a0_a002;
3866 flow_p0[n].dst_node.l2_addr = mac_addr;
3867 p0_dma_chnl[n] = 4;
3868 PR_INFO("fc_niu_asm_event", MON_INFO,
3869 psprintf("KHH-INFO-72: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3870 }
3871 }
3872 4'h8:{
3873 mac_addr = 48'h1234_56a0_a003;
3874 flow_p0[n].dst_node.l2_addr = mac_addr;
3875 p0_dma_chnl[n] = 6;
3876 PR_INFO("fc_niu_asm_event", MON_INFO,
3877 psprintf("KHH-INFO-80: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3878 }
3879 4'h9:{
3880 mac_addr = 48'h1234_56a0_a000;
3881 flow_p0[n].dst_node.l2_addr = mac_addr;
3882 p0_dma_chnl[n] = 0;
3883 PR_INFO("fc_niu_asm_event", MON_INFO,
3884 psprintf("KHH-INFO-90: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3885
3886 n++;
3887 if (n<no_of_pkts)
3888 {
3889 mac_addr = 48'h1234_56a0_a003;
3890 flow_p0[n].dst_node.l2_addr = mac_addr;
3891 p0_dma_chnl[n] = 6;
3892 PR_INFO("fc_niu_asm_event", MON_INFO,
3893 psprintf("KHH-INFO-91: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3894 }
3895 }
3896 4'ha:{
3897 mac_addr = 48'h1234_56a0_a001;
3898 flow_p0[n].dst_node.l2_addr = mac_addr;
3899 p0_dma_chnl[n] = 2;
3900 PR_INFO("fc_niu_asm_event", MON_INFO,
3901 psprintf("KHH-INFO-A0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3902
3903 n++;
3904 if (n<no_of_pkts)
3905 {
3906 mac_addr = 48'h1234_56a0_a003;
3907 flow_p0[n].dst_node.l2_addr = mac_addr;
3908 p0_dma_chnl[n] = 6;
3909 PR_INFO("fc_niu_asm_event", MON_INFO,
3910 psprintf("KHH-INFO-A1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3911 }
3912 }
3913 4'hb:{
3914 mac_addr = 48'h1234_56a0_a000;
3915 flow_p0[n].dst_node.l2_addr = mac_addr;
3916 p0_dma_chnl[n] = 0;
3917 PR_INFO("fc_niu_asm_event", MON_INFO,
3918 psprintf("KHH-INFO-B0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3919
3920 n++;
3921 if (n<no_of_pkts)
3922 {
3923 mac_addr = 48'h1234_56a0_a001;
3924 flow_p0[n].dst_node.l2_addr = mac_addr;
3925 p0_dma_chnl[n] = 2;
3926 PR_INFO("fc_niu_asm_event", MON_INFO,
3927 psprintf("KHH-INFO-B1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3928 }
3929
3930 n++;
3931 if (n<no_of_pkts)
3932 {
3933 mac_addr = 48'h1234_56a0_a003;
3934 flow_p0[n].dst_node.l2_addr = mac_addr;
3935 p0_dma_chnl[n] = 6;
3936 PR_INFO("fc_niu_asm_event", MON_INFO,
3937 psprintf("KHH-INFO-B2: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3938 }
3939 }
3940 4'hc:{
3941 mac_addr = 48'h1234_56a0_a002;
3942 flow_p0[n].dst_node.l2_addr = mac_addr;
3943 p0_dma_chnl[n] = 4;
3944 PR_INFO("fc_niu_asm_event", MON_INFO,
3945 psprintf("KHH-INFO-C0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3946
3947 n++;
3948 if (n<no_of_pkts)
3949 {
3950 mac_addr = 48'h1234_56a0_a003;
3951 flow_p0[n].dst_node.l2_addr = mac_addr;
3952 p0_dma_chnl[n] = 6;
3953 PR_INFO("fc_niu_asm_event", MON_INFO,
3954 psprintf("KHH-INFO-C1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3955 }
3956 }
3957 4'hd:{
3958 mac_addr = 48'h1234_56a0_a000;
3959 flow_p0[n].dst_node.l2_addr = mac_addr;
3960 p0_dma_chnl[n] = 0;
3961 PR_INFO("fc_niu_asm_event", MON_INFO,
3962 psprintf("KHH-INFO-D0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3963
3964 n++;
3965 if (n<no_of_pkts)
3966 {
3967 mac_addr = 48'h1234_56a0_a002;
3968 flow_p0[n].dst_node.l2_addr = mac_addr;
3969 p0_dma_chnl[n] = 4;
3970 PR_INFO("fc_niu_asm_event", MON_INFO,
3971 psprintf("KHH-INFO-D1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3972 }
3973
3974 n++;
3975 if (n<no_of_pkts)
3976 {
3977 mac_addr = 48'h1234_56a0_a003;
3978 flow_p0[n].dst_node.l2_addr = mac_addr;
3979 p0_dma_chnl[n] = 6;
3980 PR_INFO("fc_niu_asm_event", MON_INFO,
3981 psprintf("KHH-INFO-D2: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3982 }
3983 }
3984 4'he:{
3985 mac_addr = 48'h1234_56a0_a001;
3986 flow_p0[n].dst_node.l2_addr = mac_addr;
3987 p0_dma_chnl[n] = 2;
3988 PR_INFO("fc_niu_asm_event", MON_INFO,
3989 psprintf("KHH-INFO-E0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3990
3991 n++;
3992 if (n<no_of_pkts)
3993 {
3994 mac_addr = 48'h1234_56a0_a002;
3995 flow_p0[n].dst_node.l2_addr = mac_addr;
3996 p0_dma_chnl[n] = 4;
3997 PR_INFO("fc_niu_asm_event", MON_INFO,
3998 psprintf("KHH-INFO-E1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
3999 }
4000
4001 n++;
4002 if (n<no_of_pkts)
4003 {
4004 mac_addr = 48'h1234_56a0_a003;
4005 flow_p0[n].dst_node.l2_addr = mac_addr;
4006 p0_dma_chnl[n] = 6;
4007 PR_INFO("fc_niu_asm_event", MON_INFO,
4008 psprintf("KHH-INFO-E2: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
4009 }
4010 }
4011 4'hf:{
4012 mac_addr = 48'h1234_56a0_a000;
4013 flow_p0[n].dst_node.l2_addr = mac_addr;
4014 p0_dma_chnl[n] = 0;
4015 PR_INFO("fc_niu_asm_event", MON_INFO,
4016 psprintf("KHH-INFO-F0: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
4017
4018 n++;
4019 if (n<no_of_pkts)
4020 {
4021 mac_addr = 48'h1234_56a0_a001;
4022 flow_p0[n].dst_node.l2_addr = mac_addr;
4023 p0_dma_chnl[n] = 2;
4024 PR_INFO("fc_niu_asm_event", MON_INFO,
4025 psprintf("KHH-INFO-F1: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
4026 }
4027
4028 n++;
4029 if (n<no_of_pkts)
4030 {
4031 mac_addr = 48'h1234_56a0_a002;
4032 flow_p0[n].dst_node.l2_addr = mac_addr;
4033 p0_dma_chnl[n] = 4;
4034 PR_INFO("fc_niu_asm_event", MON_INFO,
4035 psprintf("KHH-INFO-F2: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
4036 }
4037
4038 n++;
4039 if (n<no_of_pkts)
4040 {
4041 mac_addr = 48'h1234_56a0_a003;
4042 flow_p0[n].dst_node.l2_addr = mac_addr;
4043 p0_dma_chnl[n] = 6;
4044 PR_INFO("fc_niu_asm_event", MON_INFO,
4045 psprintf("KHH-INFO-F3: FOR FLOW_P0[%0d], DMA_CHNL[%0d] = %0d",n,n,p0_dma_chnl[n]));
4046 }
4047 }
4048 default :
4049 {mac_addr = 48'h2722_FFFF_0005;
4050 PR_ERROR("fc_niu_asm_event", MON_ERROR,
4051 psprintf("NIU_RxGenPkt: UN-Expected MULTI_DMA[3:0] = 'h%h assignment for MAC_ID = %0d",rx_multi_dma[3:0],mac_id));
4052 }
4053 }
4054 }
4055// mac_id = 0;
4056 for(n = 0; n< no_of_pkts; n++) {
4057 PR_INFO("fc_niu_asm_event", MON_INFO,
4058 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
4059 mac_id,n,data_length));
4060 // Generate and send the packet
4061 last_packet = (n==(no_of_pkts-1));
4062 pktConfig.gen_rxPacket(flow_p0[n], data_length,p0_dma_chnl[n],mac_id,last_packet);
4063
4064 case (sweep){
4065 1: data_length = data_length + 1;
4066 2: data_length = data_length + 2;
4067 3: data_length = data_length + 3;
4068 4: data_length = data_length + 4;
4069 default : data_length = data_length;
4070 }
4071 }
4072 PR_INFO("fc_niu_asm_event", MON_INFO,
4073 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d", mac_id));
4074 }
4075 {
4076 mac_id = 1;
4077 for(n = 0; n< no_of_pkts; n++) {
4078 case (rx_multi_dma[7:4])
4079 {
4080 4'h0:{
4081 PR_ERROR("fc_niu_asm_event", MON_ERROR,
4082 psprintf("NIU_RxGenPkt: Expected MULTI_DMA[7:4] = 'h%h to be greater than 4'h0",rx_multi_dma[7:4]));
4083 }
4084 4'h1:{
4085 mac_addr = 48'h1234_56b0_b000;
4086 flow_p1[n].dst_node.l2_addr = mac_addr;
4087 p1_dma_chnl[n] = 1;
4088 PR_INFO("fc_niu_asm_event", MON_INFO,
4089 psprintf("KHH-INFO-10: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4090 }
4091 4'h2:{
4092 mac_addr = 48'h1234_56b0_b001;
4093 flow_p1[n].dst_node.l2_addr = mac_addr;
4094 p1_dma_chnl[n] = 3;
4095 PR_INFO("fc_niu_asm_event", MON_INFO,
4096 psprintf("KHH-INFO-20: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4097 }
4098 4'h3:{
4099 mac_addr = 48'h1234_56b0_b000;
4100 flow_p1[n].dst_node.l2_addr = mac_addr;
4101 p1_dma_chnl[n] = 1;
4102 PR_INFO("fc_niu_asm_event", MON_INFO,
4103 psprintf("KHH-INFO-30: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4104
4105 n++;
4106 if (n<no_of_pkts)
4107 {
4108 mac_addr = 48'h1234_56b0_b001;
4109 flow_p1[n].dst_node.l2_addr = mac_addr;
4110 p1_dma_chnl[n] = 3;
4111 PR_INFO("fc_niu_asm_event", MON_INFO,
4112 psprintf("KHH-INFO-31: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4113 }
4114 }
4115 4'h4:{
4116 mac_addr = 48'h1234_56b0_b002;
4117 flow_p1[n].dst_node.l2_addr = mac_addr;
4118 p1_dma_chnl[n] = 5;
4119 PR_INFO("fc_niu_asm_event", MON_INFO,
4120 psprintf("KHH-INFO-40: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4121 }
4122 4'h5:{
4123 mac_addr = 48'h1234_56b0_b000;
4124 flow_p1[n].dst_node.l2_addr = mac_addr;
4125 p1_dma_chnl[n] = 1;
4126 PR_INFO("fc_niu_asm_event", MON_INFO,
4127 psprintf("KHH-INFO-50: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4128
4129 n++;
4130 if (n<no_of_pkts)
4131 {
4132 mac_addr = 48'h1234_56b0_b002;
4133 flow_p1[n].dst_node.l2_addr = mac_addr;
4134 p1_dma_chnl[n] = 5;
4135 PR_INFO("fc_niu_asm_event", MON_INFO,
4136 psprintf("KHH-INFO-51: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4137 }
4138 }
4139 4'h6:{
4140 mac_addr = 48'h1234_56b0_b001;
4141 flow_p1[n].dst_node.l2_addr = mac_addr;
4142 p1_dma_chnl[n] = 3;
4143 PR_INFO("fc_niu_asm_event", MON_INFO,
4144 psprintf("KHH-INFO-60: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4145
4146 n++;
4147 if (n<no_of_pkts)
4148 {
4149 mac_addr = 48'h1234_56b0_b002;
4150 flow_p1[n].dst_node.l2_addr = mac_addr;
4151 p1_dma_chnl[n] = 5;
4152 PR_INFO("fc_niu_asm_event", MON_INFO,
4153 psprintf("KHH-INFO-61: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4154 }
4155 }
4156 4'h7:{
4157 mac_addr = 48'h1234_56b0_b000;
4158 flow_p1[n].dst_node.l2_addr = mac_addr;
4159 p1_dma_chnl[n] = 1;
4160 PR_INFO("fc_niu_asm_event", MON_INFO,
4161 psprintf("KHH-INFO-70: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4162
4163 n++;
4164 if (n<no_of_pkts)
4165 {
4166 mac_addr = 48'h1234_56b0_b001;
4167 flow_p1[n].dst_node.l2_addr = mac_addr;
4168 p1_dma_chnl[n] = 3;
4169 PR_INFO("fc_niu_asm_event", MON_INFO,
4170 psprintf("KHH-INFO-71: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4171 }
4172
4173 n++;
4174 if (n<no_of_pkts)
4175 {
4176 mac_addr = 48'h1234_56b0_b002;
4177 flow_p1[n].dst_node.l2_addr = mac_addr;
4178 p1_dma_chnl[n] = 5;
4179 PR_INFO("fc_niu_asm_event", MON_INFO,
4180 psprintf("KHH-INFO-72: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4181 }
4182 }
4183 4'h8:{
4184 mac_addr = 48'h1234_56b0_b003;
4185 flow_p1[n].dst_node.l2_addr = mac_addr;
4186 p1_dma_chnl[n] = 7;
4187 PR_INFO("fc_niu_asm_event", MON_INFO,
4188 psprintf("KHH-INFO-80: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4189 }
4190 4'h9:{
4191 mac_addr = 48'h1234_56b0_b000;
4192 flow_p1[n].dst_node.l2_addr = mac_addr;
4193 p1_dma_chnl[n] = 1;
4194 PR_INFO("fc_niu_asm_event", MON_INFO,
4195 psprintf("KHH-INFO-90: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4196
4197 n++;
4198 if (n<no_of_pkts)
4199 {
4200 mac_addr = 48'h1234_56b0_b003;
4201 flow_p1[n].dst_node.l2_addr = mac_addr;
4202 p1_dma_chnl[n] = 7;
4203 PR_INFO("fc_niu_asm_event", MON_INFO,
4204 psprintf("KHH-INFO-91: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4205 }
4206 }
4207 4'ha:{
4208 mac_addr = 48'h1234_56b0_b001;
4209 flow_p1[n].dst_node.l2_addr = mac_addr;
4210 p1_dma_chnl[n] = 3;
4211 PR_INFO("fc_niu_asm_event", MON_INFO,
4212 psprintf("KHH-INFO-A0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4213
4214 n++;
4215 if (n<no_of_pkts)
4216 {
4217 mac_addr = 48'h1234_56b0_b003;
4218 flow_p1[n].dst_node.l2_addr = mac_addr;
4219 p1_dma_chnl[n] = 7;
4220 PR_INFO("fc_niu_asm_event", MON_INFO,
4221 psprintf("KHH-INFO-A1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4222 }
4223 }
4224 4'hb:{
4225 mac_addr = 48'h1234_56b0_b000;
4226 flow_p1[n].dst_node.l2_addr = mac_addr;
4227 p1_dma_chnl[n] = 1;
4228 PR_INFO("fc_niu_asm_event", MON_INFO,
4229 psprintf("KHH-INFO-B0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4230
4231 n++;
4232 if (n<no_of_pkts)
4233 {
4234 mac_addr = 48'h1234_56b0_b001;
4235 flow_p1[n].dst_node.l2_addr = mac_addr;
4236 p1_dma_chnl[n] = 3;
4237 PR_INFO("fc_niu_asm_event", MON_INFO,
4238 psprintf("KHH-INFO-B1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4239 }
4240
4241 n++;
4242 if (n<no_of_pkts)
4243 {
4244 mac_addr = 48'h1234_56b0_b003;
4245 flow_p1[n].dst_node.l2_addr = mac_addr;
4246 p1_dma_chnl[n] = 7;
4247 PR_INFO("fc_niu_asm_event", MON_INFO,
4248 psprintf("KHH-INFO-B2: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4249 }
4250 }
4251 4'hc:{
4252 mac_addr = 48'h1234_56b0_b002;
4253 flow_p1[n].dst_node.l2_addr = mac_addr;
4254 p1_dma_chnl[n] = 5;
4255 PR_INFO("fc_niu_asm_event", MON_INFO,
4256 psprintf("KHH-INFO-C0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4257
4258 n++;
4259 if (n<no_of_pkts)
4260 {
4261 mac_addr = 48'h1234_56b0_b003;
4262 flow_p1[n].dst_node.l2_addr = mac_addr;
4263 p1_dma_chnl[n] = 7;
4264 PR_INFO("fc_niu_asm_event", MON_INFO,
4265 psprintf("KHH-INFO-C1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4266 }
4267 }
4268 4'hd:{
4269 mac_addr = 48'h1234_56b0_b000;
4270 flow_p1[n].dst_node.l2_addr = mac_addr;
4271 p1_dma_chnl[n] = 1;
4272 PR_INFO("fc_niu_asm_event", MON_INFO,
4273 psprintf("KHH-INFO-D0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4274
4275 n++;
4276 if (n<no_of_pkts)
4277 {
4278 mac_addr = 48'h1234_56b0_b002;
4279 flow_p1[n].dst_node.l2_addr = mac_addr;
4280 p1_dma_chnl[n] = 5;
4281 PR_INFO("fc_niu_asm_event", MON_INFO,
4282 psprintf("KHH-INFO-D1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4283 }
4284
4285 n++;
4286 if (n<no_of_pkts)
4287 {
4288 mac_addr = 48'h1234_56b0_b003;
4289 flow_p1[n].dst_node.l2_addr = mac_addr;
4290 p1_dma_chnl[n] = 7;
4291 PR_INFO("fc_niu_asm_event", MON_INFO,
4292 psprintf("KHH-INFO-D2: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4293 }
4294 }
4295 4'he:{
4296 mac_addr = 48'h1234_56b0_b001;
4297 flow_p1[n].dst_node.l2_addr = mac_addr;
4298 p1_dma_chnl[n] = 3;
4299 PR_INFO("fc_niu_asm_event", MON_INFO,
4300 psprintf("KHH-INFO-E0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4301
4302 n++;
4303 if (n<no_of_pkts)
4304 {
4305 mac_addr = 48'h1234_56b0_b002;
4306 flow_p1[n].dst_node.l2_addr = mac_addr;
4307 p1_dma_chnl[n] = 5;
4308 PR_INFO("fc_niu_asm_event", MON_INFO,
4309 psprintf("KHH-INFO-E1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4310 }
4311
4312 n++;
4313 if (n<no_of_pkts)
4314 {
4315 mac_addr = 48'h1234_56b0_b003;
4316 flow_p1[n].dst_node.l2_addr = mac_addr;
4317 p1_dma_chnl[n] = 7;
4318 PR_INFO("fc_niu_asm_event", MON_INFO,
4319 psprintf("KHH-INFO-E2: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4320 }
4321 }
4322 4'hf:{
4323 mac_addr = 48'h1234_56b0_b000;
4324 flow_p1[n].dst_node.l2_addr = mac_addr;
4325 p1_dma_chnl[n] = 1;
4326 PR_INFO("fc_niu_asm_event", MON_INFO,
4327 psprintf("KHH-INFO-F0: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4328
4329 n++;
4330 if (n<no_of_pkts)
4331 {
4332 mac_addr = 48'h1234_56b0_b001;
4333 flow_p1[n].dst_node.l2_addr = mac_addr;
4334 p1_dma_chnl[n] = 3;
4335 PR_INFO("fc_niu_asm_event", MON_INFO,
4336 psprintf("KHH-INFO-F1: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4337 }
4338
4339 n++;
4340 if (n<no_of_pkts)
4341 {
4342 mac_addr = 48'h1234_56b0_b002;
4343 flow_p1[n].dst_node.l2_addr = mac_addr;
4344 p1_dma_chnl[n] = 5;
4345 PR_INFO("fc_niu_asm_event", MON_INFO,
4346 psprintf("KHH-INFO-F2: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4347 }
4348
4349 n++;
4350 if (n<no_of_pkts)
4351 {
4352 mac_addr = 48'h1234_56b0_b003;
4353 flow_p1[n].dst_node.l2_addr = mac_addr;
4354 p1_dma_chnl[n] = 7;
4355 PR_INFO("fc_niu_asm_event", MON_INFO,
4356 psprintf("KHH-INFO-F3: FOR FLOW_P1[%0d], DMA_CHNL[%0d] = %0d",n,n,p1_dma_chnl[n]));
4357 }
4358 }
4359 default :
4360 {
4361 PR_ERROR("fc_niu_asm_event", MON_ERROR,
4362 psprintf("NIU_RxGenPkt: UN-Expected MULTI_DMA[7:4] = 'h%h assignment for MAC_ID = %0d",rx_multi_dma[7:4],mac_id));
4363 }
4364 }
4365 }
4366// mac_id = 1;
4367 for(n = 0; n< no_of_pkts; n++) {
4368 PR_INFO("fc_niu_asm_event", MON_INFO,
4369 psprintf("DEBUG: niu_rx_template_test: Sending frame to MAC[%0d]. Sequence: %0d, Frame Length: %0d",
4370 mac_id,n,data_length));
4371 // Generate and send the packet
4372 last_packet = (n==(no_of_pkts-1));
4373 pktConfig.gen_rxPacket(flow_p1[n], data_length,p1_dma_chnl[n],mac_id,last_packet);
4374
4375 case (sweep){
4376 1: data_length = data_length + 1;
4377 2: data_length = data_length + 2;
4378 3: data_length = data_length + 3;
4379 4: data_length = data_length + 4;
4380 default : data_length = data_length;
4381 }
4382 }
4383 PR_INFO("fc_niu_asm_event", MON_INFO,
4384 psprintf("MAQ-DEBUG: NIU_RxGenPkt Done FOR IPORT %0d", mac_id));
4385 }
4386 join none
4387 }
4388 else
4389 {
4390 PR_ERROR("fc_niu_asm_event", MON_ERROR,
4391 psprintf("NIU_RxGenPkt: Not Valid Value for rx_multi_port = %0d",rx_multi_port));
4392 }
4393}
4394#endif
4395
4396
4397
4398// ***********************************************************************************
4399
4400
4401#ifndef FC_NO_PEU_VERA
4402task AsmToVeraIntf::set_StartPEUTest () {
4403
4404 printf ("\n In set_StartPEUTest... setting StartPEUTest\n");
4405 trigger (ON, e_StartPEUTest);
4406}
4407
4408
4409//----------------------------------------------------------------
4410// Enable PCIe endpoint to expect a request from N2.
4411// This routine, called from the Assembly via a user event,
4412// triggers 1 Egress Command from N2.
4413// Since the Denali end-point errors on un-expected packets,
4414// it must be notified everytime N2 sends it a packet.
4415//
4416// cmdType: Type of command to transmit
4417// CFGRD0 = Config Read Type 0
4418// CFGRD1 = Config Read Type 1
4419// CFGWR0 = Config Write Type 0
4420// CFGWR1 = Config Write Type 1
4421// IORD = I/O Read
4422// IOWR = I/O Write
4423// MRD = Memory Read
4424// MWR = Memory Write
4425//
4426// addr: Request Address
4427//
4428// txLen: Request length in bytes.
4429//
4430// startData: Soon to be obsolete.
4431//
4432// error: currently undefined.
4433//----------------------------------------------------------------
4434
4435task AsmToVeraIntf::EnablePCIeEgCmd (string cmdType,
4436 bit [63:0] addr,
4437 bit [31:0] txLen,
4438 bit [31:0] startData,
4439 string err) {
4440
4441 N2fcPEUparams PEUparams = new ();
4442
4443 PEUparams.cmdType = cmdType;
4444 PEUparams.addr = addr;
4445 PEUparams.txLen = txLen;
4446 PEUparams.startData = startData;
4447 PEUparams.err = err;
4448
4449 mailbox_put (asm2peu_mbox, PEUparams);
4450
4451}
4452
4453//----------------------------------------------------------------
4454// Enable PCIe endpoint to transmit a DMA command to N2.
4455// This routine, called from the Assembly via a user event,
4456// triggers multple Ingress DMA commands to N2.
4457//
4458// cmdType: Type of command to transmit
4459// DMAWR = Memory Write only
4460// DMARD = Memory Read only
4461// RANDOM = Random Memory R/W
4462//
4463// StartAddr and EndAddr together define the range of addresses
4464// within which Vera is allowed to randomize.
4465//
4466// TxLen: Request length in bytes. Converted from string to
4467// hex in N2fcCtx.vr routine. Valid values
4468// RANDOM = Random Size
4469// 1 = 1 byte
4470// 2 = 2 bytes, and so on upto PCIe max size.
4471//
4472// NumCmds: Number of commands to transmit
4473//
4474// error: currently undefined.
4475//----------------------------------------------------------------
4476
4477task AsmToVeraIntf::EnablePCIeIgCmd (string cmdType,
4478 bit [63:0] StartAddr,
4479 bit [63:0] EndAddr,
4480 string txLen,
4481 bit [31:0] NumCmds,
4482 string err) {
4483
4484 N2fcPEUparams PEUparams = new ();
4485
4486 PEUparams.cmdType = cmdType;
4487 PEUparams.StartAddr = StartAddr;
4488 PEUparams.EndAddr = EndAddr;
4489 PEUparams.DMATxLen = txLen;
4490 PEUparams.NumCmds = NumCmds;
4491 PEUparams.err = err;
4492
4493 mailbox_put (asm2peu_mbox, PEUparams);
4494
4495}
4496#endif
4497
4498task AsmToVeraIntf::IosErrInj (string errtype, bit [15:0] ctag, bit [39:0] pa) {
4499
4500 integer inj_result;
4501 integer errt =1;
4502
4503 ios_err_packet err_pkt;
4504
4505// ios_ras_inj ras_injector;
4506
4507 SocErr_Type err_type;
4508
4509#ifndef GATESIM
4510 ras_interrupt.monitor_err_interrupt(ras_injector, 4000);
4511#endif
4512
4513/* ras_injector = new(niu_sii_inj_bind, dmu_sii_inj_bind, sio_niu_inj_bind, sio_dmu_inj_bind,
4514 l2_0_sio_inj_bind, l2_1_sio_inj_bind, l2_2_sio_inj_bind, l2_3_sio_inj_bind,
4515 l2_4_sio_inj_bind, l2_5_sio_inj_bind, l2_6_sio_inj_bind, l2_7_sio_inj_bind,
4516 sii_ncu_inj_bind, dbg);
4517*/
4518
4519 case (errtype) {
4520#ifndef FC_NO_NIU_T2
4521 "NIUSII_CUE": err_type = NIUSII_CUE;
4522 "NIUSII_CCE": err_type = NIUSII_CCE;
4523 "NIUSII_AP": err_type = NIUSII_AP;
4524 "NIUSII_DP": err_type = NIUSII_DP;
4525 "NIUSII_CMDP": err_type = NIUSII_CMDP;
4526 "NIUSII_IOAE": err_type = NIUSII_IOAE;
4527 "NIUSII_IOUE": err_type = NIUSII_IOUE;
4528 "SIONIU_DP": err_type = SIONIU_DP;
4529 "SIONIU_CUE": err_type = SIONIU_CUE;
4530 "SIONIU_CCE": err_type = SIONIU_CCE;
4531#endif
4532 "DMUSII_CUE": err_type = DMUSII_CUE;
4533 "DMUSII_CCE": err_type = DMUSII_CCE;
4534 "DMUSII_AP": err_type = DMUSII_AP;
4535 "DMUSII_DP": err_type = DMUSII_DP;
4536 "DMUSII_BEP": err_type = DMUSII_BEP;
4537 "DMUSII_CMDP": err_type = DMUSII_CMDP;
4538 "DMUSII_TOUT": err_type = DMUSII_TOUT;
4539 "DMUSII_IOAE": err_type = DMUSII_IOAE;
4540 "DMUSII_IOUE": err_type = DMUSII_IOUE;
4541 "SIODMU_DP": err_type = SIODMU_DP;
4542 "SIODMU_CUE": err_type = SIODMU_CUE;
4543 "SIODMU_CCE": err_type = SIODMU_CCE;
4544 "L2SIO_DP": err_type = L2SIO_DP;
4545 "L2SIO_EBIT": err_type = L2SIO_EBIT;
4546 "L2SIO_CUE": err_type = L2SIO_CUE;
4547 "L2SIO_CCE": err_type = L2SIO_CCE;
4548 "SIINCU_DP": err_type = SIINCU_DP;
4549 "SIINCU_CUE": err_type = SIINCU_CUE;
4550 "SIINCU_CCE": err_type = SIINCU_CCE;
4551 "DMUNCU_WRACK_P": err_type = DMUNCU_WRACK_P;
4552 "NCUDMU_MONDO_IDP": err_type = NCUDMU_MONDO_IDP;
4553 "SIIDMU_WRACK_P": err_type = SIIDMU_WRACK_P;
4554 default: errt = 0;
4555 }
4556
4557 err_pkt = new(err_type, ctag, pa);
4558
4559 inj_result = ras_injector.inj_err_packet(err_pkt);
4560
4561 // printf ("\n IOS Error Injector end\n");
4562}
4563
4564
4565task AsmToVeraIntf::L2ErrTrapCount(reg [8:0] count=0)
4566{
4567// DAtrap DATrp = new();
4568 gUtil.l2_trap_count(count);
4569 printf("In L2 Trap Counting task");
4570}
4571
4572task AsmToVeraIntf::IosRandErrInj (string errtype, integer num_errs, integer weight) {
4573
4574 integer inj_result;
4575 integer errt =1;
4576
4577 ios_err_packet err_pkt;
4578
4579 SocErr_Type err_type;
4580
4581#ifndef GATESIM
4582 ras_interrupt.monitor_err_interrupt(ras_injector, 4000);
4583#endif
4584
4585 case (errtype) {
4586#ifndef FC_NO_NIU_T2
4587 "NIUSII_CUE": err_type = NIUSII_CUE;
4588 "NIUSII_CCE": err_type = NIUSII_CCE;
4589 "NIUSII_AP": err_type = NIUSII_AP;
4590 "NIUSII_DP": err_type = NIUSII_DP;
4591 "SIONIU_DP": err_type = SIONIU_DP;
4592 "SIONIU_CUE": err_type = SIONIU_CUE;
4593 "SIONIU_CCE": err_type = SIONIU_CCE;
4594#endif
4595 "DMUSII_CUE": err_type = DMUSII_CUE;
4596 "DMUSII_CCE": err_type = DMUSII_CCE;
4597 "DMUSII_AP": err_type = DMUSII_AP;
4598 "DMUSII_DP": err_type = DMUSII_DP;
4599 "SIODMU_DP": err_type = SIODMU_DP;
4600 "SIODMU_CUE": err_type = SIODMU_CUE;
4601 "SIODMU_CCE": err_type = SIODMU_CCE;
4602 "L2SIO_DP": err_type = L2SIO_DP;
4603 "L2SIO_CUE": err_type = L2SIO_CUE;
4604 "L2SIO_CCE": err_type = L2SIO_CCE;
4605 "SIINCU_DP": err_type = SIINCU_DP;
4606 "SIINCU_CCE": err_type = SIINCU_CCE;
4607 "SIINCU_CUE": err_type = SIINCU_CUE;
4608 default: errt = 0;
4609 }
4610
4611// needed? err_pkt = new(err_type, ctag, pa);
4612
4613 inj_result = ras_injector.inj_rand_err(err_type, num_errs, weight);
4614
4615 // printf ("\n IOS Random Error Injector end\n");
4616}
4617
4618
4619// Use this to mark progress or a location in code. Any action can be
4620// performed based on the string passed in. This is very flexible if all
4621// you need is tid and pc.
4622task AsmToVeraIntf::marker(string what, reg [5:0] fromTid, reg [63:0] pc)
4623{
4624 case (what) {
4625 "bootEnd": {
4626 // gOutOfBoot works with User Events to show asm diag progress.
4627 // Function gUtil.getRunStatus will tell you which threads are running.
4628 // (so will top_if.core_running_status)
4629 // Function gUtil.getThreadEnables will tell you what +thread was.
4630 // (so will top_if.th_check_enable)
4631 //
4632 // for SW thread startup, you will not know what threads are supposed
4633 // to start so it will be hard to wait for all to start in that case!
4634 //
4635 // Here is how you could use gOutOfBoot if +thread is used:
4636 // while (top_if.th_check_enable !== gOutOfBoot) wait_var(gOutOfBoot);
4637 gOutOfBoot[fromTid] = 1;
4638 probe_if.gOutOfBoot[fromTid] <= gOutOfBoot[fromTid];
4639 }
4640 "bootStart": {
4641 // see comments for bootEnd above. This will clear bits in gOutOfBoot
4642 // when that thread starts boot code execution after a reset.
4643 //
4644 // Here is how you could use gOutOfBoot if +thread is used, once you
4645 // detect a warm reset has started.
4646
4647 // Any thread has started boot code after this line of code
4648 // while (top_if.th_check_enable === gOutOfBoot) wait_var(gOutOfBoot);
4649
4650 // All threads have started boot code after this line of code.
4651 // With the large staggering of 64 threads, gOutOfBoot may NEVER
4652 // be zero!!!
4653 // while (gOutOfBoot) wait_var(gOutOfBoot);
4654
4655 // All threads have finished boot code after this line of code
4656 // while (top_if.th_check_enable !== gOutOfBoot) wait_var(gOutOfBoot);
4657 gOutOfBoot[fromTid] = 0;
4658 probe_if.gOutOfBoot[fromTid] <= gOutOfBoot[fromTid];
4659 }
4660 default: error("AsmToVeraIntf::marker got unknown string (%s)!\n", what);
4661 } // case
4662
4663}
4664task AsmToVeraIntf::reset_now(string what)
4665{
4666 case (what) {
4667 "PWRON_RST": {
4668 random_rst_if.POR_from_UserEvent <= 1;
4669 }
4670 "PB_RST": {
4671 random_rst_if.PB_RST_from_UserEvent <= 1;
4672 }
4673 default: error("AsmToVeraIntf::reset_now got unknown string (%s)!\n", what);
4674 } // case
4675
4676}