[OpenSPARC-T2-DV] / verif / env / fc / vera / include / cpxorder.if.vrh

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: cpxorder.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC_CPXORDER_IF_VRH
#define INC_CPXORDER_IF_VRH

interface cpxorder {

    input ccx_rclk CLOCK hdl_node "tb_top.cpu.l2clk";
    input ccx_gdbginit_l PSAMPLE #-1 hdl_node "tb_top.cpu.rst_l2_por_";
    
    // cpxport 0,1,2,3,4,5,6,7

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc0_data_cx2";
#ifdef CCX_GATE
    input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl0__ard__dir_a";
#else
    input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl0.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc1_data_cx2";
#ifdef CCX_GATE
    input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl1__ard__dir_a";
#else
    input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl1.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc2_data_cx2";
#ifdef CCX_GATE
    input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl2__ard__dir_a";
#else
    input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl2.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc3_data_cx2";
#ifdef CCX_GATE
    input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl3__ard__dir_a";
#else
    input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl3.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc4_data_cx2";
#ifdef CCX_GATE
    input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl4__ard__dir_a";
#else
    input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl4.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc5_data_cx2";
#ifdef CCX_GATE
    input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl5__ard__dir_a";
#else
    input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl5.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc6_data_cx2";
#ifdef CCX_GATE
    input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl6__ard__dir_a";
#else
    input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl6.ard.dir_a";
#endif

    input [CPX_WIDTH-1:0] cpx_spc_data_cx2_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc7_data_cx2";
#ifdef CCX_GATE
    input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl7__ard__dir_a";
#else
    input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl7.ard.dir_a";
#endif


    // l2port 0,1,2,3, 4, 5, 6, 7
    input [7:0] sctag_cpx_req_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_req_cq";
    input sctag_cpx_atom_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag0_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_req_cq";
    input sctag_cpx_atom_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag1_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_req_cq";
    input sctag_cpx_atom_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag2_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_req_cq";
    input sctag_cpx_atom_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag3_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_req_cq";
    input sctag_cpx_atom_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag4_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_req_cq";
    input sctag_cpx_atom_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag5_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_req_cq";
    input sctag_cpx_atom_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag6_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_data_ca";

    input [7:0] sctag_cpx_req_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_req_cq";
    input sctag_cpx_atom_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_atom_cq";
    input [7:0] cpx_sctag_grant_cx_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag7_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_data_ca";

    //input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_req_cq";
#ifdef CCX_GATE
    input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "{tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_7_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_6_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_5_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_4_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_3_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_2_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_1_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_0_}";
#else
    input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.io_cpx_req_cq_d1";
#endif
    input sctag_cpx_atom_cq_8 PSAMPLE #-1 hdl_node "1'b0";
    input [7:0] cpx_sctag_grant_cx_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx_io_grant_cx";
    input [CPX_WIDTH-1:0] sctag_cpx_data_ca_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_data_ca";

}

#endif
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: cpxorder.if.vrh
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	#ifndef INC_CPXORDER_IF_VRH
	36	#define INC_CPXORDER_IF_VRH
	37
	38	interface cpxorder {
	39
	40	input ccx_rclk CLOCK hdl_node "tb_top.cpu.l2clk";
	41	input ccx_gdbginit_l PSAMPLE #-1 hdl_node "tb_top.cpu.rst_l2_por_";
	42
	43	// cpxport 0,1,2,3,4,5,6,7
	44
	45	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc0_data_cx2";
	46	#ifdef CCX_GATE
	47	input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl0__ard__dir_a";
	48	#else
	49	input dir_a_0 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl0.ard.dir_a";
	50	#endif
	51
	52	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc1_data_cx2";
	53	#ifdef CCX_GATE
	54	input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl1__ard__dir_a";
	55	#else
	56	input dir_a_1 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl1.ard.dir_a";
	57	#endif
	58
	59	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc2_data_cx2";
	60	#ifdef CCX_GATE
	61	input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl2__ard__dir_a";
	62	#else
	63	input dir_a_2 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl2.ard.dir_a";
	64	#endif
65
66	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc3_data_cx2";
67	#ifdef CCX_GATE
68	input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl3__ard__dir_a";
69	#else
70	input dir_a_3 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl3.ard.dir_a";
71	#endif
72
73	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc4_data_cx2";
74	#ifdef CCX_GATE
75	input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl4__ard__dir_a";
76	#else
77	input dir_a_4 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl4.ard.dir_a";
78	#endif
79
80	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc5_data_cx2";
81	#ifdef CCX_GATE
82	input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl5__ard__dir_a";
83	#else
84	input dir_a_5 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl5.ard.dir_a";
85	#endif
86
87	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc6_data_cx2";
88	#ifdef CCX_GATE
89	input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl6__ard__dir_a";
90	#else
91	input dir_a_6 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl6.ard.dir_a";
92	#endif
93
94	input [CPX_WIDTH-1:0] cpx_spc_data_cx2_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_spc7_data_cx2";
95	#ifdef CCX_GATE
96	input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx__cpx_arbl7__ard__dir_a";
97	#else
98	input dir_a_7 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.cpx_arbl7.ard.dir_a";
99	#endif
100
101
102	// l2port 0,1,2,3, 4, 5, 6, 7
103	input [7:0] sctag_cpx_req_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_req_cq";
104	input sctag_cpx_atom_cq_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_atom_cq";
105	input [7:0] cpx_sctag_grant_cx_0 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag0_grant_cx";
106	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_0 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag0_cpx_data_ca";
107
108	input [7:0] sctag_cpx_req_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_req_cq";
109	input sctag_cpx_atom_cq_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_atom_cq";
110	input [7:0] cpx_sctag_grant_cx_1 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag1_grant_cx";
111	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_1 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag1_cpx_data_ca";
112
113	input [7:0] sctag_cpx_req_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_req_cq";
114	input sctag_cpx_atom_cq_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_atom_cq";
115	input [7:0] cpx_sctag_grant_cx_2 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag2_grant_cx";
116	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_2 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag2_cpx_data_ca";
117
118	input [7:0] sctag_cpx_req_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_req_cq";
119	input sctag_cpx_atom_cq_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_atom_cq";
120	input [7:0] cpx_sctag_grant_cx_3 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag3_grant_cx";
121	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_3 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag3_cpx_data_ca";
122
123	input [7:0] sctag_cpx_req_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_req_cq";
124	input sctag_cpx_atom_cq_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_atom_cq";
125	input [7:0] cpx_sctag_grant_cx_4 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag4_grant_cx";
126	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_4 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag4_cpx_data_ca";
127
128	input [7:0] sctag_cpx_req_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_req_cq";
129	input sctag_cpx_atom_cq_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_atom_cq";
130	input [7:0] cpx_sctag_grant_cx_5 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag5_grant_cx";
131	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_5 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag5_cpx_data_ca";
132
133	input [7:0] sctag_cpx_req_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_req_cq";
134	input sctag_cpx_atom_cq_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_atom_cq";
135	input [7:0] cpx_sctag_grant_cx_6 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag6_grant_cx";
136	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_6 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag6_cpx_data_ca";
137
138	input [7:0] sctag_cpx_req_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_req_cq";
139	input sctag_cpx_atom_cq_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_atom_cq";
140	input [7:0] cpx_sctag_grant_cx_7 PSAMPLE #-1 hdl_node "tb_top.cpu.cpx_sctag7_grant_cx";
141	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_7 PSAMPLE #-1 hdl_node "tb_top.cpu.sctag7_cpx_data_ca";
142
143	//input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_req_cq";
144	#ifdef CCX_GATE
145	input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "{tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_7_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_6_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_5_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_4_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_3_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_2_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_1_, tb_top.cpu.ccx.cpx__io_cpx_req_cq_d1_0_}";
146	#else
147	input [7:0] sctag_cpx_req_cq_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx.io_cpx_req_cq_d1";
148	#endif
149	input sctag_cpx_atom_cq_8 PSAMPLE #-1 hdl_node "1'b0";
150	input [7:0] cpx_sctag_grant_cx_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.cpx_io_grant_cx";
151	input [CPX_WIDTH-1:0] sctag_cpx_data_ca_8 PSAMPLE #-1 hdl_node "tb_top.cpu.ccx.io_cpx_data_ca";
152
153	}
154
155	#endif