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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / vera / include / fc_top.if.vrh
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_top.if.vrh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_FC_IF_VRH
36#define INC_FC_IF_VRH
37
38
39
40#include <vera_defines.vrh>
41#include <defines.vri>
42
43#define FC_IF_OUTPUT_SKEW #0
44#define FC_IF_INPUT_SKEW #-0
45#define FC_IF_OUTPUT_EDGE NHOLD
46#define FC_IF_INPUT_EDGE NSAMPLE
47#define FC_IF_BOTH_DIR NSAMPLE NHOLD
48
49
50// interface names MUST be unique to ALL var names in ALL vera code
51// for NTB. These interface names are global names. Adding '_if'
52// is a good idea!
53
54// This line must be present -- it drives the entire Vera environment.
55// Ends up in the vshell as vera's SystemClock. Should be the FASTEST clock.
56// Is used when you do @(posedge CLOCK);
57// Each interface should still have it's own clock!
58hdl_node CLOCK "tb_top.SystemClock";
59
60interface random_rst_if {
61 input clk CLOCK hdl_node "tb_top.system_reset.Sysclk";
62// output [63:0] gOutOfBoot_4_reset PHOLD FC_IF_OUTPUT_SKEW hdl_node "tb_top.system_reset.gOutOfBoot";
63 output POR_from_UserEvent NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.system_reset.POR_from_UserEvent";
64 output PB_RST_from_UserEvent NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.system_reset.PB_RST_from_UserEvent";
65}
66
67// misc probes
68interface probe_if {
69 input [7:0] sim_status FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.sim_status";
70 input rst_l FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.reset";
71 input flush_reset_complete FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.flush_reset_complete";
72 input [63:0] th_check_enable FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.verif_args.th_check_enable";
73 input clk CLOCK hdl_node "tb_top.cpu.l2clk";
74
75 input pm FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_pm";
76 input ba01 FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba01";
77 input ba23 FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba23";
78 input ba45 FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba45";
79 input ba67 FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_spc_ba67";
80 input hashing FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ncu_sii_l2_idx_hash_en";
81
82 output [63:0] gOutOfBoot PHOLD FC_IF_OUTPUT_SKEW hdl_node "tb_top.gOutOfBoot";
83
84#ifdef TCU_GATE
85 input [7:0] jtag_instr FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "{tb_top.cpu.tcu.jtag_ctl__instr_7_,tb_top.cpu.tcu.jtag_ctl__instr_6_,tb_top.cpu.tcu.jtag_ctl__instr_5_,tb_top.cpu.tcu.jtag_ctl__instr_4_,tb_top.cpu.tcu.jtag_ctl__instr_3_,tb_top.cpu.tcu.jtag_ctl__instr_2_,tb_top.cpu.tcu.jtag_ctl__instr_1_,tb_top.cpu.tcu.jtag_ctl__tcu_jtag_tap_ctl_instr_l}";
86 input shift_dr_state FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.tcu.jtag_ctl__tcu_jtag_tap_ctl_N55";
87#else
88 input [7:0] jtag_instr FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.tcu.jtag_ctl.tcu_jtag_tap_ctl.instr";
89 input shift_dr_state FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.tcu.jtag_ctl.tcu_jtag_tap_ctl.shift_dr_state";
90#endif
91
92 input ccu_serdes_dtm FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.ccu_serdes_dtm";
93 input start_dtm_at_ccu_serdes_dtm FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.start_dtm_at_ccu_serdes_dtm";
94 input start_peu_dtm_training FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.start_peu_dtm_training";
95
96 input rst_ncu_unpark_thread FC_IF_INPUT_EDGE FC_IF_INPUT_SKEW hdl_node "tb_top.cpu.rst_ncu_unpark_thread";
97}
98
99interface period_if {
100 input clk CLOCK hdl_node "tb_top.SystemClock";
101 input [31:0] core_period FC_IF_INPUT_EDGE #-0 hdl_node "tb_top.core_period";
102 input core_period_change FC_IF_INPUT_EDGE #-3 hdl_node "tb_top.core_period_change";
103}
104
105
106interface ncu_if {
107 // NCU probes for LDST_sync
108 input clk CLOCK hdl_node "tb_top.cpu.l2clk";
109 output [39:0] b8_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pa";
110 output [145:0] b8_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b8_cpx_pkt";
111 output [2:0] b8_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b8_cpx_cid";
112 output b8_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b8_cpx_ctrue";
113 output b8_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b8_cpx_swap";
114}
115
116port ldStSync_port {
117 pa;
118 pkt;
119 cid;
120 ctrue;
121 swap;
122 clk;
123}
124
125#ifdef NOL2RTL
126interface l2_if {
127 // L2 probes for LDST_sync
128 input clk CLOCK hdl_node "tb_top.cpu.l2clk";
129
130#ifndef RTL_NO_BNK01
131 output [39:0] b0_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pa";
132 output [145:0] b0_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b0_cpx_pkt";
133 output [39:0] b1_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pa";
134 output [145:0] b1_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b1_cpx_pkt";
135 output [2:0] b0_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b0_cpx_cid";
136 output b0_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b0_cpx_ctrue";
137 output b0_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b0_cpx_swap";
138 output [2:0] b1_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b1_cpx_cid";
139 output b1_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b1_cpx_ctrue";
140 output b1_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b1_cpx_swap";
141#endif
142
143#ifndef RTL_NO_BNK23
144 output [39:0] b2_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pa";
145 output [145:0] b2_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b2_cpx_pkt";
146 output [39:0] b3_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pa";
147 output [145:0] b3_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b3_cpx_pkt";
148 output [2:0] b2_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b2_cpx_cid";
149 output b2_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b2_cpx_ctrue";
150 output b2_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b2_cpx_swap";
151 output [2:0] b3_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b3_cpx_cid";
152 output b3_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b3_cpx_ctrue";
153 output b3_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b3_cpx_swap";
154#endif
155
156#ifndef RTL_NO_BNK45
157 output [39:0] b4_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pa";
158 output [145:0] b4_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b4_cpx_pkt";
159 output [39:0] b5_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pa";
160 output [145:0] b5_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b5_cpx_pkt";
161 output [2:0] b4_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b4_cpx_cid";
162 output b4_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b4_cpx_ctrue";
163 output b4_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b4_cpx_swap";
164 output [2:0] b5_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b5_cpx_cid";
165 output b5_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b5_cpx_ctrue";
166 output b5_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b5_cpx_swap";
167#endif
168
169#ifndef RTL_NO_BNK67
170 output [39:0] b6_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pa";
171 output [145:0] b6_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b6_cpx_pkt";
172 output [39:0] b7_cpx_pa NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pa";
173 output [145:0] b7_cpx_pkt NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b7_cpx_pkt";
174 output [2:0] b6_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b6_cpx_cid";
175 output b6_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b6_cpx_ctrue";
176 output b6_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b6_cpx_swap";
177 output [2:0] b7_cpx_cid NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b7_cpx_cid";
178 output b7_cpx_ctrue NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b7_cpx_ctrue";
179 output b7_cpx_swap NR0 FC_IF_OUTPUT_SKEW hdl_node "tb_top.b7_cpx_swap";
180#endif
181
182}
183
184#ifndef RTL_NO_BNK01
185bind ldStSync_port ldStSync_bind_b0 {
186 pa l2_if.b0_cpx_pa;
187 pkt l2_if.b0_cpx_pkt;
188 cid l2_if.b0_cpx_cid;
189 ctrue l2_if.b0_cpx_ctrue;
190 swap l2_if.b0_cpx_swap;
191 clk l2_if.clk;
192}
193bind ldStSync_port ldStSync_bind_b1 {
194 pa l2_if.b1_cpx_pa;
195 pkt l2_if.b1_cpx_pkt;
196 cid l2_if.b1_cpx_cid;
197 ctrue l2_if.b1_cpx_ctrue;
198 swap l2_if.b1_cpx_swap;
199 clk l2_if.clk;
200}
201#endif
202
203#ifndef RTL_NO_BNK23
204bind ldStSync_port ldStSync_bind_b2 {
205 pa l2_if.b2_cpx_pa;
206 pkt l2_if.b2_cpx_pkt;
207 cid l2_if.b2_cpx_cid;
208 ctrue l2_if.b2_cpx_ctrue;
209 swap l2_if.b2_cpx_swap;
210 clk l2_if.clk;
211}
212bind ldStSync_port ldStSync_bind_b3 {
213 pa l2_if.b3_cpx_pa;
214 pkt l2_if.b3_cpx_pkt;
215 cid l2_if.b3_cpx_cid;
216 ctrue l2_if.b3_cpx_ctrue;
217 swap l2_if.b3_cpx_swap;
218 clk l2_if.clk;
219}
220#endif
221
222#ifndef RTL_NO_BNK45
223bind ldStSync_port ldStSync_bind_b4 {
224 pa l2_if.b4_cpx_pa;
225 pkt l2_if.b4_cpx_pkt;
226 cid l2_if.b4_cpx_cid;
227 ctrue l2_if.b4_cpx_ctrue;
228 swap l2_if.b4_cpx_swap;
229 clk l2_if.clk;
230}
231bind ldStSync_port ldStSync_bind_b5 {
232 pa l2_if.b5_cpx_pa;
233 pkt l2_if.b5_cpx_pkt;
234 cid l2_if.b5_cpx_cid;
235 ctrue l2_if.b5_cpx_ctrue;
236 swap l2_if.b5_cpx_swap;
237 clk l2_if.clk;
238}
239#endif
240
241#ifndef RTL_NO_BNK67
242bind ldStSync_port ldStSync_bind_b6 {
243 pa l2_if.b6_cpx_pa;
244 pkt l2_if.b6_cpx_pkt;
245 cid l2_if.b6_cpx_cid;
246 ctrue l2_if.b6_cpx_ctrue;
247 swap l2_if.b6_cpx_swap;
248 clk l2_if.clk;
249}
250bind ldStSync_port ldStSync_bind_b7 {
251 pa l2_if.b7_cpx_pa;
252 pkt l2_if.b7_cpx_pkt;
253 cid l2_if.b7_cpx_cid;
254 ctrue l2_if.b7_cpx_ctrue;
255 swap l2_if.b7_cpx_swap;
256 clk l2_if.clk;
257}
258#endif
259
260
261#endif
262
263
264bind ldStSync_port ldStSync_bind_b8 {
265 pa ncu_if.b8_cpx_pa;
266 pkt ncu_if.b8_cpx_pkt;
267 cid ncu_if.b8_cpx_cid;
268 ctrue ncu_if.b8_cpx_ctrue;
269 swap ncu_if.b8_cpx_swap;
270 clk ncu_if.clk;
271}
272
273port probesPort {
274 th_check_enable;
275 rst_l;
276 pm;
277 ba01;
278 ba23;
279 ba45;
280 ba67;
281}
282
283bind probesPort probesBind {
284 th_check_enable probe_if.th_check_enable;
285 rst_l probe_if.rst_l;
286 pm probe_if.pm;
287 ba01 probe_if.ba01;
288 ba23 probe_if.ba23;
289 ba45 probe_if.ba45;
290 ba67 probe_if.ba67;
291}
292
293#endif
294
Full OpenSPARC design & verification tarball including full HDL.