projects / OpenSPARC-T2-DV / blame
| Commit | Line | Data |
|---|---|---|
| 86530b38 AT |
1 | #ifndef INCL__NIU_PKTGEN_CSR_EV2A_VRH |
| 2 | #define INCL__NIU_PKTGEN_CSR_EV2A_VRH 1 | |
| 3 | ||
| 4 | #ifdef __VERA__ | |
| 5 | #ifdef FC_NO_PEU_VERA | |
| 6 | #ifdef USE_BOBO | |
| 7 | #define EV2A_HEX_VALUE(val) 64'hc900017f/**/val | |
| 8 | #else | |
| 9 | #define EV2A_HEX_VALUE(val) 64'hc900001f/**/val | |
| 10 | #endif // USE_BOBO | |
| 11 | #else // FC_NO_PEU_VERA | |
| 12 | #define EV2A_HEX_VALUE(val) 64'hc1000000/**/val | |
| 13 | #endif // FC_NO_PEU_VERA | |
| 14 | #else // __VERA__ | |
| 15 | #ifdef FC_NO_PEU_VERA | |
| 16 | #ifdef USE_BOBO | |
| 17 | #define EV2A_HEX_VALUE(val) (N2_PCIE_BASE_ADDR+MEM64_OFFSET_BASE_REG_DATA+PCIE_MEM64_OFFSET+0x17f/**/val) | |
| 18 | #else | |
| 19 | #define EV2A_HEX_VALUE(val) (N2_PCIE_BASE_ADDR+MEM64_OFFSET_BASE_REG_DATA+PCIE_MEM64_OFFSET+0x1f/**/val) | |
| 20 | #endif // USE_BOBO | |
| 21 | #else // FC_NO_PEU_VERA | |
| 22 | #define EV2A_HEX_VALUE(val) 0xc1000000/**/val | |
| 23 | #endif // FC_NO_PEU_VERA | |
| 24 | #endif // __VERA__ | |
| 25 | ||
| 26 | #define NIU_PKTGEN_CSR_EV2A_START EV2A_HEX_VALUE(00) | |
| 27 | #define NIU_PKTGEN_CSR_EV2A_END EV2A_HEX_VALUE(ff) | |
| 28 | ||
| 29 | #define NIU_PKTGEN_CSR_EV2A_RX_START EV2A_HEX_VALUE(00) | |
| 30 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_MASK1 EV2A_HEX_VALUE(00) | |
| 31 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_VAL1 EV2A_HEX_VALUE(08) | |
| 32 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_RELO1 EV2A_HEX_VALUE(10) | |
| 33 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_MASK2 EV2A_HEX_VALUE(18) | |
| 34 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_VAL2 EV2A_HEX_VALUE(20) | |
| 35 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_RELO2 EV2A_HEX_VALUE(28) | |
| 36 | #define NIU_PKTGEN_CSR_EV2A_RX_LOG_PAGE_VLD EV2A_HEX_VALUE(30) | |
| 37 | #define NIU_PKTGEN_CSR_EV2A_RBR_CFIG_A EV2A_HEX_VALUE(38) | |
| 38 | #define NIU_PKTGEN_CSR_EV2A_RBR_CFIG_B EV2A_HEX_VALUE(40) | |
| 39 | #define NIU_PKTGEN_CSR_EV2A_RCR_CFIG_A EV2A_HEX_VALUE(48) | |
| 40 | #define NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG1_0 EV2A_HEX_VALUE(50) | |
| 41 | #define NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG2 EV2A_HEX_VALUE(58) | |
| 42 | #define NIU_PKTGEN_CSR_EV2A_RXDMA_CFIG1_1 EV2A_HEX_VALUE(60) | |
| 43 | #define NIU_PKTGEN_CSR_EV2A_RBR_KICK EV2A_HEX_VALUE(68) | |
| 44 | ||
| 45 | #define NIU_PKTGEN_CSR_EV2A_TX_START EV2A_HEX_VALUE(80) | |
| 46 | #define NIU_PKTGEN_CSR_EV2A_TX_RNG_CFIG EV2A_HEX_VALUE(80) | |
| 47 | #define NIU_PKTGEN_CSR_EV2A_TX_RNG_KICK EV2A_HEX_VALUE(88) | |
| 48 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK1 EV2A_HEX_VALUE(90) | |
| 49 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE1 EV2A_HEX_VALUE(98) | |
| 50 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO1 EV2A_HEX_VALUE(a0) | |
| 51 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_MASK2 EV2A_HEX_VALUE(a8) | |
| 52 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_VALUE2 EV2A_HEX_VALUE(b0) | |
| 53 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_RELO2 EV2A_HEX_VALUE(b8) | |
| 54 | #define NIU_PKTGEN_CSR_EV2A_TX_LOG_PAGE_VLD EV2A_HEX_VALUE(c0) | |
| 55 | ||
| 56 | #endif // INCL__NIU_PKTGEN_CSR_EV2A_VRH |