projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fc / vera / interfaces / fc_shadow_scan.if.vrh
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: fc_shadow_scan.if.vrh
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef INC_FC_SHADOW_SCAN_IF_VRH
36#define INC_FC_SHADOW_SCAN_IF_VRH
37
38#include <vera_defines.vrh>
39#include "fc_top_defines.vri"
40
41//#include "tcu_top_defines.vri"
42#define INPUT_EDGE PSAMPLE
43#define INPUT_SKEW #-3
44
45interface fc_shadow_scan_if {
46 input clk CLOCK verilog_node "`TCU.gclk";
47 input spc_shadow_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscan_scan_en";
48 input [2:0] spc_shadow_scan_id INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_spc_shscanid" ;
49 input l2t_shadow_scan_en INPUT_EDGE INPUT_SKEW verilog_node "`TCU.tcu_l2t_shscan_scan_en";
50 input [117:0] spc0_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc0.tlu.ssd.shadow_unused[117:0]";
51
52#ifndef RTL_NO_SPC1
53 input [117:0] spc1_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc1.tlu.ssd.shadow_unused[117:0]";
54#endif
55#ifndef RTL_NO_SPC2
56 input [117:0] spc2_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc2.tlu.ssd.shadow_unused[117:0]";
57#endif
58#ifndef RTL_NO_SPC3
59 input [117:0] spc3_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc3.tlu.ssd.shadow_unused[117:0]";
60#endif
61#ifndef RTL_NO_SPC4
62 input [117:0] spc4_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc4.tlu.ssd.shadow_unused[117:0]";
63#endif
64#ifndef RTL_NO_SPC5
65 input [117:0] spc5_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc5.tlu.ssd.shadow_unused[117:0]";
66#endif
67#ifndef RTL_NO_SPC6
68 input [117:0] spc6_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc6.tlu.ssd.shadow_unused[117:0]";
69#endif
70#ifndef RTL_NO_SPC7
71 input [117:0] spc7_shadow_scan_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.spc7.tlu.ssd.shadow_unused[117:0]";
72#endif
73
74 input [57:0] l2t0_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t0.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t0.shadow_scan.rd_errstate_reg[27:0]}";
75 input [47:0] l2t0_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.shadow_scan.rd_notdata_reg[51:4]";
76 input [35:0] l2t0_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.shadow_scan.csr_l2_erraddr_reg[39:4]";
77
78 input [57:0] l2t1_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t1.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t1.shadow_scan.rd_errstate_reg[27:0]}";
79 input [47:0] l2t1_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t1.shadow_scan.rd_notdata_reg[51:4]";
80 input [35:0] l2t1_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t1.shadow_scan.csr_l2_erraddr_reg[39:4]";
81
82 input [57:0] l2t2_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t2.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t2.shadow_scan.rd_errstate_reg[27:0]}";
83 input [47:0] l2t2_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t2.shadow_scan.rd_notdata_reg[51:4]";
84 input [35:0] l2t2_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t2.shadow_scan.csr_l2_erraddr_reg[39:4]";
85
86 input [57:0] l2t3_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t3.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t3.shadow_scan.rd_errstate_reg[27:0]}";
87 input [47:0] l2t3_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t3.shadow_scan.rd_notdata_reg[51:4]";
88 input [35:0] l2t3_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t3.shadow_scan.csr_l2_erraddr_reg[39:4]";
89
90 input [57:0] l2t4_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t4.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t4.shadow_scan.rd_errstate_reg[27:0]}";
91 input [47:0] l2t4_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t4.shadow_scan.rd_notdata_reg[51:4]";
92 input [35:0] l2t4_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t4.shadow_scan.csr_l2_erraddr_reg[39:4]";
93
94 input [57:0] l2t5_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t5.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t5.shadow_scan.rd_errstate_reg[27:0]}";
95 input [47:0] l2t5_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t5.shadow_scan.rd_notdata_reg[51:4]";
96 input [35:0] l2t5_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t5.shadow_scan.csr_l2_erraddr_reg[39:4]";
97
98 input [57:0] l2t6_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t6.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t6.shadow_scan.rd_errstate_reg[27:0]}";
99 input [47:0] l2t6_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t6.shadow_scan.rd_notdata_reg[51:4]";
100 input [35:0] l2t6_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t6.shadow_scan.csr_l2_erraddr_reg[39:4]";
101
102 input [57:0] l2t7_rd_errstate_reg_bits INPUT_EDGE INPUT_SKEW verilog_node "{`CPU.l2t7.shadow_scan.rd_errstate_reg[63:34],`CPU.l2t7.shadow_scan.rd_errstate_reg[27:0]}";
103 input [47:0] l2t7_not_data_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t7.shadow_scan.rd_notdata_reg[51:4]";
104 input [35:0] l2t7_l2_erraddr_bits INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t7.shadow_scan.csr_l2_erraddr_reg[39:4]";
105
106}
107
108port fc_shadow_scan__port {
109 clk;
110 spc_shadow_scan_en;
111 spc_shadow_scan_id;
112 l2t_shadow_scan_en;
113 spc0_shadow_scan_bits;
114
115#ifndef RTL_NO_SPC1
116 spc1_shadow_scan_bits;
117#endif
118#ifndef RTL_NO_SPC2
119 spc2_shadow_scan_bits;
120#endif
121#ifndef RTL_NO_SPC3
122 spc3_shadow_scan_bits;
123#endif
124#ifndef RTL_NO_SPC4
125 spc4_shadow_scan_bits;
126#endif
127#ifndef RTL_NO_SPC5
128 spc5_shadow_scan_bits;
129#endif
130#ifndef RTL_NO_SPC6
131 spc6_shadow_scan_bits;
132#endif
133#ifndef RTL_NO_SPC7
134 spc7_shadow_scan_bits;
135#endif
136
137 l2t0_shadow_scan_bits;
138 l2t1_shadow_scan_bits;
139 l2t2_shadow_scan_bits;
140 l2t3_shadow_scan_bits;
141 l2t4_shadow_scan_bits;
142 l2t5_shadow_scan_bits;
143 l2t6_shadow_scan_bits;
144 l2t7_shadow_scan_bits;
145}
146
147bind fc_shadow_scan__port fc_shadow_scan_bind {
148 clk fc_shadow_scan_if.clk;
149 spc_shadow_scan_en fc_shadow_scan_if.spc_shadow_scan_en;
150 spc_shadow_scan_id fc_shadow_scan_if.spc_shadow_scan_id;
151 l2t_shadow_scan_en fc_shadow_scan_if.l2t_shadow_scan_en;
152 spc0_shadow_scan_bits fc_shadow_scan_if.spc0_shadow_scan_bits;
153
154#ifndef RTL_NO_SPC1
155 spc1_shadow_scan_bits fc_shadow_scan_if .spc1_shadow_scan_bits;
156#endif
157#ifndef RTL_NO_SPC2
158 spc2_shadow_scan_bits fc_shadow_scan_if.spc2_shadow_scan_bits;
159#endif
160#ifndef RTL_NO_SPC3
161 spc3_shadow_scan_bits fc_shadow_scan_if.spc3_shadow_scan_bits;
162#endif
163#ifndef RTL_NO_SPC4
164 spc4_shadow_scan_bits fc_shadow_scan_if.spc4_shadow_scan_bits;
165#endif
166#ifndef RTL_NO_SPC5
167 spc5_shadow_scan_bits fc_shadow_scan_if.spc5_shadow_scan_bits;
168#endif
169#ifndef RTL_NO_SPC6
170 spc6_shadow_scan_bits fc_shadow_scan_if.spc6_shadow_scan_bits;
171#endif
172#ifndef RTL_NO_SPC7
173 spc7_shadow_scan_bits fc_shadow_scan_if.spc7_shadow_scan_bits;
174#endif
175
176 l2t0_shadow_scan_bits
177 {
178 fc_shadow_scan_if.l2t0_rd_errstate_reg_bits,
179 fc_shadow_scan_if.l2t0_not_data_bits,
180 fc_shadow_scan_if.l2t0_l2_erraddr_bits
181 };
182 l2t1_shadow_scan_bits
183 {
184 fc_shadow_scan_if.l2t1_rd_errstate_reg_bits,
185 fc_shadow_scan_if.l2t1_not_data_bits,
186 fc_shadow_scan_if.l2t1_l2_erraddr_bits
187 };
188 l2t2_shadow_scan_bits
189 {
190 fc_shadow_scan_if.l2t2_rd_errstate_reg_bits,
191 fc_shadow_scan_if.l2t2_not_data_bits,
192 fc_shadow_scan_if.l2t2_l2_erraddr_bits
193 };
194 l2t3_shadow_scan_bits
195 {
196 fc_shadow_scan_if.l2t3_rd_errstate_reg_bits,
197 fc_shadow_scan_if.l2t3_not_data_bits,
198 fc_shadow_scan_if.l2t3_l2_erraddr_bits
199 };
200 l2t4_shadow_scan_bits
201 {
202 fc_shadow_scan_if.l2t4_rd_errstate_reg_bits,
203 fc_shadow_scan_if.l2t4_not_data_bits,
204 fc_shadow_scan_if.l2t4_l2_erraddr_bits
205 };
206 l2t5_shadow_scan_bits
207 {
208 fc_shadow_scan_if.l2t5_rd_errstate_reg_bits,
209 fc_shadow_scan_if.l2t5_not_data_bits,
210 fc_shadow_scan_if.l2t5_l2_erraddr_bits
211 };
212 l2t6_shadow_scan_bits
213 {
214 fc_shadow_scan_if.l2t6_rd_errstate_reg_bits,
215 fc_shadow_scan_if.l2t6_not_data_bits,
216 fc_shadow_scan_if.l2t6_l2_erraddr_bits
217 };
218 l2t7_shadow_scan_bits
219 {
220 fc_shadow_scan_if.l2t7_rd_errstate_reg_bits,
221 fc_shadow_scan_if.l2t7_not_data_bits,
222 fc_shadow_scan_if.l2t7_l2_erraddr_bits
223 };
224}
225
226#endif
227
Full OpenSPARC design & verification tarball including full HDL.