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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ssi.if.vrh | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_SSI_IF_VRH | |
36 | #define INC_SSI_IF_VRH | |
37 | ||
38 | ||
39 | #include <vera_defines.vrh> | |
40 | #include "defines.vri" | |
41 | ||
42 | interface ssi_if { | |
43 | ||
44 | input clk CLOCK verilog_node "tb_top.SSI_SCK"; | |
45 | input ssi_mosi PSAMPLE #-0 verilog_node "tb_top.SSI_MOSI"; | |
46 | output ssi_miso PHOLD #0 verilog_node "tb_top.SSI_MISO"; | |
47 | output ssi_int_l PHOLD #0 verilog_node "tb_top.SSI_EXT_INT_L"; | |
48 | input ssi_sync_l PSAMPLE #-0 verilog_node "tb_top.SSI_SYNC_L"; | |
49 | // input ssi_reset_l PSAMPLE #-0 verilog_node "tb_top.PEX_RESET_L"; | |
50 | input ssi_reset_l PSAMPLE #-0 verilog_node "tb_top.SSI_SYNC_L"; | |
51 | ||
52 | } | |
53 | ||
54 | port ssi_iport { | |
55 | clk; | |
56 | data; | |
57 | reset; | |
58 | } | |
59 | ||
60 | port ssi_oport { | |
61 | clk; | |
62 | data; | |
63 | int_l; | |
64 | sync_l; | |
65 | } | |
66 | ||
67 | ||
68 | bind ssi_iport ncu { | |
69 | clk ssi_if.clk; | |
70 | data ssi_if.ssi_mosi; | |
71 | reset ssi_if.ssi_reset_l; | |
72 | } | |
73 | ||
74 | bind ssi_oport ssi { | |
75 | clk ssi_if.clk; | |
76 | data ssi_if.ssi_miso; | |
77 | int_l ssi_if.ssi_int_l; | |
78 | sync_l ssi_if.ssi_sync_l; | |
79 | } | |
80 | ||
81 | #endif | |
82 |