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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fnx / vlib / DMUXtr / include / PEC.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: PEC.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef PEC_VRI_DEFINED
36#define PEC_VRI_DEFINED
37
38#include <vera_defines.vrh>
39#include "cReport.vrh"
40// #include "testbench.combined.vrh"
41
42#define PEC_CREDIT_TYPE__IDLE 3'b000
43
44#define PEC_CREDIT_TYPE__INIT_COMP 3'b001
45#define PEC_CREDIT_TYPE__INIT_NONPOST 3'b010
46#define PEC_CREDIT_TYPE__INIT_POST 3'b011
47
48#define PEC_CREDIT_TYPE__UPDT_COMP 3'b101
49#define PEC_CREDIT_TYPE__UPDT_NONPOST 3'b110
50#define PEC_CREDIT_TYPE__UPDT_POST 3'b111
51
52#define PEC_CREDIT_TYPE__INIT_COMP_VCNZ 8
53#define PEC_CREDIT_TYPE__INIT_NONPOST_VCNZ 9
54#define PEC_CREDIT_TYPE__INIT_POST_VCNZ 10
55
56#define PEC_CREDIT_TYPE__UPDT_COMP_VCNZ 11
57#define PEC_CREDIT_TYPE__UPDT_NONPOST_VCNZ 12
58#define PEC_CREDIT_TYPE__UPDT_POST_VCNZ 13
59
60#define PEC_CREDIT_TYPE__UPDT_COMP_NZ_AFT_INF 14
61#define PEC_CREDIT_TYPE__UPDT_NONPOST_NZ_AFT_INF 15
62#define PEC_CREDIT_TYPE__UPDT_POST_NZ_AFT_INF 16
63
64#define PEC_CREDIT_TYPE__UPDT_COMP_OVERFLOW 17
65#define PEC_CREDIT_TYPE__UPDT_NONPOST_OVERFLOW 18
66#define PEC_CREDIT_TYPE__UPDT_POST_OVERFLOW 19
67
68#define PEC_CREDIT_TYPE__RETRY 20
69
70
71
72#define PEC_TLP_CMD__IDLE 3'b000
73#define PEC_TLP_CMD__SOP 3'b110
74#define PEC_TLP_CMD__EOP 3'b011
75#define PEC_TLP_CMD__SOPEOP 3'b111
76#define PEC_TLP_CMD__DATA 3'b010
77#define PEC_TLP_CMD__ERROR 3'b001
78
79/*
80* The following "defines" specify bit ranges for fields within a 4DW PCI header
81*/
82#define PEC_PCI__HDR 127:0
83#define PEC_PCI__FMT 126:125
84#define PEC_PCI__FMT_DATA 126
85#define PEC_PCI__FMT_4DW 125
86
87#define PEC_PCI__FMT_DATA_3DW 2'b_10
88#define PEC_PCI__FMT_DATA_4DW 2'b_11
89#define PEC_PCI__FMT_NO_DATA_3DW 2'b_00
90#define PEC_PCI__FMT_NO_DATA_4DW 2'b_01
91
92#define PEC_PCI__TYPE 124:120
93#define PEC_PCI__TYPE_MEM 5'b00000
94#define PEC_PCI__TYPE_MEM_LK 5'b00001
95#define PEC_PCI__TYPE_CPL 5'b01010
96#define PEC_PCI__TYPE_CPL_LK 5'b01011
97#define PEC_PCI__TYPE_CFG0 5'b00100
98#define PEC_PCI__TYPE_CFG1 5'b00101
99#define PEC_PCI__TYPE_IO 5'b00010
100#define PEC_PCI__TYPE_MSG 5'b10000
101#define PEC_PCI__TYPE_MSG_RC_MASK 5'b00111
102#define PEC_PCI__TYPE_VALID_00 32'h00000c37
103#define PEC_PCI__TYPE_VALID_01 32'h00ff0003
104#define PEC_PCI__TYPE_VALID_10 32'h00000c35
105#define PEC_PCI__TYPE_VALID_11 32'h00ff0001
106#define PEC_PCI__TC 118:116
107#define PEC_PCI__TD 111
108#define PEC_PCI__EP 110
109#define PEC_PCI__ATTR 109:108
110#define PEC_PCI__LEN 105:96
111#define PEC_PCI__REQ_ID 95:80
112#define PEC_PCI__TLP_TAG 79:72
113#define PEC_PCI__LAST_DWBE 71:68
114#define PEC_PCI__FIRST_DWBE 67:64
115#define PEC_PCI__MSG_CODE 71:64
116#define PEC_PCI__ADDR 63:0
117#define PEC_PCI__ADDR32 63:32
118#define PEC_PCI__CPL_ID 95:80
119#define PEC_PCI__CPL_STATUS 79:77
120#define PEC_PCI__CPL_STATUS_SC 3'b_000
121#define PEC_PCI__CPL_STATUS_UR 3'b_001
122#define PEC_PCI__CPL_STATUS_CRS 3'b_010
123#define PEC_PCI__CPL_STATUS_CA 3'b_100
124#define PEC_PCI__CPL_STATUS_TIMEOUT 3'b_111
125#define PEC_PCI__CPL_STATUS_RSVD1 3'b_011
126#define PEC_PCI__CPL_STATUS_RSVD2 3'b_101
127#define PEC_PCI__CPL_STATUS_RSVD3 3'b_110
128#define PEC_PCI__CPL_STATUS_RSVD4 3'b_111
129
130#define PEC_PCI__BCM 76
131#define PEC_PCI__BYTECOUNT 75:64
132#define PEC_PCI__CPL_REQ_ID 63:48
133#define PEC_PCI__CPL_TAG 47:40
134#define PEC_PCI__LOWADDR 38:32
135
136#define PEC_PCI__MSG_CODE_ASSERT_INTA 8'h20
137#define PEC_PCI__MSG_CODE_ASSERT_INTB 8'h21
138#define PEC_PCI__MSG_CODE_ASSERT_INTC 8'h22
139#define PEC_PCI__MSG_CODE_ASSERT_INTD 8'h23
140#define PEC_PCI__MSG_CODE_DEASSERT_INTA 8'h24
141#define PEC_PCI__MSG_CODE_DEASSERT_INTB 8'h25
142#define PEC_PCI__MSG_CODE_DEASSERT_INTC 8'h26
143#define PEC_PCI__MSG_CODE_DEASSERT_INTD 8'h27
144#define PEC_PCI__MSG_CODE_PM_PME 8'h18
145#define PEC_PCI__MSG_CODE_PM_TURN_OFF 8'h19
146#define PEC_PCI__MSG_CODE_PM_TO_ACK 8'h1b
147#define PEC_PCI__MSG_CODE_PM_ACTIVE_STATE_NAK 8'h14
148#define PEC_PCI__MSG_CODE_SET_SLOT_POWER_LIMIT 8'h50
149#define PEC_PCI__MSG_CODE_ERR_COR 8'h30
150#define PEC_PCI__MSG_CODE_ERR_NONFATAL 8'h31
151#define PEC_PCI__MSG_CODE_ERR_FATAL 8'h33
152#define PEC_PCI__MSG_CODE_ATTN 8'h48
153#define PEC_PCI__MSG_CODE_VENDOR_TYPE_0 8'h7E
154#define PEC_PCI__MSG_CODE_VENDOR_TYPE_1 8'h7F
155
156
157/*
158* The following "defines" specify bit ranges for fields within a PEC record.
159*/
160#define PEC__RECD 125:0
161#define PEC__FMT 125:124
162#define PEC__FMT_DATA 125
163#define PEC__FMT_4DW 124
164#define PEC__TYPE 123:119
165#define PEC__TYPE_UR 7'b0001001
166#define PEC__TC 118:116
167#define PEC__ATTR 115:114
168#define PEC__LEN 113:104
169#define PEC__REQ_ID 103:88
170#define PEC__TLP_TAG 87:80
171#define PEC__LAST_DWBE 79:76
172#define PEC__FIRST_DWBE 75:72
173#define PEC__MSG_CODE 79:72
174#define PEC__ADDR 71:8
175#define PEC__ADDR32 39:8
176#define PEC__DWADDR 71:10
177#define PEC__DWADDR32 39:10
178#define PEC__D_PTR 7:2 /* Egress */
179#define PEC__V_PTR 9:2 /* Ingress */
180#define PEC__TERMINATE 1 /* Egress */
181#define PEC__BUF_REL 0 /* Egress */
182#define PEC__CPL_ID 103:88
183#define PEC__CPL_STATUS 87:85
184#define PEC__BCM 84
185#define PEC__BYTECOUNT 83:72
186#define PEC__CPL_REQ_ID 39:24
187#define PEC__CPL_TAG 23:16
188#define PEC__LOWADDR 14:8
189#define PEC__LOWADDR_CPL_MASK 7'b1111100
190#define PEC__LOWADDR_CPLD_MASK 7'b0111100
191#define PEC__LOWADDR_CPLD_ZERO 7'b0110000 /* Ingress */
192
193/*
194* There's a pipeline delay within the ILU when accessing the IDB
195*/
196#define PEC_IDB_ADDR_DELAY 0
197
198/*
199* Enqueue/dequeue credits are exchanged between the ILU and the DMU
200*/
201#define PEC_ILU_INGRESS_CREDITS 6
202#define PEC_ILU_EGRESS_CREDITS 4
203
204enum PECBool { e_false, e_true };
205enum PECPIOType { e_PIOMWr, e_PIOMRd,
206 e_PIOCfgIOWr, e_PIOCfgIORd};
207enum PECParamMode { e_random, e_fixed, e_random_all };
208
209
210/*
211* We'll use a enumerated type to specify ILU/TLU CSRs...
212*/
213#define PEC_LPU_CSR_MAX_COUNT 8192
214#define PEC_LPU_CSR_AHB_ADDR 14:2
215#define PEC_CSR__IS_PEC_ADDR(addr) (((addr) & 32'h00080000)!=0)
216enum PEC_CSRtype {
217 e_CSR_pec_int_en,
218 e_CSR_pec_err,
219 e_CSR_ilu_int_en,
220 e_CSR_ilu_log_en,
221 e_CSR_ilu_en_err,
222 e_CSR_ilu_err,
223 e_CSR_ilu_err_diag,
224 e_CSR_ilu_dev_cap, // ILU device capability (estar)
225 e_CSR_ilu_diagnos, // ILU Diagnostic Register
226 e_CSR_dev_cap, // TLU device capability
227 e_CSR_dev_ctl, // TLU device control
228 e_CSR_dev_status, // TLU device status
229 e_CSR_lnk_cap, // TLU link capability
230 e_CSR_lnk_ctl, // TLU link control
231 e_CSR_lnk_status, // TLU link status
232 e_CSR_slot_cap, // TLU slot capability
233 e_CSR_pme_ctl, // TLU generate PME Turn-Off message
234 e_CSR_ue_int_en,
235 e_CSR_ue_log_en,
236 e_CSR_ue_en_err,
237 e_CSR_ue_err,
238 e_CSR_ue_err_diag,
239 e_CSR_ue_recv_hdr1,
240 e_CSR_ue_recv_hdr2,
241 e_CSR_ue_xmit_hdr1,
242 e_CSR_ue_xmit_hdr2,
243 e_CSR_ce_int_en,
244 e_CSR_ce_log_en,
245 e_CSR_ce_en_err,
246 e_CSR_ce_err,
247 e_CSR_ce_err_diag,
248 e_CSR_oe_int_en,
249 e_CSR_oe_log_en,
250 e_CSR_oe_en_err,
251 e_CSR_oe_err,
252 e_CSR_oe_err_diag,
253 e_CSR_oe_recv_hdr1,
254 e_CSR_oe_recv_hdr2,
255 e_CSR_oe_xmit_hdr1,
256 e_CSR_oe_xmit_hdr2,
257 e_CSR_tlu_ctl,
258 e_CSR_tlu_stat,
259 e_CSR_tlu_diag,
260 e_CSR_tlu_debug_a,
261 e_CSR_tlu_debug_b,
262 e_CSR_ecrdt_avail,
263 e_CSR_ecrdt_used,
264 e_CSR_retry_crdt,
265 e_CSR_icrdt_init,
266 e_CSR_icrdt_avail,
267 e_CSR_icrdt_used,
268 e_CSR_tlu_prfc,
269 e_CSR_tlu_prf0,
270 e_CSR_tlu_prf1,
271 e_CSR_tlu_prf2,
272 e_CSR_serdes_rev, //DLPL/SERDES Revision
273 e_CSR_acknak_thresh, //DLPL DLL AckNak Latency Threshold
274 e_CSR_acknak_timer, //DLPL AckNak Latency Timer
275 e_CSR_replay_tim_thresh, //DLPL DLL Replay Timer Threshold
276 e_CSR_replay_timer, //DLPL DLL Replay Timer
277 e_CSR_ven_dllp_msg, //DLPL DLL Vendor DLLP Message
278 e_CSR_force_ltssm, //DLPL LTSSM Control Register
279 e_CSR_dlpl_link_cfg, //DLPL DLL Control
280 e_CSR_dlpl_link_ctl, //DLPL MACL/PCS Control
281 e_CSR_lane_skew, //DLPL MACL LANE Skew Control
282 e_CSR_symbol_num, //DLPL MACL Symbol Number Control
283 e_CSR_symbol_timer, //DLPL MACL Symbol Timer
284 e_CSR_core_status, //DLPL Core Status
285 e_CSR_dlpl_ee_log_en, //DLPL Event/Error Log Enable
286 e_CSR_dlpl_ee_int_en, //DLPL Event/Error Interrupt Enable
287 e_CSR_dlpl_ee_int_sts, //DLPL Event/Error Interrupt Status
288 e_CSR_dlpl_ee_err, //DLPL Event/Error Status Set
289 e_CSR_dlpl_ee_err_diag, //DLPL Event/Error Status Set
290 e_CSR_serdes_pll, //SERDES Control
291 e_CSR_serdes_rcvr_lane_ctl, //SERDES RECEIVER Lane 0 - 7 control
292 e_CSR_serdes_rcvr_lane_sts, //SERDES RECEIVER Lane 0 - 7 status
293 e_CSR_serdes_xmtr_lane_ctl //SERDES RECEIVER Lane 0 - 7 control
294 };
295
296enum PEC_PMtype {
297 e_PEC_PM_none, // Just a placeholder
298 e_PEC_PM_requestL1, // A ASPM request to enter L1
299 e_PEC_PM_L1, // A request/demand to enter L1
300 e_PEC_PM_L23 // A request/demand to enter L23
301 };
302
303enum PEC_FCtype {
304 e_FC_nonposted,
305 e_FC_posted,
306 e_FC_completion
307 };
308
309enum PEC_ERRtype {
310 e_ERR_none, // Not an error
311 e_ERR_ue_mfp, // Malformed packet
312 e_ERR_ue_rof, // Receiver overflow
313 e_ERR_ue_ur, // Unsupported request
314 e_ERR_ue_uc, // Unexpected completion
315 e_ERR_ue_cto, // Completion time-out
316 e_ERR_ue_fcp, // Flow-control protocol error
317 e_ERR_ue_pp, // Poisoned TLP received
318 e_ERR_ue_dlp, // Data-link protocol error(LPU)
319 e_ERR_ce_rto, // Replay time-out (LPU)
320 e_ERR_ce_rnr, // Replay roll-over (LPU)
321 e_ERR_ce_bdp, // Bad DLLP (LPU)
322 e_ERR_ce_btp, // Bad TLP (LPU)
323 e_ERR_ce_re, // Receiver error (LPU)
324 e_ERR_oe_mrc, // Memory read capture
325 e_ERR_oe_cto, // Completion time-out (dup)
326 e_ERR_oe_mfc, // Malformed completion
327 e_ERR_oe_nfp, // No forward progress
328 e_ERR_oe_lwc, // Link-width change
329 e_ERR_oe_wuc, // Unsuccessful cpl to write
330 e_ERR_oe_ruc, // Unsuccessful cpl to read
331 e_ERR_oe_crs, // Cfg cpl'n with retry status
332 e_ERR_oe_iip, // Ingress interface parity err
333 e_ERR_oe_edp, // Egress data (EDB) parity err
334 e_ERR_oe_ehp, // Egress hdr (EHB) parity err
335 e_ERR_oe_lin, // Link interrupt
336 e_ERR_oe_lrs, // Link reset
337 e_ERR_oe_ldn, // Link down
338 e_ERR_oe_lup, // Link up
339 e_ERR_oe_eru, // Egress retry buffer underflow
340 e_ERR_oe_ero, // Egress retry buffer overflow
341 e_ERR_oe_emp, // Egress minimum pkt error
342 e_ERR_oe_epe, // Egress protocol error
343 e_ERR_oe_erp, // Egress retry parity error
344 e_ERR_oe_eip, // Egress interface parity error
345 e_ERR_ilu_ihb, // Ingress hdr (IHB) parity err
346 e_ERR_dlpl_sds_los, // Serdes Loss Signal
347 e_ERR_dlpl_src_tlp, // Ingress TLP w/ inverted CRC and EDB
348 e_ERR_dlpl_unsup_dllp, // Ingress Unsupported DLLP
349 e_ERR_dlpl_ill_stp_pos, // Ingress illegal STP position
350 e_ERR_dlpl_ill_sdp_pos, // Ingress illegal SDP position
351 e_ERR_dlpl_multi_stp, // Ingress multiple stp without END/EDB
352 e_ERR_dlpl_multi_sdp, // Ingress multiple sdp without END
353 e_ERR_dlpl_ill_pad_pos, // Ingress illegal pad position
354 e_ERR_dlpl_stp_no_end_edb, // Ingress STP without END/EDB
355 e_ERR_dlpl_sdp_no_end, // Ingress STP without END
356 e_ERR_dlpl_end_no_stp_sdp, // Ingress END without STP/SDP
357 e_ERR_dlpl_sync, // Lost bit/byte sync
358 e_ERR_dlpl_ill_end_pos, // Ingress illegal END position
359 e_ERR_dlpl_kchar_dllp, // Ingress kchar in dllp
360 e_ERR_dlpl_align, // Alignment error
361 e_ERR_dlpl_elas_fifo_ovfl, // Elastic fifo overflow
362 e_ERR_dlpl_elas_fifo_unfl, // Elastic fifo underflow
363 e_ERR_dlpl_out_skip, // Number of outstanding SKIPs > 6
364 e_ERR_mmu_bypass_err, // MMU Bypass Error
365 e_ERR_mmu_translation_err, // MMU Translation Error
366 e_ERR_mmu_device_key_err, // MMU sun4v Device Key Error
367 e_ERR_msi_not_enabled_err, // MSI not enabled error
368 e_ERR_eq_not_enabled_err // Event Queue not enabled error
369 };
370
371#define PEC_ERR_isUE(err) ((err)>e_ERR_none && (err)<=e_ERR_ue_dlp)
372#define PEC_ERR_isCE(err) ((err)>=e_ERR_ce_rto && (err)<=e_ERR_ce_re)
373#define PEC_ERR_isOE(err) ((err)>=e_ERR_oe_mrc && (err)<=e_ERR_oe_eip)
374#define PEC_ERR_isILU(err) ((err)==e_ERR_ilu_ihb)
375#define PEC_ERR_isLPU(err) ( (err) == e_ERR_ue_dlp || \
376 (err) == e_ERR_ce_rto || \
377 (err) == e_ERR_ce_rnr || \
378 (err) == e_ERR_ce_bdp || \
379 (err) == e_ERR_ce_btp || \
380 (err) == e_ERR_ce_re || \
381 (err) == e_ERR_oe_lin || \
382 (err) == e_ERR_oe_lrs || \
383 (err) == e_ERR_oe_eru || \
384 (err) == e_ERR_oe_ero || \
385 (err) == e_ERR_oe_emp || \
386 (err) == e_ERR_oe_epe || \
387 (err) == e_ERR_oe_erp || \
388 (err) == e_ERR_oe_eip )
389#define PEC_ERR_isDLPL(err) ((err)>=e_ERR_dlpl_sds_los && (err)<=e_ERR_dlpl_out_skip)
390
391// Bit-masks for UE/CE/OE/ILU/DLPL flags in the PEC (top) error register
392#define PEC_ERR_UE_mask \
393 FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_FMASK
394#define PEC_ERR_CE_mask \
395 FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_FMASK
396#define PEC_ERR_OE_mask \
397 FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_FMASK
398#define PEC_ERR_ILU_mask \
399 FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_FMASK
400#define PEC_ERR_DLPL_mask \
401 FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_FMASK
402
403// Bit indices for different errors in the corresponding (lower) error registers
404#define PEC_ERR_bitIndex(err) \
405 ( PEC_ERR_isUE(err) ? \
406 ( (err) == e_ERR_ue_mfp ? \
407 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_MFP_P_POSITION \
408 : (err) == e_ERR_ue_rof ? \
409 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_ROF_P_POSITION \
410 : (err) == e_ERR_ue_ur ? \
411 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_UR_P_POSITION \
412 : (err) == e_ERR_ue_uc ? \
413 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_UC_P_POSITION \
414 : (err) == e_ERR_ue_cto ? \
415 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_CTO_P_POSITION \
416 : (err) == e_ERR_ue_fcp ? \
417 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_FCP_P_POSITION \
418 : (err) == e_ERR_ue_pp ? \
419 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_PP_P_POSITION \
420 : (err) == e_ERR_ue_dlp ? \
421 FIRE_PLC_TLU_CTB_TLR_CSR_A_UE_ERR_RW1C_ALIAS_DLP_P_POSITION \
422 : -1 ) \
423 : PEC_ERR_isCE(err) ? \
424 ( (err) == e_ERR_ce_rto ? \
425 FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_RTO_P_POSITION \
426 : (err) == e_ERR_ce_rnr ? \
427 FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_RNR_P_POSITION \
428 : (err) == e_ERR_ce_bdp ? \
429 FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_BDP_P_POSITION \
430 : (err) == e_ERR_ce_btp ? \
431 FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_BTP_P_POSITION \
432 : (err) == e_ERR_ce_re ? \
433 FIRE_PLC_TLU_CTB_TLR_CSR_A_CE_ERR_RW1C_ALIAS_RE_P_POSITION \
434 : -1 ) \
435 : PEC_ERR_isOE(err) ? \
436 ( (err) == e_ERR_oe_mrc ? \
437 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_MRC_P_POSITION \
438 : (err) == e_ERR_oe_cto ? \
439 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_CTO_P_POSITION \
440 : (err) == e_ERR_oe_mfc ? \
441 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_MFC_P_POSITION \
442 : (err) == e_ERR_oe_nfp ? \
443 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_NFP_P_POSITION \
444 : (err) == e_ERR_oe_lwc ? \
445 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_LWC_P_POSITION \
446 : (err) == e_ERR_oe_wuc ? \
447 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_WUC_P_POSITION \
448 : (err) == e_ERR_oe_ruc ? \
449 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_RUC_P_POSITION \
450 : (err) == e_ERR_oe_crs ? \
451 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_CRS_P_POSITION \
452 : (err) == e_ERR_oe_iip ? \
453 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_IIP_P_POSITION \
454 : (err) == e_ERR_oe_edp ? \
455 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EDP_P_POSITION \
456 : (err) == e_ERR_oe_ehp ? \
457 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EHP_P_POSITION \
458 : (err) == e_ERR_oe_lin ? \
459 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_LIN_P_POSITION \
460 : (err) == e_ERR_oe_lrs ? \
461 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_LRS_P_POSITION \
462 : (err) == e_ERR_oe_ldn ? \
463 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_LDN_P_POSITION \
464 : (err) == e_ERR_oe_lup ? \
465 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_LUP_P_POSITION \
466 : (err) == e_ERR_oe_eru ? \
467 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERU_P_POSITION \
468 : (err) == e_ERR_oe_ero ? \
469 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERO_P_POSITION \
470 : (err) == e_ERR_oe_emp ? \
471 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EMP_P_POSITION \
472 : (err) == e_ERR_oe_epe ? \
473 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EPE_P_POSITION \
474 : (err) == e_ERR_oe_erp ? \
475 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERP_P_POSITION \
476 : (err) == e_ERR_oe_eip ? \
477 FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EIP_P_POSITION \
478 : -1 ) \
479 : PEC_ERR_isILU(err) ? \
480 ( (err) == e_ERR_ilu_ihb ? \
481 FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POSITION \
482 : -1 ) \
483 : PEC_ERR_isDLPL(err) ? \
484 ( (err) == e_ERR_dlpl_sds_los ? \
485 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SDS_LOS_POSITION \
486 : (err) == e_ERR_dlpl_src_tlp ? \
487 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SRC_TLP_POSITION \
488 : (err) == e_ERR_dlpl_unsup_dllp ? \
489 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_UNSUP_DLLP_POSITION \
490 : (err) == e_ERR_dlpl_ill_stp_pos ? \
491 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_STP_POS_POSITION \
492 : (err) == e_ERR_dlpl_ill_sdp_pos ? \
493 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_SDP_POS_POSITION \
494 : (err) == e_ERR_dlpl_multi_stp ? \
495 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_MULTI_STP_POSITION \
496 : (err) == e_ERR_dlpl_multi_sdp ? \
497 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_MULTI_SDP_POSITION \
498 : (err) == e_ERR_dlpl_ill_pad_pos ? \
499 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_PAD_POS_POSITION \
500 : (err) == e_ERR_dlpl_stp_no_end_edb ? \
501 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_STP_NO_END_EDB_POSITION \
502 : (err) == e_ERR_dlpl_sdp_no_end ? \
503 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SDP_NO_END_POSITION \
504 : (err) == e_ERR_dlpl_end_no_stp_sdp ? \
505 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_END_EDB_NO_STP_SDP_POSITION \
506 : (err) == e_ERR_dlpl_sync ? \
507 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_SYNC_POSITION \
508 : (err) == e_ERR_dlpl_ill_end_pos ? \
509 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ILL_END_POS_POSITION \
510 : (err) == e_ERR_dlpl_kchar_dllp ? \
511 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_KCHAR_DLLP_POSITION \
512 : (err) == e_ERR_dlpl_align ? \
513 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ALIGN_POSITION \
514 : (err) == e_ERR_dlpl_elas_fifo_ovfl ? \
515 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ELASTIC_FIFO_OVRFLW_POSITION \
516 : (err) == e_ERR_dlpl_elas_fifo_unfl ? \
517 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_ELASTIC_FIFO_UNDRFLW_POSITION \
518 : (err) == e_ERR_dlpl_out_skip ? \
519 FIRE_PLC_TLU_CTB_TLR_CSR_A_EVENT_ERR_STS_CLR_RW1C_ALIAS_ERR_OUTSTANDING_SKIP_POSITION \
520 : -1 ) \
521 : -1 )
522
523// Bit indices within LPU-to-TLU status signals
524// review: not sure about thie first one
525#define PEC_ERR_LPUpos(err) ( (err) == e_ERR_ue_dlp ? 4 \
526 : (err) == e_ERR_ce_rto ? 7 \
527 : (err) == e_ERR_ce_rnr ? 4 \
528 : (err) == e_ERR_ce_bdp ? 3 \
529 : (err) == e_ERR_ce_btp ? 2 \
530 : (err) == e_ERR_ce_re ? 0 \
531 : (err) == e_ERR_oe_eru ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERU_P_POSITION \
532 : (err) == e_ERR_oe_ero ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERO_P_POSITION \
533 : (err) == e_ERR_oe_emp ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EMP_P_POSITION \
534 : (err) == e_ERR_oe_epe ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EPE_P_POSITION \
535 : (err) == e_ERR_oe_erp ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_ERP_P_POSITION \
536 : (err) == e_ERR_oe_eip ? FIRE_PLC_TLU_CTB_TLR_CSR_A_OE_ERR_RW1C_ALIAS_EIP_P_POSITION \
537 : -1 )
538
539
540/*
541parameter S_DETECT_QUIET = 5'h00;
542parameter S_DETECT_ACT = 5'h01;
543parameter S_POLL_ACTIVE = 5'h02;
544parameter S_POLL_COMPLIANCE = 5'h03;
545parameter S_POLL_CONFIG = 5'h04;
546parameter S_PRE_DETECT_QUIET = 5'h05;
547parameter S_DETECT_WAIT = 5'h06;
548parameter S_CFG_LINKWD_START = 5'h07;
549parameter S_CFG_LINKWD_ACEPT = 5'h08;
550parameter S_CFG_LANENUM_WAIT = 5'h09;
551parameter S_CFG_LANENUM_ACEPT = 5'h0A;
552parameter S_CFG_COMPLETE = 5'h0B;
553parameter S_CFG_IDLE = 5'h0C;
554parameter S_RCVRY_LOCK = 5'h0D;
555parameter S_RCVRY_RCVRCFG = 5'h0E;
556parameter S_RCVRY_IDLE = 5'h0F;
557parameter S_L0 = 5'h10;
558parameter S_L0S = 5'h11;
559parameter S_L123_SEND_EIDLE = 5'h12;
560parameter S_L1_IDLE = 5'h13;
561parameter S_L2_IDLE = 5'h14;
562parameter S_L2_WAKE = 5'h15;
563parameter S_DISABLED_ENTRY = 5'h16;
564parameter S_DISABLED_IDLE = 5'h17;
565parameter S_DISABLED = 5'h18;
566parameter S_LPBK_ENTRY = 5'h19;
567parameter S_LPBK_ACTIVE = 5'h1A;
568parameter S_LPBK_EXIT = 5'h1B;
569parameter S_LPBK_EXIT_TIMEOUT = 5'h1C;
570parameter S_HOT_RESET_ENTRY = 5'h1D;
571parameter S_HOT_RESET = 5'h1F;
572*/
573
574#endif
Full OpenSPARC design & verification tarball including full HDL.