projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: denaliPcieErrorTypes.vrh | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef DENALI_PCIEERR_TYPES_VRH | |
| 36 | #define DENALI_PCIEERR_TYPES_VRH | |
| 37 | ||
| 38 | enum denaliPcieErrorTypeT = | |
| 39 | PCIE_NO_ERROR = 0, // No error | |
| 40 | PCIE_TL_FATAL_DEN_FATAL = 1, // Inconsistent internal data structure. | |
| 41 | PCIE_PL_COR_DEN_ERROR = 2, // %s %s. | |
| 42 | PCIE_PL_NONFATAL_BIT_UNK = 3, // Detected unknown data (not 0 or 1) on lane %s[%d] (%s). | |
| 43 | PCIE_PL_NONFATAL_BIT_IDLE = 4, // Detected Electrical Idle on lane %s[%d]. | |
| 44 | PCIE_PL_NONFATAL_BIT_NIDLE = 5, // Lane %s[%d] is not Electrical Idle (%s). | |
| 45 | PCIE_PL_NONFATAL_BIT_NIDLE_MIN = 6, // Lane %s[%d] failed to remain in Electrical Idle for required time (ttxIDLEmin). | |
| 46 | PCIE_PL_NONFATAL_BIT_NIDLE_OFF = 7, // Lane %s[%d] failed to transition to Electrical Idle within required time (ttxSetToIdle). | |
| 47 | PCIE_PL_NONFATAL_BIT_DIS_NIDLE = 8, // Unconfigured lane %s[%d] is not Electrical Idle (%s). | |
| 48 | PCIE_PL_NONFATAL_SYM_DISP = 9, // Detected a symbol with incorrect running disparity %s[%d] (%s). | |
| 49 | PCIE_PL_NONFATAL_SYM_8B10B = 10, // Detected an invalid symbol (8b/10b decode error) on lane %s[%d] (%s). | |
| 50 | PCIE_PL_NONFATAL_SYM_RSV_KC = 11, // Detected a reserved special symbol on lane %s[%d] (%s). | |
| 51 | PCIE_PL_NONFATAL_MOS_NT_COM = 12, // %s[%d] Malformed Ordered Set (unterminated) - unexpected COM is found. | |
| 52 | PCIE_PL_NONFATAL_MOS_NT_STP = 13, // %s[%d] Malformed Ordered Set (unterminated) - unexpected STP is found. | |
| 53 | PCIE_PL_NONFATAL_MOS_NT_SDP = 14, // %s[%d] Malformed Ordered Set (unterminated) - unexpected SDP is found. | |
| 54 | PCIE_PL_NONFATAL_MOS_NT_END = 15, // %s[%d] Malformed Ordered Set (unterminated) - unexpected END is found. | |
| 55 | PCIE_PL_NONFATAL_MOS_NT_EDB = 16, // %s[%d] Malformed Ordered Set (unterminated) - unexpected EDB is found. | |
| 56 | PCIE_PL_NONFATAL_MOS_NT_PAD = 17, // %s[%d] Malformed Ordered Set (unterminated) - unexpected PAD is found. | |
| 57 | PCIE_PL_NONFATAL_MOS_NT_KC = 18, // %s[%d] Malformed Ordered Set (unterminated) - unexpected special symbol is found. | |
| 58 | PCIE_PL_NONFATAL_MOS_NT_DATA = 19, // %s[%d] Malformed Ordered Set (unterminated) - unexpected data symbol is found. | |
| 59 | PCIE_PL_NONFATAL_MOS_NT_UNK = 20, // %s[%d] Malformed Ordered Set (unterminated) - unknown symbol following COM. | |
| 60 | PCIE_PL_NONFATAL_MOS_UNK_KC = 21, // %s[%d] Malformed Ordered Set (unknown) - unexpected special symbol following COM. | |
| 61 | PCIE_PL_NONFATAL_MOS_FTS_NC = 22, // Malformed FTS Ordered Set - FTS symbol without a leading COM symbol. | |
| 62 | PCIE_PL_NONFATAL_MOS_FTS_L4 = 23, // %s Malformed FTS Ordered Set - less than 3 FTS symbols following COM (%s). | |
| 63 | PCIE_PL_NONFATAL_MOS_FTS_M4 = 24, // %s Malformed FTS Ordered Set - more than 3 FTS symbols following COM (%s). | |
| 64 | PCIE_PL_NONFATAL_MOS_IDL_NC = 25, // Malformed IDLE Ordered Set - IDL symbol without a leading COM symbol. | |
| 65 | PCIE_PL_NONFATAL_MOS_IDL_L4 = 26, // %s Malformed IDLE Ordered Set - less than 3 IDL symbols following COM (%s). | |
| 66 | PCIE_PL_NONFATAL_MOS_IDL_M4 = 27, // %s Malformed IDLE Ordered Set - more than 3 IDL symbols following COM (%s). | |
| 67 | PCIE_PL_NONFATAL_MOS_SKP_NC = 28, // Malformed SKIP Ordered Set - SKP symbol without a leading COM symbol. | |
| 68 | PCIE_PL_NONFATAL_MOS_SKP_L2 = 29, // %s Malformed SKIP Ordered Set - less than 1 SKP symbol following COM (%s). | |
| 69 | PCIE_PL_NONFATAL_MOS_SKP_M6 = 30, // %s Malformed SKIP Ordered Set - more than 5 SKP symbols following COM (%s). | |
| 70 | PCIE_PL_NONFATAL_MOS_SKP_T3 = 31, // %s Malformed SKIP Ordered Set - must transmit 3 SKP symbols when not Loopback Slave (%s). | |
| 71 | PCIE_PL_NONFATAL_MOS_SKP_R3 = 32, // %s Malformed SKIP Ordered Set - expects 3 SKP symbols when not Loopback Master (%s). | |
| 72 | PCIE_PL_NONFATAL_MOS_TSx_L16 = 33, // %s Malformed TS1/TS2 Ordered Set - less than 15 symbols following COM (%s). | |
| 73 | PCIE_PL_NONFATAL_MOS_TSx_M16 = 34, // %s Malformed TS1/TS2 Ordered Set - more than 15 symbols following COM (%s). | |
| 74 | PCIE_PL_NONFATAL_MOS_TSx_DR = 35, // %s[%d] Malformed TS1/TS2 Ordered Set - Data Rate Identifier is not D2.0 (%s). | |
| 75 | PCIE_PL_NONFATAL_MOS_TSx_TC = 36, // %s[%d] Multiple TS1/TS2 Training Control bits (HotReset,DisableLink,Loopback) are set (%s). | |
| 76 | PCIE_PL_NONFATAL_MOS_TSx_LKNUM = 37, // %s[%d] Malformed TS1/TS2 Ordered Set - Link Number must be one of {PAD,D0.0...D31.7} (%s). | |
| 77 | PCIE_PL_NONFATAL_MOS_TSx_LNNUM = 38, // %s[%d] Malformed TS1/TS2 Ordered Set - Lane Number must be one of {PAD,D0.0...D31.0} (%s). | |
| 78 | PCIE_PL_NONFATAL_MOS_TSx_LNNUM0 = 39, // %s[%d] Malformed TS1/TS2 Ordered Set - Lane Number exceeded physically available lanes (%s). | |
| 79 | PCIE_PL_NONFATAL_MOS_TSx_NFTS = 40, // %s[%d] Malformed TS1/TS2 Ordered Set - N_FTS must be one of {D0.0...D31.7} (%s). | |
| 80 | PCIE_PL_NONFATAL_MOS_TSx_ID = 41, // %s[%d] Malformed TS1/TS2 Ordered Set - unknown identifier (neither D10.2 nor D5.2) (%s). | |
| 81 | PCIE_PL_NONFATAL_MOS_TSx_INV = 42, // %s[%d] Malformed TS1/TS2 Ordered Set - Inverted TS identifier on a lane which was not inverted during Polling.Active (%s). | |
| 82 | PCIE_PL_NONFATAL_MOS_TSx_SCRAM = 43, // %s[%d] Malformed TS1/TS2 Ordered Set - Data characters are scrambled (%s). | |
| 83 | PCIE_PL_NONFATAL_MOS_TSx_KC = 44, // Malformed TS1/TS2 Ordered Set - illegal special symbol is found | |
| 84 | PCIE_PL_NONFATAL_MCOMP = 45, // Malformed Compliance Pattern - must be COM D10.2 COM D21.5. | |
| 85 | PCIE_PL_NONFATAL_MCOMP_NTE = 46, // Detected unterminated Compliance Pattern - missing D21.5 at the end. | |
| 86 | PCIE_PL_NONFATAL_MCOMP_NT = 47, // Detected unterminated Compliance Pattern - only have 2 symbols. | |
| 87 | PCIE_PL_NONFATAL_SYNC_LN_COM = 48, // COM is not simultaneous on all lanes of a multi-Lane Link. | |
| 88 | PCIE_PL_NONFATAL_SYNC_LN_OS = 49, // %s Ordered Sets are not consistent across all lanes (%s). | |
| 89 | PCIE_PL_NONFATAL_SYNC_LN_OSN = 50, // %s Ordered Set symbol count is not consistent across all lanes (%s). | |
| 90 | PCIE_PL_NONFATAL_LIDLE_SCRAM = 51, // D0.0 characters are scrambled, but scrambling is disabled. | |
| 91 | PCIE_PL_NONFATAL_LIDLE_NSCRAM = 52, // D0.0 characters are not scrambled, but scrambling is not disabled. | |
| 92 | PCIE_PL_NONFATAL_FRAME_BAD_STP = 53, // STP symbol is not in Lane #0 following Logical Idle. | |
| 93 | PCIE_PL_NONFATAL_FRAME_BAD_STP1 = 54, // STP symbol is not in lane #(4*N) | |
| 94 | PCIE_PL_NONFATAL_FRAME_BAD_STP2 = 55, // STP symbol does not immediately follow END/EDB. | |
| 95 | PCIE_PL_NONFATAL_FRAME_BAD_STPs = 56, // Multiple STP symbols within one symbol time. | |
| 96 | PCIE_PL_NONFATAL_FRAME_BAD_SDP = 57, // SDP symbol is not in Lane #0 following Logical Idle. | |
| 97 | PCIE_PL_NONFATAL_FRAME_BAD_SDP1 = 58, // SDP symbol is not in lane #(4*N) | |
| 98 | PCIE_PL_NONFATAL_FRAME_BAD_SDP2 = 59, // SDP symbol does not immediately follow END/EDB. | |
| 99 | PCIE_PL_NONFATAL_FRAME_BAD_SDPs = 60, // Multiple SDP symbols within one symbol time. | |
| 100 | PCIE_PL_NONFATAL_FRAME_BAD_END = 61, // END symbol has no preceding STP or SDP symbol. | |
| 101 | PCIE_PL_NONFATAL_FRAME_BAD_END1 = 62, // END symbol is not in lane #(4*N-1) | |
| 102 | PCIE_PL_NONFATAL_FRAME_BAD_EDB = 63, // EDB symbol has no preceding STP symbol. | |
| 103 | PCIE_PL_NONFATAL_FRAME_BAD_EDB1 = 64, // EDB symbol is not in lane #(4*N-1) | |
| 104 | PCIE_PL_NONFATAL_FRAME_TLP_KC = 65, // Unexpected special symbol in the midst of a TLP. | |
| 105 | PCIE_PL_NONFATAL_FRAME_TLP_STP = 66, // Unexpected STP symbol in the midst of a TLP. | |
| 106 | PCIE_PL_NONFATAL_FRAME_TLP_SDP = 67, // Unexpected SDP symbol in the midst of a TLP. | |
| 107 | PCIE_PL_NONFATAL_FRAME_DLLP_KC = 68, // Unexpected special symbol in the midst of a DLLP. | |
| 108 | PCIE_PL_NONFATAL_FRAME_DLLP_STP = 69, // Unexpected STP symbol in the midst of a DLLP. | |
| 109 | PCIE_PL_NONFATAL_FRAME_DLLP_SDP = 70, // Unexpected SDP symbol in the midst of a DLLP. | |
| 110 | PCIE_PL_NONFATAL_FRAME_DLLP_EDB = 71, // DLLP ended with EDB. | |
| 111 | PCIE_PL_NONFATAL_FRAME_PAD = 72, // Leftover lanes are not filled with PAD symbols. | |
| 112 | PCIE_PL_NONFATAL_FRAME_LIDLE = 73, // All lanes were not D0.0 in the Logical Idle state. | |
| 113 | PCIE_PL_NONFATAL_FRAME_BAD_KC = 74, // Special symbol (other than STP/SDP) in Lane #0 following Logical Idle. | |
| 114 | PCIE_PL_NONFATAL_FRAME_BAD_DATA = 75, // Data symbol in Lane #0 following Logical Idle. | |
| 115 | PCIE_PL_NONFATAL_FRAME_BAD_DATA1 = 76, // Control symbols between Ordered Sets in a training state. | |
| 116 | PCIE_PL_NONFATAL_FRAME_BAD_DATA2 = 77, // Data symbols between Ordered Sets in a training state. | |
| 117 | PCIE_PL_NONFATAL_LTSSM_DQ_TO_ACTIVE = 78, // Failed transition from Detect.Quiet to Detect.Active when any lane breaks Electrical Idle. | |
| 118 | PCIE_PL_NONFATAL_LTSSM_DQ_TO_ACTIVE2 = 79, // Failed transition from Detect.Quiet to Detect.Active when Timeout expires. | |
| 119 | PCIE_PL_NONFATAL_LTSSM_DQ_EXIT = 80, // Premature exit from Detect.Quiet. | |
| 120 | PCIE_PL_NONFATAL_LTSSM_DA_VALUE = 81, // Did not transmit non-zero common-mode value while in Detect.Active. | |
| 121 | PCIE_PL_NONFATAL_LTSSM_DA_REPEAT = 82, // When not all lanes detected receivers in Detect.Active, Transmitter did not repeat detect sequence after timeout. | |
| 122 | PCIE_PL_NONFATAL_LTSSM_DA_TO_POLL = 83, // Failed transition from Detect.Active to Polling.Active when all lanes have detected receivers. | |
| 123 | PCIE_PL_NONFATAL_LTSSM_DA_TO_POLL2 = 84, // Failed transition from Detect.Active to Polling.Active when lanes detecting receivers in 2nd sequence match those detected in 1st sequence. | |
| 124 | PCIE_PL_NONFATAL_LTSSM_DA_TO_QUIET = 85, // Failed transition from Detect.Active to Detect.Quiet when no lane detected a receiver. | |
| 125 | PCIE_PL_NONFATAL_LTSSM_DA_TO_QUIET2 = 86, // Failed transition from Detect.Active to Detect.Quiet when lanes detecting receivers in 2nd sequence do not match those detected in 1st sequence. | |
| 126 | PCIE_PL_NONFATAL_LTSSM_DA_EXIT = 87, // Premature exit from Detect.Active. | |
| 127 | PCIE_PL_NONFATAL_LTSSM_PA_TX = 88, // Transmitted data other than TS1 or SKIP ordered sets in Polling.Active. | |
| 128 | PCIE_PL_NONFATAL_LTSSM_PA_RX = 89, // Received data other than TS1, TS2, or SKIP ordered sets in Polling.Active. | |
| 129 | PCIE_PL_NONFATAL_LTSSM_PA_TX_LinkNum = 90, // Transmitted TS1 with Link!=PAD in Polling.Active. | |
| 130 | PCIE_PL_NONFATAL_LTSSM_PA_TX_LaneNum = 91, // Transmitted TS1 with Lane!=PAD in Polling.Active. | |
| 131 | PCIE_PL_NONFATAL_LTSSM_PA_TO_CFG = 92, // Failed transition from Polling.Active to Polling.Config | |
| 132 | PCIE_PL_NONFATAL_LTSSM_PA_TO_COMPL = 93, // Failed transition from Polling.Active to Polling.Compliance after timeout. | |
| 133 | PCIE_PL_NONFATAL_LTSSM_PA_EXIT_TX = 94, // Premature exit from Polling.Active -- all lanes have not transmitted enough TS1s with Link=Lane=PAD. | |
| 134 | PCIE_PL_NONFATAL_LTSSM_PA_EXIT_RX = 95, // Premature exit from Polling.Active -- all lanes have not received enough TS1s/TS2s with Link=Lane=PAD. | |
| 135 | PCIE_PL_NONFATAL_LTSSM_CI_TX = 96, // Transmitted data other than Logical Idle in Configuration.Idle. | |
| 136 | PCIE_PL_NONFATAL_LTSSM_CI_EXIT_TX = 97, // Premature exit from Configuration.Idle -- all lanes have not transmitted required Logical Idle characters. | |
| 137 | PCIE_PL_NONFATAL_LTSSM_CI_EXIT_RX = 98, // Premature exit from Configuration.Idle -- all lanes have not received required Logical Idle characters. | |
| 138 | PCIE_PL_NONFATAL_LTSSM_AD_POLLC = 99, // Illegally staying in Polling.Compliance -- all lanes have detected Electrical Idle Broken. | |
| 139 | PCIE_PL_NONFATAL_LTSSM_TXOS1_POLLC = 100, // In Polling.Compliance, illegally transmitted Ordered Set on a lane that was not detected as a Receiver in Detect. | |
| 140 | PCIE_PL_NONFATAL_LTSSM_TXOS_POLLC = 101, // Illegally transmitted Ordered Set other than Compliance and SKIP in Polling.Compliance. | |
| 141 | PCIE_PL_NONFATAL_LTSSM_EXIT_POLLCFG = 102, // Illegally staying in Polling.Configuration -- already met the condition to Polling.Configuration. | |
| 142 | PCIE_PL_NONFATAL_LTSSM_INITRX_POLLCFG = 103, // Illegally received Ordered Set while entering Polling.Configuration. | |
| 143 | PCIE_PL_NONFATAL_LTSSM_INITTX_POLLCFG = 104, // Illegally transmitted Ordered Set while entering Polling.Configuration. | |
| 144 | PCIE_PL_NONFATAL_LTSSM_TXOS1_POLLCFG = 105, // In Polling.Configuration, illegally transmitted Ordered Set on a lane that was not detected as a Receiver in Detect. | |
| 145 | PCIE_PL_NONFATAL_LTSSM_TXOS_POLLCFG = 106, // Illegally transmitted Ordered Set other than TS2 and SKIP in Polling.Configuration. | |
| 146 | PCIE_PL_NONFATAL_LTSSM_EXIT0_POLLCFG = 107, // Illegally leaving Polling.Configuration -- condition not met and timeout has not expired yet. | |
| 147 | PCIE_PL_NONFATAL_LTSSM_EX_POLLSPD = 108, // Illegally leaving in Polling.Speed -- Timeout has not expired already. | |
| 148 | PCIE_PL_NONFATAL_LTSSM_HOT_TS2 = 109, // Transmitted TS2 in HotReset state. | |
| 149 | PCIE_PL_NONFATAL_LTSSM_HOT_HotReset = 110, // TS1 Training Control HotReset bit is not asserted in HotReset state. | |
| 150 | PCIE_PL_NONFATAL_LTSSM_NHOT_HotReset = 111, // TS1/TS2 Training Control HotReset bit is asserted when not in HotReset state. | |
| 151 | PCIE_PL_NONFATAL_LTSSM_DIS_TS2 = 112, // Transmitted TS2 in Disabled state. | |
| 152 | PCIE_PL_NONFATAL_LTSSM_DIS_Disable = 113, // TS1 Training Control DisableLink bit is not asserted in Disabled state. | |
| 153 | PCIE_PL_NONFATAL_LTSSM_NDIS_Disable = 114, // TS1/TS2 Training Control DisableLink bit is asserted when not in Disabled state. | |
| 154 | PCIE_PL_NONFATAL_LTSSM_LOOP_TS2 = 115, // Transmitted TS2 in Loopback.Entry state. | |
| 155 | PCIE_PL_NONFATAL_LTSSM_LOOP_Loopback = 116, // TS1 Training Control Loopback bit is not asserted in Loopback.Entry state. | |
| 156 | PCIE_PL_NONFATAL_LTSSM_NLOOP_Loopback = 117, // TS1/TS2 Training Control Loopback bit is asserted when not in Loopback.Entry state. | |
| 157 | PCIE_PL_NONFATAL_LTSSM_POLL_linkUp = 118, // 'LinkUp' is not Deasserted while in Polling. | |
| 158 | PCIE_PL_NONFATAL_LTSSM_DET_linkUp = 119, // 'LinkUp' is not Deasserted while in Detect. | |
| 159 | PCIE_PL_NONFATAL_LTSSM_LOOP_linkUp = 120, // 'LinkUp' is not Deasserted while in Loopback. | |
| 160 | PCIE_PL_NONFATAL_LTSSM_DIS_linkUp = 121, // 'LinkUp' is not Deasserted while in Disabled. | |
| 161 | PCIE_PL_NONFATAL_LTSSM_HOT_linkUp = 122, // 'LinkUp' is not Deasserted while in HotReset. | |
| 162 | PCIE_PL_NONFATAL_LTSSM_CFG0_linkUp = 123, // 'LinkUp' is not Deasserted when entering Configuration.LinkWidth.Start from Detect.Active. | |
| 163 | PCIE_PL_NONFATAL_LTSSM_CFG1_linkUp = 124, // 'LinkUp' is not Asserted when entering Configuration.LinkWidth.Start from Recovery. | |
| 164 | PCIE_PL_NONFATAL_LTSSM_RCV_linkUp = 125, // 'LinkUp' is not Asserted while in Recovery. | |
| 165 | PCIE_PL_NONFATAL_LTSSM_L0_linkUp = 126, // 'LinkUp' is not Asserted while in L0. | |
| 166 | PCIE_PL_NONFATAL_LTSSM_L0s_linkUp = 127, // 'LinkUp' is not Asserted while in L0s. | |
| 167 | PCIE_PL_NONFATAL_LTSSM_L1_linkUp = 128, // 'LinkUp' is not Asserted while in L1. | |
| 168 | PCIE_PL_NONFATAL_LTSSM_L2_linkUp = 129, // 'LinkUp' is not Asserted while in L2. | |
| 169 | PCIE_PL_NONFATAL_LTSSM_DET_inTraining = 130, // 'inTraining' is not Deasserted while in Detect. | |
| 170 | PCIE_PL_NONFATAL_LTSSM_POLL_inTraining = 131, // 'inTraining' is not Deasserted while in Polling. | |
| 171 | PCIE_PL_NONFATAL_LTSSM_CFG_inTraining = 132, // 'inTraining' is not Asserted when entering Configuration. | |
| 172 | PCIE_PL_NONFATAL_LTSSM_RCV_inTraining = 133, // 'inTraining' is not Asserted while in Recovery. | |
| 173 | PCIE_PL_NONFATAL_LTSSM_LOOP_inTraining = 134, // 'inTraining' is not Deasserted while in Loopback. | |
| 174 | PCIE_PL_NONFATAL_LTSSM_DIS_inTraining = 135, // 'inTraining' is not Deasserted while in Disabled. | |
| 175 | PCIE_PL_NONFATAL_LTSSM_HOT_inTraining = 136, // 'inTraining' is not Deasserted while in HotReset. | |
| 176 | PCIE_PL_NONFATAL_LTSSM_L0_inTraining = 137, // 'inTraining' is not Deasserted while in L0. | |
| 177 | PCIE_PL_NONFATAL_LTSSM_L0s_inTraining = 138, // 'inTraining' is not Deasserted while in L0s. | |
| 178 | PCIE_PL_NONFATAL_LTSSM_L1_inTraining = 139, // 'inTraining' is not Deasserted while in L1. | |
| 179 | PCIE_PL_NONFATAL_LTSSM_L2_inTraining = 140, // 'inTraining' is not Deasserted while in L2. | |
| 180 | PCIE_DL_NONFATAL_DL_INACTIVE_TX_DLLP = 141, // DLL.2.1#14 : A DLLP was transmitted in DL_Inactive state. | |
| 181 | PCIE_DL_NONFATAL_VC0_FC1_SEQ_BAD = 142, // DLL.3.1#3 : FC_INIT1 dllp sequence interrupted for VC%d - Expected : %s; Actual : %s. | |
| 182 | PCIE_DL_NONFATAL_VC07_FC_INIT1_TYPE_BAD = 143, // DLL.3.1#3 : Incorrect dllp type sent in FC1_Init for VC%d - Expected : %s; Actual : %s. | |
| 183 | PCIE_DL_NONFATAL_VC0_FC_INIT1_VC_BAD = 144, // DLL.3.1#3 : Incorrect VC for DLLP sent in FC1_Init - Expected : %d; Actual : %d. | |
| 184 | PCIE_DL_NONFATAL_VC0_FC_INIT1_TX_TLP = 145, // DLL.3.1#3 : A TLP was sent in FC1_Init for VC0. | |
| 185 | PCIE_DL_NONFATAL_VC17_FC1_SEQ_BAD = 146, // DLL.3.1#4 : FC_INIT1 dllp sequence interrupted for VC%d - Expected : %s; Actual : %s. | |
| 186 | PCIE_DL_NONFATAL_VC17_FC1_TIMER_EXP = 147, // DLL.3.1#4 : FC_INIT1 timer expired for VC%d | |
| 187 | PCIE_DL_NONFATAL_VC0_FC2_SEQ_BAD = 148, // DLL.3.1#6 : FC_INIT2 dllp sequence interrupted for VC%d - Expected : %s; Actual : %s. | |
| 188 | PCIE_DL_NONFATAL_VC0_FC_INIT2_TX_TLP = 149, // DLL.3.1#6 : A TLP was sent in FC2_Init for VC0. | |
| 189 | PCIE_DL_NONFATAL_VC07_FC_INIT2_TYPE_BAD = 150, // DLL.3.1#6 : Incorrect dllp type sent in FC2_Init for VC%d - Expected : %s; Actual : %s. | |
| 190 | PCIE_DL_NONFATAL_VC0_FC_INIT2_VC_BAD = 151, // DLL.3.1#6 : Incorrect VC for DLLP sent in FC2_Init - Expected : %d; Actual : %d. | |
| 191 | PCIE_DL_NONFATAL_VC17_FC2_SEQ_BAD = 152, // DLL.3.1#7 : FC_INIT2 dllp sequence interrupted for VC%d - Expected : %s; Actual : %s. | |
| 192 | PCIE_DL_NONFATAL_VC17_FC2_TIMER_EXP = 153, // DLL.3.1#7 : FC_INIT2 timer expired for VC%d | |
| 193 | PCIE_DL_NONFATAL_DLLP_RSRVD_BAD = 154, // DLL.4.1#1 : Non-zero reserved bits found in dllp. | |
| 194 | PCIE_DL_COR_DLLP_CRC_BAD = 155, // DLL.4.1#3 : CRC check failed for %s DLLP. Expect:0x%x, Actual:0x%x. | |
| 195 | PCIE_DL_NONFATAL_INIT_FC_NOT_IN_INIT = 156, // DLL.4.1#4 : The device transmitted an FC_INIT DLLP while not in Init state. | |
| 196 | PCIE_DL_NONFATAL_ACK_NAK_RSRVD_BAD = 157, // DLL.4.1#7 : Non-zero reserved bits found in ack/nak dllp. | |
| 197 | PCIE_DL_NONFATAL_FC1_INIT_RSRVD_BAD = 158, // DLL.4.1#11 : Non-zero reserved bits found in FC1_Init dllp. | |
| 198 | PCIE_DL_NONFATAL_FC2_INIT_RSRVD_BAD = 159, // DLL.4.1#18 : Non-zero reserved bits found in FC2_Init dllp. | |
| 199 | PCIE_DL_NONFATAL_UPDATE_FC_RSRVD_BAD = 160, // DLL.4.1#25 : Non-zero reserved bits found in ack/nak dllp. | |
| 200 | PCIE_DL_NONFATAL_PWR_MGMT_RSRVD_BAD = 161, // DLL.4.1#25 : Non-zero reserved bits found in pwr mgmt dllp. | |
| 201 | PCIE_DL_NONFATAL_REPLAY_TIMER_EXP_BAD_TLP = 162, // DLL.5.2#1 : Incorrect seq num (%d) TLP sent - the replay timer has expired. | |
| 202 | PCIE_DL_NONFATAL_REPLAY_TIMER_EXP_BAD_PKT = 163, // DLL.5.2#1 : Incorrect packet sent - the replay timer has expired. | |
| 203 | PCIE_DL_COR_REPLAY_ROLLOVER = 164, // DLL.5.2#2 : Unexpected seq num (%d) TLP sent - replay rollover occurred - link needed retraining. | |
| 204 | PCIE_DL_NONFATAL_TLP_BAD_INIT_SEQ_NUM = 165, // DLL.5.2#3 : The first TLP transmitted after coming out of DL_Inactive must have a sequence number of zero (Actual : %d). | |
| 205 | PCIE_DL_NONFATAL_REPLAY_NOT_COMPLETED = 166, // DLL.5.2#8 : Incorrect seq num (%d) TLP sent - the replay has not completed. | |
| 206 | PCIE_DL_NONFATAL_REPLAY_INTERRUPTED = 167, // DLL.5.2#8 : Incorrect packet type sent - the replay has not completed. | |
| 207 | PCIE_DL_NONFATAL_REPLAY_TLP_ORDER_BAD = 168, // DLL.5.2#10 : Incorrect seq num (%d) Replay TLP sent. | |
| 208 | PCIE_DL_NONFATAL_REPLAY_BEFORE_EXP = 169, // DLL.5.2#13 : The replay started without the timer having expired. | |
| 209 | PCIE_DL_NONFATAL_DL_INACTIVE_TX_TLP = 170, // DLL.2.1#13 : A TLP was transmitted in DL_Inactive state. | |
| 210 | PCIE_DL_NONFATAL_ACK_SEQ_BAD = 171, // DLL.5.2#16 : Incorrect seq num in Ack Dllp : Expected '%d'; Sent '%d'. | |
| 211 | PCIE_DL_COR_NULL_TLP_CRC_BAD = 172, // DLL.5.3#1 : CRC check failed for %s NULL TLP. Expect:0x%x, Actual:0x%x. | |
| 212 | PCIE_DL_COR_TLP_CRC_BAD = 173, // DLL.5.3#2 : CRC check failed for %s TLP. Expect:0x%x, Actual:0x%x. | |
| 213 | PCIE_DL_NONFATAL_UNSCH_NAK = 174, // DLL.5.3#4 : Unexpected Nak DLLP (seq:%d) sent - was not scheduled. | |
| 214 | PCIE_DL_NONFATAL_ACK_NAK_TIMER_EXP = 175, // DLL.5.3#4 : The ackNak latency timer has expired. | |
| 215 | PCIE_DL_NONFATAL_UNEXP_PKT = 176, // Unexpected packet %s - Expected : %s; Actual : %s. | |
| 216 | PCIE_DL_NONFATAL_UNKNOWN_DLLP_TYPE = 177, // Unknown dllp type %s. | |
| 217 | PCIE_DL_NONFATAL_DLLP_SIZE_BAD = 178, // Incorrect size in a DLLP (%d bytes) - must be 6 bytes. | |
| 218 | PCIE_DL_NONFATAL_NAK_LATE = 179, // The device should have transmitted a NAK by now. | |
| 219 | PCIE_DL_NONFATAL_ACK_LATE = 180, // The device should have transmitted an ACK by now. | |
| 220 | PCIE_DL_NONFATAL_NAK_SEQ_BAD = 181, // Incorrect seq num in Nak Dllp : Expected '%d'; Sent '%d'. | |
| 221 | PCIE_DL_NONFATAL_FC_INIT_SEQ_BAD = 182, // Unexpected FC INIT DLLP %s - %s. | |
| 222 | PCIE_DL_NONFATAL_TLP_SEQ_BAD = 183, // Unexpected seq num TLP sent - Expected : %d; Transmitted : %d. | |
| 223 | PCIE_DL_NONFATAL_TLP_SIZE_BAD = 184, // The %s %sTLP size was less than 6 bytes (actual : %d bytes). | |
| 224 | PCIE_DL_NONFATAL_TLP_SEQ_NUM_RSRVD_BAD = 185, // The reserved bits preceding the seq num for a TLP must be initialized to zero. | |
| 225 | PCIE_DL_NONFATAL_RETRY_BUFFER_FULL = 186, // The device transmitted a TLP even though there was not enough space for it in the retry buffer; needed : %d bytes, available : %d bytes. | |
| 226 | PCIE_DL_NONFATAL_REPLAY_LATE = 187, // The replay started late. | |
| 227 | PCIE_DL_NONFATAL_RETRY_PKT_LEN_MISMATCH = 188, // Len mismatch for retry packet with seq num '%d' : Expected '%d'; Sent '%d'. | |
| 228 | PCIE_DL_NONFATAL_RETRY_PKT_DATA_MISMATCH = 189, // Data mismatch for retry packet with seq num '%d'. | |
| 229 | PCIE_DL_COR_OUT_OF_SEQ_TLP = 190, // Out of sequence TLP received.%s | |
| 230 | PCIE_DL_COR_REPLAY_TIMEOUT = 191, // Replay Timeout | |
| 231 | PCIE_DL_COR_REPLAY_NUM_ROLLOVER = 192, // Replay Num Rollover | |
| 232 | PCIE_DL_FATAL_PROTOCOL_ERROR = 193, // Data Link Layer Protocol Error: received '%s' dllp with seqNum = %d (last ack seq : %d) | |
| 233 | PCIE_TL_FATAL_CFG_UNKPT = 194, // Port function:%s, unknown portType (%u) in PCI Express Capabilities Register (offset 02h). | |
| 234 | PCIE_TL_FATAL_CFG_MAXBUS = 195, // At port_%u, BUS enumeration exceeded the maximum %u, stopping at '%s'. | |
| 235 | PCIE_TL_FATAL_CFG_HDRTYPE = 196, // Port function:%s is Type_%u, differs from the expected Type_%u. | |
| 236 | PCIE_TL_FATAL_CFG_HDRMF = 197, // Port function:%s is%s part of multi-function device, but it should%s be. | |
| 237 | PCIE_TL_COR_CFG_PORTARB = 198, // %s: Illegally defines Port Arbitration table at offset 0x%x. But the Port Arbitration Capability is Round-Robin in '%s'. | |
| 238 | PCIE_TL_COR_CFG_PORTARB1 = 199, // %s: Missing the required Port Arbitration table. But the Port Arbitration Capability is not Round-Robin in '%s'. | |
| 239 | PCIE_TL_COR_CFG_PORTARB2 = 200, // %s: Port Arbitration Capability incorrectly contains non-0 (0x%x) in reserved bits [7:6] in '%s'. | |
| 240 | PCIE_TL_COR_CFG_PORTARB3 = 201, // %s: Device/Type value (%u) in '%s' is not a Switch. But a Port Arbitration Table is specified for VC resource %d. | |
| 241 | PCIE_TL_COR_CFG_VCARB = 202, // %s: Illegally defines VC Arbitration table in '%s'. But the Low Priority Extended VC Count is 0 in '%s'. | |
| 242 | PCIE_TL_COR_CFG_VCARB1 = 203, // %s: Missing the required VC Arbitration table in '%s'. But the Low Priority Extended VC Count (%d) is greater than 0 in '%s', and the arbitration is enabled. | |
| 243 | PCIE_TL_COR_CFG_VCARB2 = 204, // %s Illegally defines VC Arbitration table at offset 0x%x in '%s'. But the arbitration is not enabled in '%s'. | |
| 244 | PCIE_TL_COR_CFG_VCARB3 = 205, // %s: VC Arbitration Capability incorrectly contains non-0 (0x%x) in reserved bit[7:4] in '%s'. | |
| 245 | PCIE_TL_COR_CFG_CHGTYPE = 206, // Not permitted : changing configuration header type Type0 %s Type1. | |
| 246 | PCIE_TL_COR_CFG_CHGTYPE0 = 207, // Detecting TYPE %u at port function (%s). | |
| 247 | PCIE_TL_COR_CFG_BADTYPE = 208, // Defining %s configuration space, contradicting what the device needs (%s). | |
| 248 | PCIE_TL_COR_CFG_CAPID0 = 209, // New capability type [%d] is invalid. | |
| 249 | PCIE_TL_COR_CFG_CAPOVRLAP = 210, // At port function '%s', new capability '%s' overlaps the Register address [0x%02x] with a capability '%s' that is defined earlier. | |
| 250 | PCIE_TL_COR_CFG_CAPOVRLAP0 = 211, // At downstream port function '%s', new capability '%s' overlaps the Register address [0x%02x] with a capability '%s' defined earlier. | |
| 251 | PCIE_TL_COR_CFG_CAPREDEF = 212, // %s: Redefining capability '%s' is not permitted. | |
| 252 | PCIE_TL_COR_CFG_CAPREDEF0 = 213, // At downstream %s: Redefining capability '%s' is not permitted. | |
| 253 | PCIE_TL_COR_CFG_MIXTYPE = 214, // Port %s%s%s%u has mixed function types (function%u:Type%u, function%u:Type_%u) at the downstream side of the link. | |
| 254 | PCIE_TL_COR_CFG_MIXDIRP = 215, // Port %s%s%s%u has mixed port types (function%u:%sstream, function%u:%sstream) at the downstream side of the link. | |
| 255 | PCIE_TL_COR_CFG_EN_IORd = 216, // TLP IORd cannot be processed because IO Enable bit in Command register is not set. | |
| 256 | PCIE_TL_COR_CFG_EN_IOWr = 217, // TLP IOWr cannot be processed because IO Enable bit in Command register is not set. | |
| 257 | PCIE_TL_COR_CFG_EN_MRd = 218, // TLP MRd cannot be processed because Memory Enable bit in Command register is not set. | |
| 258 | PCIE_TL_COR_CFG_EN_MRdLk = 219, // TLP MRdLk cannot be processed because Memory Enable bit in Command register is not set. | |
| 259 | PCIE_TL_COR_CFG_EN_MWr = 220, // TLP MWr cannot be processed because Memory Enable bit in Command register is not set. | |
| 260 | PCIE_TL_COR_CFG_INTX_PV1 = 221, // CFG.5.5#1 : Interrupt Pin value must be 1 for single function device with INTx enabled. | |
| 261 | PCIE_TL_COR_CFG_INTX_NPV = 222, // CFG.5.5#1 : Interrupt Pin value is 0 though INTx is not disabled in Command register. | |
| 262 | PCIE_TL_COR_CFG_INTX_NPV0 = 223, // CFG.5.5#1 : At downstream %s: Interrupt Pin value is 0 though INTx is not disabled in Command register. | |
| 263 | PCIE_TL_NONFATAL_CFG_INTX_PV = 224, // CFG.5.5#1 : Interrupt Pin value (%u) must be 0 because INTx is disabled in Command register. | |
| 264 | PCIE_TL_NONFATAL_CFG_INTX_PV0 = 225, // CFG.5.5#1 : At downstream %s: Interrupt Pin value (%u) must be 0 because INTx is disabled in Command register. | |
| 265 | PCIE_TL_NONFATAL_CFG_vlINTBCD = 226, // Transmitting TLP (%s) is not permitted because this is a single function device. | |
| 266 | PCIE_TL_NONFATAL_CFG_vlINTBCD0 = 227, // Received TLP (%s), this is not permitted because the downstream is a single function device. | |
| 267 | PCIE_TL_NONFATAL_CFG_INTXPIN_RSV = 228, // Interrupt Pin value (%u) is reserved and is not within [0:4]. | |
| 268 | PCIE_TL_NONFATAL_CFG_INTXPIN_RSV0 = 229, // At downstream %s: Interrupt Pin value (%u) is reserved and is not within [0:4]. | |
| 269 | PCIE_TL_NONFATAL_CFG_vlINTxPIN = 230, // CFG.5.5#2 CFG.5.5#3 : Transmitting TLP (%s), contradicting to Interrupt Pin value (%u). | |
| 270 | PCIE_TL_NONFATAL_CFG_vlINTxPIN0 = 231, // CFG.5.5#2 CFG.5.5#3 : Receiving TLP (%s), contradicting to Interrupt Pin value (%u) at a downstream device. | |
| 271 | PCIE_TL_FATAL_CFG_TC_DEL0TC = 232, // CFG.11.7#12 : Cannot remove TC0 from mapping to VC0, which is reserved mapping, corrected before writing to Register. | |
| 272 | PCIE_TL_FATAL_CFG_TC_DELTC = 233, // Cannot remove TC%d from %s for VC%d, because VC%d is Enabled and there are some pending transactions with this TC. | |
| 273 | PCIE_TL_FATAL_CFG_TC_DELTC0 = 234, // Cannot remove TC%d from %s for VC%d at the downstream Link, because VC%d is Enabled and there are some pending transactions with this TC. | |
| 274 | PCIE_TL_FATAL_CFG_TC_NVCID = 235, // Cannot modify VC ID from %d to %d in %s, because VC%d is Enabled. | |
| 275 | PCIE_TL_FATAL_CFG_TC_NVCID0 = 236, // Cannot modify VC ID from %d to %d in %s at the downstream Link, because VC%d is Enabled. | |
| 276 | PCIE_TL_FATAL_CFG_TC_0MAP0 = 237, // Traffic Class 0 (TC0) must be mapped to VC0 - detected TC0 mapped to VC%d | |
| 277 | PCIE_TL_FATAL_CFG_TC_0NMAP0 = 238, // Traffic Class 0 (TC0) must be mapped to VC0 - detected TC0 not mapped to VC0 | |
| 278 | PCIE_TL_FATAL_CFG_TC_1MAPN = 239, // A Traffic Class (TC%d) must not be mapped to multiple VCs (%d, %d ...) | |
| 279 | PCIE_TL_FATAL_CFG_TC_1MAP = 240, // A Traffic Class (TC%d) is mapped to an uninitialized VC | |
| 280 | PCIE_TL_COR_CFG_VCDONE0_1 = 241, // VC %u was disabled already, will not clear the Negotiation Pending. | |
| 281 | PCIE_TL_FATAL_CFG_VCARB1_1 = 242, // Selected VC arbitration method, %s, which is not supported at this port. | |
| 282 | PCIE_TL_FATAL_CFG_VCARB2_1 = 243, // Selected VC arbitration method, %s, but the corresponding table is empty. | |
| 283 | PCIE_TL_FATAL_CFG_VCARB3_2 = 244, // Selected VC arbitration method, %s, but the table length (%u) is not correct. | |
| 284 | PCIE_TL_FATAL_CFG_VCARB4_3 = 245, // Selected VC arbitration method, %s, but the table entry(%u) specifies unsupported VC(%d). | |
| 285 | PCIE_TL_FATAL_CFG_VCARB0 = 246, // VC Arbitration Capability is not specified. | |
| 286 | PCIE_TL_FATAL_CFG_VCM_3 = 247, // VC%u is specified in more than one Resource Control registers (%u, %u). | |
| 287 | PCIE_TL_FATAL_CFG_VC0EN = 248, // VC0 must be Enabled in its Resource Control register. | |
| 288 | PCIE_TL_FATAL_CFG_VC0EN0 = 249, // Cannot disable VC0 in its Resource Control register, corrected before writing to Register. | |
| 289 | PCIE_TL_FATAL_CFG_VCDIS0 = 250, // Cannot disable VC%d because there are some pending transactions using this VC, corrected before writing to its Resource Register. | |
| 290 | PCIE_TL_FATAL_CFG_VCID0 = 251, // VC0 may only be associated with the first Resource Control register, detected resId[%d]<->VC%d | |
| 291 | PCIE_TL_FATAL_CFG_VCN_1 = 252, // VC%d cannot be associated with the first Resource Control register | |
| 292 | PCIE_TL_FATAL_CFG_LPVC_2 = 253, // Low Power Extended VC Count (%d) must not be greater than Extended VC Count (%d). | |
| 293 | PCIE_TL_FATAL_CFG_TC_F0 = 254, // TC/VC mapping must be associated with Function 0 of a PCI Express Port | |
| 294 | PCIE_TL_FATAL_CFG_MT_2 = 255, // Reserved value %u for Memory Address Type in Base Register %d. | |
| 295 | PCIE_TL_FATAL_CFG_MTNI_2 = 256, // Both Base Registers %u [64-bit memory mapped] and %u [not implemented] need to be implemented. | |
| 296 | PCIE_TL_FATAL_CFG_MTM64_2 = 257, // Consecutive Base Registers %u and %u can not both be Memory mapped and 64-bit. | |
| 297 | PCIE_TL_COR_CFG_FNBAD_2 = 258, // Specified invalid function number %d as part of the requester ID, corrected to use %d. | |
| 298 | PCIE_TL_FATAL_CFG_UQID_4 = 259, // Requester ID (busNum=%d devNum=%d funcNum=%d) is defined for two port functions [%s, %s]. | |
| 299 | PCIE_TL_FATAL_CFG_UNKQID_4 = 260, // Requester ID at port %d (busNum=%d devNum=%d funcNum=%d) is not defined in the entire system. | |
| 300 | PCIE_TL_NONFATAL_CFG_SFN = 261, // %s: belongs to a single function port, illegally specified non-0 function for this Port (busNum=%d devNum=%d funcNum=%d) . | |
| 301 | PCIE_TL_FATAL_CFG_RUQID_4 = 262, // Failed to assign the Requester ID to port function (%s) (busNum=%d devNum=%d funcNum=%d) - not unique in the entire system. | |
| 302 | PCIE_TL_FATAL_CFG_UQMEM_4 = 263, // BAR_%u at Port function (%s) has the global base address (0x%08llx) which is not unique in the entire system. | |
| 303 | PCIE_TL_FATAL_CFG_UQBN_3 = 264, // At port %d, the bus numbers (%d, %d) must be the same for both ends of the same link. | |
| 304 | PCIE_TL_FATAL_CFG_UQDN_3 = 265, // At port %d, the device numbers cannot be the same (%d) for both ends of the same link. | |
| 305 | PCIE_TL_FATAL_CFG_EQFN0_2 = 266, // At port %d, detected duplicate port function (%u) at downstream device. | |
| 306 | PCIE_TL_FATAL_CFG_NEDN0_5 = 267, // At port %d, downstream port functions (%s, %s) have different device numbers (%u, %u). | |
| 307 | PCIE_TL_FATAL_CFG_DNF0_2 = 268, // Downstream port %d has multi functions (found function %u), which is not allowed. | |
| 308 | PCIE_TL_FATAL_CFG_LKWDN_2 = 269, // Value (0x%x) for register, %s, specified none of the legal link widths (1, 2, 4, 8, 12, 16, 32). | |
| 309 | PCIE_TL_FATAL_CFG_LKWDS_2 = 270, // Value (0x%x) for register, %s, specified some illegal link width(s). Legal ones are (1, 2, 4, 8, 12, 16, 32). | |
| 310 | PCIE_TL_FATAL_CFG_LKWD0_2 = 271, // Value (0x%x) for register, %s, does not specify 1, which is the required legal link width among (1, 2, 4, 8, 12, 16, 32). | |
| 311 | PCIE_TL_FATAL_CFG_TXQPLS_2 = 272, // Payload buffer size (%d bytes) for Transmit Queue must be at least %d (bytes). | |
| 312 | PCIE_TL_FATAL_CFG_TXQS_2 = 273, // Transaction queue size (%d) for Transmit Queue must be at least %d. | |
| 313 | PCIE_TL_FATAL_CFG_MODI_3 = 274, // Model Interface Id (%d) for register, %s, is undefined. It must be smaller than %d. | |
| 314 | PCIE_TL_FATAL_CFG_MODC0_2 = 275, // Value (0x%x) for register , %s, must specify one of the Model Layers(1000b-TL 0100b-DL 0010b-PL). | |
| 315 | PCIE_TL_FATAL_CFG_MODCD_2 = 276, // Value (0x%x) for register , %s, must specify DL(0100b) if both TL(1000b) and PL(0010) are specified. | |
| 316 | PCIE_TL_FATAL_CFG_DEVRESET = 277, // Device failed its initialization. Reset system/software to initial state. | |
| 317 | PCIE_TL_FATAL_CFG_DID_TXCPLQ = 278, // There are some pending requests in TX Completion Queue [port_%d] while the Device ID changes to [bus:%d device:%d function:%d]. | |
| 318 | PCIE_TL_FATAL_CFG_DID_RXCPLQ = 279, // There are some pending requests in RX Completion Queue [port_%d] while the Device ID changes to [bus:%d device:%d function:%d]. | |
| 319 | PCIE_TL_FATAL_CFG_DID_TXQ = 280, // There are some pending transactions in Transmit Queue while the Device ID changes to [bus:%d device:%d function:%d]. | |
| 320 | PCIE_TL_FATAL_CFG_DID_USERQ = 281, // There are some pending transactions in User Queue while the Device ID changes to [bus:%d device:%d function:%d]. | |
| 321 | PCIE_TL_FATAL_CFG_MID_TXCPLQ = 282, // There are some pending memory transactions in TX Completion Queue [port_%d] that reference the memory defined by '%s', which is changing its base address from [0x%llx] to [0x%llx]. | |
| 322 | PCIE_TL_FATAL_CFG_MID_TXCPLQ0 = 283, // There are some pending memory transactions in TX Completion Queue [port_%d] that reference the memory defined by '%s' at the downstream Link, which is changing its base address from [0x%llx] to [0x%llx]. | |
| 323 | PCIE_TL_FATAL_CFG_MID_RXCPLQ = 284, // There are some pending memory transactions in RX Completion Queue [port_%d] that reference the memory defined by '%s', which is changing its base address from [0x%llx] to [0x%llx]. | |
| 324 | PCIE_TL_FATAL_CFG_MID_RXCPLQ0 = 285, // There are some pending memory transactions in RX Completion Queue [port_%d] that reference the memory defined by '%s' at the downstream Link, which is changing its base address from [0x%llx] to [0x%llx]. | |
| 325 | PCIE_TL_FATAL_CFG_MID_TXQ = 286, // There are some pending memory transactions in Transmit Queue [port_%d] that reference the memory defined by '%s', which is changing its base address from [0x%llx] to [0x%llx]. | |
| 326 | PCIE_TL_FATAL_CFG_MID_TXQ0 = 287, // There are some pending memory transactions in Transmit Queue [port_%d] that reference the memory defined by '%s' at the downstream Link, which is changing its base address from [0x%llx] to [0x%llx]. | |
| 327 | PCIE_TL_FATAL_CFG_MID_USERQ = 288, // There are some pending transactions in User Queue [port_%d] that might reference the memory defined by '%s', which is changing its base address from [0x%llx] to [0x%llx]. | |
| 328 | PCIE_TL_FATAL_CFG_MID_USERQ0 = 289, // There are some pending transactions in User Queue [port_%d] that might reference the memory defined by '%s' at the downstream Link, which is changing its base address from [0x%llx] to [0x%llx]. | |
| 329 | PCIE_TL_FATAL_CFG_VC_UP = 290, // VC%d from VC Resource %d must be Enabled before any TC is mapped to it. | |
| 330 | PCIE_TL_COR_CFG_VC_0TC = 291, // Disable VC%d because no TC is mapped to it. | |
| 331 | PCIE_TL_FATAL_CFG_VC_TC = 292, // TC/VC mapping must be identical for both sides of a PCI Express Link | |
| 332 | PCIE_TL_COR_VC_DISUS_1 = 293, // Attempt to disable VC %u, which is not supported at this port. | |
| 333 | PCIE_TL_COR_VC_DISLD_1 = 294, // Attempt to disable VC %u, which still has traffic running. | |
| 334 | PCIE_TL_FATAL_FCPE_INI_PH = 295, // InitFC value (%d) is less than the minimum PH FC credit requirement (%d). | |
| 335 | PCIE_TL_FATAL_FCPE_INI_PD = 296, // InitFC value (%d) is less than the minimum PD FC credit requirement (%d). | |
| 336 | PCIE_TL_FATAL_FCPE_INI_NPH = 297, // InitFC value (%d) is less than the minimum NPH FC credit requirement (%d). | |
| 337 | PCIE_TL_FATAL_FCPE_INI_NPD = 298, // InitFC value (%d) is less than the minimum NPD FC credit requirement (%d). | |
| 338 | PCIE_TL_FATAL_FCPE_INI_CPLH = 299, // InitFC value (%d) is less than the minimum CPLH FC credit requirement (%d) . | |
| 339 | PCIE_TL_FATAL_FCPE_INI_CPLD = 300, // InitFC value (%d) is less than the minimum CPLD FC credit requirement (%d) . | |
| 340 | PCIE_TL_NONFATAL_FCPE_INI_NE_1 = 301, // New InitFC value '%d' of [%s %s] differs from earlier value 'Unlimited'. | |
| 341 | PCIE_TL_NONFATAL_FCPE_INI_NE0_1 = 302, // New InitFC value 'Unlimited' of [%s %s] differs from earlier value '%d'. | |
| 342 | PCIE_TL_NONFATAL_FCPE_INI_NE_2 = 303, // New InitFC value '%d' of [%s %s] differs from earlier value '%d'. | |
| 343 | PCIE_TL_NONFATAL_FCPE_INI_NEXP_1 = 304, // New InitFC value '%d' of [%s %s] differs from expected value 'Unlimited' in configuration. | |
| 344 | PCIE_TL_NONFATAL_FCPE_INI_NEXP0_1 = 305, // New InitFC value 'Unlimited' of [%s %s] differs from expected value '%d' in configuration. | |
| 345 | PCIE_TL_NONFATAL_FCPE_INI_NEXP_2 = 306, // New InitFC value '%d' of [%s %s] differs from expected value '%d' in configuration. | |
| 346 | PCIE_TL_FATAL_FCPE_N0 = 307, // UpdateFC DLLP cannot contain non-zero credits to a VC with an Infinite limit. | |
| 347 | PCIE_TL_NONFATAL_FCPE_RXOVFL = 308, // Received a TLP that exceeded the Allocated Credits. | |
| 348 | PCIE_TL_NONFATAL_FCPE_TXOVFL = 309, // Monitor Mode: Detected a transmitted TLP that exceeded the Transmit Credit Limits. | |
| 349 | PCIE_TL_NONFATAL_FCPE_VC = 310, // Cannot update the FC Credit to Unenabled VC%d. | |
| 350 | PCIE_TL_COR_TLP_OVF_HDR = 311, // Value 0x%x (%u) of the header field '%s' exceeded the maximum 0x%x (%u), truncated to 0x%x (%u). | |
| 351 | PCIE_TL_NONFATAL_TLP_TR_OVFL = 312, // Transmit Queue overflowed (max:%d). | |
| 352 | PCIE_TL_NONFATAL_TLP_PL_OVFL = 313, // Transmit Queue payload size overflowed (max:%d current:%d). | |
| 353 | PCIE_TL_COR_SCH_TC_UNK_3 = 314, // Scheduled TC (%d) is out of supported range [0 : %d], convert to %d. | |
| 354 | PCIE_TL_NONFATAL_TLP_MF_CplCRS = 315, // Malformed TLP - %s with Configuration Request Retry Status corresponds to TLP (%s) that is not a Configuration Request. | |
| 355 | PCIE_TL_NONFATAL_TLP_MF_vlFmtType = 316, // Malformed TLP - illegal Fmt (%d) and Type(%d) combination. | |
| 356 | PCIE_TL_NONFATAL_TLP_MF_vlSizeDWalign = 317, // Malformed TLP - Packet size (%d bytes) is not in increments of four-Byte Double Words. | |
| 357 | PCIE_TL_NONFATAL_TLP_MF_vlEmpty = 318, // Malformed TLP - Empty packet. | |
| 358 | PCIE_TL_NONFATAL_TLP_MF_vlEmptyVal = 319, // Malformed TLP - Specified (%s*) type, %d bits, but no data is provided. | |
| 359 | PCIE_TL_NONFATAL_TLP_MF_vlUnkVal = 320, // Malformed TLP - Specified %d bits data of unknown type (%d). | |
| 360 | PCIE_TL_NONFATAL_TLP_MF_vlMinSize = 321, // Malformed TLP - Packet has %d bits, less than the required minimum %d bits. | |
| 361 | PCIE_TL_NONFATAL_TLP_MF_vlSizeTotal = 322, // Malformed TLP - Actual Packet size (%d bytes) differs from the calculated (%d bytes) based on [Fmt:%d Type:%d TD:%d length:%d]. | |
| 362 | PCIE_TL_NONFATAL_TLP_MF_vlLenMPL = 323, // Malformed TLP - Payload Length (%d DWords) is greater than Max_Payload_Size (%d DWords) in Device Control Register. | |
| 363 | PCIE_TL_NONFATAL_TLP_MF_vlLenMRR = 324, // Malformed TLP - Request size (%d DWords) is greater than Max_Read_Request_Size (%d DWords) in Device Control Register%s. | |
| 364 | PCIE_TL_NONFATAL_TLP_MF_vlLen4KB = 325, // Malformed TLP - Address/Length combinations [(0x%llx mod 4K) + %d = 0x%llx] cross 4K memory boundary. | |
| 365 | PCIE_TL_NONFATAL_TLP_MF_vlLenRsv = 326, // Malformed TLP - Non-0 Length field (%d), which is Reserved and should be 0 based on its [Fmt:%d Type:%d]. | |
| 366 | PCIE_TL_NONFATAL_TLP_MF_vlLenRsv0 = 327, // Malformed TLP [%s] - Non-0 Length field (%d), which is Reserved and should be 0. | |
| 367 | PCIE_TL_NONFATAL_TLP_MF_vlAddr4GB = 328, // Malformed TLP - can not use 64-bit format if address is below 4GB [start:0x%llx end:0x%llx]. | |
| 368 | PCIE_TL_NONFATAL_TLP_MF_vl1stBE = 329, // Malformed TLP - First DW BE is 0, but the payload length (%d DWords) is greater than 1. | |
| 369 | PCIE_TL_NONFATAL_TLP_MF_vlLastBE0 = 330, // Malformed TLP - Last DW BE (0x%x) is not 0, but the payload length is 1 DW. | |
| 370 | PCIE_TL_NONFATAL_TLP_MF_vlLastBE1 = 331, // Malformed TLP - Last DW BE is 0, but the payload length (%d DWords) is greater than 1. | |
| 371 | PCIE_TL_NONFATAL_TLP_MF_vlNC1stBE = 332, // Malformed TLP - Non-contiguous First DW BE (0x%x) is not permitted if the payload length (%d DWords) is greater than 2. | |
| 372 | PCIE_TL_NONFATAL_TLP_MF_vlNClastBE = 333, // Malformed TLP - Non-contiguous Last DW BE (0x%x) is not permitted if the payload length (%d DWords) is greater than 2. | |
| 373 | PCIE_TL_NONFATAL_TLP_MF_vlTag0 = 334, // Malformed TLP - Tag[7:5] (0x%x) is not 0 when transmitting non-posted TLP & Extended Tag is not enabled. | |
| 374 | PCIE_TL_NONFATAL_TLP_MF_vlCfgBus = 335, // Malformed TLP - target.busNumber (%d) of the Configuration request differs from what the device stores (%d). | |
| 375 | PCIE_TL_NONFATAL_TLP_MF_vlCfgDev = 336, // Malformed TLP - target.deviceNumber (%d) of the Configuration request differs from what the device stores (%d). | |
| 376 | PCIE_TL_NONFATAL_TLP_MF_vlCfgFun = 337, // Malformed TLP - target.functionNumber (%d) of the Configuration request differs from what the device stores (%d). | |
| 377 | PCIE_TL_NONFATAL_TLP_MF_vlRidBus = 338, // Malformed TLP - RequesterID.busNumber (%d) differs from what the device stores (%d). | |
| 378 | PCIE_TL_NONFATAL_TLP_MF_vlRidDev = 339, // Malformed TLP - RequesterID.deviceNumber (%d) differs from what the device stores (%d). | |
| 379 | PCIE_TL_NONFATAL_TLP_MF_vlRidFunc = 340, // Malformed TLP - RequesterID.functionNumber (%d) differs from what the device stores (%d). | |
| 380 | PCIE_TL_NONFATAL_FN_OFB = 341, // Discarding TLP - Function number %u is out of range [0:%u]. | |
| 381 | PCIE_TL_NONFATAL_TLP_MF_vlPoison = 342, // Malformed TLP - Poisoned bit is 1, but it is not CplD, MWr, CfgWr0, CfgWr1, or MsgD (non-vendor). | |
| 382 | PCIE_TL_NONFATAL_TLP_UR_Poison = 343, // Discarding a posted-TLP (%s), that contains poisoned data (EP==1). | |
| 383 | PCIE_TL_NONFATAL_TLP_MF_vlIOpkgLEN = 344, // Malformed TLP - IO request can only have Length==1, but it has (%d). | |
| 384 | PCIE_TL_NONFATAL_TLP_MF_vlIOpkg = 345, // Malformed TLP - IO request can only use TC0, but it has TC%d. | |
| 385 | PCIE_TL_NONFATAL_TLP_MF_vlCFGpkgLEN = 346, // Malformed TLP - Configuration request can only have Length==1, but it has (%d). | |
| 386 | PCIE_TL_NONFATAL_TLP_MF_vlCFGpkg = 347, // Malformed TLP - Configuration request can only use TC0, but it has TC%d. | |
| 387 | PCIE_TL_NONFATAL_TLP_MF_vlIOExpEp = 348, // Malformed TLP - PCIE Express Endpoint cannot generate IO request. | |
| 388 | PCIE_TL_NONFATAL_TLP_MF_vlCfgRx = 349, // Malformed TLP - A downstream port cannot handle Configuration requests from downstream components. | |
| 389 | PCIE_TL_NONFATAL_TLP_MF_vlCfgTx = 350, // Malformed TLP - An Upstream port cannot transmit Configuration requests to upstream components. | |
| 390 | PCIE_TL_NONFATAL_TLP_MF_vlMsgRout = 351, // Malformed TLP - Out of range Message Routing code (%d), it must be within [0 : 5]. | |
| 391 | PCIE_TL_NONFATAL_TLP_MF_vlINTxUP = 352, // TXN.2.13#5 TXN.2.13#6 : Malformed TLP - INTx message is not issued by an upstream port. | |
| 392 | PCIE_TL_NONFATAL_TLP_MF_vlINTxTC = 353, // TXN.2.13#7 TXN.2.13#8 : Malformed TLP - INTx is not carrying TC0 in the header, it has TC%d. | |
| 393 | PCIE_TL_NONFATAL_TLP_MF_vlMsgPMErsvF = 354, // Malformed TLP - PM_Active_State_Nak msg has non-0 (%d) as function # in Requester ID. | |
| 394 | PCIE_TL_NONFATAL_TLP_MF_vlMsgLOCKrsvF = 355, // Malformed TLP - Unlock msg has non-0 (%d) as function # in Requester ID. | |
| 395 | PCIE_TL_NONFATAL_TLP_MF_vlINTxRID = 356, // Malformed TLP - INTx has non-0 (%d) as function # in Requester ID. | |
| 396 | PCIE_TL_NONFATAL_TLP_MF_vlINTxCmd = 357, // TXN.2.13#13 : Malformed TLP - Cannot transmit INTx because InterruptDisable bit is set in Command Register. | |
| 397 | PCIE_TL_NONFATAL_TLP_MF_vlINTxMSI = 358, // Malformed TLP - Cannot transmit INTx because Capability 'Message Signaled Interrupts' is enabled. | |
| 398 | PCIE_TL_NONFATAL_TLP_MF_vlMSILen = 359, // Malformed TLP - MSI's payload length, Expect:1 Actual:%u. | |
| 399 | PCIE_TL_NONFATAL_TLP_MF_vlMSIFBE = 360, // Malformed TLP - MSI's first BE, Expect:0x3 Actual:0x%x (only byte1 byte0). | |
| 400 | PCIE_TL_NONFATAL_TLP_MF_vlMSIATTR = 361, // Malformed TLP - MSI's ATTR[1:0], Expect:1 Actual:%u (strong ordering and no-snoop). | |
| 401 | PCIE_TL_NONFATAL_TLP_MF_vlMSI16D = 362, // Malformed TLP - MSI's payload data (%s) has non-0 value in bits[31:16]. | |
| 402 | PCIE_TL_NONFATAL_TLP_MF_vlMSID = 363, // Malformed TLP - MSI's payload data (%s) does not match what is stored in register 'MSI Message Data' (%s) in bits[31:%u]. | |
| 403 | PCIE_TL_NONFATAL_TLP_MF_vlPMTC = 364, // TXN.2.14#4 TXN.2.14#5 : Malformed TLP - Power Management Message TLP is not carrying TC0 in the header, it has TC%d. | |
| 404 | PCIE_TL_NONFATAL_TLP_MF_vlERRTC = 365, // Malformed TLP - Error Signaling Message TLP is not carrying TC0 in the header, it has TC%d. | |
| 405 | PCIE_TL_NONFATAL_TLP_MF_vlLOCKTC = 366, // Malformed TLP - Locked Transactions Support TLP is not carrying TC0 in the header, it has TC%d. | |
| 406 | PCIE_TL_NONFATAL_TLP_MF_vlSLOTTC = 367, // Malformed TLP - Slot Power Limit TLP is not carrying TC0 in the header, it has TC%d. | |
| 407 | PCIE_TL_NONFATAL_TLP_MF_vlSLOTlen = 368, // Malformed TLP - Payload length (%d) must be 1 in Slot Power Limit TLP. | |
| 408 | PCIE_TL_NONFATAL_TLP_MF_vlMsgPkg = 369, // Malformed Message TLP - Illegal combination of TLP type (%s), Rout(0x%x), and msgCode (0x%x). | |
| 409 | PCIE_TL_NONFATAL_TLP_MF_vlAttrMRsv = 370, // Malformed TLP - Attribute field (%d) is not 0, but packet is non-Vendor defined Message request. | |
| 410 | PCIE_TL_NONFATAL_TLP_MF_vlAttrCRsv = 371, // Malformed TLP [%s] - Attribute field (%d) is reserved for Configuration request, it must be 0. | |
| 411 | PCIE_TL_NONFATAL_TLP_MF_vlVDid = 372, // Malformed TLP - CompleterId:0x%04x is not 0 (Byte 8-9), but the Vendor_defined Message is not using By-ID routing, it is using %s. | |
| 412 | PCIE_TL_NONFATAL_TLP_MF_vlAttrIORsv = 373, // Malformed TLP [%s] - Attribute field (%d) is reserved for IO request, it must be 0. | |
| 413 | PCIE_TL_NONFATAL_TLP_MF_vlRsvH0 = 374, // Malformed TLP - Non-0 Reserved bit(s) in TLP header, Byte0 - Byte3 . | |
| 414 | PCIE_TL_NONFATAL_TLP_MF_vlRsvHcfg = 375, // Malformed TLP - Non-0 Reserved bit(s) in Configuration TLP header, Byte10 - Byte11. | |
| 415 | PCIE_TL_NONFATAL_TLP_MF_vlRsvMAddr = 376, // Malformed TLP - Non-0 Reserved bits(s), Address[1:0], in Memory Request TLP. | |
| 416 | PCIE_TL_NONFATAL_TLP_MF_vlRsvIOAddr = 377, // Malformed TLP - Non-0 Reserved bits(s), Address[1:0], in IO Request TLP. | |
| 417 | PCIE_TL_NONFATAL_TLP_MF_vlInitReq = 378, // Malformed TLP - Cannot initiate non-posted requests prior to receiving first CfgWr0. | |
| 418 | PCIE_TL_NONFATAL_TLP_MF_vlCplId0_Cpl = 379, // Malformed TLP - Cpl prior to receiving first CfgWr0 must have 0's as device ID, but detected [bus:%d device:%d function:%d]. | |
| 419 | PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplD = 380, // Malformed TLP - CplD prior to receiving first CfgWr0 must have 0's as device ID, but detected [bus:%d device:%d function:%d]. | |
| 420 | PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplLk = 381, // Malformed TLP - CplLk prior to receiving first CfgWr0 must have 0's as device ID, but detected [bus:%d device:%d function:%d]. | |
| 421 | PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplDLk = 382, // Malformed TLP - CplDLk prior to receiving first CfgWr0 must have 0's as device ID, but detected [bus:%d device:%d function:%d]. | |
| 422 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MRd32 = 383, // Malformed TLP - Cannot accept request MRd32 prior to initializing the device, e.g. first CfgWr0. | |
| 423 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MRd64 = 384, // Malformed TLP - Cannot accept request MRd64 prior to initializing the device, e.g. first CfgWr0. | |
| 424 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MRdLk32 = 385, // Malformed TLP - Cannot accept request MRdLk32 prior to initializing the device, e.g. first CfgWr0. | |
| 425 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MRdLk64 = 386, // Malformed TLP - Cannot accept request MRdLk64 prior to initializing the device, e.g. first CfgWr0. | |
| 426 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MWr32 = 387, // Malformed TLP - Cannot accept request MWr32 prior to initializing the device, e.g. first CfgWr0. | |
| 427 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MWr64 = 388, // Malformed TLP - Cannot accept request MWr64 prior to initializing the device, e.g. first CfgWr0. | |
| 428 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_IOWr = 389, // Malformed TLP - Cannot accept request IOWr prior to initializing the device, e.g. first CfgWr0. | |
| 429 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_IORd = 390, // Malformed TLP - Cannot accept request IORd prior to initializing the device, e.g. first CfgWr0. | |
| 430 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_Cpl = 391, // Malformed TLP - Cannot accept request Cpl prior to initializing the device, e.g. first CfgWr0. | |
| 431 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_CplD = 392, // Malformed TLP - Cannot accept request CplD prior to initializing the device, e.g. first CfgWr0. | |
| 432 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_CplLk = 393, // Malformed TLP - Cannot accept request CplLk prior to initializing the device, e.g. first CfgWr0. | |
| 433 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_CplDLk = 394, // Malformed TLP - Cannot accept request CplDLk prior to initializing the device, e.g. first CfgWr0. | |
| 434 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_Msg = 395, // Malformed TLP - Cannot accept request Msg prior to initializing the device, e.g. first CfgWr0. | |
| 435 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_MsgD = 396, // Malformed TLP - Cannot accept request MsgD prior to initializing the device, e.g. first CfgWr0. | |
| 436 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_CfgRd0 = 397, // Malformed TLP - Cannot accept request CfgRd0 prior to initializing the device, e.g. first CfgWr0. | |
| 437 | PCIE_TL_NONFATAL_TLP_MF_vlInitMio_CfgRd1 = 398, // Malformed TLP - Cannot accept request CfgRd1 prior to initializing the device, e.g. first CfgWr0. | |
| 438 | PCIE_TL_NONFATAL_TLP_MF_vlCplBCM0 = 399, // Malformed Completion TLP - BCM must not be set by PCI Express completer. | |
| 439 | PCIE_TL_NONFATAL_TLP_MF_vlCplSt = 400, // Malformed Completion TLP - Reserved completion status (%u). | |
| 440 | PCIE_TL_NONFATAL_TLP_MF_vlLkMrd = 401, // Illegal Locked Read Request TLP - RC can not be a Completer of the Lock Semantics. | |
| 441 | PCIE_TL_NONFATAL_TLP_MF_vlLkExpEp = 402, // PCI Express Endpoint does not support Lock Semantics. | |
| 442 | PCIE_TL_NONFATAL_TLP_MF_vlLkCpl = 403, // Illegal Locked Completion TLP - RC can not be a Completer of the Lock Semantics. | |
| 443 | PCIE_TL_NONFATAL_TLP_MF_vlLkReq = 404, // Illegal Locked Request TLP - Only RC can initiate. | |
| 444 | PCIE_TL_NONFATAL_TLP_MF_vlLkEP = 405, // Illegal Locked TLP - PCI Express Endpoint does not support Locked accesses. | |
| 445 | PCIE_TL_NONFATAL_TLP_MF_vlLkTC0 = 406, // Illegal Locked TLP - only default traffic class (TC0) is allowed. | |
| 446 | PCIE_TL_NONFATAL_TLP_MF_vlMsgINTxtx = 407, // This device (%s) cannot be Transmitter of INTx msg TLP - only Endpoint, Switch, or Bridge can. | |
| 447 | PCIE_TL_NONFATAL_TLP_MF_vlMsgINTxrx = 408, // This device (%s) cannot be Receiver of INTx msg TLP - only Root Complex or Switch can. | |
| 448 | PCIE_TL_NONFATAL_TLP_MF_vlMsgNaktx = 409, // This device (%s) cannot be Transmitter of PM_Active_State_Nak msg TLP - only Root Complex or Switch can. | |
| 449 | PCIE_TL_NONFATAL_TLP_MF_vlMsgNakrx = 410, // This device (%s) cannot be Receiver of PM_Active_State_Nak msg TLP - only Endpoint, Switch, or Bridge can. | |
| 450 | PCIE_TL_NONFATAL_TLP_MF_vlMsgPMEtx = 411, // This device (%s) cannot be Transmitter of PM_PME msg TLP - only Endpoint, Switch, or Bridge can. | |
| 451 | PCIE_TL_NONFATAL_TLP_MF_vlMsgPMErx = 412, // This device (%s) cannot be Receiver of PM_PME msg TLP - only Root Complex or Switch can. | |
| 452 | PCIE_TL_NONFATAL_TLP_MF_vlMsgOfftx = 413, // This device (%s) cannot be Transmitter of PM_Turn_Off msg TLP - only Root Complex can. | |
| 453 | PCIE_TL_NONFATAL_TLP_MF_vlMsgOffrx = 414, // This device (%s) cannot be Receiver of PM_Turn_Off msg TLP - only Endpoint or Bridge can. | |
| 454 | PCIE_TL_NONFATAL_TLP_MF_vlMsgAcktx = 415, // This device (%s) cannot be Transmitter of PM_TO_Ack msg TLP - only Endpoint or Bridge can. | |
| 455 | PCIE_TL_NONFATAL_TLP_MF_vlMsgAckrx = 416, // This device (%s) cannot be Receiver of PM_TO_Ack msg TLP - only Root Complex can. | |
| 456 | PCIE_TL_NONFATAL_TLP_MF_vlMsgERRtx = 417, // This device (%s) cannot be Transmitter of Error Signaling msg TLP - only Endpoint or Bridge can. | |
| 457 | PCIE_TL_NONFATAL_TLP_MF_vlMsgERRrx = 418, // This device (%s) cannot be Receiver of Error Signaling msg TLP - only Root Complex can. | |
| 458 | PCIE_TL_NONFATAL_TLP_MF_vlMsgLOCKtx = 419, // This device (%s) cannot be Transmitter of Unlock msg TLP - only Root Complex can. | |
| 459 | PCIE_TL_NONFATAL_TLP_MF_vlMsgLOCKrx = 420, // TPL.3.1#2 : This device (%s) cannot be Receiver of Unlock msg TLP - only Endpoint or Bridge can. | |
| 460 | PCIE_TL_NONFATAL_TLP_MF_vlMsgSLOTtx = 421, // This device (%s) cannot be Transmitter of Slot Power Limit msg TLP - only Root Complex or Bridge can. | |
| 461 | PCIE_TL_NONFATAL_TLP_MF_vlMsgSLOTrx = 422, // This device (%s) cannot be Receiver of Slot Power Limit msg TLP - only Endpoint, Switch, or Bridge can. | |
| 462 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOfftx = 423, // This device (%s) cannot be Transmitter of Attention_Indicator_Off msg TLP - only Root Complex or Bridge can. | |
| 463 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOffrx = 424, // This device (%s) cannot be Receiver of Attention_Indicator_Off msg TLP - only Endpoint, Switch, or Bridge can. | |
| 464 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOntx = 425, // This device (%s) cannot be Transmitter of Attention_Indicator_On msg TLP - only Root Complex or Bridge can. | |
| 465 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOnrx = 426, // This device (%s) cannot be Receiver of Attention_Indicator_On msg TLP - only Endpoint, Switch, or Bridge can. | |
| 466 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPABlktx = 427, // This device (%s) cannot be Transmitter of Attention_Indicator_Blink msg TLP - only Root Complex or Bridge can. | |
| 467 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPABlkrx = 428, // This device (%s) cannot be Receiver of Attention_Indicator_Blink msg TLP - only Endpoint, Switch, or Bridge can. | |
| 468 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOfftx = 429, // This device (%s) cannot be Transmitter of Power_Indicator_Off msg TLP - only Root Complex or Bridge can. | |
| 469 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOffrx = 430, // This device (%s) cannot be Receiver of Power_Indicator_Off msg TLP - only Endpoint, Switch, or Bridge can. | |
| 470 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOntx = 431, // This device (%s) cannot be Transmitter of Power_Indicator_On msg TLP - only Root Complex or Bridge can. | |
| 471 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOnrx = 432, // This device (%s) cannot be Receiver of Power_Indicator_On msg TLP - only Endpoint, Switch, or Bridge can. | |
| 472 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPBlktx = 433, // This device (%s) cannot be Transmitter of Power_Indicator_Blink msg TLP - only Root Complex or Bridge can. | |
| 473 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPBlkrx = 434, // This device (%s) cannot be Receiver of Power_Indicator_Blink msg TLP - only Endpoint, Switch, or Bridge can. | |
| 474 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAttntx = 435, // This device (%s) cannot be Transmitter of Attention_Button_Pressed msg TLP - only Endpoint, Switch, or Bridge can. | |
| 475 | PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAttnrx = 436, // This device (%s) cannot be Receiver of Attention_Button_Pressed msg TLP - only Root Complex or Bridge can. | |
| 476 | PCIE_TL_FATAL_TL_INIT1 = 437, // Failed transmitting an initialization packet - invalid data, rejected. Will retry. | |
| 477 | PCIE_TL_NONFATAL_TLP_MF_RPFWD = 438, // Root Port (%u) cannot re-direct the received non-posted TLP (%s) through the same link to a downstream port function (%s) with address [0x%llx]. | |
| 478 | PCIE_TL_NONFATAL_TLP_CPLUDNSW = 439, // Downstream Switch port (bus:%u dev:%u func:%u) does not have the originating Request of the Completion TLP %s [transId=0x03%x]. | |
| 479 | PCIE_TL_NONFATAL_TLP_SWUPOBF = 440, // TLP %s is forwarded to upstream Switch port, but the function %u is out of range defined by [0, %u]. | |
| 480 | PCIE_TL_NONFATAL_TLP_SWUPUI = 441, // TLP %s is forwarded to upstream Switch port, but the function %u has not been initialized. | |
| 481 | PCIE_TL_NONFATAL_TLP_SWPEER = 442, // TLP %s is routed to peer downstream Switch port, but no port-function is located based on [bus:%u dev:%u func:%u]. | |
| 482 | PCIE_TL_NONFATAL_TLP_CPLQ0_1 = 443, // Cannot find matching Request for the Completion TLP [transId=0x%x]. | |
| 483 | PCIE_TL_COR_TLP_CPLQ0_2 = 444, // Completion Queue in TL is over the limit (%u), current size is %u. | |
| 484 | PCIE_TL_NONFATAL_TLP_CPLBC_IORd_1 = 445, // The Byte Count (%d) of the Completion for request IORd must be 4. | |
| 485 | PCIE_TL_NONFATAL_TLP_CPLBC_IOWr_1 = 446, // The Byte Count (%d) of the Completion for request IOWr must be 4. | |
| 486 | PCIE_TL_NONFATAL_TLP_CPLBC_CfgRd0_1 = 447, // The Byte Count (%d) of the Completion for request CfgRd0 must be 4. | |
| 487 | PCIE_TL_NONFATAL_TLP_CPLBC_CfgRd1_1 = 448, // The Byte Count (%d) of the Completion for request CfgRd1 must be 4. | |
| 488 | PCIE_TL_NONFATAL_TLP_CPLBC_CfgWr0_1 = 449, // The Byte Count (%d) of the Completion for request CfgWr0 must be 4. | |
| 489 | PCIE_TL_NONFATAL_TLP_CPLBC_CfgWr1_1 = 450, // The Byte Count (%d) of the Completion for request CfgWr1 must be 4. | |
| 490 | PCIE_TL_NONFATAL_TLP_CPLLA_IORd_1 = 451, // The Lower Address (%d) of the Completion for request IORd must be 0. | |
| 491 | PCIE_TL_NONFATAL_TLP_CPLLA_IOWr_1 = 452, // The Lower Address (%d) of the Completion for request IOWr must be 0. | |
| 492 | PCIE_TL_NONFATAL_TLP_CPLLA_CfgRd0_1 = 453, // The Lower Address (%d) of the Completion for request CfgRd0 must be 0. | |
| 493 | PCIE_TL_NONFATAL_TLP_CPLLA_CfgRd1_1 = 454, // The Lower Address (%d) of the Completion for request CfgRd1 must be 0. | |
| 494 | PCIE_TL_NONFATAL_TLP_CPLLA_CfgWr0_1 = 455, // The Lower Address (%d) of the Completion for request CfgWr0 must be 0. | |
| 495 | PCIE_TL_NONFATAL_TLP_CPLLA_CfgWr1_1 = 456, // The Lower Address (%d) of the Completion for request CfgWr1 must be 0. | |
| 496 | PCIE_TL_NONFATAL_TLP_CPLUID_MRd32_1 = 457, // The TransactionId:0x%06x for request 32-bit MRd already existed for an early request in the Completion Queue. | |
| 497 | PCIE_TL_NONFATAL_TLP_CPLUID_MRd64_1 = 458, // The TransactionId:0x%06x for request 64-bit MRd already existed for an early request in the Completion Queue. | |
| 498 | PCIE_TL_NONFATAL_TLP_CPLUID_MRdLk32_1 = 459, // The TransactionId:0x%06x for request 32-bit MRdLk already existed for an early request in the Completion Queue. | |
| 499 | PCIE_TL_NONFATAL_TLP_CPLUID_MRdLk64_1 = 460, // The TransactionId:0x%06x for request 64-bit MRdLk already existed for an early request in the Completion Queue. | |
| 500 | PCIE_TL_NONFATAL_TLP_CPLUID_IORd_1 = 461, // The TransactionId:0x%06x for request IORd already existed for an early request in the Completion Queue. | |
| 501 | PCIE_TL_NONFATAL_TLP_CPLUID_IOWr_1 = 462, // The TransactionId:0x%06x for request IOWr already existed for an early request in the Completion Queue. | |
| 502 | PCIE_TL_NONFATAL_TLP_CPLUID_CfgRd0_1 = 463, // The TransactionId:0x%06x for request CfgRd0 already existed for an early request in the Completion Queue. | |
| 503 | PCIE_TL_NONFATAL_TLP_CPLUID_CfgRd1_1 = 464, // The TransactionId:0x%06x for request CfgRd1 already existed for an early request in the Completion Queue. | |
| 504 | PCIE_TL_NONFATAL_TLP_CPLUID_CfgWr0_1 = 465, // The TransactionId:0x%06x for request CfgWr0 already existed for an early request in the Completion Queue. | |
| 505 | PCIE_TL_NONFATAL_TLP_CPLUID_CfgWr1_1 = 466, // The TransactionId:0x%06x for request CfgWr1 already existed for an early request in the Completion Queue. | |
| 506 | PCIE_TL_NONFATAL_TLP_CPLATTR_MRd32_2 = 467, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request 32-bit MRd. | |
| 507 | PCIE_TL_NONFATAL_TLP_CPLATTR_MRd64_2 = 468, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request 64-bit MRd. | |
| 508 | PCIE_TL_NONFATAL_TLP_CPLATTR_MRdLk32_2 = 469, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request 32-bit MRdLk. | |
| 509 | PCIE_TL_NONFATAL_TLP_CPLATTR_MRdLk64_2 = 470, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request 64-bit MRdLk. | |
| 510 | PCIE_TL_NONFATAL_TLP_CPLATTR_IORd_2 = 471, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request IORd. | |
| 511 | PCIE_TL_NONFATAL_TLP_CPLATTR_IOWr_2 = 472, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request IOWr. | |
| 512 | PCIE_TL_NONFATAL_TLP_CPLATTR_CfgRd0_2 = 473, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request CfgRd0. | |
| 513 | PCIE_TL_NONFATAL_TLP_CPLATTR_CfgRd1_2 = 474, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request CfgRd1. | |
| 514 | PCIE_TL_NONFATAL_TLP_CPLATTR_CfgWr0_2 = 475, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request CfgWr0. | |
| 515 | PCIE_TL_NONFATAL_TLP_CPLATTR_CfgWr1_2 = 476, // Mismatch in Attr (cpl:%d req:%d) in the Completion for the request CfgWr1. | |
| 516 | PCIE_TL_NONFATAL_TLP_CPLTC_MRd32_2 = 477, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request 32-bit MRd. | |
| 517 | PCIE_TL_NONFATAL_TLP_CPLTC_MRd64_2 = 478, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request 64-bit MRd. | |
| 518 | PCIE_TL_NONFATAL_TLP_CPLTC_MRdLk32_2 = 479, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request 32-bit MRdLk. | |
| 519 | PCIE_TL_NONFATAL_TLP_CPLTC_MRdLk64_2 = 480, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request 64-bit MRdLk. | |
| 520 | PCIE_TL_NONFATAL_TLP_CPLTC_IORd_2 = 481, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request IORd. | |
| 521 | PCIE_TL_NONFATAL_TLP_CPLTC_IOWr_2 = 482, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request IOWr. | |
| 522 | PCIE_TL_NONFATAL_TLP_CPLTC_CfgRd0_2 = 483, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request CfgRd0. | |
| 523 | PCIE_TL_NONFATAL_TLP_CPLTC_CfgRd1_2 = 484, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request CfgRd1. | |
| 524 | PCIE_TL_NONFATAL_TLP_CPLTC_CfgWr0_2 = 485, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request CfgWr0. | |
| 525 | PCIE_TL_NONFATAL_TLP_CPLTC_CfgWr1_2 = 486, // Mismatch in Tc (cpl:%d req:%d) in the Completion for the request CfgWr1. | |
| 526 | PCIE_TL_COR_TLP_SLOT_RSV = 487, // Slot Power Limit TLP contains non-0 payload (0x%x) in reserved bits [31:10]. | |
| 527 | PCIE_TL_NONFATAL_TLP_CPLBC_IORd_2 = 488, // Expected ByteCount (%d) differs from actual (%d) in the Completion for the request IORd. | |
| 528 | PCIE_TL_NONFATAL_TLP_CPLBC_MRd32_2 = 489, // Expected ByteCount (%d) differs from actual (%d) in the Completion for the request 32-bit MRd. | |
| 529 | PCIE_TL_NONFATAL_TLP_CPLBC_MRd64_2 = 490, // Expected ByteCount (%d) differs from actual (%d) in the Completion for the request 64-bit MRd. | |
| 530 | PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk32_2 = 491, // Expected ByteCount (%d) differs from actual (%d) in the Completion for the request 32-bit MRdLk. | |
| 531 | PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk64_2 = 492, // Expected ByteCount (%d) differs from actual (%d) in the Completion for the request 64-bit MRdLk. | |
| 532 | PCIE_TL_NONFATAL_TLP_CPLLA_IORd_2 = 493, // Received LowerAddress[6:0]=0x%x, contradicting expected (0x%x), in the Completion for the request 32-bit IORd. | |
| 533 | PCIE_TL_NONFATAL_TLP_CPLLA_MRd32_2 = 494, // Received LowerAddress[6:0]=0x%x, contradicting expected (0x%x), in the first Completion for the request 32-bit MRd. | |
| 534 | PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk32_2 = 495, // Received LowerAddress[6:0]=0x%x, contradicting expected (0x%x), in the first Completion for the request 32-bit MRdLk. | |
| 535 | PCIE_TL_NONFATAL_TLP_CPLLA_MRd64_2 = 496, // Received LowerAddress[6:0]=0x%x, contradicting expected (0x%x), in the first Completion for the request 64-bit MRd. | |
| 536 | PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk64_2 = 497, // Received LowerAddress[6:0]=0x%x, contradicting expected (0x%x), in the first Completion for the request 64-bit MRdLk. | |
| 537 | PCIE_TL_NONFATAL_TLP_CPLLA128_MRd32_1 = 498, // When RCB==128, LowerAddress[6:0] (0x%x) in non-first Completion for the request, 32-bit MRd, must be 0. | |
| 538 | PCIE_TL_NONFATAL_TLP_CPLLA128_MRd64_1 = 499, // When RCB==128, LowerAddress[6:0] (0x%x) in non-first Completion for the request, 64-bit MRd, must be 0. | |
| 539 | PCIE_TL_NONFATAL_TLP_CPLLA128_MRdLk32_1 = 500, // When RCB==128, LowerAddress[6:0] (0x%x) in non-first Completion for the request, 32-bit MRdLk, must be 0. | |
| 540 | PCIE_TL_NONFATAL_TLP_CPLLA128_MRdLk64_1 = 501, // When RCB==128, LowerAddress[6:0] (0x%x) in non-first Completion for the request, 64-bit MRdLk, must be 0. | |
| 541 | PCIE_TL_NONFATAL_TLP_CPLLA64_MRd32_1 = 502, // When RCB==64, LowerAddress[5:0] (0x%x) in non-first Completion for the request, 32-bit MRd, must be 0. | |
| 542 | PCIE_TL_NONFATAL_TLP_CPLLA64_MRd64_1 = 503, // When RCB==64, LowerAddress[5:0] (0x%x) in non-first Completion for the request, 64-bit MRd, must be 0. | |
| 543 | PCIE_TL_NONFATAL_TLP_CPLLA64_MRdLk32_1 = 504, // When RCB==64, LowerAddress[5:0] (0x%x) in non-first Completion for the request, 32-bit MRdLk, must be 0. | |
| 544 | PCIE_TL_NONFATAL_TLP_CPLLA64_MRdLk64_1 = 505, // When RCB==64, LowerAddress[5:0] (0x%x) in non-first Completion for the request, 64-bit MRdLk, must be 0. | |
| 545 | PCIE_TL_NONFATAL_TLP_CPLRCB_MRd32_3 = 506, // When RCB==%d, LowerAddress(0x%x) + Payload(%d) does not align at RCB boundary in Completion for the request 32-bit MRd. | |
| 546 | PCIE_TL_NONFATAL_TLP_CPLRCB_MRd64_3 = 507, // When RCB==%d, LowerAddress(0x%x) + Payload(%d) does not align at RCB boundary in Completion for the request 64-bit MRd. | |
| 547 | PCIE_TL_NONFATAL_TLP_CPLRCB_MRdLk32_3 = 508, // When RCB==%d, LowerAddress(0x%x) + Payload(%d) does not align at RCB boundary in Completion for the request 32-bit MRdLk. | |
| 548 | PCIE_TL_NONFATAL_TLP_CPLRCB_MRdLk64_3 = 509, // When RCB==%d, LowerAddress(0x%x) + Payload(%d) does not align at RCB boundary in Completion for the request 64-bit MRdLk. | |
| 549 | PCIE_TL_NONFATAL_TLP_CPLLEN_MRd32 = 510, // Request 32-bit MRd received additional data (%d bytes) more than requested. | |
| 550 | PCIE_TL_NONFATAL_TLP_CPLLEN_MRdLk32 = 511, // Request 32-bit MRdLk received additional data (%d bytes) more than requested. | |
| 551 | PCIE_TL_NONFATAL_TLP_CPLLEN_MRd64 = 512, // Request 64-bit MRd received additional data (%d bytes) more than requested. | |
| 552 | PCIE_TL_NONFATAL_TLP_CPLLEN_MRdLk64 = 513, // Request 64-bit MRdLk received additional data (%d bytes) more than requested. | |
| 553 | PCIE_TL_NONFATAL_TLP_CPLST_UR_2 = 514, // Completion TLP Cpl returns status UR - TransactionId:0x%06x CompleterId:0x%04x. | |
| 554 | PCIE_TL_NONFATAL_TLP_CPLST_CRS_2 = 515, // Completion TLP Cpl returns status CRS - TransactionId:0x%06x CompleterId:0x%04x. | |
| 555 | PCIE_TL_NONFATAL_TLP_CPLST_CA_2 = 516, // Completion TLP Cpl returns status CA - TransactionId:0x%06x CompleterId:0x%04x. | |
| 556 | PCIE_TL_NONFATAL_TLP_CPLST_DUR_2 = 517, // Completion TLP CplD returns status UR - TransactionId:0x%06x CompleterId:0x%04x. | |
| 557 | PCIE_TL_NONFATAL_TLP_CPLST_DCRS_2 = 518, // Completion TLP CplD returns status CRS - TransactionId:0x%06x CompleterId:0x%04x. | |
| 558 | PCIE_TL_NONFATAL_TLP_CPLST_DCA_2 = 519, // Completion TLP CplD returns status CA - TransactionId:0x%06x CompleterId:0x%04x. | |
| 559 | PCIE_TL_NONFATAL_TLP_CPLST_LKUR_2 = 520, // Completion TLP CplLk returns status UR - TransactionId:0x%06x CompleterId:0x%04x. | |
| 560 | PCIE_TL_NONFATAL_TLP_CPLST_LKCRS_2 = 521, // Completion TLP CplLk returns status CRS - TransactionId:0x%06x CompleterId:0x%04x. | |
| 561 | PCIE_TL_NONFATAL_TLP_CPLST_LKCA_2 = 522, // Completion TLP CplLk returns status CA - TransactionId:0x%06x CompleterId:0x%04x. | |
| 562 | PCIE_TL_NONFATAL_TLP_CPLST_DLKUR_2 = 523, // Completion TLP CplLkD returns status UR - TransactionId:0x%06x CompleterId:0x%04x. | |
| 563 | PCIE_TL_NONFATAL_TLP_CPLST_DLKCRS_2 = 524, // Completion TLP CplLkD returns status CRS - TransactionId:0x%06x CompleterId:0x%04x. | |
| 564 | PCIE_TL_NONFATAL_TLP_CPLST_DLKCA_2 = 525, // Completion TLP CplLkD returns status CA - TransactionId:0x%06x CompleterId:0x%04x. | |
| 565 | PCIE_TL_NONFATAL_TLP_CPLND_2 = 526, // Completion TLP Cpl returns no data, which is required by the request %s - [TransactionId:0x%06x CompleterId:0x%04x]. | |
| 566 | PCIE_TL_NONFATAL_TLP_CPLNDLK_2 = 527, // Completion TLP CplLk returns no data, which is required by the request %s - [TransactionId:0x%06x CompleterId:0x%04x]. | |
| 567 | PCIE_TL_NONFATAL_TLP_CPLD_2 = 528, // Completion TLP CplD returns data, which is not required by the request %s - [TransactionId:0x%06x CompleterId:0x%04x]. | |
| 568 | PCIE_TL_NONFATAL_TLP_CPLDLK_2 = 529, // Completion TLP CplLkD returns data, which is not required by the request %s - [TransactionId:0x%06x CompleterId:0x%04x]. | |
| 569 | PCIE_TL_NONFATAL_TLP_ADOVF_4 = 530, // Request %s overflows address space, reject the request [startAddr:0x%lx byteCnt:%d maxLowAddrBits:0x%x]. | |
| 570 | PCIE_TL_NONFATAL_TLP_ADNON_1 = 531, // Request %s with %s address [0x%llx] refers to a non-existing or out-of-range Memory/IO device, reject the request. | |
| 571 | PCIE_TL_NONFATAL_TLP_ADNON0_1 = 532, // Request %s with address [0x%llx] refers to a Memory/IO device defined at the downstream, reject the request. | |
| 572 | PCIE_TL_NONFATAL_TLP_IDNON_2 = 533, // TLP packet %s with %s Id [0x%llx] refers to a non-existing or out-of-range device, reject the packet. | |
| 573 | PCIE_TL_COR_TLP_PORT_3 = 534, // TLP packet %s to port %d, but the packet data indicates to port %d, reject the packet. | |
| 574 | PCIE_TL_NONFATAL_TLP_TAG = 535, // No unique Tag number is available for the new Request that requires a Transaction ID. | |
| 575 | PCIE_TL_COR_TLP_DISTAG = 536, // Cannot disable Extended Tag because it is used by some outstanding Requests. | |
| 576 | PCIE_TL_COR_TLP_DISPH = 537, // Cannot disable Phantom Function because there exist outstanding Requests. | |
| 577 | PCIE_TL_COR_TLP_DISPH_2 = 538, // Cannot shrink TAG range by changing Phantom Function from %d to %d because there exist outstanding Requests in the TAG range. | |
| 578 | PCIE_TL_COR_TLP_FNRNG_4 = 539, // Function number %d is not in valid range [%d, %d], required according to phantom number settings. Changed to function %d | |
| 579 | PCIE_TL_COR_TLP_USERTAG_2 = 540, // Function (%u) and Tag (%u) identified an unfinished transaction, discard the transaction. | |
| 580 | PCIE_TL_COR_TLP_USERTAG0_2 = 541, // Function (%u) and Tag (%u) form an out-of-range transaction Tag, discard the transaction. | |
| 581 | PCIE_TL_COR_TLP_MIO_2 = 542, // Request %s with address [0x%llx] refers to a non-%s mapped device. | |
| 582 | PCIE_TL_COR_TLP_UR_1 = 543, // Request %s is not supported by this device. | |
| 583 | PCIE_TL_COR_TLP_WRCRB_4 = 544, // Register (id=%lu) is out-of-range [%d : %d] when writing to RCRB %s. | |
| 584 | PCIE_TL_COR_TLP_CPLTO_2 = 545, // Timeout value (%s) expired: Request %s was %s and waiting for Completion. Dropping this request. | |
| 585 | PCIE_TL_NONFATAL_TLP_FAIL_TX = 546, // TLP Packet failed the protocol check, will not be transmitted. | |
| 586 | PCIE_TL_NONFATAL_TLP_FAIL_RX = 547, // The received TLP Packet failed the protocol check. | |
| 587 | PCIE_TL_COR_CFG_EEP_MINBAR = 548, // Minimum address range by a BAR in a PCIE Express Endpoint is 128 bytes (7 bits). | |
| 588 | PCIE_TL_COR_PKT_UNKT = 549, // Discarding packet with unknown type (%u). | |
| 589 | PCIE_TL_COR_CFG_PTRRSV0 = 550, // Downstream %s: Capability pointer Register '%s' has non-0 value 0x%x in reserved bits [1:0]. | |
| 590 | PCIE_TL_COR_CFG_PTRRSV = 551, // %s: Capability pointer Register '%s' has non-0 value 0x%x in reserved bits [1:0]. | |
| 591 | PCIE_TL_COR_CFG_CAPID = 552, // Illegal capability ID (%d) starting at address 0x%x, pointed by register '%s', at port function '%s'. | |
| 592 | PCIE_TL_COR_CFG_PTROVF0 = 553, // Downstream %s:Capability pointer Register '%s' has value (%u) that is over the limit 0x%X. | |
| 593 | PCIE_TL_COR_CFG_STOVF = 554, // Capability '%s' at port function (%s) has starting address (0x%02x) that is over the limit 0x%02x. | |
| 594 | PCIE_TL_COR_CFG_CAPNST = 555, // New capability '%s' at port function (%s) does not have a valid starting address. | |
| 595 | PCIE_TL_COR_CFG_PTROVF = 556, // %s: Capability pointer Register '%s' has value (%u) that is over the limit 0x%X. | |
| 596 | PCIE_TL_COR_CFG_PORTTYPE = 557, // Port Function:%s has type '%s', but it should be '%s'. | |
| 597 | PCIE_TL_COR_CFG_BUSNUM = 558, // Port Function:%s has Bus Number '%u', but it should be '%u'. | |
| 598 | PCIE_TL_FATAL_SYS_IOMAX = 559, // Exceeding system limit (0x%llx) on %u-bit IO mapped memory. It needs more than 0x%llx. | |
| 599 | PCIE_TL_FATAL_SYS_IOBMAX = 560, // Exceeding system limit (0x%llx) on %u-bit IO mapped memory. The starting address is bigger than 0x%llx. | |
| 600 | PCIE_TL_FATAL_SYS_IOEMAX = 561, // Exceeding system limit (0x%llx) on %u-bit IO mapped memory. The starting address: 0x%llx total bytes is more than 0x%llx. | |
| 601 | PCIE_TL_FATAL_SYS_MEMMAX = 562, // Exceeding system limit (0x%llx) on %u-bit space memory. It needs more than 0x%llx. | |
| 602 | PCIE_TL_FATAL_SYS_MEMBMAX = 563, // Exceeding system limit (0x%llx) on %u-bit space memory. The starting address is bigger than 0x%llx. | |
| 603 | PCIE_TL_FATAL_SYS_MEMEMAX = 564, // Exceeding system limit (0x%llx) on %u-bit space memory. The starting address: 0x%llx total bytes is more than 0x%llx. | |
| 604 | PCIE_TL_FATAL_CFG1_MAX64 = 565, // Port function (%s) failed the assignment to BARs, exceeding 64-bit limit (0x%llx + 0x%llx > 0x%llx). | |
| 605 | PCIE_TL_COR_CFG1_PMEMB0 = 566, // Port function (%s) does not implement Prefetchable Memory range, but the Base register (0x%04x) is not 0 when read after written 0xFFFF. | |
| 606 | PCIE_TL_COR_CFG1_PMEML0 = 567, // Port function (%s) does not implement Prefetchable Memory range, but the Limit register (0x%04x) is not 0 when read after written 0xFFFF. | |
| 607 | PCIE_TL_COR_CFG1_IOB0 = 568, // Port function (%s) does not implement IO Memory range, but the Base register (0x%04x) is not 0 when read after written 0xFFFF. | |
| 608 | PCIE_TL_COR_CFG1_IOL0 = 569, // Port function (%s) does not implement IO Memory range, but the Limit register (0x%04x) is not 0 when read after written 0xFFFF. | |
| 609 | PCIE_TL_COR_CFG1_PMEMBL4 = 570, // The lower 4-bits of the Prefetchable Memory Base (0x%04x) and Limit (0x%04x) must be equal. | |
| 610 | PCIE_TL_COR_CFG1_PMEMBVAL = 571, // The %u-bit Prefetchable Memory Base (0x%04x) are Read-Writable, should be 0xfff%u when read after written 0xffff. | |
| 611 | PCIE_TL_COR_CFG1_PMEMLVAL = 572, // The %u-bit Prefetchable Memory Limit (0x%04x) are Read-Writable, should be 0xfff%u when read after written 0xffff. | |
| 612 | PCIE_TL_COR_CFG1_PMEMBRSV = 573, // The lower 4-bits of the Prefetchable Memory Base (0x%04x) must be 0 or 1. | |
| 613 | PCIE_TL_COR_CFG1_PMEMLRSV = 574, // The lower 4-bits of the Prefetchable Memory Limit (0x%04x) must be 0 or 1. | |
| 614 | PCIE_TL_COR_CFG1_PMEMUBVAL = 575, // Device supports %u-bit Prefetchable Memory Range, the Upper 32 Base (0x%08x) are Read-Writable, should be 0x08%x when read after written 0xffffffff. | |
| 615 | PCIE_TL_COR_CFG1_PMEMULVAL = 576, // Device supports %u-bit Prefetchable Memory Range, the Upper 32 Limit (0x%08x) are Read-Writable, should be 0x08%x when read after written 0xffffffff. | |
| 616 | PCIE_TL_COR_CFG1_PMEMUBVAL0 = 577, // Device does not support Prefetchable Memory Range, the Upper 32 Base (0x%08x) are Read-Only, should be 0x00000000 when read after written 0xffffffff. | |
| 617 | PCIE_TL_COR_CFG1_PMEMULVAL0 = 578, // Device does not support Prefetchable Memory Range, the Upper 32 Limit (0x%08x) are Read-Only, should be 0x00000000 when read after written 0xffffffff. | |
| 618 | PCIE_TL_COR_CFG1_IOUR = 579, // Virtual bridge (%s) does not support %s IO Range, the %u-bit IO memories behind the bridge are accessible only through normal (non-prefetchable) 32-bit Memory Range mechanism. | |
| 619 | PCIE_TL_COR_CFG1_PMEMUR = 580, // Virtual bridge (%s) does not support %s Prefetchable Memory Range, the %u-bit Prefetchable Memories behind the bridge are accessible only through normal (non-prefetchable) 32-bit Memory Range mechanism. | |
| 620 | PCIE_TL_COR_CFG_M64PF = 581, // BAR_%u at port function (%s) illegally defines a non-prefetchable 64-bit Memory with address width (%u bits). Coerced it to 'prefetchable', because only prefetchable memory may have address width greater than 31. | |
| 621 | PCIE_TL_COR_CFG1_IOBL4 = 582, // The lower 4-bits of the IO Base (0x%02x) and Limit (0x%02x) must be equal. | |
| 622 | PCIE_TL_COR_CFG1_IOBVAL = 583, // The %u-bit IO Base (0x%02x) are Read-Writable, should be 0xf%u when read after written 0xff. | |
| 623 | PCIE_TL_COR_CFG1_IOLVAL = 584, // The %u-bit IO Limit (0x%02x) are Read-Writable, should be 0xf%u when read after written 0xff. | |
| 624 | PCIE_TL_COR_CFG1_IOBRSV = 585, // The lower 4-bits of the IO Base (0x%02x) must be 0 or 1. | |
| 625 | PCIE_TL_COR_CFG1_IOLRSV = 586, // The lower 4-bits of the IO Limit (0x%02x) must be 0 or 1. | |
| 626 | PCIE_TL_COR_CFG1_IOUBVAL = 587, // Device supports 32-bit IO Range, the IO Upper 16 Base (0x%04x) are Read-Writable, should be 0xffff when read after written 0xffff. | |
| 627 | PCIE_TL_COR_CFG1_IOULVAL = 588, // Device supports 32-bit IO Range, the IO Upper 16 Limit (0x%04x) are Read-Writable, should be 0xffff when read after written 0xffff. | |
| 628 | PCIE_TL_COR_CFG1_IOUBVAL0 = 589, // Device does not support 32-bit IO Range, the IO Upper 16 Base (0x%04x) are Read-Only, should be 0x0000 when read after written 0xffff. | |
| 629 | PCIE_TL_COR_CFG1_IOULVAL0 = 590, // Device does not support 32-bit IO Range, the IO Upper 16 Limit (0x%04x) are Read-Only, should be 0x0000 when read after written 0xffff. | |
| 630 | PCIE_TL_COR_CFG1_MEMBVAL = 591, // The Memory Base (0x%04x) register should be 0xFFF0 when read after written 0xffff. | |
| 631 | PCIE_TL_COR_CFG1_MEMLVAL = 592, // The Memory Limit (0x%04x) register should be 0xFFF0 when read after written 0xffff. | |
| 632 | PCIE_TL_COR_MIO_MEMRNG0_5 = 593, // Downstream %s: BAR_%u, configured as %s: its address size (%d bits) is not in range [%d : %d]. | |
| 633 | PCIE_TL_COR_MIO_MEMRNG_5 = 594, // %s: BAR_%u, configured as %s: its address size (%d bits) is not in range [%d : %d]. | |
| 634 | PCIE_TL_COR_MIO_EEPRNG_2 = 595, // BAR_%u at PCI Express Endpoint, its address size (%d bits) must be at least 7 (128 bytes). | |
| 635 | PCIE_TL_COR_MIO_MEMLOW0_4 = 596, // Downstream %s: BAR_%u, configured as %s: its value (0x%x), when read, is not 0 at lower bits [%d : %d]. | |
| 636 | PCIE_TL_COR_MIO_MEMLOW_4 = 597, // %s: BAR_%u, configured as %s: its value (0x%x), when read, is not 0 at lower bits [%d : %d]. | |
| 637 | PCIE_TL_COR_MIO_IORSV01_1 = 598, // BAR_%u at port function '%s', configured as 32-bit IO: its reserved bit[1], when read, is not 0. | |
| 638 | PCIE_TL_COR_MIO_IORSV1_1 = 599, // BAR_%u, configured as 32-bit IO: its reserved bit[1], when read, is not 0. | |
| 639 | PCIE_TL_COR_MIO_MEMTYPE0_2 = 600, // BAR_%u at port function '%s', specified an unknown memory type (value=%d, must be 0 or 2). | |
| 640 | PCIE_TL_COR_MIO_MEMTYPE_2 = 601, // BAR_%u specified an unknown memory type (value=%d, must be 0 or 2). | |
| 641 | PCIE_TL_COR_MIO_MEM64N_1 = 602, // BAR_%u, the last one available, cannot specify a 64-bit Memory. | |
| 642 | PCIE_TL_COR_MIO_BA_4 = 603, // %s[%s] is assigned an overlapped base address 0x%llx (must be >= 0x%llx). | |
| 643 | PCIE_TL_COR_MIO_OVF64 = 604, // %s[%s] is assigned an invalid base address 0x%llx (+length:0x%llx overflows 64-bit address range), exhausting 64-bit memory space. | |
| 644 | PCIE_TL_COR_MIO_OVF32 = 605, // %s[%s], %s, is assigned an invalid base address 0x%llx (+length:0x%llx overflows 32-bit address range), exhausting 32-bit memory space. | |
| 645 | PCIE_TL_COR_TLP_ADDRSELF_2 = 606, // TLP %s is addressing own memory by address 0x%llx, reject the packet. | |
| 646 | PCIE_TL_COR_TLP_IDSELF_2 = 607, // TLP %s is referencing itself through ID 0x%llx, reject the packet. | |
| 647 | PCIE_TL_NONFATAL_TLP_PLN0_Msg = 608, // TLP Msg (%s) has non-0 in payload (0x%x) at bits [%d : %d]. | |
| 648 | PCIE_TL_NONFATAL_TLP_PLN0_MsgD = 609, // TLP MsgD (%s) has non-0 in payload (0x%x) at bits [%d : %d]. | |
| 649 | PCIE_TL_NONFATAL_TLP_ECRC_0 = 610, // TD field is 0 in the RawTlp, but the device port is capable and enabled to generate ECRC. | |
| 650 | PCIE_TL_NONFATAL_TLP_ECRC_1 = 611, // TD field is 1 in the RawTlp, but the device port is not capable and enabled to generate ECRC. | |
| 651 | PCIE_TL_NONFATAL_TLP_ECRC_MRd32 = 612, // TLP 32-bit MRd has invalid ECRC: expect-0x%x actual-0x%x. | |
| 652 | PCIE_TL_NONFATAL_TLP_ECRC_MRdLk32 = 613, // TLP 32-bit MRdLk has invalid ECRC: expect-0x%x actual-0x%x. | |
| 653 | PCIE_TL_NONFATAL_TLP_ECRC_MRd64 = 614, // TLP 64-bit MRd has invalid ECRC: expect-0x%x actual-0x%x. | |
| 654 | PCIE_TL_NONFATAL_TLP_ECRC_MRdLk64 = 615, // TLP 64-bit MRdLk has invalid ECRC: expect-0x%x actual-0x%x. | |
| 655 | PCIE_TL_NONFATAL_TLP_ECRC_MWr32 = 616, // TLP 32-bit MWr has invalid ECRC: expect-0x%x actual-0x%x. | |
| 656 | PCIE_TL_NONFATAL_TLP_ECRC_MWr64 = 617, // TLP 64-bit MWr has invalid ECRC: expect-0x%x actual-0x%x. | |
| 657 | PCIE_TL_NONFATAL_TLP_ECRC_IORd = 618, // TLP IORd has invalid ECRC: expect-0x%x actual-0x%x. | |
| 658 | PCIE_TL_NONFATAL_TLP_ECRC_IOWr = 619, // TLP IOWr has invalid ECRC: expect-0x%x actual-0x%x. | |
| 659 | PCIE_TL_NONFATAL_TLP_ECRC_CfgRd0 = 620, // TLP CfgRd0 has invalid ECRC: expect-0x%x actual-0x%x. | |
| 660 | PCIE_TL_NONFATAL_TLP_ECRC_CfgRd1 = 621, // TLP CfgRd1 has invalid ECRC: expect-0x%x actual-0x%x. | |
| 661 | PCIE_TL_NONFATAL_TLP_ECRC_CfgWr0 = 622, // TLP CfgWr0 has invalid ECRC: expect-0x%x actual-0x%x. | |
| 662 | PCIE_TL_NONFATAL_TLP_ECRC_CfgWr1 = 623, // TLP CfgWr1 has invalid ECRC: expect-0x%x actual-0x%x. | |
| 663 | PCIE_TL_NONFATAL_TLP_ECRC_Msg = 624, // TLP Msg has invalid ECRC: expect-0x%x actual-0x%x. | |
| 664 | PCIE_TL_NONFATAL_TLP_ECRC_MsgD = 625, // TLP MsgD has invalid ECRC: expect-0x%x actual-0x%x. | |
| 665 | PCIE_TL_NONFATAL_TLP_ECRC_Cpl = 626, // TLP Cpl has invalid ECRC: expect-0x%x actual-0x%x. | |
| 666 | PCIE_TL_NONFATAL_TLP_ECRC_CplD = 627, // TLP CplD has invalid ECRC: expect-0x%x actual-0x%x. | |
| 667 | PCIE_TL_NONFATAL_TLP_ECRC_CplLk = 628, // TLP CplLk has invalid ECRC: expect-0x%x actual-0x%x. | |
| 668 | PCIE_TL_NONFATAL_TLP_ECRC_CplDLk = 629, // TLP CplLkD has invalid ECRC: expect-0x%x actual-0x%x. | |
| 669 | PCIE_TL_NONFATAL_TLP_MF_MSGBYIDDN = 630, // Downstream %s port unexpectedly received a TLP %s with routing '%s' (reqid:%0x04x) back through itself to downstream components. | |
| 670 | PCIE_TL_NONFATAL_TLP_MF_MSGBYIDUP = 631, // Upstream %s port unexpectedly received a TLP %s with routing '%s' (reqid:%0x04x) back through itself to upstream components. | |
| 671 | PCIE_TL_NONFATAL_TLP_MF_MSGTORC = 632, // %sstream %s port unexpectedly received a TLP %s with routing '%s'. | |
| 672 | PCIE_TL_NONFATAL_TLP_MF_MSGNID = 633, // TLP (%s) with routing method (%s) specifies an unknown device (requester id:0x%04x), at port function (%s). | |
| 673 | PCIE_TL_NONFATAL_TLP_MF_PLDWalign = 634, // Payload data size (%d bits) is not in increments of four-Byte Double Words. | |
| 674 | PCIE_TL_NONFATAL_TLP_MF_PLSize = 635, // Payload data size (%d bits) is less than the minimum(%d bits). | |
| 675 | PCIE_TL_NONFATAL_TLP_EI_PLDWalign = 636, // Payload size (%d) is not in increments of four-Byte Double Words through error injection, truncating %s bits. | |
| 676 | PCIE_TL_NONFATAL_VC_ARB0_2 = 637, // VC number (%u) in arbitration table entry (%d) is not supported at this port, convert to VC0. | |
| 677 | PCIE_TL_NONFATAL_VC_ARB1_1 = 638, // Number of entries (%u) in the arbitration table is not supported at this port. | |
| 678 | PCIE_TL_NONFATAL_MEM_NREG_2 = 639, // Combination of [extReg:%d regNum:%d] from %s does not identify a valid address in Configuration space at this port. | |
| 679 | PCIE_TL_FATAL_RTLP_ECRC_N = 640, // Reject the outbound RawTlp -- missing the required ECRC. | |
| 680 | PCIE_TL_FATAL_RTLP_ECRC_0 = 641, // Reject the outbound RawTlp -- specified ECRC which is not required. | |
| 681 | PCIE_TL_FATAL_CFG_BRCHG = 642, // Change base address to memory defined by '%s' [base:0x%llx type:%s bits:%u] at port-function %s, after device configuration at time %s. | |
| 682 | PCIE_TL_FATAL_CFG_BRCHG1 = 643, // Change base address to memory defined by '%s' [base:0x%llx type:%s bits:%u] at port-function %s, after device configuration at time %s. | |
| 683 | PCIE_TL_FATAL_CFG_BRNEW = 644, // New memory defined by '%s' [base:0x%llx type:%s bits:%u] at port-function %s, after device configuration at time %s. | |
| 684 | PCIE_TL_FATAL_CFG_BRNEW1 = 645, // New memory defined by '%s' [base:0x%llx type:%s bits:%u] at port-function %s, after device configuration at time %s. | |
| 685 | PCIE_TL_COR_CFG_DCPLRSV = 646, // %s: Max_Payload_Size code (0x%x) in register '%s' is not in legal range [0 : 5], change to maximum 5. | |
| 686 | PCIE_TL_COR_CFG_DCRDRSV = 647, // %s: Max_Read_Request_Size code (0x%x) in register '%s' is not in legal range [0 : 5], change to maximum 5. | |
| 687 | PCIE_TL_COR_CFG_DCRDMPL = 648, // %s: Max_Read_Request_Size code (0x%x) is illegally greater than Max_Payload_Size code (0x%x) in register '%s', change to 0x%x. | |
| 688 | PCIE_TL_COR_CFG_DCPLMCAP = 649, // %s: Max_Payload_Size code (0x%x) in register '%s' is illegally greater than the supported (0x%x) set in Capabiity register. | |
| 689 | PCIE_TL_COR_CFG_DCPLRSV0 = 650, // At downstream %s: Max_Payload_Size code (0x%x) in register '%s' is not in legal range [0 : 5], change to maximum 5. | |
| 690 | PCIE_TL_COR_CFG_DCRDRSV0 = 651, // At downstream %s: Max_Read_Request_Size code (0x%x) in register '%s' is not in legal range [0 : 5], change to maximum 5. | |
| 691 | PCIE_TL_COR_CFG_DCRDMPL0 = 652, // At downstream %s: Max_Read_Request_Size code (0x%x) is illegally greater than Max_Payload_Size code (0x%x) in register '%s', change to 0x%x. | |
| 692 | PCIE_TL_COR_CFG_DCPLMCAP0 = 653, // At downstream %s: Max_Payload_Size code (0x%x) in register '%s' is illegally greater than the supported (0x%x) set in Capabiity register, change to 0x%x. | |
| 693 | PCIE_TL_COR_DEN_DELAY_SYS = 654, // Ignore the packet delay (%u) specified for this system TLP (%s) during System Configuration Initialization. | |
| 694 | PCIE_TL_COR_CMPCFG_VAL = 655, // Data from CplD differs from Expected in register, offset at 0x%x. Expected:%s Received:%s. | |
| 695 | PCIE_TL_COR_CMPCFG_SIZE = 656, // Expected data size (%u bits) differs from CplD's payload size (%u bits) for register, offset at 0x%x. | |
| 696 | PCIE_TL_COR_CMPMEM_SIZE = 657, // Expected data size (%u bits) differs from CplD's payload size (%u bits) for the memory read Request. | |
| 697 | PCIE_TL_COR_CMPMEM_VAL = 658, // Returned Data for Read-Request differs from the Expected. The first difference is at byte address 0x%llx, Expected:%s Received:%s. | |
| 698 | PCIE_TL_NONFATAL_TLP_MF_vlCfg1 = 659, // %s TLP %s, but %s Port Function is defined as Configuration 0. | |
| 699 | PCIE_TL_NONFATAL_TLP_MF_vlCfg0 = 660, // %s TLP %s, but %s Port Function (transmitter) is not defined as Configuration 1. | |
| 700 | PCIE_TL_NONFATAL_MON_REG = 661, // Through cplD, detected that Monitor and Device have different values in register, offset at 0x%x Monitor:%s. Device:%s. | |
| 701 | PCIE_TL_NONFATAL_MON_MEM = 662, // Through cplD, detected that Monitor and Device have different values. The first difference is at byte address 0x%llx in memory defined by register %s, Device:%s Monitor:%s. | |
| 702 | PCIE_TL_COR_TLP_PLX = 663, // Non 0/1 payload values in the outbound packet; replacing with %s. | |
| 703 | PCIE_TL_COR_TLP_EXPPLX = 664, // Non 0/1 values in the expected Payload; replacing with %s. | |
| 704 | PCIE_TL_COR_TLP_PLOVF = 665, // Some %s byte value overflows (over 8-bits), truncating it to smaller value. | |
| 705 | PCIE_TL_FATAL_TLP_BR_NILBUS = 666, // %s addresses a device [bus:%u dev:%u func:%u], but this Bridge has no device behind. | |
| 706 | PCIE_TL_FATAL_TLP_BR_OBBUS = 667, // %s addresses a device [bus:%u dev:%u func:%u], whose bus is not within range [%u , %u] behind this Bridge. | |
| 707 | PCIE_TL_FATAL_TLP_BR_OBABUS = 668, // %s addresses a device [bus:%u dev:%u func:%u]. Though the bus is within range [%u , %u] defined by the Configuration registers, the actual bus is not detected by the Bridge. | |
| 708 | PCIE_TL_FATAL_TLP_SW_CNILID = 669, // The requester id [bus:%u dev:%u func:%u] of this Completion %s is unknown to Switch port function (%s), which defines bus range [%u, %u]. | |
| 709 | PCIE_TL_FATAL_TLP_BR_NILDEV = 670, // %s addresses a non-existing device [bus:%u dev:%u func:%u] behind the Bridge. No device is attached to the specified bus. | |
| 710 | PCIE_TL_FATAL_TLP_BR_OBDEV = 671, // %s addresses a non-existing device [bus:%u dev:%u func:%u] behind the Bridge. | |
| 711 | PCIE_TL_FATAL_TLP_SW_NILBUS = 672, // %s addresses a device [bus:%u dev:%u func:%u], but this Switch has no device behind. | |
| 712 | PCIE_TL_FATAL_TLP_SW_OBBUS = 673, // %s addresses a device [bus:%u dev:%u func:%u], whose bus is not within range [%u , %u] behind this Switch. | |
| 713 | PCIE_TL_FATAL_TLP_SW_OBABUS = 674, // %s addresses a device [bus:%u dev:%u func:%u]. Though the bus is within range [%u , %u] defined by the Configuration registers, the actual bus is not detected by the Switch. | |
| 714 | PCIE_TL_FATAL_TLP_SW_NILDEV = 675, // %s addresses a non-existing device [bus:%u dev:%u func:%u] behind the Switch. No device is attached to the specified bus. | |
| 715 | PCIE_TL_FATAL_TLP_SW_OBDEV = 676, // %s addresses a non-existing device [bus:%u dev:%u func:%u] behind the Switch. | |
| 716 | PCIE_TL_NONFATAL_TLP_COR_ERR_MISMATCH = 677, // Mismatch in the number of Correctable Error Msg Tlp's transmitted by the device - Expected : %d; Actual : %d. | |
| 717 | PCIE_TL_NONFATAL_TLP_FATAL_ERR_MISMATCH = 678, // Mismatch in the number of Fatal Error Msg Tlp's transmitted by the device - Expected : %d; Actual : %d. | |
| 718 | PCIE_TL_NONFATAL_TLP_NONFATAL_ERR_MISMATCH = 679, // Mismatch in the number of Non-Fatal Error Msg Tlp's transmitted by the device - Expected : %d; Actual : %d. | |
| 719 | PCIE_MAX_ERROR_ID = 680 ; | |
| 720 | ||
| 721 | ||
| 722 | #endif // DENALI_PCIEERR_TYPES_VRH |