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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / fnx / vlib / FNXPCIEXactor / src / FNXPCIEXactorStatsDatabase.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: FNXPCIEXactorStatsDatabase.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "DenaliPCIE.vri"
36
37// FNXPCIEXactor library
38#include "FNXPCIEXactorDefines.vri"
39
40// report library
41#include "cReport.vrh"
42#include "FNXPCIEXactorReportMacros.vri"
43
44class FNXPCIEXactorStatsDatabase {
45
46 // Base Class and Method Names For QR Macros
47 local string ClassName = "FNXPCIEXactorStatsDatabase";
48 local string MethodName = null;
49
50 local ReportClass MyReport;
51 local string XactorName;
52
53 // Overall TLP Statistics
54 integer NumTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
55
56 // Overall DLLP Statistics
57 integer NumDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
58
59 // DLLP Distribution
60 integer NumAckDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
61 integer NumNakDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
62 integer NumUpFCPDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
63 integer NumUpFCNPDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
64 integer NumUpFCCplDLLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
65
66 // TLP Distribution
67 integer NumMWr32TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
68 integer NumMWr64TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
69
70 integer NumMRd32TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
71 integer NumMRd64TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
72 integer NumMRdLk32TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
73 integer NumMRdLk64TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
74
75 integer NumIOWrTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
76 integer NumIORdTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
77
78 integer NumCfgWr0TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
79 integer NumCfgRd0TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
80 integer NumCfgWr1TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
81 integer NumCfgRd1TLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
82
83 integer NumCplTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
84 integer NumCplDTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
85 integer NumCplLkTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
86 integer NumCplDLkTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
87
88 integer NumMsgTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
89 integer NumMsgDTLPs[FNX_PCIE_XTR_NUM_STAT_DIRS];
90
91 // TLP Length
92 integer MWr32Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
93 integer MWr64Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
94 integer MRd32Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
95 integer MRd64Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
96 integer IOWrBytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
97 integer IORdBytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
98 integer CfgWr0Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
99 integer CfgRd0Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
100 integer CfgWr1Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
101 integer CfgRd1Bytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
102 integer CplDBytes[FNX_PCIE_XTR_NUM_STAT_DIRS][FNX_PCIE_XTR_NUM_STAT_TYPES];
103
104 // constructor
105 task new( ReportClass _Report,
106 string _XactorName );
107
108 // public methods
109 task Reset();
110 function string GetStr();
111 task Display( ReportType rptType );
112 task UpdatePkt( FNXPCIEXactorPacket pkt,
113 integer statDir );
114}
115
116task FNXPCIEXactorStatsDatabase::new( ReportClass _Report,
117 string _XactorName )
118{
119 string MethodName = "new";
120
121 MyReport = _Report;
122 XactorName = _XactorName;
123 Reset();
124}
125
126task FNXPCIEXactorStatsDatabase::Reset()
127{
128 string MethodName = "Reset";
129 string tmp, whiteSpaceStr;
130 integer i, j;
131
132 for (i=0; i < FNX_PCIE_XTR_NUM_STAT_DIRS; i++) {
133 NumTLPs[i] = 0;
134 NumMWr32TLPs[i] = 0;
135 NumMWr64TLPs[i] = 0;
136 NumMRd32TLPs[i] = 0;
137 NumMRd64TLPs[i] = 0;
138 NumMRdLk32TLPs[i] = 0;
139 NumMRdLk64TLPs[i] = 0;
140 NumIOWrTLPs[i] = 0;
141 NumIORdTLPs[i] = 0;
142 NumCfgWr0TLPs[i] = 0;
143 NumCfgRd0TLPs[i] = 0;
144 NumCfgWr1TLPs[i] = 0;
145 NumCfgRd1TLPs[i] = 0;
146 NumCplTLPs[i] = 0;
147 NumCplDTLPs[i] = 0;
148 NumCplLkTLPs[i] = 0;
149 NumCplDLkTLPs[i] = 0;
150 NumMsgTLPs[i] = 0;
151 NumMsgDTLPs[i] = 0;
152
153 NumDLLPs[i] = 0;
154 NumAckDLLPs[i] = 0;
155 NumNakDLLPs[i] = 0;
156 NumUpFCPDLLPs[i] = 0;
157 NumUpFCNPDLLPs[i] = 0;
158 NumUpFCCplDLLPs[i] = 0;
159
160 for (j=0; j < FNX_PCIE_XTR_NUM_STAT_TYPES; j++) {
161 if (j === FNX_PCIE_XTR_STAT_TYPE_MIN) {
162 MWr32Bytes[i][j] = 512; // Default Min to Maximum Size To Ease Math Later
163 MWr64Bytes[i][j] = 512;
164 MRd32Bytes[i][j] = 4096;
165 MRd64Bytes[i][j] = 4096;
166 CplDBytes[i][j] = 512;
167 IOWrBytes[i][j] = 4;
168 IORdBytes[i][j] = 4;
169 CfgWr0Bytes[i][j] = 4;
170 CfgRd0Bytes[i][j] = 4;
171 CfgWr1Bytes[i][j] = 4;
172 CfgRd1Bytes[i][j] = 4;
173 } else {
174 MWr32Bytes[i][j] = 0;
175 MWr64Bytes[i][j] = 0;
176 MRd32Bytes[i][j] = 0;
177 MRd64Bytes[i][j] = 0;
178 CplDBytes[i][j] = 0;
179 IOWrBytes[i][j] = 0;
180 IORdBytes[i][j] = 0;
181 CfgWr0Bytes[i][j] = 0;
182 CfgRd0Bytes[i][j] = 0;
183 CfgWr1Bytes[i][j] = 0;
184 CfgRd1Bytes[i][j] = 0;
185 }
186 }
187 }
188}
189
190function string FNXPCIEXactorStatsDatabase::GetStr()
191{
192 string MethodName = "GetStr";
193 string tmp, dirStr;
194 integer i;
195
196 // Add TLP Information
197 for (i=0; i < FNX_PCIE_XTR_NUM_STAT_DIRS; i++) {
198
199 if (i === FNX_PCIE_XTR_STAT_DIR_XMIT)
200 sprintf( tmp, "TLPs Transmitted\n" );
201 if (i === FNX_PCIE_XTR_STAT_DIR_RCV)
202 sprintf( tmp, "\nTLPs Received\n" );
203 GetStr = { GetStr, tmp };
204
205
206 sprintf( tmp, " Type Num Min Max Avg Total\n" );
207 GetStr = { GetStr, tmp };
208 sprintf( tmp, " Total %7d\n", NumTLPs[i] );
209 GetStr = { GetStr, tmp };
210 sprintf( tmp, " MWr32 %7d %4d %4d %4d %0d\n", NumMWr32TLPs[i],
211 MWr32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
212 MWr32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
213 MWr32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
214 MWr32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
215 GetStr = { GetStr, tmp };
216 sprintf( tmp, " MWr64 %7d %4d %4d %4d %0d\n", NumMWr64TLPs[i],
217 MWr64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
218 MWr64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
219 MWr64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
220 MWr64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
221 GetStr = { GetStr, tmp };
222 sprintf( tmp, " MRd32 %7d %4d %4d %4d %0d\n", NumMRd32TLPs[i],
223 MRd32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
224 MRd32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
225 MRd32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
226 MRd32Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
227 GetStr = { GetStr, tmp };
228 sprintf( tmp, " MRd64 %7d %4d %4d %4d %0d\n", NumMRd64TLPs[i],
229 MRd64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
230 MRd64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
231 MRd64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
232 MRd64Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
233 GetStr = { GetStr, tmp };
234 sprintf( tmp, " MRdLk32 %7d\n", NumMRdLk32TLPs[i] );
235 GetStr = { GetStr, tmp };
236 sprintf( tmp, " MRdLk64 %7d\n", NumMRdLk64TLPs[i] );
237 GetStr = { GetStr, tmp };
238 sprintf( tmp, " IOWr %7d %4d %4d %4d %0d\n", NumIOWrTLPs[i],
239 IOWrBytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
240 IOWrBytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
241 IOWrBytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
242 IOWrBytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
243 GetStr = { GetStr, tmp };
244 sprintf( tmp, " IORd %7d %4d %4d %4d %0d\n", NumIORdTLPs[i],
245 IORdBytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
246 IORdBytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
247 IORdBytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
248 IORdBytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
249 GetStr = { GetStr, tmp };
250 sprintf( tmp, " CfgWr0 %7d %4d %4d %4d %0d\n", NumCfgWr0TLPs[i],
251 CfgWr0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
252 CfgWr0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
253 CfgWr0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
254 CfgWr0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
255 GetStr = { GetStr, tmp };
256 sprintf( tmp, " CfgRd0 %7d %4d %4d %4d %0d\n", NumCfgRd0TLPs[i],
257 CfgRd0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
258 CfgRd0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
259 CfgRd0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
260 CfgRd0Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
261 GetStr = { GetStr, tmp };
262 sprintf( tmp, " CfgWr1 %7d %4d %4d %4d %0d\n", NumCfgWr1TLPs[i],
263 CfgWr1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
264 CfgWr1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
265 CfgWr1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
266 CfgWr1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
267 GetStr = { GetStr, tmp };
268 sprintf( tmp, " CfgRd1 %7d %4d %4d %4d %0d\n", NumCfgRd1TLPs[i],
269 CfgRd1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
270 CfgRd1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
271 CfgRd1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
272 CfgRd1Bytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
273 GetStr = { GetStr, tmp };
274 sprintf( tmp, " Cpl %7d\n", NumCplTLPs[i] );
275 GetStr = { GetStr, tmp };
276 sprintf( tmp, " CplD %7d %4d %4d %4d %0d\n", NumCplDTLPs[i],
277 CplDBytes[i][FNX_PCIE_XTR_STAT_TYPE_MIN],
278 CplDBytes[i][FNX_PCIE_XTR_STAT_TYPE_MAX],
279 CplDBytes[i][FNX_PCIE_XTR_STAT_TYPE_AVG],
280 CplDBytes[i][FNX_PCIE_XTR_STAT_TYPE_TOTAL] );
281 GetStr = { GetStr, tmp };
282 sprintf( tmp, " CplLk %7d\n", NumCplLkTLPs[i] );
283 GetStr = { GetStr, tmp };
284 sprintf( tmp, " CplDLk %7d\n", NumCplDLkTLPs[i] );
285 GetStr = { GetStr, tmp };
286 sprintf( tmp, " Msg %7d\n", NumMsgTLPs[i] );
287 GetStr = { GetStr, tmp };
288 sprintf( tmp, " MsgD %7d", NumMsgDTLPs[i] );
289 GetStr = { GetStr, tmp };
290 }
291
292 // Add DLLP Information
293 for (i=0; i < FNX_PCIE_XTR_NUM_STAT_DIRS; i++) {
294 if (i === FNX_PCIE_XTR_STAT_DIR_XMIT)
295 sprintf( tmp, "\nDLLPs Transmitted\n" );
296 if (i === FNX_PCIE_XTR_STAT_DIR_RCV)
297 sprintf( tmp, "\nDLLPs Received\n" );
298 GetStr = { GetStr, tmp };
299
300 sprintf( tmp, " Type Num\n" );
301 GetStr = { GetStr, tmp };
302 sprintf( tmp, " Total %7d\n", NumDLLPs[i] );
303 GetStr = { GetStr, tmp };
304 sprintf( tmp, " Ack %7d\n", NumAckDLLPs[i] );
305 GetStr = { GetStr, tmp };
306 sprintf( tmp, " Nak %7d\n", NumNakDLLPs[i] );
307 GetStr = { GetStr, tmp };
308 sprintf( tmp, " UpFCP %7d\n", NumUpFCPDLLPs[i] );
309 GetStr = { GetStr, tmp };
310 sprintf( tmp, " UpFCNP %7d\n", NumUpFCNPDLLPs[i] );
311 GetStr = { GetStr, tmp };
312 sprintf( tmp, " UpFCCpl %7d", NumUpFCCplDLLPs[i] );
313 GetStr = { GetStr, tmp };
314 }
315}
316
317task FNXPCIEXactorStatsDatabase::Display( ReportType rptType )
318{
319 string MethodName = "Display";
320
321 PCIEX_QR_Type( rptType, GetStr() );
322}
323
324task FNXPCIEXactorStatsDatabase::UpdatePkt( FNXPCIEXactorPacket pkt,
325 integer statDir )
326{
327 string MethodName = "UpdatePkt";
328
329 if ((statDir !== FNX_PCIE_XTR_STAT_DIR_XMIT) && (statDir !== FNX_PCIE_XTR_STAT_DIR_RCV))
330 PCIEX_QR_ERR( "%s-> Illegal Statistic Direction=%0d Specified.",
331 XactorName, statDir );
332
333 if (pkt.isTlp()) {
334 NumTLPs[statDir]++;
335
336 if (pkt.isTlpIORequest()) {
337 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_IORD) {
338 NumIORdTLPs[statDir]++;
339 IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
340 if (pkt.NumBytes() < IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
341 IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
342 if (IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
343 IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
344 IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = IORdBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumIORdTLPs[statDir];
345 }
346 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_IOWR) {
347 NumIOWrTLPs[statDir]++;
348 IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
349 if (pkt.NumBytes() < IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
350 IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
351 if (IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
352 IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
353 IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = IOWrBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumIOWrTLPs[statDir];
354 }
355 }
356 else {
357 if (pkt.isTlpCfgRequest()) {
358 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CFGRD0) {
359 NumCfgRd0TLPs[statDir]++;
360 CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
361 if (pkt.NumBytes() < CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
362 CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
363 if (CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
364 CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
365 CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = CfgRd0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumCfgRd0TLPs[statDir];
366 }
367 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CFGWR0) {
368 NumCfgWr0TLPs[statDir]++;
369 CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
370 if (pkt.NumBytes() < CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
371 CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
372 if (CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
373 CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
374 CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = CfgWr0Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumCfgWr0TLPs[statDir];
375 }
376 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CFGRD1) {
377 NumCfgRd1TLPs[statDir]++;
378 CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
379 if (pkt.NumBytes() < CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
380 CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
381 if (CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
382 CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
383 CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = CfgRd1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumCfgRd1TLPs[statDir];
384 }
385 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CFGWR1) {
386 NumCfgWr1TLPs[statDir]++;
387 CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
388 if (pkt.NumBytes() < CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
389 CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
390 if (CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
391 CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
392 CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = CfgWr1Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumCfgWr1TLPs[statDir];
393 }
394 }
395 else {
396 if (pkt.isTlpMemRequest32()) {
397 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MRD_32) {
398 NumMRd32TLPs[statDir]++;
399 MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
400 if (pkt.NumBytes() < MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
401 MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
402 if (MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
403 MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
404 MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = MRd32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumMRd32TLPs[statDir];
405 }
406 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MRDLK_32)
407 NumMRdLk32TLPs[statDir]++;
408 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MWR_32) {
409 NumMWr32TLPs[statDir]++;
410 MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
411 if (pkt.NumBytes() < MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
412 MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
413 if (MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
414 MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
415 MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = MWr32Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumMWr32TLPs[statDir];
416 }
417 }
418 else {
419 if (pkt.isTlpMemRequest64()) {
420 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MRD_64) {
421 NumMRd64TLPs[statDir]++;
422 MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
423 if (pkt.NumBytes() < MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
424 MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
425 if (MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
426 MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
427 MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = MRd64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumMRd64TLPs[statDir];
428 }
429 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MRDLK_64)
430 NumMRdLk64TLPs[statDir]++;
431 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_MWR_64) {
432 NumMWr64TLPs[statDir]++;
433 MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
434 if (pkt.NumBytes() < MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
435 MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
436 if (MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
437 MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
438 MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = MWr64Bytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumMWr64TLPs[statDir];
439 }
440 }
441 else {
442 if (pkt.isTlpCompletion()) {
443 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CPL)
444 NumCplTLPs[statDir]++;
445 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CPLD) {
446 NumCplDTLPs[statDir]++;
447 CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] += pkt.NumBytes();
448 if (pkt.NumBytes() < CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN])
449 CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MIN] = pkt.NumBytes();
450 if (CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] < pkt.NumBytes())
451 CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_MAX] = pkt.NumBytes();
452 CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_AVG] = CplDBytes[statDir][FNX_PCIE_XTR_STAT_TYPE_TOTAL] / NumCplDTLPs[statDir];
453 }
454 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CPLLK)
455 NumCplLkTLPs[statDir]++;
456 if (pkt.GetFmtType() === FNX_PCIE_XTR_FMT_TYPE_CPLDLK)
457 NumCplDLkTLPs[statDir]++;
458 }
459 else {
460 if (pkt.isTlpMessage()) {
461 if (pkt.GetFmtType() =?= FNX_PCIE_XTR_FMT_TYPE_MSG)
462 NumMsgTLPs[statDir]++;
463 if (pkt.GetFmtType() =?= FNX_PCIE_XTR_FMT_TYPE_MSGD)
464 NumMsgDTLPs[statDir]++;
465 }
466 }
467 }
468 }
469 }
470 }
471 }
472 if (pkt.isDllp()) {
473 NumDLLPs[statDir]++;
474
475 if (pkt.isDllpAckNak()) {
476
477 if (pkt.DllpType === FNX_PCIE_XTR_DLLP_TYPE_ACK)
478 NumAckDLLPs[statDir]++;
479 if (pkt.DllpType === FNX_PCIE_XTR_DLLP_TYPE_NAK)
480 NumNakDLLPs[statDir]++;
481 }
482 else {
483 if (pkt.isDllpFC()) {
484 if (pkt.DllpType =?= FNX_PCIE_XTR_DLLP_TYPE_UPDATE_FC_P)
485 NumUpFCPDLLPs[statDir]++;
486 if (pkt.DllpType =?= FNX_PCIE_XTR_FC_DLLP_TYPE_UPDATE_FC_NP)
487 NumUpFCNPDLLPs[statDir]++;
488 if (pkt.DllpType =?= FNX_PCIE_XTR_DLLP_TYPE_UPDATE_FC_CPL)
489 NumUpFCCplDLLPs[statDir]++;
490 }
491 }
492 }
493}
Full OpenSPARC design & verification tarball including full HDL.