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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: report_verilog_tasks.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module report_verilog_tasks; | |
36 | ||
37 | //////////////////////////////////////////////////////////////////////////////// | |
38 | // Class variable accessors | |
39 | ||
40 | task report_verilog_set_global_print_threshold; | |
41 | input [31:0] new_print_threshold; | |
42 | input [31:0] locked_by; | |
43 | ||
44 | begin | |
45 | $report_set_global_print_threshold(new_print_threshold, locked_by); | |
46 | end | |
47 | endtask // report_verilog_set_global_print_threshold | |
48 | ||
49 | // report_verilog_get_global_print_threshold: unnecessary -- use ReportClass::get_global_print_threshold() | |
50 | ||
51 | task report_verilog_set_max_error_count; | |
52 | input [31:0] max_error_count; | |
53 | ||
54 | begin | |
55 | $report_set_max_error_count(max_error_count); | |
56 | end | |
57 | endtask // report_verilog_set_max_error_count | |
58 | ||
59 | // report_verilog_get_max_error_count: unnecessary -- use ReportClass::get_max_error_count() | |
60 | ||
61 | task report_verilog_inc_global_error_count; | |
62 | begin | |
63 | $report_inc_global_error_count; | |
64 | end | |
65 | endtask // report_verilog_inc_global_error_count | |
66 | ||
67 | task report_verilog_get_global_error_count; | |
68 | output [31:0] global_error_count; | |
69 | ||
70 | begin | |
71 | global_error_count = $report_get_global_error_count; | |
72 | end | |
73 | endtask // report_verilog_get_global_error_count | |
74 | ||
75 | task report_verilog_inc_global_warning_count; | |
76 | begin | |
77 | $report_inc_global_warning_count; | |
78 | end | |
79 | endtask // report_verilog_inc_global_warning_count | |
80 | ||
81 | task report_verilog_get_global_warning_count; | |
82 | output [31:0] global_warning_count; | |
83 | ||
84 | begin | |
85 | global_warning_count = $report_get_global_warning_count; | |
86 | end | |
87 | endtask // report_verilog_get_global_warning_count | |
88 | ||
89 | task report_verilog_set_short_pathnames; | |
90 | input [31:0] short_names; | |
91 | ||
92 | begin | |
93 | $report_set_short_pathnames(short_names); | |
94 | end | |
95 | endtask // report_verilog_set_short_pathnames | |
96 | ||
97 | // report_verilog_get_short_pathnames: unnecessary -- use ReportClass::get_short_pathnames() | |
98 | ||
99 | task report_verilog_set_path_prefix; | |
100 | input [256*8:0] path_prefix_str; | |
101 | ||
102 | begin | |
103 | $report_set_path_prefix(path_prefix_str); | |
104 | end | |
105 | endtask | |
106 | ||
107 | task report_verilog_set_exit_on_error; | |
108 | input [31:0] exit_on_error; | |
109 | ||
110 | begin | |
111 | $report_set_exit_on_error(exit_on_error); | |
112 | end | |
113 | endtask | |
114 | ||
115 | task report_verilog_get_exit_on_error; | |
116 | output [31:0] exit_on_error; | |
117 | ||
118 | begin | |
119 | exit_on_error = $report_get_exit_on_error; | |
120 | end | |
121 | endtask | |
122 | ||
123 | task report_verilog_disable_fatal_errors; | |
124 | input [31:0] num_nonfatal_cycles; | |
125 | ||
126 | begin | |
127 | $report_disable_fatal_errors(num_nonfatal_cycles); | |
128 | end | |
129 | endtask // report_verilog_disable_fatal_errors | |
130 | ||
131 | // report_verilog_get_num_remaining_nonfatal_cycles: unnecessary -- use ReportClass::get_num_... | |
132 | ||
133 | task report_verilog_set_show_simulation_time; | |
134 | input [31:0] show_sim_time; | |
135 | ||
136 | begin | |
137 | $report_set_show_simulation_time(show_sim_time); | |
138 | end | |
139 | endtask // report_verilog_set_show_simulation_time | |
140 | ||
141 | // report_verilog_get_show_simulation_time: unnecessary -- use ReportClass::get_show_simulation_time | |
142 | ||
143 | ||
144 | //////////////////// | |
145 | ||
146 | task report_verilog_test_complete; | |
147 | input [31:0] cycle; | |
148 | input [31:0] errors; | |
149 | input [31:0] warnings; | |
150 | ||
151 | begin | |
152 | $write("\n================================================================================\nReport:: Cycle at finish: %0d\nReport:: Total errors\t = %0d\nReport:: Total warnings\t = %0d\n", cycle, errors, warnings); | |
153 | $report_print_cycles_per_second; | |
154 | end | |
155 | ||
156 | endtask // report_verilog_test_complete | |
157 | ||
158 | ||
159 | ||
160 | ////////////////////////////////////////////////////////////////// | |
161 | // Set defaults | |
162 | // | |
163 | task report_verilog_set_default_print_level; | |
164 | input [31:0] report_type; | |
165 | input [31:0] print_level; | |
166 | ||
167 | begin | |
168 | $report_set_default_print_level(report_type, print_level); | |
169 | end | |
170 | endtask // report_verilog_set_default_print_level | |
171 | ||
172 | // | |
173 | task report_verilog_set_default_error_level; | |
174 | input [31:0] report_type; | |
175 | input [31:0] error_level; | |
176 | ||
177 | begin | |
178 | $report_set_default_error_level(report_type, error_level); | |
179 | end | |
180 | endtask // report_verilog_set_default_error_level | |
181 | ||
182 | // | |
183 | task report_verilog_set_default_table_mode; | |
184 | input [31:0] report_type; | |
185 | input [31:0] table_mode; | |
186 | ||
187 | begin | |
188 | $report_set_default_table_mode(report_type, table_mode); | |
189 | end | |
190 | endtask // report_verilog_set_default_table_mode | |
191 | ||
192 | ||
193 | //////////////////////////////////////////////////////////////////////////////// | |
194 | // Instance variable accessors | |
195 | ||
196 | task report_verilog_set_print_level; | |
197 | input [(256*8)-1:0] regexp; | |
198 | input [31:0] report_type; | |
199 | input [31:0] print_level; | |
200 | ||
201 | begin | |
202 | $report_set_print_level(regexp, report_type, print_level); | |
203 | end | |
204 | endtask // report_verilog_set_print_level | |
205 | ||
206 | task report_verilog_set_error_level; | |
207 | input [(256*8)-1:0] regexp; | |
208 | input [31:0] report_type; | |
209 | input [31:0] error_level; | |
210 | ||
211 | begin | |
212 | $report_set_error_level(regexp, report_type, error_level); | |
213 | end | |
214 | endtask // report_verilog_set_error_level | |
215 | ||
216 | task report_verilog_set_table_mode; | |
217 | input [(256*8)-1:0] regexp; | |
218 | input [31:0] report_type; | |
219 | input [31:0] table_mode; | |
220 | ||
221 | begin | |
222 | $report_set_table_mode(regexp, report_type, table_mode); | |
223 | end | |
224 | endtask // report_verilog_set_table_mode | |
225 | ||
226 | // | |
227 | task report_verilog_print_cycles_per_second; | |
228 | begin | |
229 | $report_print_cycles_per_second; | |
230 | end | |
231 | endtask //report_print_cycles_per_second | |
232 | ||
233 | endmodule // report_verilog_tasks |