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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ilu_peu_rtl_encrypted.flist | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | ||
36 | +incdir+$DV_ROOT/design/dmu/dmu_l/dmu/rtl | |
37 | +incdir+$DV_ROOT/design/peu/peu_l/peu/rtl | |
38 | +incdir+$DV_ROOT/design/pcie_common/include/rtl | |
39 | +incdir+$DV_ROOT/design/pcie_common/csr/rtl | |
40 | ||
41 | +incdir+$DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/ | |
42 | $DV_ROOT/design/peu/peu_l/peu/rtl/peu.h | |
43 | $DV_ROOT/design/pcie_common/include/rtl/pcie.h | |
44 | $DV_ROOT/design/pcie_common/csr/rtl/pcie_csr_defines.h | |
45 | ||
46 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/pcie_defs.vh | |
47 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_defs.vh | |
48 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_hdr.vh | |
49 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_lib.vh | |
50 | // AT, 12/20/04: Not needed $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/adm_defs.vh | |
51 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/dlpl_user.vh | |
52 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/port_cfg.vh | |
53 | ||
54 | $DV_ROOT/design/plp/plp_l/plp/rtl/plp.vp | |
55 | $DV_ROOT/design/plp/plp_tlg_l/plp_tlg/rtl/plp_tlg.vp | |
56 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm.vp | |
57 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_pl_reg.vp | |
58 | // $DV_ROOT/design/plp/plp_cdm_l/plp_cdm/rtl/cdm_reg_decode.vp | |
59 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_1sx16.vp | |
60 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_1sx16.vp | |
61 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1s.vp | |
62 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_deskew_slv_1sx16.vp | |
63 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_link_1sx16.vp | |
64 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pipe.vp | |
65 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_pkt_finder_1sx16.vp | |
66 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1s.vp | |
67 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_seq_finder_1sx16.vp | |
68 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble.vp | |
69 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/scramble_x16.vp | |
70 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_1sx16.vp | |
71 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_byte_xmt_1sx16.vp | |
72 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_ltssm.vp | |
73 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_pipe.vp | |
74 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_128b.vp | |
75 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_dlp_extract.vp | |
76 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_link_cntrl.vp | |
77 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/rdlh_tlp_extract_128b.vp | |
78 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_128b.vp | |
79 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_control_128b.vp | |
80 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_dllp_gen.vp | |
81 | // Rmvd from Cascade 2.1 Rls: $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_insert_crc.vp | |
82 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_retrybuf_128b.vp | |
83 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlh/rtl/xdlh_tlp_gen_128b.vp | |
84 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_128b.vp | |
85 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc.vp | |
86 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_arb.vp | |
87 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_decode.vp | |
88 | $DV_ROOT/design/plp/plp_dlpl_l/plp_tlh/rtl/rtlh_fc_gen.vp | |
89 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/loopback_1s.vp | |
90 | $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/phy_1s.vp | |
91 | $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/phy_1sx16.vp | |
92 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/pipe2phy_1s.vp | |
93 | // $DV_ROOT/design/plp/plp_phy_l/plp_phy/rtl/pipe_multilane.vp | |
94 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_8b10b_1s.vp | |
95 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_cdet_1s.vp | |
96 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/rphy_elasbuf_1s.vp | |
97 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/sdm_1s.vp | |
98 | $DV_ROOT/design/plp/plp_phy_l/plp_pcs/rtl/xphy_8b10b_1s.vp | |
99 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/serdes_1s.vp | |
100 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/rphy_deser_1s.vp | |
101 | //$DV_ROOT/design/plp/plp_phy_l/plp_sds/rtl/xphy_ser_1s.vp | |
102 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/crc_128b.vp | |
103 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/decode8b10b.vp | |
104 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/delay_n.vp | |
105 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/encode8b10b.vp | |
106 | // $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/sync.vp | |
107 | $DV_ROOT/design/plp/plp_dlpl_l/plp_dlpl/rtl/cx_pl_16A.vp | |
108 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/rmlh_reverse.vp | |
109 | $DV_ROOT/design/plp/plp_dlpl_l/plp_mlh/rtl/xmlh_reverse.vp | |
110 | $DV_ROOT/design/peu/peu_l/peu/rtl/peu.v | |
111 | ||
112 | ||
113 | $DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust_array.v | |
114 | $DV_ROOT/libs/n2sram/async/n2_com_64x132async_dp_cust_l/n2_com_64x132async_dp_cust/rtl/n2_com_64x132async_dp_cust.v | |
115 | $DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust_array.v | |
116 | $DV_ROOT/libs/n2sram/async/n2_com_256x132async_dp_cust_l/n2_com_256x132async_dp_cust/rtl/n2_com_256x132async_dp_cust.v | |
117 | $DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust_array.v | |
118 | $DV_ROOT/libs/n2sram/dp/n2_peu_dp_256x138s_cust_l/n2_peu_dp_256x138s_cust/rtl/n2_peu_dp_256x138s_cust.v | |
119 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_defines.h | |
120 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_defines.h | |
121 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl_entry.v | |
122 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ctl.v | |
123 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts_entry.v | |
124 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_sts.v | |
125 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off_entry.v | |
126 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_trn_off.v | |
127 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici_entry.v | |
128 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_ici.v | |
129 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag_entry.v | |
130 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_diag.v | |
131 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log_entry.v | |
132 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_log.v | |
133 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en_entry.v | |
134 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_int_en.v | |
135 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err_entry.v | |
136 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_oe_err.v | |
137 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1_entry.v | |
138 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr1.v | |
139 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2_entry.v | |
140 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_roe_hdr2.v | |
141 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1_entry.v | |
142 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr1.v | |
143 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2_entry.v | |
144 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_toe_hdr2.v | |
145 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc_entry.v | |
146 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prfc.v | |
147 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0_entry.v | |
148 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf0.v | |
149 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1_entry.v | |
150 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf1.v | |
151 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2_entry.v | |
152 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_prf2.v | |
153 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a_entry.v | |
154 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_a.v | |
155 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b_entry.v | |
156 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tlu_dbg_sel_b.v | |
157 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap_entry.v | |
158 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_cap.v | |
159 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl_entry.v | |
160 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_ctl.v | |
161 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts_entry.v | |
162 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_dev_sts.v | |
163 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap_entry.v | |
164 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_cap.v | |
165 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl_entry.v | |
166 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_ctl.v | |
167 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts_entry.v | |
168 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lnk_sts.v | |
169 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log_entry.v | |
170 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_log.v | |
171 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en_entry.v | |
172 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_int_en.v | |
173 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err_entry.v | |
174 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ue_err.v | |
175 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1_entry.v | |
176 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr1.v | |
177 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2_entry.v | |
178 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_rue_hdr2.v | |
179 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1_entry.v | |
180 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr1.v | |
181 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2_entry.v | |
182 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_tue_hdr2.v | |
183 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log_entry.v | |
184 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_log.v | |
185 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en_entry.v | |
186 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_int_en.v | |
187 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err_entry.v | |
188 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ce_err.v | |
189 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_50.v | |
190 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csrpipe_5.v | |
191 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev_entry.v | |
192 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_peu_dlpl_serdes_rev.v | |
193 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh_entry.v | |
194 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_thresh.v | |
195 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer_entry.v | |
196 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_acknak_timer.v | |
197 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh_entry.v | |
198 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_tim_thresh.v | |
199 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer_entry.v | |
200 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_replay_timer.v | |
201 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg_entry.v | |
202 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_ven_dllp_msg.v | |
203 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm_entry.v | |
204 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_force_ltssm.v | |
205 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg_entry.v | |
206 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_cfg.v | |
207 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl_entry.v | |
208 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_link_ctl.v | |
209 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew_entry.v | |
210 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_lane_skew.v | |
211 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num_entry.v | |
212 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_num.v | |
213 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer_entry.v | |
214 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_symbol_timer.v | |
215 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll_entry.v | |
216 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_pll.v | |
217 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl_entry.v | |
218 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_ctl.v | |
219 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status_entry.v | |
220 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_receiver_lane_status.v | |
221 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl_entry.v | |
222 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_ctl.v | |
223 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status_entry.v | |
224 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_xmitter_lane_status.v | |
225 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg_entry.v | |
226 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_serdes_macro_test_cfg.v | |
227 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status_entry.v | |
228 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_core_status.v | |
229 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en_entry.v | |
230 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_int_en.v | |
231 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en_entry.v | |
232 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_log_en.v | |
233 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr_entry.v | |
234 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr_event_err_sts_clr.v | |
235 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_default_grp.v | |
236 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_stage_mux_only.v | |
237 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_addr_decode.v | |
238 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_csr.v | |
239 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_csr.v | |
240 | $DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.h | |
241 | $DV_ROOT/design/ptl/ptl_l/ptl/rtl/ptl.v | |
242 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb.v | |
243 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr.v | |
244 | // $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_lpr_ahb.v | |
245 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr.v | |
246 | $DV_ROOT/design/ptl/ptl_ctb_l/ptl_ctb/rtl/ptl_ctb_tlr_rio.v | |
247 | $DV_ROOT/design/ptl/ptl_sbs_l/ptl_sbs/rtl/ptl_sbs.v | |
248 | $DV_ROOT/design/ptl/ptl_mb0_l/ptl_mb0/rtl/ptl_mb0.v | |
249 | $DV_ROOT/design/ptl/ptl_edb_l/ptl_edb/rtl/ptl_edb.v | |
250 | $DV_ROOT/design/ptl/ptl_ehb_l/ptl_ehb/rtl/ptl_ehb.v | |
251 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.h | |
252 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl.v | |
253 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hcs.v | |
254 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_hps.v | |
255 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_fcs.v | |
256 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_rcs.v | |
257 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_lcs.v | |
258 | $DV_ROOT/design/ptl/ptl_etl_l/ptl_etl/rtl/ptl_etl_dbg.v | |
259 | $DV_ROOT/design/ptl/ptl_idb_l/ptl_idb/rtl/ptl_idb.v | |
260 | $DV_ROOT/design/ptl/ptl_ihb_l/ptl_ihb/rtl/ptl_ihb.v | |
261 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.h | |
262 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl.v | |
263 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_idc.v | |
264 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ifc.v | |
265 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihc.v | |
266 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ihp.v | |
267 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_ipp.v | |
268 | $DV_ROOT/design/ptl/ptl_itl_l/ptl_itl/rtl/ptl_itl_itc.v | |
269 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc.v | |
270 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_tpm.v | |
271 | $DV_ROOT/design/ptl/ptl_pmc_l/ptl_pmc/rtl/ptl_pmc_lpm.v | |
272 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.h | |
273 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb.v | |
274 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_rar.v | |
275 | $DV_ROOT/design/ptl/ptl_rsb_l/ptl_rsb/rtl/ptl_rsb_ctrl.v | |
276 | ||
277 | // | |
278 | $DV_ROOT/design/psr/psr_l/psr/rtl/psr.v | |
279 | // $DV_ROOT/design/psr/psr_l/psr/rtl/WIZ6C2B8N5D1.v | |
280 | // $DV_ROOT/design/psr/psr_l/psr/rtl/WIZ6C2XXN5X1.vp | |
281 | ||
282 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/wiz6c2b8n5d2t.v | |
283 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/WIZ6C2XXN5X2.vp | |
284 | ||
285 | -v $DV_ROOT/design/psr/psr_l/psr/rtl/NIAGARA2_REFCLK_BOTTOM1.v | |
286 | -v $DV_ROOT/libs/serdes/ljcb/ljcb_l/iclkrx18gat/rtl/iclkrx18gat.v |