Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / soma_fastlink.spc
CommitLineData
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AT
1--
2--======================================================================
3--Copyright 1999-2003 by Denali Software, Inc. All rights reserved.
4--======================================================================
5--
6--This SOMA file describes a memory model, using Denali Software's
7--proprietary SOMA language. By using this SOMA file, you agree to the
8--following terms. If you do not agree to these terms, you may not use
9--this SOMA file.
10--
11--Subject to the restrictions set forth below, Denali Software grants
12--you a non-exclusive, non-transferable license only to use this SOMA
13--file to simulate the memory described in it using tools supplied by
14--Denali Software.
15--
16--You may not:
17--
18-- (1) Use this SOMA file to create software programs or tools that use
19-- SOMA files as either input or output.
20--
21-- (2) Modify this SOMA file or the SOMA language in any manner.
22--
23-- (3) Use this SOMA file to create other languages for describing
24-- memory models.
25--
26-- (4) Distribute this SOMA file to others.
27--
28--This SOMA file is based on information received by Denali Software
29--from third parties. DENALI SOFTWARE PROVIDES THIS SOMA FILE "AS IS"
30--AND EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES AND
31--CONDITIONS, INCLUDING BUT NOT LIMITED TO WARRANTIES AND CONDITIONS OF
32--MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND
33--NONINFRINGEMENT. DENALI SOFTWARE'S AGGREGATE LIABILITY ARISING FROM
34--YOUR USE OF THIS SOMA FILE IS LIMITED TO ONE U.S. DOLLAR.
35--
36--If you have any questions or if you would like to inquire about
37--obtaining additional or different rights in SOMA files or the SOMA
38--language, please contact Denali Software, at www.denali.com or at
39--info@denalisoft.com.
40--
41--Written on 03 Apr 2003
42--PureView version: 3.100 $DENALI: /home/scratch/guoqing/work/main/platform/SunOS/denali
43Version 0.001
44pcie
45
46Sizes
47SpecVersion "1.0A2"
48linkWidths "1 2 4 8"
49numDownPort 1
50numRCRB 0
51BusNumber 0
52portNumber 0
53numFunc 1
54FuncNumber 0
55RCRBid 0
56configID 0
57portRCRBid 0
58VendorID 0
59DeviceID 0
60RevisionID 0
61BaseClass 0
62SubClass 0
63InterfaceClass 0
64InterruptNum 1
65ROMsize 0
66SubSysID 0
67SubVendorID 0
68Breg0Width 64
69Breg0Size 36
70Breg0RdMin 0
71Breg0RdMax 0
72Breg1Width 32
73Breg1Size 10
74Breg1RdMin 0
75Breg1RdMax 0
76Breg2Width 32
77Breg2Size 10
78Breg2RdMin 0
79Breg2RdMax 0
80Breg3Width 32
81Breg3Size 10
82Breg3RdMin 0
83Breg3RdMax 0
84Breg4Width 32
85Breg4Size 10
86Breg4RdMin 0
87Breg4RdMax 0
88Breg5Width 32
89Breg5Size 10
90Breg5RdMin 0
91Breg5RdMax 0
92BrPrimBus 0
93BrSecBus 0
94BrSubBus 0
95brBreg0Width 32
96brBreg0Size 10
97brBreg0RdMin 0
98brBreg0RdMax 0
99brBreg1Width 32
100brBreg1Size 10
101brBreg1RdMin 0
102brBreg1RdMax 0
103PMSCsel 0
104PMSCsca 0
105PMSCdata 0
106PMCaux 0
107MSInumMsg 1
108PCIEdevMaxPL 4096
109PCIEdevPF 3
110PCIEdevTag 8
111PCIEdevPowLimit 0
112PCIEdcMaxPL 512
113PCIEdcMaxRead 4096
114PCIElkPort 0
115PCIElcRCB 64
116PCIEslNum 0
117PCIEslPowLimit 0
118PCIEXvc1Evc 0
119PCIEXvc1LEvc 0
120PCIEXvc1Arb 0
121PCIEXvcARsel 0
122PCIEXvcARtab "0"
123PCIEXvcR0FCPH 115
124PCIEXvcR0FCPD 2047
125PCIEXvcR0FCNPH 115
126PCIEXvcR0FCNPD 2047
127PCIEXvcR0FCCPLH 0
128PCIEXvcR0FCCPLD 0
129PCIEXvcR0time 0
130PCIEXvcR0map 255
131PCIEXvcR0sel 0
132PCIEXvcR0tab "0"
133PCIEXvcR1FCPH 1
134PCIEXvcR1FCPD 257
135PCIEXvcR1FCNPH 1
136PCIEXvcR1FCNPD 1
137PCIEXvcR1FCCPLH 0
138PCIEXvcR1FCCPLD 0
139PCIEXvcR1time 0
140PCIEXvcR1map 0
141PCIEXvcR1sel 0
142PCIEXvcR1vcID 1
143PCIEXvcR1tab "0"
144PCIEXds1 0
145PCIEXds2 0
146PCIEXpbDVal 0
147PCIEXpbDsubState 0
148PCIEXpbDstate 0
149CntPollingActiveTS1 16
150CntPollingConfigTS1 16
151linkNum "0"
152numFTS 2
153invertPolarity "0"
154DLretBuf 4096
155TLplSize 40960
156TLtrSize 32
157TLCplQSize 64
158vendorIDS ""
159PCIEXvcR2FCPH 1
160PCIEXvcR2FCPD 257
161PCIEXvcR2FCNPH 1
162PCIEXvcR2FCNPD 1
163PCIEXvcR2FCCPLH 0
164PCIEXvcR2FCCPLD 0
165PCIEXvcR2time 0
166PCIEXvcR2map 0
167PCIEXvcR2sel 0
168PCIEXvcR2vcID 1
169PCIEXvcR2tab "0"
170PCIEXvcR3FCPH 1
171PCIEXvcR3FCPD 257
172PCIEXvcR3FCNPH 1
173PCIEXvcR3FCNPD 1
174PCIEXvcR3FCCPLH 0
175PCIEXvcR3FCCPLD 0
176PCIEXvcR3time 0
177PCIEXvcR3map 0
178PCIEXvcR3sel 0
179PCIEXvcR3vcID 1
180PCIEXvcR3tab "0"
181PCIEXvcR4FCPH 1
182PCIEXvcR4FCPD 257
183PCIEXvcR4FCNPH 1
184PCIEXvcR4FCNPD 1
185PCIEXvcR4FCCPLH 0
186PCIEXvcR4FCCPLD 0
187PCIEXvcR4time 0
188PCIEXvcR4map 0
189PCIEXvcR4sel 0
190PCIEXvcR4vcID 1
191PCIEXvcR4tab "0"
192PCIEXvcR5FCPH 1
193PCIEXvcR5FCPD 257
194PCIEXvcR5FCNPH 1
195PCIEXvcR5FCNPD 1
196PCIEXvcR5FCCPLH 0
197PCIEXvcR5FCCPLD 0
198PCIEXvcR5time 0
199PCIEXvcR5map 0
200PCIEXvcR5sel 0
201PCIEXvcR5vcID 1
202PCIEXvcR5tab "0"
203PCIEXvcR6FCPH 1
204PCIEXvcR6FCPD 257
205PCIEXvcR6FCNPH 1
206PCIEXvcR6FCNPD 1
207PCIEXvcR6FCCPLH 0
208PCIEXvcR6FCCPLD 0
209PCIEXvcR6time 0
210PCIEXvcR6map 0
211PCIEXvcR6sel 0
212PCIEXvcR6vcID 1
213PCIEXvcR6tab "0"
214PCIEXvcR7FCPH 1
215PCIEXvcR7FCPD 257
216PCIEXvcR7FCNPH 1
217PCIEXvcR7FCNPD 1
218PCIEXvcR7FCCPLH 0
219PCIEXvcR7FCCPLD 0
220PCIEXvcR7time 0
221PCIEXvcR7map 0
222PCIEXvcR7sel 0
223PCIEXvcR7vcID 1
224PCIEXvcR7tab "0"
225laneRXstatus " 0 1"
226txLaneSKEW "0"
227numSKIP 1
228laneTxDisable " 0"
229laneRxDisable " 0"
230redundantInitFc1Dllps 2
231redundantInitFc2Dllps 2
232DevNumber 0
233CardBus 0
234portCount 1
235CacheLsize 0
236InterruptLine 0
237capPtr 0
238Cardbus 0
239ROMsize0 0
240BrSLTval 0
241ROMsize1 0
242PMCaddr 0
243capPMPtr 0
244MSIaddr 0
245capMSIPtr 0
246AGPaddr 0
247capAGPPtr 0
248AGPsize 3
249VPDaddr 0
250capVPDPtr 0
251VPDsize 2
252SLOTaddr 0
253capSLOTPtr 0
254SLOTsize 1
255HSaddr 0
256capHSPtr 0
257HSsize 1
258PCIXaddr 0
259capPCIXPtr 0
260PCIXsize 1
261AMDaddr 0
262capAMDPtr 0
263AMDsize 1
264VSaddr 0
265capVSPtr 0
266VSsize 4
267DPaddr 0
268capDPPtr 0
269DPsize 1
270CRCaddr 0
271capCRCPtr 0
272CRCsize 1
273HPaddr 0
274capHPPtr 0
275HPsize 1
276PCIEaddr 0
277capPEPtr 0
278PCIEAEaddr 0
279capAEPtr 0
280PCIEVCaddr 0
281capVCPtr 0
282PCIEXvcARloc 0
283PCIEDSaddr 0
284capDSPtr 0
285PCIEPBaddr 0
286capPBPtr 0
287numSymbolErrors 4
288skipIntervalMax 1538
289skipIntervalMin 1180
290beaconSymbol "K28.5+"
291DlTxQueueDelay 2
292DlRxQueueDelay 0
293capSLOTcnt 0
294capSSIDaddr 0
295capSSIDPtr 0
296capSSIDvid 0
297capSSIDsid 0
298
299Features
300ModelMode 1
301DeviceMode 1
302MonitorMode 0
303Layer 1
304modelTLP 1
305modelLLP 1
306modelPLP 1
307intLayer 1
308intLbit 1
309intLsymbol 0
310intLbyte 0
311intLpipe 0
312intLpacket 0
313DeviceType 1
314RC 0
315Switch 0
316Bridge 0
317PCIEtoPCI 0
318PCItoPCIE 0
319Endpoint 1
320Express 1
321Legacy 0
322Port 1
323genSoma 1
324genRCRB 0
325genConfig0 1
326genConfig1 0
327upstream 1
328hasRCRB 0
329ConfigSpace 1
330CommonConfig 1
331ClassCode 0
332BIST 0
333Command 1
334IOspace 1
335MEMspace 1
336EnBusMaster 0
337EnParityError 0
338EnSERR 0
339DisINT 0
340ROMbase 0
341ROMen 0
342config0 1
343baseReg0 1
344Breg0IO 0
345Breg0Pref 0
346baseReg1 1
347Breg1IO 0
348Breg1Pref 0
349baseReg2 0
350Breg2IO 0
351Breg2Pref 0
352baseReg3 0
353Breg3IO 0
354Breg3Pref 0
355baseReg4 0
356Breg4IO 0
357Breg4Pref 0
358baseReg5 0
359Breg5IO 0
360Breg5Pref 0
361config1 1
362brBaseReg0 0
363brBreg0IO 0
364brBreg0Pref 0
365brBaseReg1 0
366brBreg1IO 0
367brBreg1Pref 0
368BrIOrange 0
369BrIO16 0
370BrIO32 0
371BrPreMemRange 0
372BrPreMem32 0
373BrPreMem64 0
374BridgeCtrl 0
375BrPerrRes 0
376BrSERR 0
377PMCap 1
378PMdata 0
379PMCd1 0
380PMCd2 0
381PMCd3cold 0
382PMCd3hot 0
383PMCdsi 0
384MSI 0
385MSI64en 0
386PCIECap 1
387PCIEslot 0
388PCIEdev 1
389PCIEdevL0 0
390PCIEdevL00 1
391PCIEdevL01 0
392PCIEdevL02 0
393PCIEdevL03 0
394PCIEdevL04 0
395PCIEdevL05 0
396PCIEdevL06 0
397PCIEdevL07 0
398PCIEdevL1 0
399PCIEdevL10 1
400PCIEdevL11 0
401PCIEdevL12 0
402PCIEdevL13 0
403PCIEdevL14 0
404PCIEdevL15 0
405PCIEdevL16 0
406PCIEdevL17 0
407PCIEdevAttB 0
408PCIEdevAttI 0
409PCIEdevPowI 0
410PCIEdevPowScale 0
411PCIEdevPowScale0 1
412PCIEdevPowScale1 0
413PCIEdevPowScale2 0
414PCIEdevPowScale3 0
415PCIEdc 0
416PCIEdcCorErr 0
417PCIEdcNonFatalErr 0
418PCIEdcFatalErr 0
419PCIEdcUR 0
420PCIEdcRelOrder 0
421PCIEdcEtag 1
422PCIEdcPF 1
423PCIEdcAux 0
424PCIEdcNoSnoop 1
425PCIElk 0
426PCIElkL0 1
427PCIElkL00 1
428PCIElkL01 0
429PCIElkL02 0
430PCIElkL03 0
431PCIElkL04 0
432PCIElkL05 0
433PCIElkL06 0
434PCIElkL1support 1
435PCIElkL1 0
436PCIElkL10 0
437PCIElkL11 0
438PCIElkL12 0
439PCIElkL13 0
440PCIElkL14 0
441PCIElkL15 0
442PCIElkL16 0
443PCIElkL17 0
444PCIElc 0
445PCIElcL1 0
446PCIElcLkDis 0
447PCIElcExtSyn 0
448PCIEls 1
449PCIElsSlot 1
450PCIEsl 0
451PCIEslAttB 0
452PCIEslPow 0
453PCIEslMRL 0
454PCIEslAttI 0
455PCIEslPowI 0
456PCIEslHPS 0
457PCIEslHPen 0
458PCIEslPowScale 0
459PCIEslPowScale0 1
460PCIEslPowScale1 0
461PCIEslPowScale2 0
462PCIEslPowScale3 0
463PCIEsc 0
464PCIEscAttB 0
465PCIEscPowF 0
466PCIEscMRL 0
467PCIEscPres 0
468PCIEscCom 0
469PCIEscHPI 0
470PCIErc 0
471PCIErcCorErr 0
472PCIErcNonFatalErr 0
473PCIErcFatalErr 0
474PCIErcPME 0
475PCIEX 1
476PCIEXae 1
477PCIEXaeUM 0
478PCIEXaeUMtrain 0
479PCIEXaeUMdll 1
480PCIEXaeUMpoison 1
481PCIEXaeUMfc 0
482PCIEXaeUMcplTO 0
483PCIEXaeUMcplAB 0
484PCIEXaeUMun 0
485PCIEXaeUMofl 1
486PCIEXaeUMmal 1
487PCIEXaeUMecrc 0
488PCIEXaeUMus 0
489PCIEXaeUV 0
490PCIEXaeUVtrain 1
491PCIEXaeUVdll 1
492PCIEXaeUVpoison 0
493PCIEXaeUVfc 0
494PCIEXaeUVcplTO 0
495PCIEXaeUVcplAB 0
496PCIEXaeUVun 0
497PCIEXaeUVofl 1
498PCIEXaeUVmal 1
499PCIEXaeUVecrc 0
500PCIEXaeUVus 0
501PCIEXaeCM 0
502PCIEXaeCMrec 0
503PCIEXaeCMtlp 0
504PCIEXaeCMDLLP 0
505PCIEXaeCMrepN 0
506PCIEXaeCMrepT 0
507PCIEXaeCT 0
508PCIEXaeCTgenEn 0
509PCIEXaeCTgenCap 0
510PCIEXaeCTchkEn 0
511PCIEXaeCTchkCap 0
512PCIEXaeRC 0
513PCIEXaeRCcor 0
514PCIEXaeRCnonFatal 0
515PCIEXaeRCfatal 0
516PCIEXvc 1
517PCIEXvc1 0
518PCIEXvc2 0
519PCIEXvc2arb1 0
520PCIEXvc2arb2 0
521PCIEXvc2arb4 0
522PCIEXvc2arb8 0
523PCIEXvcR0 1
524PCIEXvcR0FC 1
525PCIEXvcR0Ca 0
526PCIEXvcR0Arb 0
527PCIEXvcR0Arb0 1
528PCIEXvcR0Arb1 0
529PCIEXvcR0Arb2 0
530PCIEXvcR0Arb3 0
531PCIEXvcR0Arb4 0
532PCIEXvcR0Arb5 0
533PCIEXvcR0APS 0
534PCIEXvcR0snoop 0
535PCIEXvcR0CT 1
536PCIEXvcR1 1
537PCIEXvcR1FC 1
538PCIEXvcR1Ca 0
539PCIEXvcR1Arb 0
540PCIEXvcR1Arb0 1
541PCIEXvcR1Arb1 0
542PCIEXvcR1Arb2 0
543PCIEXvcR1Arb3 0
544PCIEXvcR1Arb4 0
545PCIEXvcR1Arb5 0
546PCIEXvcR1APS 0
547PCIEXvcR1snoop 0
548PCIEXvcR1CT 0
549PCIEXds 0
550PCIEXpb 0
551PCIEXpbD 0
552PCIEXpbDsca 1
553PCIEXpbDsca0 1
554PCIEXpbDsca1 0
555PCIEXpbDsca2 0
556PCIEXpbDsca3 0
557PCIEXpbDtype 1
558PCIEXpbDtype0 1
559PCIEXpbDtype1 0
560PCIEXpbDtype2 0
561PCIEXpbDtype3 0
562PCIEXpbDtype7 0
563PCIEXpbDrail 1
564PCIEXpbDrail0 1
565PCIEXpbDrail1 0
566PCIEXpbDrail2 0
567PCIEXpbDrail7 0
568PCIEXpbC 0
569PCIEXpbCsys 0
570prot 1
571PL 1
572supportLaneReversal 1
573reverseLanes 0
574elecIdleValue 1
575elecIdleValue0 0
576elecIdleValue1 1
577elecIdleValueZ 0
578usePosSKP 0
579DLL 0
580TL 1
581application 0
582Sideband 1
583sbWake 0
584sbReset 1
585PCIEXvcR2 1
586PCIEXvcR2FC 1
587PCIEXvcR2Ca 0
588PCIEXvcR2Arb 0
589PCIEXvcR2Arb0 1
590PCIEXvcR2Arb1 0
591PCIEXvcR2Arb2 0
592PCIEXvcR2Arb3 0
593PCIEXvcR2Arb4 0
594PCIEXvcR2Arb5 0
595PCIEXvcR2APS 0
596PCIEXvcR2snoop 0
597PCIEXvcR2CT 0
598PCIEXvcR3 1
599PCIEXvcR3FC 1
600PCIEXvcR3Ca 0
601PCIEXvcR3Arb 0
602PCIEXvcR3Arb0 1
603PCIEXvcR3Arb1 0
604PCIEXvcR3Arb2 0
605PCIEXvcR3Arb3 0
606PCIEXvcR3Arb4 0
607PCIEXvcR3Arb5 0
608PCIEXvcR3APS 0
609PCIEXvcR3snoop 0
610PCIEXvcR3CT 0
611PCIEXvcR4 1
612PCIEXvcR4FC 1
613PCIEXvcR4Ca 0
614PCIEXvcR4Arb 0
615PCIEXvcR4Arb0 1
616PCIEXvcR4Arb1 0
617PCIEXvcR4Arb2 0
618PCIEXvcR4Arb3 0
619PCIEXvcR4Arb4 0
620PCIEXvcR4Arb5 0
621PCIEXvcR4APS 0
622PCIEXvcR4snoop 0
623PCIEXvcR4CT 0
624PCIEXvcR5 1
625PCIEXvcR5FC 1
626PCIEXvcR5Ca 0
627PCIEXvcR5Arb 0
628PCIEXvcR5Arb0 1
629PCIEXvcR5Arb1 0
630PCIEXvcR5Arb2 0
631PCIEXvcR5Arb3 0
632PCIEXvcR5Arb4 0
633PCIEXvcR5Arb5 0
634PCIEXvcR5APS 0
635PCIEXvcR5snoop 0
636PCIEXvcR5CT 0
637PCIEXvcR6 1
638PCIEXvcR6FC 1
639PCIEXvcR6Ca 0
640PCIEXvcR6Arb 0
641PCIEXvcR6Arb0 1
642PCIEXvcR6Arb1 0
643PCIEXvcR6Arb2 0
644PCIEXvcR6Arb3 0
645PCIEXvcR6Arb4 0
646PCIEXvcR6Arb5 0
647PCIEXvcR6APS 0
648PCIEXvcR6snoop 0
649PCIEXvcR6CT 0
650PCIEXvcR7 1
651PCIEXvcR7FC 1
652PCIEXvcR7Ca 0
653PCIEXvcR7Arb 0
654PCIEXvcR7Arb0 1
655PCIEXvcR7Arb1 0
656PCIEXvcR7Arb2 0
657PCIEXvcR7Arb3 0
658PCIEXvcR7Arb4 0
659PCIEXvcR7Arb5 0
660PCIEXvcR7APS 0
661PCIEXvcR7snoop 0
662PCIEXvcR7CT 0
663pipeDevice 0
664pipeMacro 0
665pipe8bit 1
666pipe16bit 0
667RCRB 0
668BARspec 1
669ROMbase0 0
670BrSecLat 1
671BrSLTBurst2 1
672BrSLT8 0
673BrSLThardW 0
674BrSecSt 0
675BrSecSt66 0
676BrSecStB2B 0
677BrSecStDev 0
678BrSecStDev0 1
679BrSecStDev1 0
680BrSecStDev2 0
681ROMbase1 0
682BrISA 0
683BrVGA 0
684BrVGA16 0
685BrMasterAbort 0
686BrFastB2B 0
687BrSecDCTimer 0
688BrTimerSerrEn 0
689PMEsupport 0
690PMEd0 1
691PMEd1 1
692PMEd2 1
693MSIen 0
694AGP 0
695VPD 0
696SLOT 0
697HS 0
698PCIX 0
699AMD 0
700VS 0
701DP 0
702CRC 0
703HotPlug 0
704PCIElcAspmDis 1
705PCIEXae2UM 0
706PCIEXae2UMta 0
707PCIEXae2UMma 0
708PCIEXae2UMrta 0
709PCIEXae2UMrma 1
710PCIEXae2UMue 1
711PCIEXae2UMucMsg 0
712PCIEXae2UMucData 1
713PCIEXae2UMucAttr 1
714PCIEXae2UMucAddr 1
715PCIEXae2UMdelay 1
716PCIEXae2UMperr 0
717PCIEXae2UMserr 1
718PCIEXae2UMint 0
719PCIEXae2US 0
720PCIEXae2USta 0
721PCIEXae2USma 0
722PCIEXae2USrta 0
723PCIEXae2USrma 0
724PCIEXae2USue 0
725PCIEXae2USucMsg 1
726PCIEXae2USucData 0
727PCIEXae2USucAttr 1
728PCIEXae2USucAddr 1
729PCIEXae2USdelay 0
730PCIEXae2USperr 0
731PCIEXae2USserr 1
732PCIEXae2USint 0
733reverseLaneNumbers 0
734skipInterval 0
735mergeErrMsgs 0
736disVDMsg0 0
737disVDMsg1 0
738disPoisonTX 0
739AS_EP 0
740capSLOT1st 0
741SSID 0
742
743Pins
744TX TX 8
745TX_ TX_ 8
746RX RX 8
747RX_ RX_ 8
748CLK_TX CLK_TX 1
749CLK_RX CLK_RX 1
750TxData TxData 8
751TxDataK TxDataK 1
752RxData RxData 8
753RxDataK RxDataK 1
754PCLK PCLK 1
755WAKE_ WAKE_ 1
756PERST_ PERST_ 1
757TxDetectRx TxDetectRx 1
758TxElecIdle TxElecIdle 1
759TxCompliance TxCompliance 1
760RxPolarity RxPolarity 1
761Reset_ Reset_ 1
762PowerDown PowerDown 2
763RxValid RxValid 1
764PhyStatus PhyStatus 1
765RxElecIdle RxElecIdle 1
766RxStatus RxStatus 3
767
768Timing
769ttoPollSpeed 400.12 ps
770ttoCfgLnWaitUp 2 ms
771ttoCfgLnWaitDn 2 ms
772ttoPollConfig 48 ms
773ttoPollActive 2 us
774ttoDetectQuiet 400 ns
775ttoDetectActive 200 ns
776ttoCfgLkStartDn 24 ms
777ttoCfgLkStartUp 24 ms
778ttoCfgCompDn 2 ms
779ttoCfgCompUp 24 ms
780ttoCfgLkAcceptDn 2 ms
781ttoCfgLkAcceptUp 2 ms
782ttoCfgIdle 2 ms
783ttoRcvrCfg 48 ms
784ttoRcvrLock 24 ms
785ttoRcvrIdle 2 ms
786ttoDisabled 2 ms
787ttoHotReset 2 ms
788ttoLoopback 2 ms
789ttoTLCpl 1000 ns
790ttxUImin 399.88 ps
791ttxUImax 400.12 ps
792ttxIDLEmin 50 clk
793ttxSetToIDLEmax 20 clk
794ttxLaneSKEWmax 1300 ps
795ttxCxLKmin 0 ms
796ttxCxLKmax 1 ms
797trxUImin 399.88 ps
798trxUImax 400.12 ps
799trxSetToDetectmax 10 ms
800trxTotalSKEWmax 20 ns
801ttoFcInitRollover disabled
802ttxIdleToDiff disabled