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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / N2fc / N2fcInitStrategy.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: N2fcInitStrategy.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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34// ========== Copyright Header End ============================================
35#include <vera_defines.vrh>
36
37// model some of the NCU/PIU CSRs
38extern N2fcPiuShadowRegs PiuCsrs;
39
40class N2fcInitStrategy extends ilupeuStrategyBase {
41
42 //PCIEXtr transaction used for initializing Denali Xactor
43 FNXPCIEXactorTransaction regTrans;
44 denali_root_monitor_PCIEXactorTransaction denali_root_monitor_regTrans;
45
46
47 bit[ ILUPEU_CSR_WIDTH-1:0 ] csrRegTmpData, csrRegTmpData1;
48 bit[ FNX_PCIE_XTR_REG_DEN_WIDTH-1:0 ] tempDenaliData;
49 bit[15:0] tempDenaliPeuData; // storing Denali PCI Express type registers data
50 // local static bit dmuXtrEnabled = 0;
51 bit Retrain = 0;
52
53
54 task new( ReportClass _Report,
55 CSRCollection _CSR,
56 ilupeuPodClass _Pod,
57 // denali_root_monitor_PodClass _denali_root_monitor_Pod,
58 ilupeuScenario _Scenario );
59
60 task Execute();
61 task SetFastLinkTraining();
62 task DenaliGotoRecovery();
63 task DisableDenaliErrs();
64 task RetrainInit();
65 task Change_soma_parameters(string _str1 ); // task to change denali soma timing etc. parameter
66
67 task SetDenaliInitFlowControl();
68}
69
70
71
72task N2fcInitStrategy::new( ReportClass _Report,
73 CSRCollection _CSR,
74 ilupeuPodClass _Pod,
75 ilupeuScenario _Scenario ){
76 super.new( _Report,
77 _CSR,
78 _Pod,
79 _Scenario );
80}
81
82task N2fcInitStrategy::RetrainInit(){
83 bit Retrain = 1;
84}
85
86
87
88// task to change denali soma timing parameter
89task N2fcInitStrategy::Change_soma_parameters(string _str1) {
90 integer Err;
91 string str1;
92 // str1 = "mmsomaset tb_top.pcie_root_monitor ttoTLCpl 1 us ";
93 str1 = _str1;
94 Err = DenaliDDVTclEval(str1);
95 // bad status when = 1
96 if (Err == 1) {
97 printf("AC: Error: changing soma parameter: %s at time %d \n", str1, get_time(LO));
98 }
99 else {
100 printf("AC: changing soma parameter: %s at time %d \n", str1, get_time(LO));
101 }
102}
103
104task N2fcInitStrategy::Execute(){
105
106 integer reset_duration;
107 bit [3:0] calculatedWidth;
108
109 // integer change_soma_status = 0;
110 string soma_completion_timeout_string = "";
111 string soma_turnoff_scramble_string = "";
112
113 // use in replay timer value
114 integer rx_L0s_adj ;
115
116 // denali link width
117 bit [FNX_PCIE_XTR_REG_DEN_EXP_LINK_CAP_MAX_LINK_WIDTH_WIDTH-1:0] denaliLinkCapMaxLinkWdth;
118
119 printf("AC: inside initstrategy execute , before doing soma changes \n");
120 //=============== change soma parameters
121 //changing soma completion timeout ttoTLCpl timing value
122 // change_soma_status = $mmsomaset ("tb_top.pcie_root_monitor","ttoTLCpl", "1","us");
123
124 soma_completion_timeout_string = "mmsomaset tb_top.pcie_root_monitor ttoTLCpl 30 us ";
125
126// Change_soma_parameters(soma_completion_timeout_string);
127
128 // example for turn off scrambler
129 // soma_turnoff_scramble_string = "mmsetvar PciePhyScrambleData 0";
130 // Change_soma_parameters(soma_turnoff_scramble_string);
131
132
133 // get command line link width parameter
134 if (get_plus_arg(CHECK, "denali_link_width=")) {
135 denaliLinkCapMaxLinkWdth = get_plus_arg(NUM, "denali_link_width=");
136 Scenario.denaliLinkCapMaxLinkWdth = denaliLinkCapMaxLinkWdth;
137 printf("AC: denali_link_width command plus arg detected, Scenario.denaliLinkCapMaxLinkWdth = %d\n", Scenario.denaliLinkCapMaxLinkWdth);
138 }
139 else {
140 printf("AC: denali_link_width command plus arg is not set, Scenario.denaliLinkCapMaxLinkWdth = %d\n", Scenario.denaliLinkCapMaxLinkWdth);
141 }
142
143 // before first regTrans inside initstrategy \n");
144
145 //Create the Transaction used for Denali register access
146 regTrans = new( Pod.FNXPCIEBldr );
147 // denali_root_monitor_regTrans = new( denali_root_monitor.Pod.denali_root_monitor_PCIEBldr );
148 denali_root_monitor_regTrans = new( Pod.denali_root_monitor_PCIEBldr );
149
150 ////////////////////////////
151 // Disable RC Error messages
152 printf("Suppressing Denali Errors\n");
153 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_PL_NONFATAL_TTX_IDLE_SET_TO_IDLE );
154 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_PL_NONFATAL_LTSSM_POLL_ACTIVE_TO1_EARLY );
155 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE_1 );
156 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE0_1 );
157 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE_2 );
158 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_1 );
159 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP0_1 );
160 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_PH );
161 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_PD );
162 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_NPH );
163 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_NPD );
164 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_CPLH );
165 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_CPLD );
166
167 case( Scenario.denaliLinkCapMaxLinkWdth ){
168 8: regTrans.SetRcvDetLanes( 8'hff );
169 4: regTrans.SetRcvDetLanes( 8'h0f );
170 2: regTrans.SetRcvDetLanes( 8'h03 );
171 1: regTrans.SetRcvDetLanes( 8'h01 );
172 default: regTrans.SetRcvDetLanes( 8'hff );
173 }
174
175 //If this is a retraining then let the test control resets
176 if( !Retrain ){
177 // 11/9/04
178 repeat(400) @(posedge CLOCK);
179 }
180
181 //Make sure Denali is out of reset
182 regTrans.SetDenaliReset( 1'b0 );
183
184 //If Fast Sim is not set then change the Denali Timeout values to match the
185 // PCIE spec for endpoint and monitor
186 if( Scenario.FastLinkTraining == 0 ){
187 //Change the timeout parameters in Denali using somaset
188 Change_soma_parameters("mmsomaset tb_top.pcieA ttoPollActive 24 ms");
189 Change_soma_parameters("mmsomaset tb_top.pcieA ttoDetectQuiet 12 us");
190 Change_soma_parameters("mmsomaset tb_top.pcieA ttoDetectActive 12 ms");
191 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_PACT, 1024 );
192
193 Change_soma_parameters("mmsomaset tb_top.pcie_root_monitor ttoPollActive 24 ms");
194 Change_soma_parameters("mmsomaset tb_top.pcie_root_monitor ttoDetectQuiet 12 ms");
195 Change_soma_parameters("mmsomaset tb_top.pcie_root_monitor ttoDetectActive 12 ms");
196 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_PACT, 1024 );
197
198 }
199
200
201 //Used to disable Denali TX lanes
202 // regTrans.WriteDenaliReg( PCIE_REG_DEN_LN_TX_DISABLE, 32'hffffff00 );
203
204 //Set which Denali TX lanes will get Inverted Polarity
205 regTrans.WriteDenaliReg( PCIE_REG_DEN_LN_INVERSION, Scenario.denaliLanePolarityInvert );
206
207 //Set Denali to reverse the lanes
208 if( Scenario.denaliLaneReverse ){
209 regTrans.WriteDenaliReg( PCIE_REG_DEN_LN_REVERSAL, 32'h3 );
210 }
211
212 //Need to write to Allowed Link Widths register as just writing to Denali Link Capability might not work
213 if( Scenario.denaliLinkCapMaxLinkWdth < 8 ){
214 case( Scenario.denaliLinkCapMaxLinkWdth ){
215 4 : tempDenaliData = 32'hb; //x4,x2,x1
216 2 : tempDenaliData = 32'h3; //x2,x1
217 1 : tempDenaliData = 32'h1; //x1
218 default: tempDenaliData = 32'h8b; //x8,x4,x2,x1
219 }
220
221 regTrans.WriteDenaliReg( PCIE_REG_DEN_ALLOWED_WIDTHS, tempDenaliData );
222 }
223
224 //Set Denali to reverse the lanes
225 if( Scenario.denaliLaneReverse ){
226 regTrans.WriteDenaliReg( PCIE_REG_DEN_LN_REVERSAL, 32'h3 );
227 }
228
229 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_DEN_TLQ_CTRL_ST );
230 tempDenaliData[10:9] = PCIE_RXCPLQ_TimeOut_enable;
231 regTrans.WriteDenaliReg( PCIE_REG_DEN_TLQ_CTRL_ST, tempDenaliData );
232
233 //Determine the right link width
234 if( Scenario.ilupeuLinkCapMaxLinkWdth >= Scenario.denaliLinkCapMaxLinkWdth ){
235 calculatedWidth = Scenario.denaliLinkCapMaxLinkWdth;
236 }
237 else{
238 calculatedWidth = Scenario.ilupeuLinkCapMaxLinkWdth;
239 }
240
241
242 SetDenaliInitFlowControl();
243
244 //Set the Denali Link Capability bits
245 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_EXP_LINK_CAP );
246 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_EXP_LINK_CAP_MAX_LINK_WIDTH_SLC ] = Scenario.denaliLinkCapMaxLinkWdth;
247 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_EXP_LINK_CAP_PORT_NUM_SLC ] = Scenario.denaliLinkCapPortNumber;
248 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_EXP_LINK_CAP_ASPM_SUPPORT_SLC ] = Scenario.denaliLinkCapASPM;
249
250 regTrans.WriteDenaliReg( PCIE_REG_EXP_LINK_CAP, tempDenaliData );
251
252 //Set the Denali Link Control
253 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_DEN_LINK_CTRL );
254 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_LINK_CTRL_TS_DISABLE_SCRAMBLING_SLC ] = Scenario.denaliLtssmDisableScrambling;
255 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_LINK_CTRL_TS_HOT_RST_SLC ] = Scenario.denaliLtssmHotReset;
256 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_LINK_CTRL_TS_DISABLE_LINK_SLC ] = Scenario.denaliLtssmLinkDisable;
257 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_LINK_CTRL_TS_LOOPBACK_SLC ] = Scenario.denaliLtssmLinkLoopback;
258
259 regTrans.WriteDenaliReg( PCIE_REG_DEN_LINK_CTRL, tempDenaliData );
260
261 //Set the Denali N_FTS transmitted in TSx
262 regTrans.WriteDenaliReg( PCIE_REG_DEN_TX_NFTS, Scenario.denaliLtssmNFTS );
263
264 //Set the Denali ACK/NAK and Replay timers
265 regTrans.WriteDenaliReg( PCIE_REG_DEN_ACK_NAK_FREQ_TIMER, Scenario.denaliAckNakLatencyTimerThreshold );
266
267 //Set the replay timer according to the PCIE spec pg.140 table 3-4 unless
268 // a value is passed in from the test
269 if( Scenario.denaliReplayTimerThreshold == 258 ){
270 //case( Scenario.ilupeuMaxPayload ){
271 case( PiuCsrs.piuMaxPayloadSize>>7 ){
272 0:{ case( calculatedWidth ){ //mps=128
273 1: Scenario.denaliReplayTimerThreshold = 711;
274 2: Scenario.denaliReplayTimerThreshold = 384;
275 4: Scenario.denaliReplayTimerThreshold = 219;
276 8: Scenario.denaliReplayTimerThreshold = 201;
277 }
278 }
279 1:{ case( calculatedWidth ){ //mps=256
280 1: Scenario.denaliReplayTimerThreshold = 1248;
281 2: Scenario.denaliReplayTimerThreshold = 651;
282 4: Scenario.denaliReplayTimerThreshold = 354;
283 8: Scenario.denaliReplayTimerThreshold = 321;
284 }
285 }
286 2:{ case( calculatedWidth ){ //mps=512
287 1: Scenario.denaliReplayTimerThreshold = 1677;
288 2: Scenario.denaliReplayTimerThreshold = 867;
289 4: Scenario.denaliReplayTimerThreshold = 462;
290 8: Scenario.denaliReplayTimerThreshold = 258;
291 }
292 }
293 }
294 }
295 // Rx_L0s_adj = 1us / 4ns = 250
296 rx_L0s_adj = 250;
297 Scenario.denaliReplayTimerThreshold += rx_L0s_adj;
298
299
300 regTrans.WriteDenaliReg( PCIE_REG_DEN_REPLAY_TIMER, Scenario.denaliReplayTimerThreshold );
301
302 //The Denali denaliMaxPayload is set in the soma file to ? - change to 1k
303 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_EXP_DEV_CAP );
304 tempDenaliData[2:0] = 3'h3; // 3=1k 2=512 1=256
305 regTrans.WriteDenaliReg( PCIE_REG_EXP_DEV_CAP, tempDenaliData );
306 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_EXP_DEV_CTRL );
307 //Enable Denali to send TLPs with the relaxed ordering bit set even though
308 tempDenaliData[4] = 1;
309 tempDenaliData[7:5] = Scenario.denaliMaxPayload;
310 regTrans.WriteDenaliReg( PCIE_REG_EXP_DEV_CTRL, tempDenaliData );
311
312 //Set the Denali Replay buffer to 32k so we can transmit big packets and not worry about size
313 regTrans.WriteDenaliReg( PCIE_REG_DEN_RETRY_SIZE, 32'h8000 );
314 //Set the Initial Link Numbers transmitted on TS1
315 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN0, Scenario.denaliLtssmLinkNumber );
316 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN1, Scenario.denaliLtssmLinkNumber );
317 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN2, Scenario.denaliLtssmLinkNumber );
318 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN3, Scenario.denaliLtssmLinkNumber );
319 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN4, Scenario.denaliLtssmLinkNumber );
320 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN5, Scenario.denaliLtssmLinkNumber );
321 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN6, Scenario.denaliLtssmLinkNumber );
322 regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN7, Scenario.denaliLtssmLinkNumber );
323
324//If this is a retraining then let the test control resets
325 //if( !Retrain ){
326
327 // 11/9/04
328 //repeat(400) @(posedge CLOCK);
329 //
330
331 // after 400 clock cycles before reset_duration inside initstrategy \n");
332 //The ILU-PEU comes up in reset so just determine how long the
333 // reset duration is
334 //reset_duration = RandUtil.Rand32(Scenario.minResetDuration,Scenario.maxResetDuration);
335 //repeat(reset_duration/2) @(posedge CLOCK);
336 //Remove Power On Reset after 1/2 of reset duration - review Is this ok?
337
338 //dmuXtrEnabled = 1;
339
340
341 //} //End !Retrain
342
343// after resetN = 1, before setting scenario.NPH etc. \n");
344 //Set initial advertised credits
345 //NPDC, CHC, CDC are all advertised as infinite and can't be set in the CSR
346 // so just set them here in case they got set in the test
347 Scenario.ilupeuInitialNonPostedDataCredit = 12'hfff;
348 Scenario.ilupeuInitialCompletionHeaderCredit = 8'hff;
349 Scenario.ilupeuInitialCompletionDataCredit = 12'hfff;
350 //Set max values per Fire PRM
351 if( Scenario.ilupeuInitialPostedDataCredit > 12'hc0 ){
352 Scenario.ilupeuInitialPostedDataCredit = 12'hc0;
353 }
354 //If the total of the header credits is too big then set to the default values
355 if( (Scenario.ilupeuInitialPostedHeaderCredit + Scenario.ilupeuInitialNonPostedHeaderCredit) > 8'h30 ){
356 Scenario.ilupeuInitialPostedHeaderCredit = 8'h20;
357 Scenario.ilupeuInitialNonPostedHeaderCredit = 8'h10;
358 }
359
360 //set same data to denali root monitor Flow Control Register
361 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_PH, Scenario.ilupeuInitialPostedHeaderCredit);
362 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_PD, Scenario.ilupeuInitialPostedDataCredit);
363 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_NPH, Scenario.ilupeuInitialNonPostedHeaderCredit);
364 // These are unlimited, check if value 0 is right
365 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_NPD, 0);
366 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_CPLH, 0);
367 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_CPLD, 0);
368
369
370
371if( !Retrain ){
372 //Toggle warm reset to allow values set above to propogate
373
374} //End !Retrain
375
376 // ILU-PEU CSR's must be written after reset goes away
377 //Set the Max Payload field in the Device control configuration register
378// csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_dev_ctl.read();
379// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_DEV_CTL_MPS_SLC] = Scenario.ilupeuMaxPayload;
380// CSR.fire_plc_tlu_ctb_tlr_csr_a_dev_ctl.write(csrRegTmpData,CSRT_DAEMON);
381
382 //set same data to denali root monitor Express Device Control register
383 tempDenaliPeuData[15:8] = 8'h0;
384 //tempDenaliPeuData[7:5] = Scenario.ilupeuMaxPayload; // is 0, 1, or 2
385 tempDenaliPeuData[7:5] = (PiuCsrs.piuMaxPayloadSize>>7); // piuMaxPayloadSize is 128, 256, or 512
386 tempDenaliPeuData[4:0] = 5'h0;
387 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_DEN_FC0_PH, tempDenaliPeuData);
388
389
390
391 //Set PTL Control Register completion time out and Non posted write single threading
392 // - should default to a downstream port - bit 0 = 1
393// csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.read();
394// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_CTO_SEL_SLC] = Scenario.ilupeuCmplTimeOut;
395// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_NPWR_EN_SLC] = Scenario.ilupeuNPWrtEnSnglThrd;
396// csrRegTmpData[1] = Scenario.ilupeuSlotClkConfig;
397////Moved to LinkTrainingStrategy
398//// csrRegTmpData[8] = 0; //Turn off remain in detect.quiet
399// CSR.fire_plc_tlu_ctb_tlr_csr_a_tlu_ctl.write(csrRegTmpData,CSRT_DAEMON);
400
401 // For Denali root monitor:
402 // set in pureview : ilupeuCmplTimeOut = ttoTLCpl
403 // Non posted write single thread: not needed in Denali
404 // Slot clock config: set in
405
406
407 //Link Capability register is read only
408
409 //Set the link control register
410// csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_ctl.read();
411// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_ASPM_SLC ] = Scenario.ilupeuLinkCtrlASPM;
412// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_RCB_SLC ] = Scenario.ilupeuLinkCtrlRCB;
413// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_DISABLE_SLC ] = Scenario.ilupeuLinkCtrlLinkDisable;
414// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_RETRAIN_SLC ] = Scenario.ilupeuLinkCtrlRetrainLink;
415// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_CLOCK_SLC ] = Scenario.ilupeuLinkCtrlCommonClkConfig;
416// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_LNK_CTL_EXTSYNC_SLC ] = Scenario.ilupeuLinkCtrlExtendedSync;
417// CSR.fire_plc_tlu_ctb_tlr_csr_a_lnk_ctl.write(csrRegTmpData,CSRT_DAEMON);
418
419 //set same data to denali root monitor Express Link Control register
420 tempDenaliPeuData[15:8] = 8'h0;
421 tempDenaliPeuData[7] = Scenario.ilupeuLinkCtrlExtendedSync;
422 tempDenaliPeuData[6] = Scenario.ilupeuLinkCtrlCommonClkConfig;
423 tempDenaliPeuData[5] = Scenario.ilupeuLinkCtrlRetrainLink;
424 tempDenaliPeuData[4] = Scenario.ilupeuLinkCtrlLinkDisable;
425 tempDenaliPeuData[3] = Scenario.ilupeuLinkCtrlRCB;
426 tempDenaliPeuData[2] = 1'b0;
427 tempDenaliPeuData[1:0] = Scenario.ilupeuLinkCtrlASPM;
428 denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_EXP_LINK_CTRL, tempDenaliPeuData);
429
430
431 //Set the slot capabilities register
432 //Only write the register if a value is passed in from the test. This is for RFE 1987
433 // so we can test that a SET_SLOT_POWER message is NOT sent by default
434// if( Scenario.ilupeuSetPowerLimitValue || Scenario.ilupeuSetPowerLimitScale ){
435// csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_slt_cap.read();
436// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_SPLV_SLC ] = Scenario.ilupeuSetPowerLimitValue;
437// csrRegTmpData[ FIRE_PLC_TLU_CTB_TLR_CSR_A_SLT_CAP_SPLS_SLC ] = Scenario.ilupeuSetPowerLimitScale;
438// //CSR.fire_plc_tlu_ctb_tlr_csr_a_slt_cap.write(csrRegTmpData,CSRT_DAEMON);
439// }
440
441 //set same data to denali root monitor Express Slot Capabilities register
442 //denali_root_monitor_regTrans.WriteDenaliReg(PCIE_REG_EXP_SLOT_CAP, csrRegTmpData);
443
444
445 //Set link config register N2-OKAY
446 //In N2 PRM 0.7 this is called the PEU DLPL DLL Control Register
447 //csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_link_cfg.read();
448 //csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_ACK_FREQ_SLC] = 1;//N2 review Scenario.;
449// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CFG_DATA_LINK_ENABLE_SLC] = 1;//N2 review Scenario.;
450
451 //CSR.fire_plc_tlu_ctb_tlr_csr_a_link_cfg.write(csrRegTmpData,CSRT_DAEMON);
452
453
454/*
455N2 - Orphaned ???
456 lpusdRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_LINK_DISABLE_REQ_SLC] = Scenario.lpusdLtssmLinkDisable;
457 lpusdRegTmpData[FIRE_PLC_TLU_CTB_LPR_CSR_A_PCIE_LPU_LTSSM_CNTL_HOT_RESET_SLC] = Scenario.lpusdLtssmHotReset;
458*/
459
460 //Set fields for the ilupeu link control register
461 //In N2 PRM 0.7 this is called the PEU DLPL MACL/PCS Control Register
462 //Set the disable scrambling field for the ilupeu link control register
463 //This should also set the disable scrambling bit in the physical layer configuration register
464// csrRegTmpData = CSR.fire_plc_tlu_ctb_tlr_csr_a_link_ctl.read(CSRT_OMNI);
465
466// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_SCRAMBLE_DISABLE_SLC] = Scenario.ilupeuLtssmDisableScrambling;
467//// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_LTSSM_LPBK_EN_SLC] = Scenario.ilupeuLtssmLinkLoopback; //Removed in PRM .81
468// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_FAST_LINK_MODE_SLC] = Scenario.FastLinkTraining;
469// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_LINK_CAPABLE_SLC] = Scenario.ilupeuLinkCapMaxLinkWdth;
470// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_N_FTS_SLC] = Scenario.ilupeuLtssmNFTS;
471// csrRegTmpData[FIRE_PLC_TLU_CTB_TLR_CSR_A_LINK_CTL_LINK_NUM_SLC] = Scenario.ilupeuLtssmLinkNumber;
472
473 //CSR.fire_plc_tlu_ctb_tlr_csr_a_link_ctl.write(csrRegTmpData,CSRT_DAEMON);
474
475 //Set the Initial Link Numbers transmitted on TS1 for denali root monitor
476 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN0, Scenario.ilupeuLtssmLinkNumber );
477 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN1, Scenario.ilupeuLtssmLinkNumber );
478 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN2, Scenario.ilupeuLtssmLinkNumber );
479 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN3, Scenario.ilupeuLtssmLinkNumber );
480 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN4, Scenario.ilupeuLtssmLinkNumber );
481 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN5, Scenario.ilupeuLtssmLinkNumber );
482 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN6, Scenario.ilupeuLtssmLinkNumber );
483 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TS1_LKNUM_LN7, Scenario.ilupeuLtssmLinkNumber );
484 //Set the Denali N_FTS transmitted in TSx
485 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_TX_NFTS, Scenario.ilupeuLtssmNFTS );
486 ////////////////////////////
487 // Disable RC Error messages
488 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_PL_NONFATAL_TTX_IDLE_SET_TO_IDLE );
489 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_PL_NONFATAL_LTSSM_POLL_ACTIVE_TO1_EARLY );
490 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE_1 );
491 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE0_1 );
492 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NE_2 );
493 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_1 );
494 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP0_1 );
495 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_PH );
496 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_PD );
497 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_NPH );
498 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_NPD );
499 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_CPLH );
500 denali_root_monitor_regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_INI_NEXP_2_CPLD );
501
502 //Need to write to Allowed Link Widths register as just writing to Denali Link Capability might not work
503 if( Scenario.ilupeuLinkCapMaxLinkWdth <= 8 ){
504 case( Scenario.ilupeuLinkCapMaxLinkWdth ){
505 4 : tempDenaliData = 32'hb; //x4,x2,x1
506 2 : tempDenaliData = 32'h3; //x2,x1
507 1 : tempDenaliData = 32'h1; //x1
508 default: tempDenaliData = 32'h8b; //x8,x4,x2,x1
509 }
510
511 denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_ALLOWED_WIDTHS, tempDenaliData );
512 }
513
514
515
516
517
518
519 //Set the replay timer according to the PCIE spec pg.140 table 3-4 unless
520 // a value is passed in from the test
521
522//#ifndef N2_FC
523// if( Scenario.ilupeuReplayTimerThreshold == Scenario.ilupeuReplayTimerThresholdDflt ){
524// case( Scenario.ilupeuMaxPayload ){
525// 0: { case( calculatedWidth ){ //mps=128
526// 1: Scenario.ilupeuReplayTimerThreshold = 711;
527// 2: Scenario.ilupeuReplayTimerThreshold = 384;
528// 4: Scenario.ilupeuReplayTimerThreshold = 219;
529// 8: Scenario.ilupeuReplayTimerThreshold = 201;
530// }
531// }
532// 1: { case( calculatedWidth ){ //mps=256
533// 1: Scenario.ilupeuReplayTimerThreshold = 1248;
534// 2: Scenario.ilupeuReplayTimerThreshold = 651;
535// 4: Scenario.ilupeuReplayTimerThreshold = 354;
536// 8: Scenario.ilupeuReplayTimerThreshold = 321;
537// }
538// }
539// 2: { case( calculatedWidth ){ //mps=512
540// 1: Scenario.ilupeuReplayTimerThreshold = 1677;
541// 2: Scenario.ilupeuReplayTimerThreshold = 867;
542// 4: Scenario.ilupeuReplayTimerThreshold = 462;
543// 8: Scenario.ilupeuReplayTimerThreshold = 258;
544// }
545// }
546// }
547// }
548// CSR.fire_plc_tlu_ctb_tlr_csr_a_replay_tim_thresh.write( Scenario.ilupeuReplayTimerThreshold );
549
550// // Set denali root monitor replay timer threshold value
551// denali_root_monitor_regTrans.WriteDenaliReg( PCIE_REG_DEN_REPLAY_TIMER, Scenario.ilupeuReplayTimerThreshold );
552
553//#endif
554
555/* review
556 //Set the ACK/NAK latency timer threshold to a new value if it is set in the test
557 if( Scenario.lpusdAckNakLatencyTimerThreshold !== Scenario.lpusdAckNakLatencyTimerThresholdDflt ){
558 CSR.fire_plc_tlu_ctb_lpr_csr_a_pcie_lpu_acknak_latency.write( Scenario.lpusdAckNakLatencyTimerThreshold );
559 }
560*/
561
562
563 //Set up Interrupt masks here D1.5 review
564
565 //Set up Vendor IDs for Vendor Defined TLPs
566 regTrans.WriteDenaliReg( PCIE_REG_DEN_VENDOR_IDS, {Scenario.denaliVendorDefinedVendorID2 ,Scenario.denaliVendorDefinedVendorID1} );
567
568if( !Retrain ){
569 //Disable all Denali errors that aren't needed
570 DisableDenaliErrs();
571} //End !Retrain
572
573 printf("AC: at end of initstrategy execute \n");
574
575}
576
577
578task N2fcInitStrategy::SetFastLinkTraining(){
579
580}
581
582
583task N2fcInitStrategy::DenaliGotoRecovery(){
584
585 tempDenaliData = regTrans.ReadDenaliReg( PCIE_REG_DEN_LINK_CTRL );
586 tempDenaliData[ FNX_PCIE_XTR_REG_DEN_LINK_CTRL_GOTO_RECOVERY_SLC ] = 1'b1;
587
588
589}
590
591
592task N2fcInitStrategy::DisableDenaliErrs(){
593
594 //If Denali received a reset then all the SuppressDenaliErr set in the FNXPCIEXtr need to be set again so just do it here
595 Pod.FNXPCIEBldr.DenaliMemoryModelInit();
596
597//N2 review - Do we really need to disable these errors, needed to get testbench up
598 //Since were not following PCIE protocol disable these errors that
599 // expect a cfg write before anything else N2
600 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlInitReq );
601 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplId0_Cpl );
602 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplD );
603 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplLk );
604 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplId0_CplDLk );
605
606 // Malformed TLP - INTx has non-0 (%d) as function # in Requester ID
607 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlINTxRID );
608
609 //[PCISIG-CFG.5.5#2[#3]]. Transmitting TLP (Assert_INTB), the corresponding pin value is not specified in Interrupt Pin register(s)
610 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTxPIN );
611
612 // Transmitting TLP (Deassert_INTC) is not permitted because this is a single function device.
613 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTBCD );
614
615
616//End N2 review - Do we really need to disable these errors, needed to get testbench up
617
618
619/* review These should not be needed since I'm now using the transaction layer
620 //Suppress the Flow Control error so any number of credits can be advertised
621 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_RXOVFL );
622
623 // Supress [NONFATAL-PoisonedTlp] TLP_UR_Poison [PCISIG-TXN.7.3#4[#5]] since this will be randomized
624 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_UR_Poison );
625
626 //Disable Denali from reporting the TSx Disable Scrambling bit set when not in LTSSM Configuration State
627 if( Scenario.lpusdLtssmDisableScrambling ){
628 regTrans.SuppressDenaliErr( PCIE_PL_NONFATAL_SCRAM_DISABLE );
629 }
630
631 // Supress TLP_MF_vlLkEP [PCISIG-TPL.3.3#4]. Illegal Locked TLP - PCI Express Endpoint does not support Locked accesses
632 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkEP );
633
634 // Supress TLP_MF_vlLkTC0 [PCISIG]. Malformed Locked TLP - only default traffic class (TC0) is allowed
635 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkTC0 );
636
637 // Supress TLP_MF_vlPoison [PCISIG-TXN.7.3#1[#2]]. Poisoned TLP [MRdLk_64] - Poisoned bit is 1,
638 // but it is not CplD, MWr, CfgWr0, CfgWr1, or MsgDk
639 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlPoison );
640
641 // Supress TLP_MF_vl1stBE [PCISIG-TXN.2.6#1]. Malformed TLP - First DW BE is 0,
642 // but the payload length (1024 DWords) is greater than 1
643 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vl1stBE );
644
645
646 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLastBE1 );
647 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlNC1stBE );
648 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlNClastBE );
649 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPL_Poison );
650 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplSt );
651
652 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkReq ); //Initiating an illegal Locked Request - only RC can initiate.
653 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlIOExpEp ); //Erroneous TLP - Express Endpoint cannot generate IO request
654 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlIOpkgLEN ); //Malformed TLP - IO request can only have Length==1, but it has x
655 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCfgTx ); //Erroneous TLP - An Upstream port cannot transmit Configuration requests to upstream components
656
657 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgPkg ); //Erroneous TLP - Illegal combination of TLP type (Msg), Rout(0x4), and msgCode (0x56)
658 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgRout ); //Erroneous TLP - Message Routing value (6) is Reserved, it must be within [0 : 5]. It will be treated as 'Terminate at Receiver
659 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgERRrx ); //This device (ExpressEP) cannot be Receiver of Error Signaling msg TLP - only Root Complex can
660 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTBCD0 ); //Received INTx Msg TLP (Deassert_INTB), this is not permitted because the downstream is a single function device
661 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTxPIN0 ); //Receiving TLP (Deassert_INTB), the corresponding pin value is not specified in Interrupt Pin register(s). The port at the other side of the link defines pin values
662 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCfg0 ); //To transmit TLP CfgWr0, but the other end Port Function (transmitter) is not defined as Configuration 1
663 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCFGpkgLEN ); //Malformed TLP - Configuration request can only have Length==1, but it has X
664 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgINTxrx ); //This device (ExpressEP) cannot be Receiver of INTx msg TLP - only Root Complex or Switch can
665 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAttnrx ); //This device (ExpressEP) cannot be Receiver of Attention_Button_Pressed msg TLP - only Root Complex or Bridge can
666
667 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlINTxRID ); //Erroneous TLP - INTx has non-0 (5) as function # in RequesterID
668 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTBCD ); //Transmitting INTx Msg TLP (Deassert_INTD) on behalf of the internal resource of this device is not permitted because this is a single function device
669 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_CFG_vlINTxPIN ); //Transmitting TLP (Deassert_INTD), the corresponding pin value is not specified in Interrupt Pin register(s). This port defines pin values (1)
670 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPBlktx ); //This device (ExpressEP) cannot be Transmitter of Power_Indicator_Blink msg TLP - only Root Complex or Bridge can
671 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgAckrx ); //This device (ExpressEP) cannot be Receiver of PM_TO_Ack msg TLP - only Root Complex can
672 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgPMErx ); // This device (ExpressEP) cannot be Receiver of PM_PME msg TLP - only Root Complex or Switch can
673 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_PLN0_Msg ); // TLP Msg (SLOT_Power_Limit) has non-0 in payload (0x13a3fd5b) at bits [31 : 10]
674 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgSLOTtx ); //This device (ExpressEP) cannot be Transmitter of Slot Power Limit msg TLP - only Root Complex or Bridge can
675 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgLOCKtx ); //This device (ExpressEP) cannot be Transmitter of Unlock msg TLP - only Root Complex can
676 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgNaktx ); //This device (ExpressEP) cannot be Transmitter of PM_Active_State_Nak msg TLP - only Root Complex or Switch can
677 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOntx ); //This device (ExpressEP) cannot be Transmitter of Attention_Indicator_On msg TLP - only Root Complex or Bridge can
678 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgOfftx ); //This device (ExpressEP) cannot be Transmitter of PM_Turn_Off msg TLP - only Root Complex can
679 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOfftx ); //This device (ExpressEP) cannot be Transmitter of Power_Indicator_Off msg TLP - only Root Complex or Bridge can
680 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPAOfftx ); //This device (ExpressEP) cannot be Transmitter of Attention_Indicator_Off msg TLP - only Root Complex or Bridge can
681 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPPOntx ); //This device (ExpressEP) cannot be Transmitter of Attention_Indicator_On msg TLP - only Root Complex or Bridge can
682 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlMsgHPABlktx ); //This device (ExpressEP) cannot be Transmitter of Attention_Indicator_Blink msg TLP - only Root Complex or Bridge can
683 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlNC1stBE2 ); //Malformed TLP - Non-contiguous First DW BE (0x%x) is not permitted if the payload length is 2 and address (low32:0x%08x) is not QWord aligned
684 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlNClastBE2 ); //Malformed TLP - Non-contiguous Last DW BE (0x2) is not permitted if the payload length is 2 and address (low32:0x4869cc64) is not QWord aligned
685 regTrans.SuppressDenaliErr( PCIE_TL_COR_TLP_SLOT_RSV ); //Slot Power Limit TLP contains non-0 payload (0x692d7af7) in reserved bits [31:10]
686 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_CFG_DID_TXCPLQ ); // There are some pending requests in TX Completion Queue [port_%d] while the Device ID changes to
687 regTrans.SuppressDenaliErr( PCIE_TL_COR_TLP_USERTAG_2 ); // Function (7) and Tag (109) identified an unfinished transaction, discard the transaction
688 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_PH ); //InitFC value (%d) is less than the minimum PH FC credit requirement
689 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_PD ); //InitFC value (%d) is less than the minimum PD FC credit requirement
690 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_NPH ); //InitFC value (%d) is less than the minimum NPH FC credit requirement
691 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_NPD ); //InitFC value (%d) is less than the minimum NPD FC credit requirement
692 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_CPLH ); //InitFC value (%d) is less than the minimum CPLH FC credit requirement
693 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_CPLD ); //InitFC value (%d) is less than the minimum CPLD FC credit requirement
694 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlCplBCM0 ); //TXN.2.21#8 : Erroneous TLP - Completion's BCM must not be set by PCI Express completer
695 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLQ0_1 ); //Cannot find matching Request for the Completion TLP [transId=0xc136ad], discard the packet
696 regTrans.SuppressDenaliErr( PCIE_TL_FATAL_CFG_TC_1MAP ); //Malformed TLP - Traffic Class (TC6) is not mapped to an active VC
697 regTrans.SuppressDenaliErr( PCIE_TL_NONFATAL_FCPE_VC ); //Cannot update the FC Credit to not yet enabled VC-1
698 regTrans.SuppressDenaliErr( PCIE_TL_COR_CFG_PTRRSV ); //Capability pointer Register '%s' has non-0 value 0x%x in reserved bits [1:0]
699 regTrans.SuppressDenaliErr( PCIE_TL_COR_CFG_PTRRSV0 ); //Downstream %s: Capability pointer Register '%s' has non-0 value 0x%x in reserved bits [1:0]
700
701
702
703
704
705
706*/
707
708//review added for Denali version _047
709regTrans.tempSuppressDenaliErr( PCIE_TL_FATAL_FCPE_INI_PD ); //InitFC value (%d) is less than the minimum PD FC credit requirement
710regTrans.tempSuppressDenaliErr( PCIE_TL_COR_TLP_DIFF_CPLST );
711regTrans.tempSuppressDenaliErr( PCIE_PL_COR_PM_UTX_TO_ACK_NR );
712regTrans.tempSuppressDenaliErr( PCIE_PL_COR_PM_UTX_TO_ACK_D3HOT );
713
714//Needed because not all Error transactions complete correctly
715regTrans.tempSuppressDenaliErr( PCIE_TL_COR_TLP_USERTAG_2 ); //identified an unfinished transaction, discard the transaction
716
717}
718
719task N2fcInitStrategy::SetDenaliInitFlowControl(){
720 // ==================================================
721 //Set the Initial Flow Control values in Denali First
722
723 if ( get_plus_arg(CHECK, "PEU_FC_PH") ) {
724 Scenario.denaliInitialPostedHeaderCredit = get_plus_arg(NUM, "PEU_FC_PH");
725 }
726 Report.report(RTYP_DEBUG_1,"N2fcInitStrategy::Execute: Scenario.denaliInitialPostedHeaderCredit = %d \n", Scenario.denaliInitialPostedHeaderCredit);
727
728 if ( get_plus_arg(CHECK, "PEU_FC_NPH") ) {
729 Scenario.denaliInitialNonPostedHeaderCredit = get_plus_arg(NUM, "PEU_FC_NPH");
730 }
731 Report.report(RTYP_DEBUG_1,"N2fcInitStrategy::Execute: Scenario.denaliInitialNonPostedHeaderCredit = %d \n", Scenario.denaliInitialNonPostedHeaderCredit);
732
733 if ( get_plus_arg(CHECK, "PEU_FC_PD") ) {
734 Scenario.denaliInitialPostedDataCredit = get_plus_arg(NUM, "PEU_FC_PD");
735 }
736 Report.report(RTYP_DEBUG_1,"N2fcInitStrategy::Execute: Scenario.denaliInitialPostedDataCredit = %d \n", Scenario.denaliInitialPostedDataCredit);
737
738 // Note: since Denali's definition of inifite means to set their PCIE_REG_DEN to FFFFFFFF and the legacy bit definition
739 // for scenario.denaliInitialxxHeaderCredit are defined as 8 or 12 bits, so need to introduce the denali_xx_xx_infinite
740 // variables
741
742 //credits-Posted Header
743 if (Scenario.denali_FC_PH_infinite == 1) {
744 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_PH, 32'hFFFFFFFF );
745 Scenario.denaliInitialPostedHeaderCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_PHC_WIDTH'h0;
746 }
747 else {
748 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_PH, Scenario.denaliInitialPostedHeaderCredit );
749 }
750
751 //credits-Posted Data
752 if (Scenario.denali_FC_PD_infinite == 1) {
753 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_PD, 32'hFFFFFFFF );
754 Scenario.denaliInitialPostedDataCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_PDC_WIDTH'h0;
755 }
756 else {
757 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_PD, Scenario.denaliInitialPostedDataCredit);
758 }
759
760 //credits-NonPosted Header
761 if (Scenario.denali_FC_NPH_infinite == 1) {
762 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_NPH, 32'hFFFFFFFF );
763 Scenario.denaliInitialNonPostedHeaderCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_NHC_WIDTH'h0;
764 }
765 else {
766 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_NPH, Scenario.denaliInitialNonPostedHeaderCredit );
767 }
768
769 //credits-NonPosted Data
770 if (Scenario.denali_FC_NPD_infinite == 1) {
771 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_NPD, 32'hFFFFFFFF );
772 Scenario.denaliInitialNonPostedDataCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_NDC_WIDTH'h0;
773 }
774 else {
775 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_NPD, Scenario.denaliInitialNonPostedDataCredit );
776 }
777
778 //credits-Completion Header
779 if (Scenario.denali_FC_CPLH_infinite == 1) {
780 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_CPLH, 32'hFFFFFFFF );
781 Scenario.denaliInitialCompletionHeaderCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_CHC_WIDTH'h0;
782 }
783 else {
784 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_CPLH, Scenario.denaliInitialCompletionHeaderCredit );
785 }
786
787 //credits-Completion Data
788 if (Scenario.denali_FC_CPLD_infinite == 1) {
789 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_CPLD, 32'hFFFFFFFF );
790 Scenario.denaliInitialCompletionDataCredit = FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_ICI_CDC_WIDTH'h0;
791 }
792 else {
793 regTrans.WriteDenaliReg( PCIE_REG_DEN_FC0_CPLD, Scenario.denaliInitialCompletionDataCredit );
794 }
795}
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