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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / N2str / ilupeuBootPEUStr.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilupeuBootPEUStr.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35class BootPEUStr extends PEUStrBase
36 {
37
38/* Only need 1 Report object and Xtr's will be instantiated
39 in the Pod class
40 local DMUXtr f_DMUXtr;
41
42 local ReportClass f_CSRXtrReport;
43
44 local ReportClass f_PECXtrReport;
45 local PECXtrBaseConfiguration f_PECXtrConfig;
46 local PECXtrBaseErrorCenter f_PECXtrError;
47 local PECXtrTop f_PECXtr;
48
49 local ReportClass f_PCIEXtrReport;
50 local PECXtrBaseErrorCenter f_PCIEXtrError;
51 local PCIEXtrAPI f_PCIEXtr;
52
53 local LPUXtr f_LPUXtr;
54*/
55
56 local integer initPostHdr; // Initial posted header credits
57 local integer initPostData; // Initial posted data credits
58 local integer initNpstHdr; // Init'l non-posted hdr credits
59 local integer initNpstData; // Init'l non-posted data credits
60 local integer initCplnHdr; // Init'l completion hdr credits
61 local integer initCplnData; // Init'l completion data credits
62 local integer initRetry; // Init'l LPU retry-buffer size/credits
63 local bit envIntEnable; // Should the env't monitor interrupts?
64
65 public integer _numPhyLanes;
66 public integer _numActiveLanes;
67 public bit _fastTrain;
68 public PECBool _txEnableScramble;
69 public PECBool _rxEnableScramble;
70
71 public integer _FCTxTimeOutPosted;
72 public integer _FCTxTimeOutNonPosted;
73 public integer _FCTxTimeOutCompletion;
74
75 public integer _reset_txCycleQuantity;
76 public integer _bypass_txCycleQuantity;
77 public integer _detect_txCycleQuantity;
78
79 public integer _polling_active_txCycles;
80 public integer _polling_configuration_txCycles;
81
82 public integer _configuration_linkwidth_start_txCycles;
83 public integer _configuration_linkwidth_accept_txCycles;
84 public integer _configuration_lanenum_wait_txCycles;
85 public integer _configuration_lanenum_accept_txCycles;
86 public integer _configuration_complete_txCycles;
87 public integer _configuration_idle_txCycles;
88
89 public integer _recovery_rcvr_lock_txCycles;
90 public integer _recovery_rcvr_cfg_txCycles;
91 public integer _recovery_idle_txCycles;
92
93//N2 classes
94 local ilupeuCSR f_CSRXtr;
95 protected ReportClass Report;
96 protected ilupeuPodClass Pod;
97 protected CSRCollection CSR;
98 protected ilupeuScenario Scenario;
99 string Name;
100
101 //Init Strategy
102#ifdef N2_FC
103 N2fcInitStrategy InitStrat;
104#else
105 ilupeuInitStrategy InitStrat;
106#endif
107
108//END N2 classes
109
110 task new( ReportClass _Report,
111 ilupeuScenario _Scenario )
112 {
113 super.new(null);
114 Report = _Report;
115 Scenario = _Scenario;
116 initPostHdr = 16;
117 initPostData = 64;
118 initNpstHdr = 16;
119 initNpstData = 64;
120 initCplnHdr = 16;
121 initCplnData = 64;
122 initRetry = 4096;
123 envIntEnable = 1; //lets start by defaulting to ints enabled;
124
125 this._numPhyLanes = 8;
126 this._numActiveLanes = 8;
127 this._fastTrain = 1;
128 this._txEnableScramble = e_false;
129 this._rxEnableScramble = e_false;
130
131 this._FCTxTimeOutPosted = 75;
132 this._FCTxTimeOutNonPosted = 75;
133 this._FCTxTimeOutCompletion = 75;
134
135 this._reset_txCycleQuantity = 72;
136 this._bypass_txCycleQuantity = 12;
137 this._detect_txCycleQuantity = 16;
138
139 this._polling_active_txCycles = 16;
140 this._polling_configuration_txCycles = 16;
141
142 this._configuration_linkwidth_start_txCycles = 0;
143 this._configuration_linkwidth_accept_txCycles = 0;
144 this._configuration_lanenum_wait_txCycles = 0;
145 this._configuration_lanenum_accept_txCycles = 0;
146 this._configuration_complete_txCycles = 16;
147 this._configuration_idle_txCycles = 16;
148
149 this._recovery_rcvr_lock_txCycles = 0;
150 this._recovery_rcvr_cfg_txCycles = 16;
151 this._recovery_idle_txCycles = 16;
152 }
153
154 task Execute()
155 {
156
157/* N2 - Use the Pod and Init Strategy to handle initialization
158 Need to map variables below to Scenario
159 bit usePCIE;
160
161 // Are we using the PCI-Express xactor?
162 usePCIE = get_plus_arg( CHECK, "LPU" );
163 if ( usePCIE )
164 printf( "BootPEUStr: Using PCI-Express transactor with LPU\n" );
165 else
166 printf( "BootPEUStr: Using PEC core transactor (without LPU)\n" );
167
168
169 if ( usePCIE )
170 {
171 //
172 // Instantiate the PCI Express transactor (early)
173 //
174
175 f_PCIEXtrReport = new();
176 f_PCIEXtrReport.set_global_print_threshold( RPRT_NONMASKABLE );
177
178 f_PECXtrConfig = new( bindTlpIngress, bindTlpEgress, // po_pxPkt
179 bindFcEgress, bindFcIngress, // po_pxFC
180 bindPecClk, bindPecClk, // po_pxTimerClock
181 bindXtrClk ); // XactorClk
182
183 f_PECXtrConfig._txInitalPostedHeaderCredit = initPostHdr;
184 f_PECXtrConfig._txInitalPostedDataCredit = initPostData;
185 f_PECXtrConfig._txInitalNonPostedHeaderCredit = initNpstHdr;
186 f_PECXtrConfig._txInitalNonPostedDataCredit = initNpstData;
187 f_PECXtrConfig._txInitalCompletionHeaderCredit = initCplnHdr;
188 f_PECXtrConfig._txInitalCompletionDataCredit = initCplnData;
189
190 f_PCIEXtrError = new(f_PCIEXtrReport);
191
192 f_PCIEXtr = new(f_PCIEXtrReport, // ReportClass a_report
193 bd_pxATimerClock, // po_pxTimerClock a_SKPTxClock
194 bd_pxATimerClock, // po_pxTimerClock a_SKPRxClock
195 bd_pxATimerClock, // po_pxTimerClock a_FCTxClock
196 bd_pxATimerClock, // po_pxTimerClock a_FCRxClock
197 bd_pxATimerClock, // po_pxTimerClock a_SNTxClock
198 bd_pxATimerClock, // po_pxTimerClock a_SNRxClock
199 bd_pxATimerClock, // po_pxTimerClock a_APIClock
200
201 0, // integer a_xid
202 "PCIEXtr0", // string a_name
203 this._numPhyLanes, // integer a_numPhyLanes
204 this._numActiveLanes, // integer a_numActiveLanes
205
206 0, // integer a_txIdleCyclesAfterTLP
207 0, // integer a_txIdleCyclesAfterDLLP
208
209 e_false, // PECBool a_bypassFlowControlInit
210
211 initPostHdr, // bit [7:0] a_txInitalPostedHeaderCredit
212 initNpstHdr, // bit [7:0] a_txInitalNonPostedHeaderCredit
213 initCplnHdr, // bit [7:0] a_txInitalCompletionHeaderCredit
214
215 initPostData, // bit [11:0] a_txInitalPostedDataCredit
216 initNpstData, // bit [11:0] a_txInitalNonPostedDataCredit
217 initCplnData, // bit [11:0] a_txInitalCompletionDataCredit
218
219 8'h_20, // bit [7:0] a_rxInitalPostedHeaderCredit
220 8'h_10, // bit [7:0] a_rxInitalNonPostedHeaderCredit
221 8'h_00, // bit [7:0] a_rxInitalCompletionHeaderCredit
222
223 12'h_0C0, // bit [11:0] a_rxInitalPostedDataCredit
224 12'h_000, // bit [11:0] a_rxInitalNonPostedDataCredit
225 12'h_000, // bit [11:0] a_rxInitalCompletionDataCredit
226
227 this._FCTxTimeOutPosted,
228 this._FCTxTimeOutNonPosted,
229 this._FCTxTimeOutCompletion,
230
231 e_false, // PECBool a_FCViolatePosted
232 e_false, // PECBool a_FCViolateNonPosted
233 e_false, // PECBool a_FCViolateCompletion
234
235 150, // integer a_SNTxTimeOut
236 450, // integer a_SNRxTimeOut
237
238 3, // integer a_SKPTxLength
239 1180, // integer a_SKPTxTimeOut
240 5664, // integer a_SKPRxTimeOut
241
242 e_false, // PECBool a_bypassLinkTraining
243
244 0, // integer a_linkNum
245 140, // integer a_txNFTS
246 140, // integer a_rxNFTS
247
248 this._txEnableScramble, // PECBool a_txEnableScramble
249 this._rxEnableScramble, // PECBool a_rxEnableScramble
250
251 this._reset_txCycleQuantity,
252 this._bypass_txCycleQuantity,
253 this._detect_txCycleQuantity,
254
255 this._polling_active_txCycles,
256 this._polling_configuration_txCycles,
257
258 this._configuration_linkwidth_start_txCycles,
259 this._configuration_linkwidth_accept_txCycles,
260 this._configuration_lanenum_wait_txCycles,
261 this._configuration_lanenum_accept_txCycles,
262 this._configuration_complete_txCycles,
263 this._configuration_idle_txCycles,
264
265 this._recovery_rcvr_lock_txCycles,
266 this._recovery_rcvr_cfg_txCycles,
267 this._recovery_idle_txCycles
268 );
269
270
271 f_PCIEXtr.enableAutoTxAck();
272 }
273 // Wait for reset to be asserted
274 @( posedge CLOCK );
275*/
276
277 /* Gotta push credit stuff into the
278 TLU during reset! */
279 /* These interfaces are not connected
280 to anything if the LPU exists. */
281/* N2 -
282 if ( !usePCIE )
283 {
284 TLU_EgressCredit.type = 0;
285 TLU_EgressCredit.vc = 0;
286 TLU_EgressCredit.retry = initRetry;
287 }
288*/
289
290/* N2 - - Enabled in the Pod
291 //
292 // Fire up the CSR-ring transactor
293*/
294
295/* N2 - Use the InitStrategy
296 if ( !usePCIE )
297 {
298 // ...and hook-up the AHB port to the TLU (eventually)
299 TLU_AHB.Srdata = 32'b0;
300 TLU_AHB.Sready = 1'b0;
301 TLU_AHB.Sresp = 2'b0;
302
303 // ...and tell the TLU what the LPU's thinking about
304 TLU_PM.dllprecv = 3'b0;
305 TLU_PM.curr = 3'b001; // Say that we're currently in L0
306 TLU_PM.status = 8'b0; // Say that we're busy busy busy!
307 TLU_Control.int = 1'b0;
308 TLU_Control.reset = 1'b0;
309 TLU_Control.ue = 8'b0;
310 TLU_Control.ce = 8'b0;
311 TLU_Control.oe = 8'b0;
312 TLU_Control.status = 8'b0; // Say that the data-link is inactive
313 TLU_Control.dbga = 8'b0;
314 TLU_Control.dbgb = 8'b0;
315 }
316*/
317
318/* N2 Use the Pod to enable the Xtr's
319 //
320 // Instantiate the DMU transactor.
321 //
322 ILU_EgressPEC.enq = 1'b0;
323 ILU_IngressPEC.deq = 1'b0;
324 ILU_IngressRel.enq = 1'b0;
325 ILU_IngressData.addr = 8'b0;
326
327 TLU_IngressTLP.cmd = 3'b0;
328 TLU_EgressTLP.dack = 1'b0;
329 TLU_Control.link = 1'b0;
330
331 f_DMUXtr = new( bindDMUingress, bindDMUegress );
332 f_DMUXtr.enableXtr();
333
334 //
335 // Instantiate the PEC transactor.
336 //
337 if ( !usePCIE )
338 {
339 f_PECXtrReport = new();
340 f_PECXtrReport.set_global_print_threshold( RPRT_NONMASKABLE );
341 f_PECXtrConfig = new( bindTlpIngress, bindTlpEgress, // po_pxPkt
342 bindFcEgress, bindFcIngress, // po_pxFC
343 bindPecClk, bindPecClk, // po_pxTimerClock
344 bindXtrClk ); // XactorClk
345
346 f_PECXtrConfig._txInitalPostedHeaderCredit = initPostHdr;
347 f_PECXtrConfig._txInitalPostedDataCredit = initPostData;
348 f_PECXtrConfig._txInitalNonPostedHeaderCredit = initNpstHdr;
349 f_PECXtrConfig._txInitalNonPostedDataCredit = initNpstData;
350 f_PECXtrConfig._txInitalCompletionHeaderCredit = initCplnHdr;
351 f_PECXtrConfig._txInitalCompletionDataCredit = initCplnData;
352
353 f_PECXtrError = new(f_PECXtrReport);
354 f_PECXtr = new( f_PECXtrError, f_PECXtrConfig );
355 f_PECXtr.enableXtr();
356 }
357
358 // Start the "LPU transactor" which combines the PEC and PCIE transactors.
359 f_LPUXtr = new( usePCIE );
360 if ( usePCIE )
361 {
362 f_LPUXtr.usePCIEX( f_PCIEXtr, f_PECXtrConfig, f_PCIEXtrError,
363 // these may be needed to instance a new transactor
364 this._numPhyLanes,
365 this._numActiveLanes,
366 this._fastTrain,
367 this._txEnableScramble,
368 this._rxEnableScramble,
369
370 this._FCTxTimeOutPosted,
371 this._FCTxTimeOutNonPosted,
372 this._FCTxTimeOutCompletion,
373
374 this._reset_txCycleQuantity,
375 this._bypass_txCycleQuantity,
376 this._detect_txCycleQuantity,
377
378 this._polling_active_txCycles,
379 this._polling_configuration_txCycles,
380
381 this._configuration_linkwidth_start_txCycles,
382 this._configuration_linkwidth_accept_txCycles,
383 this._configuration_lanenum_wait_txCycles,
384 this._configuration_lanenum_accept_txCycles,
385 this._configuration_complete_txCycles,
386 this._configuration_idle_txCycles,
387
388 this._recovery_rcvr_lock_txCycles,
389 this._recovery_rcvr_cfg_txCycles,
390 this._recovery_idle_txCycles
391 );
392 } else {
393 f_LPUXtr.usePEC( f_PECXtr, f_PECXtrConfig, f_PECXtrError );
394 }
395
396END - N2 Use the Pod to enable the Xtr's
397*/
398
399 //Instantiate the Pod here that holds the enabled
400 // DMUXtr and FNXPCIEXactor and CSR-ring transactor
401 Pod = new( Report ); //
402
403 // Wait for reset to be asserted
404 @( posedge CLOCK );
405
406 /* Gotta push credit stuff into the
407 TLU during reset! */
408 //Initialize the csr's and handle reset
409 InitStrat = new ( Report,
410 Pod.CSRXtr.CSR,
411 Pod,
412 Scenario );
413
414 InitStrat.Execute();
415
416 //
417 // Fire up the environment after reset ends
418 //
419//N2 @( posedge CLOCK );
420//N2 TLU_Control.link = void;
421
422 f_env = new( Pod,
423 Scenario,
424 initRetry );
425 f_env.enableEnv( envIntEnable );
426
427 //Set the Denali lane skew
428 setLaneSkew();
429
430/* N2
431 if ( usePCIE )
432 {
433 fork
434 {
435 f_LPUXtr.collectTLP();
436 }
437 join none
438 }
439*/
440
441 // All done!
442 } /* end Execute */
443
444 task reBoot(){
445
446 //Initialize the csr's and handle reset
447 InitStrat = new ( Report,
448 Pod.CSRXtr.CSR,
449 Pod,
450 Scenario );
451 InitStrat.RetrainInit();
452 InitStrat.Execute();
453
454
455 //Enable the Interrupts
456 fork
457 f_env.monitorInt(1);
458 join none
459
460 //Set the Denali lane skew
461 setLaneSkew();
462 }
463
464 task slowClock( bit halfSpeed )
465 {
466//N2 review ENV_Control.slow <= halfSpeed; // Undriven means 200Mhz
467 return;
468 } // end slowClock //
469 task setClkSkew( integer skew )
470 {
471//N2 review ENV_Control.clkskew <= skew;
472 return;
473 } // end setClkSkew //
474 task setClkDrift( integer drift )
475 {
476//N2 review ENV_Control.clkdrift <= drift;
477 return;
478 } // end setClkDrift //
479 task setDriftPeriod( integer period )
480 {
481//N2 review ENV_Control.driftperiod <= period;
482 return;
483 } // end setDriftPeriod //
484
485 task setResetLength( integer clks )
486 {
487 return;
488 }
489 task setPostedCredits( integer hdr, integer data )
490 {
491 //N2 -Don't know if I still need these set so leave alone
492 initPostHdr = hdr;
493 initPostData = data;
494 //N2 -Also set the Scenario
495 Scenario.denaliInitialPostedHeaderCredit = hdr;
496 Scenario.denaliInitialPostedDataCredit = data;
497 //
498 return;
499 } // end setPostedCredits //
500 task setNonpostedCredits( integer hdr, integer data )
501 {
502 //N2 -Don't know if I still need these set so leave alone
503 initNpstHdr = hdr;
504 initNpstData = data;
505 //N2 -Also set the Scenario
506 Scenario.denaliInitialNonPostedHeaderCredit = hdr;
507 Scenario.denaliInitialNonPostedDataCredit = data;
508 return;
509 } // end setNonpostedCredits //
510 task setCompletionCredits( integer hdr, integer data )
511 {
512 //N2 -Don't know if I still need these set so leave alone
513 initCplnHdr = hdr;
514 initCplnData = data;
515 //N2 -Also set the Scenario
516 Scenario.denaliInitialCompletionHeaderCredit = hdr;
517 Scenario.denaliInitialCompletionDataCredit = data;
518 return;
519 } // end setCompletionCredits //
520 task setRetryCredits( integer retry )
521 {
522 if ( retry >= 512 )
523 initRetry = retry - (retry%16);
524 return;
525 } // end setRetryCredits //
526 task disableInterrupts()
527 {
528 envIntEnable = 0;
529 return;
530 } // end disableInterrupts //
531 task setPhyConfig( integer a_numPhyLanes = 8,
532 integer a_numActiveLanes = 8,
533 bit a_fastTrain = 1,
534 PECBool a_txEnableScramble = e_false,
535 PECBool a_rxEnableScramble = e_false
536 )
537 {
538 this._numPhyLanes = a_numPhyLanes;
539 this._numActiveLanes = a_numActiveLanes;
540 this._fastTrain = a_fastTrain;
541 this._txEnableScramble = a_txEnableScramble;
542 this._rxEnableScramble = a_rxEnableScramble;
543
544 // These are the timing parameters for fast and slow training
545 this._detect_txCycleQuantity = ( this._fastTrain ) ? 16 : 3000000;
546 this._polling_active_txCycles = ( this._fastTrain ) ? 16 : 1500;
547
548 return;
549 } // end setPhyConfig //
550 task getPhyConfig( var integer a_numPhyLanes,
551 var integer a_numActiveLanes,
552 var bit a_fastTrain,
553 var PECBool a_txEnableScramble,
554 var PECBool a_rxEnableScramble
555 )
556 {
557 a_numPhyLanes = this._numPhyLanes;
558 a_numActiveLanes = this._numActiveLanes;
559 a_fastTrain = this._fastTrain;
560 a_txEnableScramble = this._txEnableScramble;
561 a_rxEnableScramble = this._rxEnableScramble;
562 return;
563 } // end getPhyConfig //
564 /*
565 * getEnv - Return the initialized test environment
566 */
567 function PEUTestEnv getEnv()
568 {
569 getEnv = f_env;
570 } /* end getEnv */
571
572 task setLaneSkew(){
573
574 f_env.setDenaliLaneSkew( 0, 0, 0, 0,
575 Scenario.Lane0Skew );
576 f_env.setDenaliLaneSkew( 1, 0, 0, 0,
577 Scenario.Lane1Skew );
578 f_env.setDenaliLaneSkew( 2, 0, 0, 0,
579 Scenario.Lane2Skew );
580 f_env.setDenaliLaneSkew( 3, 0, 0, 0,
581 Scenario.Lane3Skew );
582 f_env.setDenaliLaneSkew( 4, 0, 0, 0,
583 Scenario.Lane4Skew );
584 f_env.setDenaliLaneSkew( 5, 0, 0, 0,
585 Scenario.Lane5Skew );
586 f_env.setDenaliLaneSkew( 6, 0, 0, 0,
587 Scenario.Lane6Skew );
588 f_env.setDenaliLaneSkew( 7, 0, 0, 0,
589 Scenario.Lane7Skew );
590 }
591
592 } /* end BootPEUStr */
Full OpenSPARC design & verification tarball including full HDL.