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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / N2str / ilupeuDmaURRdLkPEUStr.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilupeuDmaURRdLkPEUStr.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35class DmaURRdLkPEUStr extends DmaURBasePEUStr {
36
37
38 // ******************************************************************
39 // The Test Environment objects need to execute the strategy.
40 // ******************************************************************
41 local PEUTestEnv _env;
42 local integer _errQueue;
43
44
45 // ******************************************************************
46 // TLP Fields - These fields will be randomized using the parameters
47 // in the following section, and obeying the constraints defined
48 // within this class.
49 //
50 // Request & Completion Field Pairs
51 // ******************************************************************
52 local bit [1:0] _format_req;
53 local bit [1:0] _format_cpl;
54 local bit [4:0] _type_req;
55 local bit [4:0] _type_cpl;
56
57 local bit [2:0] _tc;
58
59 local bit _td_req;
60 local bit _td_cpl;
61 local bit _ep_req;
62 local bit _ep_cpl;
63
64 local bit [1:0] _attr;
65 local rand bit [9:0] _len_req;
66 local bit [9:0] _len_cpl;
67 local bit [15:0] _req_id;
68 local bit [7:0] _tag;
69 local rand bit [31:0] _addr_lsb;
70 local bit [31:0] _addr_msb;
71
72 local rand bit [3:0] _last_dwbe;
73 local rand bit [3:0] _first_dwbe;
74
75 local bit [15:0] _cpl_id;
76 local bit [2:0] _cpl_status;
77 local bit _bcm;
78 local bit [11:0] _byte_count;
79 local bit [6:0] _lower_addr;
80 local integer _data;
81
82
83 // ******************************************************************
84 // Constructor
85 // ******************************************************************
86 public task new(PEUTestEnv a_env, (integer a_errQueue = 'bx));
87
88
89 // ******************************************************************
90 // Execute the strategy.
91 // ******************************************************************
92 public task Execute();
93}
94
95
96
97//-------------------------------------------------------------------
98// Method Name:
99// Description:
100//-------------------------------------------------------------------
101task DmaURRdLkPEUStr::new(PEUTestEnv a_env, (integer a_errQueue = 'bx)) {
102
103
104 super.new(a_env);
105 this._env = a_env;
106 this._errQueue = a_errQueue;
107}
108
109
110
111//-------------------------------------------------------------------
112// Method Name:
113// Description:
114//-------------------------------------------------------------------
115task DmaURRdLkPEUStr::Execute() {
116
117
118 bit [PEC_PCI__HDR] reqHdr;
119 bit [PEC_PCI__HDR] cplHdr;
120
121
122 randcase {
123 1 : this._format_req = PEC_PCI__FMT_NO_DATA_3DW;
124 1 : this._format_req = PEC_PCI__FMT_NO_DATA_4DW;
125 }
126
127 this._format_cpl = PEC_PCI__FMT_NO_DATA_3DW;
128
129 this._type_req = PEC_PCI__TYPE_MEM_LK;
130 this._type_cpl = PEC_PCI__TYPE_CPL_LK;
131
132 //this._tc = urandom_range(3'b_111, 3'b_000);
133 this._tc = 3'b_000;
134
135 this._td_req = urandom_range(1'b_1, 1'b_0);
136 this._td_cpl = 1'b_0;
137
138 randcase {
139 this._ep_req_prob_false : this._ep_req = 1'b_0;
140 this._ep_req_prob_true : this._ep_req = 1'b_1;
141 }
142
143 this._ep_cpl = 1'b_0;
144
145 this._attr = urandom_range(2'b_11, 2'b_00);
146 this._len_req = urandom_range(1023,0);
147 this._len_cpl = 10'h_0;
148 this._req_id = urandom_range(16'h_FFFF, 16'h_0001);
149 //Denali can hold a TLP from being transmitted if a previous TLP
150 // with the same tag and Request ID has not completed yet. This only
151 // should happen with error TLPs. To help with this make all bad REQs
152 // PEC_PCI__REQ_ID[0] = 1
153 this._req_id[0] = 1'b1;
154
155 //this._tag = urandom_range(8'h_FF, 8'h_00);
156 _env.allocDmaTag( this._tag );
157 this._addr_lsb = urandom();
158 this._addr_msb = urandom_range(32'h_FFFF_FFFF, 32'h_0000_0001);
159
160 this._addr_lsb[11:2] = 0;
161
162
163 randcase{
164 1:this._last_dwbe = 4'b0001;
165 1:this._last_dwbe = 4'b0011;
166 1:this._last_dwbe = 4'b0111;
167 1:this._last_dwbe = 4'b1111;
168 }
169 randcase{
170 1:this._first_dwbe = 4'b1000;
171 1:this._first_dwbe = 4'b1100;
172 1:this._first_dwbe = 4'b1110;
173 1:this._first_dwbe = 4'b1111;
174 }
175
176 this._cpl_id = 16'h_0000;
177 this._cpl_status = PEC_PCI__CPL_STATUS_UR;
178 this._bcm = urandom_range(1'h_1, 1'h_0);
179 this._byte_count = 12'h_004;
180 this._lower_addr = 7'b_000_0000;
181
182 this._data = urandom_range(255, 0);
183
184 reqHdr [PEC_PCI__HDR] = {128{1'b_0}};
185 reqHdr [PEC_PCI__FMT] = this._format_req;
186 reqHdr [PEC_PCI__TYPE] = this._type_req;
187 reqHdr [PEC_PCI__TC] = this._tc;
188 reqHdr [PEC_PCI__TD] = this._td_req;
189 reqHdr [PEC_PCI__EP] = this._ep_req;
190 reqHdr [PEC_PCI__ATTR] = this._attr;
191 reqHdr [PEC_PCI__LEN] = this._len_req;
192 reqHdr [PEC_PCI__REQ_ID] = this._req_id;
193 reqHdr [PEC_PCI__TLP_TAG] = this._tag;
194 reqHdr [PEC_PCI__LAST_DWBE] = this._last_dwbe;
195 reqHdr [PEC_PCI__FIRST_DWBE] = this._first_dwbe;
196 reqHdr [PEC_PCI__ADDR] = (this._format_req[0] === 1'b1) ?
197 ({this._addr_msb, this._addr_lsb[31:2], 2'b_00}) :
198 ({this._addr_lsb[31:2], 2'b_00, 32'h_0000_0000});
199printf( "len=%h addr=%h\n", reqHdr[PEC_PCI__LEN], reqHdr[PEC_PCI__ADDR] );
200
201 cplHdr [PEC_PCI__HDR] = {128{1'b_0}};
202 cplHdr [PEC_PCI__FMT] = this._format_cpl;
203 cplHdr [PEC_PCI__TYPE] = this._type_cpl;
204 cplHdr [PEC_PCI__TC] = this._tc;
205 cplHdr [PEC_PCI__TD] = this._td_cpl;
206 cplHdr [PEC_PCI__EP] = this._ep_cpl;
207 cplHdr [PEC_PCI__ATTR] = this._attr;
208 cplHdr [PEC_PCI__LEN] = this._len_cpl;
209 cplHdr [PEC_PCI__CPL_ID] = this._cpl_id;
210 cplHdr [PEC_PCI__CPL_STATUS] = this._cpl_status;
211 cplHdr [PEC_PCI__BCM] = this._bcm;
212 cplHdr [PEC_PCI__BYTECOUNT] = this._byte_count;
213 cplHdr [PEC_PCI__CPL_REQ_ID] = this._req_id;
214 cplHdr [PEC_PCI__CPL_TAG] = this._tag;
215 cplHdr [PEC_PCI__LOWADDR] = this._lower_addr;
216
217 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkReq );
218 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkEP );
219
220 if ( super.f_abortErrTlp )
221 {
222 this._env.drivePCIE(reqHdr, this._data, *, *, *, 1);
223 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkReq );
224 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkEP );
225 this._env.waitIngressLatency(reqHdr);
226 }
227 else
228 {
229 this._env.reserveIngressCredits(reqHdr);
230 this._env.drivePCIE(reqHdr, this._data);
231 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkReq );
232 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_MF_vlLkEP );
233 this._env.consumeIngressCredits(reqHdr);
234 this._env.expectILU(reqHdr, this._data);
235
236 mailbox_put(this._errQueue, e_ERR_ue_ur);
237 mailbox_put(this._errQueue, reqHdr );
238
239 this._env.driveILU(cplHdr, 0, this._data);
240 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLST_LKUR_2 );
241 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk32_2 );
242 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk64_2 );
243 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk32_2 );
244 this._env.Pod.FNXPCIEEnableTrans.tempSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk64_2 );
245 this._env.expectPCIE(cplHdr, this._data);
246 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLST_LKUR_2 );
247 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk32_2 );
248 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLBC_MRdLk64_2 );
249 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk32_2 );
250 this._env.Pod.FNXPCIEEnableTrans.unSuppressDenaliErr( PCIE_TL_NONFATAL_TLP_CPLLA_MRdLk64_2 );
251 }
252
253 _env.freeDmaTag( this._tag );
254}
Full OpenSPARC design & verification tarball including full HDL.