Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / N2str / ilupeuEhbErrPEUStr.vr
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1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilupeuEhbErrPEUStr.vr
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35class EhbErrPEUStr extends PEUStrBase
36 {
37 integer f_errQueue; // A mailbox for bad pkt headers
38 integer f_len; // The packet's payload length
39 bit f_lenSpecified; // Was a length specified?
40 bit[4:0] f_type; // The packet's type
41 bit f_typeSpecified; // Was a type specified?
42 bit[3:0] f_mask; // Which bits to flip?
43
44 task new( PEUTestEnv a_env )
45 {
46 super.new( a_env );
47 f_errQueue = 0;
48 f_lenSpecified = 0;
49 f_typeSpecified = 0;
50 f_mask = 4'b0;
51 }
52
53 task SetErrQueue( integer a_queue )
54 {
55 f_errQueue = a_queue;
56 } /* end SetErrQueue */
57
58 task SetLength( integer a_len )
59 {
60 f_len = a_len;
61 f_lenSpecified = 1;
62 } /* end SetLength */
63
64 task SetType( integer a_type )
65 {
66 f_type = a_type;
67 f_typeSpecified = 1;
68 } /* end SetType */
69
70 task SetMask( bit[3:0] a_mask )
71 {
72 f_mask = a_mask;
73 } /* end SetMask */
74
75 task Execute()
76 {
77 bit[PEC_PCI__HDR] egressHdr; // The egress TLP's header
78 integer egressData; // A payload descriptor
79 bit[7:0] tlpTag; // The tag for the TLP
80 bit[7:0] egressAddr; // The DOU starting address
81 bit[PEC_PCI__HDR] ingressHdr; // The ingress TLP's header
82 integer ingressData; // A payload descriptor
83 bit[3:0] errMask;
84 bit hdrOnly;
85
86 if ( f_mask != 0 )
87 errMask = f_mask;
88 else
89 errMask = urandom()%15 + 1;
90
91 if ( f_lenSpecified && f_len == 0 )
92 hdrOnly = 1;
93 else if ( f_lenSpecified )
94 hdrOnly = 0;
95 else
96 hdrOnly = urandom() % 2;
97
98
99 // Build a TLP, using the specified
100 // type and length, if any.
101 if ( !f_typeSpecified )
102 {
103 randcase
104 {
105 4 : { f_type = PEC_PCI__TYPE_MEM; {if( hdrOnly ) f_len = urandom()%4 + 1;
106 else f_len = urandom()%2 + 1;} }
107 1 : { f_type = PEC_PCI__TYPE_CFG0; f_len = 1; }
108 1 : { f_type = PEC_PCI__TYPE_CFG1; f_len = 1; }
109 1 : { f_type = PEC_PCI__TYPE_IO; f_len = 1; }
110 1 : { f_type = PEC_PCI__TYPE_CPL; f_len = urandom()%32 + 1; }
111 }
112 }
113
114 else if ( !f_lenSpecified || f_len == 0 )
115 {
116 if ( f_type == PEC_PCI__TYPE_CPL )
117 f_len = urandom()%32 + 1;
118 else if ( (f_type == PEC_PCI__TYPE_MEM) && hdrOnly )
119 f_len = urandom()%4 + 1;
120 else if ( (f_type == PEC_PCI__TYPE_MEM) && !hdrOnly )
121 f_len = urandom()%2 + 1;
122 else
123 f_len = 1;
124 }
125
126 // If a completion (with data) was
127 // requested, then base it on a DMA
128 // read request (which we won't submit).
129 if ( f_type == PEC_PCI__TYPE_CPL )
130 {
131 f_env.allocDmaTag( tlpTag );
132 f_env.genIngressRdReq( tlpTag, ingressHdr, ingressData, f_len );
133 f_env.genEgressCpl( ingressHdr, egressHdr, egressData );
134 f_env.allocCplData( ingressHdr[PEC_PCI__LEN],
135 egressHdr[PEC_PCI__LOWADDR],
136 egressAddr );
137 }
138
139 // If a PIO-write was requested,
140 // then get a tag and push a config
141 // write through, just to be sure that
142 // the tag isn't already in the pipe.
143 else if ( !hdrOnly )
144 {
145 f_env.allocWrTag( tlpTag, egressAddr );
146 f_env.genEgressWrReq( tlpTag, egressHdr, egressData,
147 1, PEC_PCI__TYPE_CFG0 );
148 f_env.driveILU( egressHdr, egressAddr, egressData );
149 f_env.expectPCIE( egressHdr, egressData );
150 f_env.genIngressCpl( egressHdr, ingressHdr, ingressData );
151 f_env.drivePCIE( ingressHdr, ingressData );
152 f_env.expectILU( ingressHdr, ingressData );
153 f_env.genEgressWrReq( tlpTag, egressHdr, egressData, f_len, f_type );
154 }
155
156 else
157 {
158 f_env.allocRdTag( tlpTag );
159 f_env.genEgressRdReq( tlpTag, egressHdr, egressData, f_len, f_type );
160 }
161
162 // Present the TLP to the ILU, and
163 // specify that parity errors are to
164 // be injected into the EHB.
165 // We aren't going to release the tag
166 // so that only one error is injected.
167 f_env.injectEHBerror( tlpTag, errMask );
168 f_env.driveILU( egressHdr, egressAddr, egressData );
169
170 // We can't expect the TLP from the TLU
171 // since it is corrupted. But we do
172 // expect to enter the "drain state".
173 f_env.enterDrainState();
174// fork
175// f_env.expectPCIE( egressHdr, egressData );
176// join none
177 f_env.waitDrainState();
178
179 // Tell the error-checker about this
180 // bad-boy.
181 if ( f_errQueue != 0 )
182 {
183 mailbox_put( f_errQueue, e_ERR_oe_ehp );
184 mailbox_put( f_errQueue, 128'hx );
185 }
186
187 } /* end Execute */
188 } /* end EhbErrPEUStr */