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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / csrtool / cib_a.csr_define.vri
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: cib_a.csr_define.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#ifndef CIB_A_CSR_DEFINE
36#define CIB_A_CSR_DEFINE
37
38//-------------------------------------------------------
39//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN
40//-------------------------------------------------------
41
42`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ADDR 27'b000000011001010001000000000
43`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR 30'b000000011001010001000000000000
44`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_en"
45`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_WIDTH 64
46`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_DEPTH 1
47`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SLC 63:0
48`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_INT_SLC 63:0
49`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POSITION 0
50`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_en"
51`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_LOW_ADDR_WIDTH 0
52`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ADDR_RANGE 26:0
53`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000011110000
54`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
55`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000011110000
56`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
57`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
58`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
59`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
60`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_RMASK 64'b0000000000000000000000000000000000000000000000000000000011110000
61`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111100001111
62`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
63`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000011110000
64`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_INTERNAL_REG 1
65`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ALIASED_FROM 0
66`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_ZERO_TIME_OMNI 1
67`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_JTAG_RD 1
68`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_JTAG_WR 1
69`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_SLOW_RD 1
70`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_SLOW_WR 1
71`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_MED_RD 1
72`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_MED_WR 1
73`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_FAST_RD 1
74`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_HW_ACC_PIO_FAST_WR 1
75`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_NUM_FIELDS 4
76`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_FID 0
77`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_SLC 7:7
78`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_WIDTH 1
79`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_INT_SLC 0:0
80`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_POSITION 7
81`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
82`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
83`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_POR_VALUE 1'b1
84`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE3_FIELD_NAME "spare3"
85`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_FID 1
86`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_SLC 6:6
87`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_WIDTH 1
88`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_INT_SLC 0:0
89`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_POSITION 6
90`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
91`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
92`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_POR_VALUE 1'b1
93`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE2_FIELD_NAME "spare2"
94`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_FID 2
95`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_SLC 5:5
96`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_WIDTH 1
97`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_INT_SLC 0:0
98`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_POSITION 5
99`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
100`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
101`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_POR_VALUE 1'b1
102`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_SPARE1_FIELD_NAME "spare1"
103`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_FID 3
104`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_SLC 4:4
105`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_WIDTH 1
106`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_INT_SLC 0:0
107`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_POSITION 4
108`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
109`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
110`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_POR_VALUE 1'b1
111`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_EN_IHB_PE_FIELD_NAME "ihb_pe"
112
113//-------------------------------------------------------
114//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN
115//-------------------------------------------------------
116
117`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ADDR 27'b000000011001010001000000001
118`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR 30'b000000011001010001000000001000
119`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_NAME "fire_dlc_ilu_cib_csr_a_ilu_int_en"
120`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_WIDTH 64
121`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_DEPTH 1
122`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SLC 63:0
123`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_INT_SLC 63:0
124`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POSITION 0
125`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_int_en"
126`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_LOW_ADDR_WIDTH 0
127`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ADDR_RANGE 26:0
128`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
129`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
130`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_WRITE_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
131`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
132`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
133`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
134`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
135`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
136`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
137`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
138`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
139`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_INTERNAL_REG 1
140`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ALIASED_FROM 0
141`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_ZERO_TIME_OMNI 1
142`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_JTAG_RD 1
143`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_JTAG_WR 1
144`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_SLOW_RD 1
145`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_SLOW_WR 1
146`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_MED_RD 1
147`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_MED_WR 1
148`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_FAST_RD 1
149`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_HW_ACC_PIO_FAST_WR 1
150`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_NUM_FIELDS 8
151`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_FID 0
152`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_SLC 39:39
153`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_WIDTH 1
154`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_INT_SLC 0:0
155`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_POSITION 39
156`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
157`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
158`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_POR_VALUE 1'b0
159`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_S_FIELD_NAME "spare3_s"
160`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_FID 1
161`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_SLC 38:38
162`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_WIDTH 1
163`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_INT_SLC 0:0
164`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_POSITION 38
165`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
166`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
167`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_POR_VALUE 1'b0
168`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_S_FIELD_NAME "spare2_s"
169`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_FID 2
170`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_SLC 37:37
171`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_WIDTH 1
172`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_INT_SLC 0:0
173`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_POSITION 37
174`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
175`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
176`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_POR_VALUE 1'b0
177`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_S_FIELD_NAME "spare1_s"
178`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_FID 3
179`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_SLC 36:36
180`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_WIDTH 1
181`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_INT_SLC 0:0
182`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_POSITION 36
183`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
184`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
185`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_POR_VALUE 1'b0
186`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_S_FIELD_NAME "ihb_pe_s"
187`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_FID 4
188`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_SLC 7:7
189`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_WIDTH 1
190`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_INT_SLC 0:0
191`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_POSITION 7
192`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
193`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
194`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_POR_VALUE 1'b0
195`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE3_P_FIELD_NAME "spare3_p"
196`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_FID 5
197`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_SLC 6:6
198`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_WIDTH 1
199`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_INT_SLC 0:0
200`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_POSITION 6
201`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
202`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
203`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_POR_VALUE 1'b0
204`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE2_P_FIELD_NAME "spare2_p"
205`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_FID 6
206`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_SLC 5:5
207`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_WIDTH 1
208`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_INT_SLC 0:0
209`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_POSITION 5
210`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
211`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
212`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_POR_VALUE 1'b0
213`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_SPARE1_P_FIELD_NAME "spare1_p"
214`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_FID 7
215`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_SLC 4:4
216`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_WIDTH 1
217`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_INT_SLC 0:0
218`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_POSITION 4
219`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
220`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
221`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_POR_VALUE 1'b0
222`define FIRE_DLC_ILU_CIB_CSR_A_ILU_INT_EN_IHB_PE_P_FIELD_NAME "ihb_pe_p"
223
224//-------------------------------------------------------
225//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR
226//-------------------------------------------------------
227
228`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ADDR 27'b000000011001010001000000010
229`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR 30'b000000011001010001000000010000
230`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_NAME "fire_dlc_ilu_cib_csr_a_ilu_en_err"
231`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_WIDTH 64
232`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_DEPTH 1
233`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SLC 63:0
234`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_INT_SLC 63:0
235`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POSITION 0
236`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_en_err"
237`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_LOW_ADDR_WIDTH 0
238`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ADDR_RANGE 26:0
239`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
240`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_READ_ONLY_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
241`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
242`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
243`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
244`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
245`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
246`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
247`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
248`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
249`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
250`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_INTERNAL_REG 0
251`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_EXTERNAL_DECODE_REG 1
252`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ALIASED_FROM 0
253`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_ZERO_TIME_OMNI 0
254`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_JTAG_RD 1
255`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_JTAG_WR 1
256`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_SLOW_RD 1
257`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_SLOW_WR 1
258`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_MED_RD 1
259`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_MED_WR 1
260`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_FAST_RD 1
261`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_HW_ACC_PIO_FAST_WR 1
262`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_NUM_FIELDS 8
263`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_FID 0
264`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_SLC 39:39
265`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_WIDTH 1
266`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_INT_SLC 0:0
267`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_POSITION 39
268`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
269`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
270`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_POR_VALUE 1'b0
271`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_S_FIELD_NAME "spare3_s"
272`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_FID 1
273`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_SLC 38:38
274`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_WIDTH 1
275`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_INT_SLC 0:0
276`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_POSITION 38
277`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
278`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
279`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_POR_VALUE 1'b0
280`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_S_FIELD_NAME "spare2_s"
281`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_FID 2
282`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_SLC 37:37
283`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_WIDTH 1
284`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_INT_SLC 0:0
285`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_POSITION 37
286`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
287`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
288`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_POR_VALUE 1'b0
289`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_S_FIELD_NAME "spare1_s"
290`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_FID 3
291`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_SLC 36:36
292`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_WIDTH 1
293`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_INT_SLC 0:0
294`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_POSITION 36
295`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
296`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
297`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_POR_VALUE 1'b0
298`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_S_FIELD_NAME "ihb_pe_s"
299`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_FID 4
300`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_SLC 7:7
301`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_WIDTH 1
302`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_INT_SLC 0:0
303`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_POSITION 7
304`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
305`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
306`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_POR_VALUE 1'b0
307`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE3_P_FIELD_NAME "spare3_p"
308`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_FID 5
309`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_SLC 6:6
310`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_WIDTH 1
311`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_INT_SLC 0:0
312`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_POSITION 6
313`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
314`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
315`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_POR_VALUE 1'b0
316`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE2_P_FIELD_NAME "spare2_p"
317`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_FID 6
318`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_SLC 5:5
319`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_WIDTH 1
320`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_INT_SLC 0:0
321`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_POSITION 5
322`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
323`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
324`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_POR_VALUE 1'b0
325`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_SPARE1_P_FIELD_NAME "spare1_p"
326`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_FID 7
327`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_SLC 4:4
328`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_WIDTH 1
329`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_INT_SLC 0:0
330`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_POSITION 4
331`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
332`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
333`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_POR_VALUE 1'b0
334`define FIRE_DLC_ILU_CIB_CSR_A_ILU_EN_ERR_IHB_PE_P_FIELD_NAME "ihb_pe_p"
335
336//-------------------------------------------------------
337//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS
338//-------------------------------------------------------
339
340`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ADDR 27'b000000011001010001000000011
341`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR 30'b000000011001010001000000011000
342`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_err_rw1c_alias"
343`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_WIDTH 64
344`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_DEPTH 1
345`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SLC 63:0
346`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_INT_SLC 63:0
347`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POSITION 0
348`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_err_rw1c_alias"
349`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_LOW_ADDR_WIDTH 0
350`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ADDR_RANGE 26:0
351`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
352`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
353`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
354`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
355`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
356`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_CLEAR_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
357`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
358`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
359`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
360`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_LD_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
361`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
362`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_INTERNAL_REG 1
363`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ALIASED_FROM 0
364`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_ZERO_TIME_OMNI 1
365`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_JTAG_RD 1
366`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_JTAG_WR 1
367`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_SLOW_RD 1
368`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_SLOW_WR 1
369`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_MED_RD 1
370`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_MED_WR 1
371`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_FAST_RD 1
372`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_HW_ACC_PIO_FAST_WR 1
373`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_NUM_FIELDS 8
374`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FID 0
375`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_SLC 39:39
376`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_WIDTH 1
377`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_INT_SLC 0:0
378`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POSITION 39
379`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
380`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
381`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_POR_VALUE 1'b0
382`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_S_FIELD_NAME "spare3_s"
383`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FID 1
384`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_SLC 38:38
385`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_WIDTH 1
386`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_INT_SLC 0:0
387`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POSITION 38
388`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
389`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
390`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_POR_VALUE 1'b0
391`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_S_FIELD_NAME "spare2_s"
392`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FID 2
393`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_SLC 37:37
394`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_WIDTH 1
395`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_INT_SLC 0:0
396`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POSITION 37
397`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
398`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
399`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_POR_VALUE 1'b0
400`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_S_FIELD_NAME "spare1_s"
401`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FID 3
402`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_SLC 36:36
403`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_WIDTH 1
404`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_INT_SLC 0:0
405`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POSITION 36
406`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
407`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
408`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_POR_VALUE 1'b0
409`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_S_FIELD_NAME "ihb_pe_s"
410`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FID 4
411`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_SLC 7:7
412`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_WIDTH 1
413`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_INT_SLC 0:0
414`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POSITION 7
415`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
416`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
417`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_POR_VALUE 1'b0
418`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE3_P_FIELD_NAME "spare3_p"
419`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FID 5
420`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_SLC 6:6
421`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_WIDTH 1
422`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_INT_SLC 0:0
423`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POSITION 6
424`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
425`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
426`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_POR_VALUE 1'b0
427`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE2_P_FIELD_NAME "spare2_p"
428`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FID 6
429`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_SLC 5:5
430`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_WIDTH 1
431`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_INT_SLC 0:0
432`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POSITION 5
433`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
434`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
435`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_POR_VALUE 1'b0
436`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_SPARE1_P_FIELD_NAME "spare1_p"
437`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FID 7
438`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_SLC 4:4
439`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_WIDTH 1
440`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_INT_SLC 0:0
441`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POSITION 4
442`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
443`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
444`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_POR_VALUE 1'b0
445`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1C_ALIAS_IHB_PE_P_FIELD_NAME "ihb_pe_p"
446
447//-------------------------------------------------------
448//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS
449//-------------------------------------------------------
450
451`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ADDR 27'b000000011001010001000000100
452`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR 30'b000000011001010001000000100000
453`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_err_rw1s_alias"
454`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WIDTH 64
455`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_DEPTH 1
456`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SLC 63:0
457`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_INT_SLC 63:0
458`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POSITION 0
459`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_log_err_rw1s_alias"
460`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_LOW_ADDR_WIDTH 0
461`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ADDR_RANGE 26:0
462`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_READ_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
463`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
464`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
465`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
466`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SET_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
467`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
468`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
469`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_RMASK 64'b0000000000000000000000001111000000000000000000000000000011110000
470`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_RESERVED_BIT_MASK 64'b1111111111111111111111110000111111111111111111111111111100001111
471`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_LD_MASK 64'b0000000000000000000000001111000000000000000000000000000011110000
472`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
473`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_INTERNAL_REG 1
474`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ALIASED_FROM "fire_dlc_ilu_cib_csr_a_ilu_log_err_rw1c_alias"
475`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_ZERO_TIME_OMNI 1
476`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_JTAG_RD 1
477`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_JTAG_WR 1
478`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_SLOW_RD 1
479`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_SLOW_WR 1
480`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_MED_RD 1
481`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_MED_WR 1
482`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_FAST_RD 1
483`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_HW_ACC_PIO_FAST_WR 1
484`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_NUM_FIELDS 8
485`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FID 0
486`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_SLC 39:39
487`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_WIDTH 1
488`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_INT_SLC 0:0
489`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POSITION 39
490`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
491`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
492`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_POR_VALUE 1'b0
493`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_S_FIELD_NAME "spare3_s"
494`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FID 1
495`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_SLC 38:38
496`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_WIDTH 1
497`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_INT_SLC 0:0
498`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POSITION 38
499`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
500`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
501`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_POR_VALUE 1'b0
502`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_S_FIELD_NAME "spare2_s"
503`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FID 2
504`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_SLC 37:37
505`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_WIDTH 1
506`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_INT_SLC 0:0
507`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POSITION 37
508`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
509`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
510`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_POR_VALUE 1'b0
511`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_S_FIELD_NAME "spare1_s"
512`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FID 3
513`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_SLC 36:36
514`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_WIDTH 1
515`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_INT_SLC 0:0
516`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POSITION 36
517`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
518`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
519`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_POR_VALUE 1'b0
520`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_S_FIELD_NAME "ihb_pe_s"
521`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FID 4
522`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_SLC 7:7
523`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_WIDTH 1
524`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_INT_SLC 0:0
525`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POSITION 7
526`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
527`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
528`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_POR_VALUE 1'b0
529`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE3_P_FIELD_NAME "spare3_p"
530`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FID 5
531`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_SLC 6:6
532`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_WIDTH 1
533`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_INT_SLC 0:0
534`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POSITION 6
535`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
536`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
537`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_POR_VALUE 1'b0
538`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE2_P_FIELD_NAME "spare2_p"
539`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FID 6
540`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_SLC 5:5
541`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_WIDTH 1
542`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_INT_SLC 0:0
543`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POSITION 5
544`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
545`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
546`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_POR_VALUE 1'b0
547`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_SPARE1_P_FIELD_NAME "spare1_p"
548`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FID 7
549`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_SLC 4:4
550`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_WIDTH 1
551`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_INT_SLC 0:0
552`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POSITION 4
553`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
554`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
555`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_POR_VALUE 1'b0
556`define FIRE_DLC_ILU_CIB_CSR_A_ILU_LOG_ERR_RW1S_ALIAS_IHB_PE_P_FIELD_NAME "ihb_pe_p"
557
558//-------------------------------------------------------
559//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN
560//-------------------------------------------------------
561
562`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ADDR 27'b000000011001010001100000000
563`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR 30'b000000011001010001100000000000
564`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_NAME "fire_dlc_ilu_cib_csr_a_pec_int_en"
565`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_WIDTH 64
566`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_DEPTH 1
567`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_SLC 63:0
568`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_INT_SLC 63:0
569`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POSITION 0
570`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_FIELD_NAME "fire_dlc_ilu_cib_csr_a_pec_int_en"
571`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_LOW_ADDR_WIDTH 0
572`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ADDR_RANGE 26:0
573`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_READ_MASK 64'b1000000000000000000000000000000000000000000000000000000000001111
574`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
575`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_WRITE_MASK 64'b1000000000000000000000000000000000000000000000000000000000001111
576`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
577`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
578`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
579`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
580`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_RMASK 64'b1000000000000000000000000000000000000000000000000000000000001111
581`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_RESERVED_BIT_MASK 64'b0111111111111111111111111111111111111111111111111111111111110000
582`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
583`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
584`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_INTERNAL_REG 1
585`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ALIASED_FROM 0
586`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_ZERO_TIME_OMNI 1
587`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_JTAG_RD 1
588`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_JTAG_WR 1
589`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_SLOW_RD 1
590`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_SLOW_WR 1
591`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_MED_RD 1
592`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_MED_WR 1
593`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_FAST_RD 1
594`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_HW_ACC_PIO_FAST_WR 1
595`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_NUM_FIELDS 5
596`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_FID 0
597`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_SLC 63:63
598`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_WIDTH 1
599`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_INT_SLC 0:0
600`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_POSITION 63
601`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000
602`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
603`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_POR_VALUE 1'b0
604`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_FIELD_NAME "pec"
605`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_FID 1
606`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_SLC 3:3
607`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_WIDTH 1
608`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_INT_SLC 0:0
609`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_POSITION 3
610`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
611`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
612`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_POR_VALUE 1'b0
613`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_ILU_FIELD_NAME "pec_ilu"
614`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_FID 2
615`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_SLC 2:2
616`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_WIDTH 1
617`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_INT_SLC 0:0
618`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_POSITION 2
619`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
620`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
621`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_POR_VALUE 1'b0
622`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_UE_FIELD_NAME "pec_ue"
623`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_FID 3
624`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_SLC 1:1
625`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_WIDTH 1
626`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_INT_SLC 0:0
627`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_POSITION 1
628`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
629`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
630`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_POR_VALUE 1'b0
631`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_CE_FIELD_NAME "pec_ce"
632`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_FID 4
633`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_SLC 0:0
634`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_WIDTH 1
635`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_INT_SLC 0:0
636`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_POSITION 0
637`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
638`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
639`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_POR_VALUE 1'b0
640`define FIRE_DLC_ILU_CIB_CSR_A_PEC_INT_EN_PEC_OE_FIELD_NAME "pec_oe"
641
642//-------------------------------------------------------
643//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR
644//-------------------------------------------------------
645
646`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ADDR 27'b000000011001010001100000001
647`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR 30'b000000011001010001100000001000
648`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_NAME "fire_dlc_ilu_cib_csr_a_pec_en_err"
649`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_WIDTH 64
650`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_DEPTH 1
651`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_SLC 63:0
652`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_INT_SLC 63:0
653`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POSITION 0
654`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_FIELD_NAME "fire_dlc_ilu_cib_csr_a_pec_en_err"
655`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_LOW_ADDR_WIDTH 0
656`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ADDR_RANGE 26:0
657`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
658`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111
659`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
660`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
661`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
662`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
663`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
664`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_RMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
665`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111110000
666`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
667`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
668`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_INTERNAL_REG 0
669`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_EXTERNAL_DECODE_REG 1
670`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ALIASED_FROM 0
671`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ZERO_TIME_OMNI 0
672`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_JTAG_RD 1
673`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_JTAG_WR 1
674`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_SLOW_RD 1
675`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_SLOW_WR 1
676`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_MED_RD 1
677`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_MED_WR 1
678`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_FAST_RD 1
679`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_HW_ACC_PIO_FAST_WR 1
680`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_NUM_FIELDS 4
681`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_FID 0
682`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_SLC 3:3
683`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_WIDTH 1
684`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_INT_SLC 0:0
685`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_POSITION 3
686`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
687`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
688`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_POR_VALUE 1'b0
689`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_ILU_FIELD_NAME "ilu"
690`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_FID 1
691`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_SLC 2:2
692`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_WIDTH 1
693`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_INT_SLC 0:0
694`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_POSITION 2
695`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
696`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
697`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_POR_VALUE 1'b0
698`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_UE_FIELD_NAME "ue"
699`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_FID 2
700`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_SLC 1:1
701`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_WIDTH 1
702`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_INT_SLC 0:0
703`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_POSITION 1
704`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
705`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
706`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_POR_VALUE 1'b0
707`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_CE_FIELD_NAME "ce"
708`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_FID 3
709`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_SLC 0:0
710`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_WIDTH 1
711`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_INT_SLC 0:0
712`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_POSITION 0
713`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
714`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
715`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_POR_VALUE 1'b0
716`define FIRE_DLC_ILU_CIB_CSR_A_PEC_EN_ERR_OE_FIELD_NAME "oe"
717
718//-------------------------------------------------------
719//----- Variable definitions for register FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS
720//-------------------------------------------------------
721
722`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ADDR 27'b000000011001010010000000000
723`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR 30'b000000011001010010000000000000
724`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_NAME "fire_dlc_ilu_cib_csr_a_ilu_diagnos"
725`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_WIDTH 64
726`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_DEPTH 1
727`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_SLC 63:0
728`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_INT_SLC 63:0
729`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POSITION 0
730`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_FIELD_NAME "fire_dlc_ilu_cib_csr_a_ilu_diagnos"
731`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_LOW_ADDR_WIDTH 0
732`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ADDR_RANGE 26:0
733`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_READ_MASK 64'b0000000000000000000000000000001111111111111111111111111100111100
734`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
735`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_WRITE_MASK 64'b0000000000000000000000000000001111111111111111111111111100001100
736`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
737`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000110000
738`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
739`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
740`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RMASK 64'b0000000000000000000000000000001111111111111111111111111100111100
741`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RESERVED_BIT_MASK 64'b1111111111111111111111111111110000000000000000000000000011000011
742`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000110000
743`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_POR_VALUE 64'b0000000000000000000000000000001111111111111111110000000000000000
744`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_INTERNAL_REG 1
745`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ALIASED_FROM 0
746`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ZERO_TIME_OMNI 1
747`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_JTAG_RD 1
748`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_JTAG_WR 1
749`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_SLOW_RD 1
750`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_SLOW_WR 1
751`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_MED_RD 1
752`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_MED_WR 1
753`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_FAST_RD 1
754`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_HW_ACC_PIO_FAST_WR 1
755`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_NUM_FIELDS 23
756`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_FID 0
757`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_SLC 33:33
758`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_WIDTH 1
759`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_INT_SLC 0:0
760`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_POSITION 33
761`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
762`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
763`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_POR_VALUE 1'b1
764`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL1_FIELD_NAME "enpll1"
765`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_FID 1
766`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_SLC 32:32
767`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_WIDTH 1
768`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_INT_SLC 0:0
769`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_POSITION 32
770`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
771`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
772`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_POR_VALUE 1'b1
773`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENPLL0_FIELD_NAME "enpll0"
774`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_FID 2
775`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_SLC 31:31
776`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_WIDTH 1
777`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_INT_SLC 0:0
778`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_POSITION 31
779`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000
780`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
781`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_POR_VALUE 1'b1
782`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX7_FIELD_NAME "entx7"
783`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_FID 3
784`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_SLC 30:30
785`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_WIDTH 1
786`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_INT_SLC 0:0
787`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_POSITION 30
788`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_FMASK 64'b0000000000000000000000000000000001000000000000000000000000000000
789`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
790`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_POR_VALUE 1'b1
791`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX6_FIELD_NAME "entx6"
792`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_FID 4
793`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_SLC 29:29
794`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_WIDTH 1
795`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_INT_SLC 0:0
796`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_POSITION 29
797`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_FMASK 64'b0000000000000000000000000000000000100000000000000000000000000000
798`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
799`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_POR_VALUE 1'b1
800`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX5_FIELD_NAME "entx5"
801`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_FID 5
802`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_SLC 28:28
803`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_WIDTH 1
804`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_INT_SLC 0:0
805`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_POSITION 28
806`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_FMASK 64'b0000000000000000000000000000000000010000000000000000000000000000
807`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
808`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_POR_VALUE 1'b1
809`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX4_FIELD_NAME "entx4"
810`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_FID 6
811`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_SLC 27:27
812`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_WIDTH 1
813`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_INT_SLC 0:0
814`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_POSITION 27
815`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_FMASK 64'b0000000000000000000000000000000000001000000000000000000000000000
816`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
817`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_POR_VALUE 1'b1
818`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX3_FIELD_NAME "entx3"
819`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_FID 7
820`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_SLC 26:26
821`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_WIDTH 1
822`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_INT_SLC 0:0
823`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_POSITION 26
824`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_FMASK 64'b0000000000000000000000000000000000000100000000000000000000000000
825`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
826`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_POR_VALUE 1'b1
827`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX2_FIELD_NAME "entx2"
828`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_FID 8
829`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_SLC 25:25
830`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_WIDTH 1
831`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_INT_SLC 0:0
832`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_POSITION 25
833`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_FMASK 64'b0000000000000000000000000000000000000010000000000000000000000000
834`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
835`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_POR_VALUE 1'b1
836`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX1_FIELD_NAME "entx1"
837`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_FID 9
838`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_SLC 24:24
839`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_WIDTH 1
840`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_INT_SLC 0:0
841`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_POSITION 24
842`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_FMASK 64'b0000000000000000000000000000000000000001000000000000000000000000
843`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
844`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_POR_VALUE 1'b1
845`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENTX0_FIELD_NAME "entx0"
846`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_FID 10
847`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_SLC 23:23
848`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_WIDTH 1
849`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_INT_SLC 0:0
850`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_POSITION 23
851`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_FMASK 64'b0000000000000000000000000000000000000000100000000000000000000000
852`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
853`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_POR_VALUE 1'b1
854`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX7_FIELD_NAME "enrx7"
855`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_FID 11
856`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_SLC 22:22
857`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_WIDTH 1
858`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_INT_SLC 0:0
859`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_POSITION 22
860`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_FMASK 64'b0000000000000000000000000000000000000000010000000000000000000000
861`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
862`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_POR_VALUE 1'b1
863`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX6_FIELD_NAME "enrx6"
864`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_FID 12
865`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_SLC 21:21
866`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_WIDTH 1
867`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_INT_SLC 0:0
868`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_POSITION 21
869`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_FMASK 64'b0000000000000000000000000000000000000000001000000000000000000000
870`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
871`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_POR_VALUE 1'b1
872`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX5_FIELD_NAME "enrx5"
873`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_FID 13
874`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_SLC 20:20
875`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_WIDTH 1
876`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_INT_SLC 0:0
877`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_POSITION 20
878`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
879`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
880`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_POR_VALUE 1'b1
881`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX4_FIELD_NAME "enrx4"
882`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_FID 14
883`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_SLC 19:19
884`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_WIDTH 1
885`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_INT_SLC 0:0
886`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_POSITION 19
887`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
888`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
889`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_POR_VALUE 1'b1
890`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX3_FIELD_NAME "enrx3"
891`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_FID 15
892`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_SLC 18:18
893`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_WIDTH 1
894`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_INT_SLC 0:0
895`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_POSITION 18
896`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
897`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
898`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_POR_VALUE 1'b1
899`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX2_FIELD_NAME "enrx2"
900`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_FID 16
901`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_SLC 17:17
902`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_WIDTH 1
903`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_INT_SLC 0:0
904`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_POSITION 17
905`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
906`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
907`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_POR_VALUE 1'b1
908`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX1_FIELD_NAME "enrx1"
909`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_FID 17
910`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_SLC 16:16
911`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_WIDTH 1
912`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_INT_SLC 0:0
913`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_POSITION 16
914`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
915`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
916`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_POR_VALUE 1'b1
917`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_ENRX0_FIELD_NAME "enrx0"
918`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_FID 18
919`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_SLC 15:12
920`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_WIDTH 4
921`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_INT_SLC 3:0
922`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_POSITION 12
923`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_FMASK 64'b0000000000000000000000000000000000000000000000001111000000000000
924`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
925`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_POR_VALUE 4'b0000
926`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_PAR_FIELD_NAME "edi_par"
927`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_FID 19
928`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_SLC 11:8
929`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_WIDTH 4
930`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_INT_SLC 3:0
931`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_POSITION 8
932`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_FMASK 64'b0000000000000000000000000000000000000000000000000000111100000000
933`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
934`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_POR_VALUE 4'b0000
935`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_PAR_FIELD_NAME "ehi_par"
936`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_FID 20
937`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_SLC 5:5
938`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_WIDTH 1
939`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_INT_SLC 0:0
940`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_POSITION 5
941`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
942`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
943`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_POR_VALUE 1'b0
944`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EDI_TRIG_FIELD_NAME "edi_trig"
945`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_FID 21
946`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_SLC 4:4
947`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_WIDTH 1
948`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_INT_SLC 0:0
949`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_POSITION 4
950`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
951`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
952`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_POR_VALUE 1'b0
953`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_EHI_TRIG_FIELD_NAME "ehi_trig"
954`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_FID 22
955`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_SLC 3:2
956`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_WIDTH 2
957`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_INT_SLC 1:0
958`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_POSITION 2
959`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001100
960`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
961`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_POR_VALUE 2'b00
962`define FIRE_DLC_ILU_CIB_CSR_A_ILU_DIAGNOS_RATE_SCALE_FIELD_NAME "rate_scale"
963
964
965#endif
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