projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: ilu_peu.if.vri | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | #ifndef ILU_PEU_IF_VRI | |
| 36 | #define ILU_PEU_IF_VRI | |
| 37 | ||
| 38 | #include "top_defines.vri" | |
| 39 | //#include "dmu.h" | |
| 40 | ||
| 41 | interface if_ILU_PEU { | |
| 42 | //------------------------------------------------------------------------ | |
| 43 | // Clock and Reset Signals | |
| 44 | //------------------------------------------------------------------------ | |
| 45 | #ifdef N2_FC | |
| 46 | #ifdef DMU_GATE | |
| 47 | input iol2clk CLOCK verilog_node "`DMU.iol2clk";// inputclock 375 MHz | |
| 48 | input j2d_por_l INPUT_EDGE INPUT_SKEW verilog_node "`DMU.rst_por_"; | |
| 49 | input j2d_rst_l INPUT_EDGE INPUT_SKEW verilog_node "`DMU.rst_wmr_"; | |
| 50 | #else | |
| 51 | input iol2clk CLOCK verilog_node "`ILU.l1clk";// inputclock 375 MHz | |
| 52 | input j2d_por_l INPUT_EDGE INPUT_SKEW verilog_node "`PEU.rst_por_"; | |
| 53 | input j2d_rst_l INPUT_EDGE INPUT_SKEW verilog_node "`PEU.rst_wmr_"; | |
| 54 | #endif // DMU_GATE | |
| 55 | #else | |
| 56 | input iol2clk CLOCK;// inputclock 375 MHz | |
| 57 | ||
| 58 | output j2d_por_l OUTPUT_EDGE OUTPUT_SKEW verilog_node "`PEU.rst_por_"; | |
| 59 | output j2d_rst_l OUTPUT_EDGE OUTPUT_SKEW verilog_node "`PEU.rst_wmr_"; | |
| 60 | ||
| 61 | #endif | |
| 62 | ||
| 63 | //------------------------------------------------------------------------ | |
| 64 | // data path - | |
| 65 | // note: k2y_buf_addr_vld_monitor & y2k_buf_addr_vld_monitor are added | |
| 66 | // for the use in DMU-ILU monitor only | |
| 67 | //------------------------------------------------------------------------ | |
| 68 | // output k2y_buf_addr_vld_monitor verilog_node "MAQ"; | |
| 69 | #ifndef N2_FC | |
| 70 | output [7:0] k2y_buf_addr OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_buf_addr";// read pointer to IDB | |
| 71 | output [127:0] k2y_buf_data OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_buf_data";// payload | |
| 72 | output [3:0] k2y_buf_dpar OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_buf_dpar";// word parity for the payload | |
| 73 | #endif | |
| 74 | #ifdef DMU_GATE | |
| 75 | input [127:0] y2k_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_data";// 16-byte data | |
| 76 | input [3:0] y2k_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_dpar";// data parity | |
| 77 | input [7:0] y2k_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_buf_addr";// read address to DOU | |
| 78 | #else | |
| 79 | input [127:0] y2k_buf_data INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_data";// 16-byte data | |
| 80 | input [3:0] y2k_buf_dpar INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_dpar";// data parity | |
| 81 | // input y2k_buf_addr_vld_monitor verilog_node "MAQ"; | |
| 82 | input [7:0] y2k_buf_addr INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_buf_addr";// read address to DOU | |
| 83 | #endif // DMU_GATE | |
| 84 | //------------------------------------------------------------------------ | |
| 85 | // record interface to TMU | |
| 86 | //------------------------------------------------------------------------ | |
| 87 | #ifndef N2_FC | |
| 88 | output k2y_rcd_deq OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_rcd_deq";// ingress record fifo dequeue | |
| 89 | output [125:0] k2y_rcd OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_rcd";// egress PEC rcd | |
| 90 | output k2y_rcd_enq OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_rcd_enq";// egress enqueue for PEC rcd | |
| 91 | #endif | |
| 92 | #ifdef DMU_GATE | |
| 93 | input [125:0] y2k_rcd INPUT_EDGE INPUT_SKEW verilog_node "{`DMU.y2k_rcd,10'h0}";// ingress PEC record | |
| 94 | input y2k_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rcd_enq";// ingress PEC record enqueue | |
| 95 | input y2k_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rcd_deq";// egress rcd fifo dequeue | |
| 96 | #else | |
| 97 | //DMU is 116 bits wide so add 10'b0 to LSB when hooking up to DMUXtr in ilu_peu_top.vcon | |
| 98 | input [125:0] y2k_rcd INPUT_EDGE INPUT_SKEW verilog_node "{`ILU.y2k_rcd,10'h0}";// ingress PEC record | |
| 99 | input y2k_rcd_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rcd_enq";// ingress PEC record enqueue | |
| 100 | input y2k_rcd_deq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rcd_deq";// egress rcd fifo dequeue | |
| 101 | #endif // DMU_GATE | |
| 102 | //------------------------------------------------------------------------ | |
| 103 | // release interface with TMU | |
| 104 | //------------------------------------------------------------------------ | |
| 105 | #ifndef N2_FC | |
| 106 | output [8:0] k2y_rel_rcd OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_rel_rcd";// ingress 1 PCIE FC data credit (16-byte data) w/ d_ptr | |
| 107 | output k2y_rel_enq OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_rel_enq"; // ingress enqueue for release record | |
| 108 | #endif | |
| 109 | #ifdef DMU_GATE | |
| 110 | input [8:0] y2k_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "{`DMU.ilu_eil_relgen_y2k_rel_rcd_reg_8_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_7_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_6_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_5_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_4_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_3_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_2_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_1_.q, `DMU.ilu_eil_relgen_y2k_rel_rcd_reg_0_.q}";//egress release rcd | |
| 111 | ||
| 112 | input y2k_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_rel_enq";// egress enqueue for release rcd | |
| 113 | #else | |
| 114 | ||
| 115 | input [8:0] y2k_rel_rcd INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rel_rcd";// egress release rcd | |
| 116 | input y2k_rel_enq INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_rel_enq";// egress enqueue for release rcd | |
| 117 | #endif // DMU_GATE | |
| 118 | //------------------------------------------------------------------------ | |
| 119 | // DOU DMA Rd Cpl Buffer status rcd interface with CLU | |
| 120 | //------------------------------------------------------------------------ | |
| 121 | #ifndef N2_FC | |
| 122 | output [5:0] k2y_dou_dptr OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_dou_dptr"; | |
| 123 | output k2y_dou_err OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_dou_err"; | |
| 124 | output k2y_dou_vld OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_dou_vld"; | |
| 125 | #endif | |
| 126 | //------------------------------------------------------------------------ | |
| 127 | // DMU misc. interface | |
| 128 | //------------------------------------------------------------------------ | |
| 129 | #ifdef DMU_GATE | |
| 130 | input [2:0] y2k_mps INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_mps";// max. payld size to CMU | |
| 131 | input y2k_int_l INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_int_l";// interrupt req to IMU | |
| 132 | input p2d_drain INPUT_EDGE INPUT_SKEW verilog_node "`DMU.p2d_drain"; // drain req to ILU | |
| 133 | #else | |
| 134 | input [2:0] y2k_mps INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_mps";// max. payld size to CMU | |
| 135 | input y2k_int_l INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_int_l";// interrupt req to IMU | |
| 136 | input p2d_drain INPUT_EDGE INPUT_SKEW verilog_node "`ILU.p2d_drain"; // drain req to ILU | |
| 137 | #endif // DMU_GATE | |
| 138 | ||
| 139 | //------------------------------------------------------------------------ | |
| 140 | // CSR ring to DMU | |
| 141 | //------------------------------------------------------------------------ | |
| 142 | #ifdef DMU_GATE | |
| 143 | output [31:0] k2y_csr_ring_out OUTPUT_EDGE OUTPUT_SKEW verilog_node "`DMU.k2y_csr_ring_out"; | |
| 144 | input [31:0] y2k_csr_ring_in INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_csr_ring_in"; | |
| 145 | #else | |
| 146 | output [31:0] k2y_csr_ring_out OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_csr_ring_out"; | |
| 147 | input [31:0] y2k_csr_ring_in INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_csr_ring_in"; | |
| 148 | #endif // DMU_GATE | |
| 149 | ||
| 150 | //------------------------------------------------------------------------ | |
| 151 | // debug ports | |
| 152 | //------------------------------------------------------------------------ | |
| 153 | #ifndef N2_FC | |
| 154 | output [5:0] k2y_dbg_sel_a OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_dbg_sel_a"; | |
| 155 | output [5:0] k2y_dbg_sel_b OUTPUT_EDGE OUTPUT_SKEW verilog_node "`ILU.k2y_dbg_sel_b"; | |
| 156 | #endif | |
| 157 | #ifdef DMU_GATE | |
| 158 | input [7:0] y2k_dbg_a INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_dbg_a"; | |
| 159 | input [7:0] y2k_dbg_b INPUT_EDGE INPUT_SKEW verilog_node "`DMU.y2k_dbg_b"; | |
| 160 | #else | |
| 161 | input [7:0] y2k_dbg_a INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_dbg_a"; | |
| 162 | input [7:0] y2k_dbg_b INPUT_EDGE INPUT_SKEW verilog_node "`ILU.y2k_dbg_b"; | |
| 163 | #endif // DMU_GATE | |
| 164 | } // end of interface if_ILU_PEU | |
| 165 | ||
| 166 | ||
| 167 | ||
| 168 | interface if_ILU_PEU_PCIE { | |
| 169 | //Clock | |
| 170 | input refclk CLOCK verilog_node "`TOP.PCIE_Clock_250";// inputclock 250 MHz | |
| 171 | // Denali Clocks | |
| 172 | // input DEN_CLK_TX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_CLK_TX"; | |
| 173 | input DEN_CLK_RX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_CLK_RX"; | |
| 174 | ||
| 175 | // Misc Port in FNXPCIEXactor | |
| 176 | output DEN_RESET OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.DEN_RESET"; | |
| 177 | ||
| 178 | //The Recieve Detect signals were used in FNX , Included here but not connected to N2 | |
| 179 | output RCV_DET_MODE OUTPUT_EDGE OUTPUT_SKEW;//1bit | |
| 180 | output [7:0] RCV_DET_LANES OUTPUT_EDGE OUTPUT_SKEW verilog_node "`TOP.RCV_DET_LANES"; //8bit | |
| 181 | output [7:0] ELEC_IDLE_LANES OUTPUT_EDGE OUTPUT_SKEW; //8bit | |
| 182 | // output [7:0] RCV_DET_LANES PRZ OUTPUT_SKEW verilog_node "`TOP.TX_P"; //8bit | |
| 183 | ||
| 184 | ||
| 185 | } // end of interface if_ILU_PEU | |
| 186 | ||
| 187 | interface if_ILU_PEU_PCIE_RX { | |
| 188 | //Clock | |
| 189 | input refclk CLOCK verilog_node "`TOP.DEN_CLK_TX";// inputclock 250 MHz | |
| 190 | // Denali Clocks | |
| 191 | input DEN_CLK_TX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.DEN_CLK_TX"; | |
| 192 | } | |
| 193 | ||
| 194 | ||
| 195 | #ifndef N2_FC | |
| 196 | #ifndef N2_IOS | |
| 197 | interface if_ILU_PEU_blunt_end_clock { | |
| 198 | // Clock | |
| 199 | input blunt_end_clock CLOCK verilog_node "`TOP.blunt_end_clock"; | |
| 200 | // RX and TX signals | |
| 201 | input [7:0] TX PSAMPLE verilog_node "`TOP.TX_P"; | |
| 202 | input [7:0] RX PSAMPLE verilog_node "`TOP.RX_P"; | |
| 203 | #ifndef PEU_SYSTEMC_T2 | |
| 204 | input [9:0] PSR_TX PSAMPLE verilog_node "`TOP.cpu.peu.peu_psr_td_b0sds0[9:0]"; | |
| 205 | input [9:0] PSR_RX PSAMPLE verilog_node "`TOP.cpu.peu.psr_peu_rd_b0sds0[9:0]"; | |
| 206 | #endif | |
| 207 | } | |
| 208 | #endif | |
| 209 | #endif | |
| 210 | ||
| 211 | interface if_denali_root_monitor_PCIE { | |
| 212 | //Clock | |
| 213 | input refclk CLOCK verilog_node "`TOP.PCIE_Clock_250";// inputclock 250 MHz | |
| 214 | // Denali Clocks | |
| 215 | input denali_root_monitor_CLK_TX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.denali_root_monitor_CLK_TX"; | |
| 216 | input denali_root_monitor_CLK_RX INPUT_EDGE INPUT_SKEW verilog_node "`TOP.denali_root_monitor_CLK_RX"; | |
| 217 | ||
| 218 | // Misc Port in FNXPCIEXactor | |
| 219 | input denali_root_monitor_RESET INPUT_EDGE INPUT_SKEW verilog_node "`TOP.denali_root_monitor_RESET"; | |
| 220 | ||
| 221 | ||
| 222 | } // end of interface if_ILU_PEU | |
| 223 | ||
| 224 | ||
| 225 | ||
| 226 | //Used for injecting errors to EHB | |
| 227 | interface EHB { | |
| 228 | input reqEmpty PSAMPLE #-1; | |
| 229 | input reqFull PSAMPLE #-1; | |
| 230 | input cplEmpty PSAMPLE #-1; | |
| 231 | input cplFull PSAMPLE #-1; | |
| 232 | output errReq PHOLD #1; | |
| 233 | output [3:0] errSel PHOLD #1; | |
| 234 | output [7:0] errTag PHOLD #1; | |
| 235 | input [127:0] errHdr PSAMPLE #-1; | |
| 236 | input errForced PSAMPLE #-1; | |
| 237 | input errAck PSAMPLE #-1; | |
| 238 | input clk CLOCK; } | |
| 239 | ||
| 240 | //Used for injecting errors to IHB | |
| 241 | interface IHB { | |
| 242 | input empty PSAMPLE #-1; | |
| 243 | input full PSAMPLE #-1; | |
| 244 | output errReq PHOLD #1; | |
| 245 | output [3:0] errSel PHOLD #1; | |
| 246 | output [7:0] errTag PHOLD #1; | |
| 247 | input errAck PSAMPLE #-1; | |
| 248 | input [127:0] errHdr PSAMPLE #-1; | |
| 249 | input errForced PSAMPLE #-1; | |
| 250 | input err PSAMPLE #-1; | |
| 251 | input clk CLOCK; } | |
| 252 | ||
| 253 | ||
| 254 | ||
| 255 | ||
| 256 | #endif // ILU_PEU_IF_VRI | |
| 257 | ||
| 258 |