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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / ilu_peu / vera / strategy / ilupeuTlpStrategyBase.vr
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ilupeuTlpStrategyBase.vr
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
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8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
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12//
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16// GNU General Public License for more details.
17//
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32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#include "CTStrategyBase.vrh"
36
37virtual class ilupeuTlpStrategyBase extends ilupeuStrategyBase {
38
39 //Inherited from ilupeuStrategyBase
40 //CSRCollection CSR;
41 //ReportClass Report;
42 //ilupeuPodClass Pod;
43 //ilupeuScenario Scenario;
44 //Random Utilities
45 //FNXRandomUtil RandUtil;
46
47 //Transaction and Packet Types
48 FNXPCIEXactorTransaction TlpTrans;
49 FNXPCIEXactorPacket TlpPkt;
50 bit [ILUPEU_TLP_HDR_WIDTH-1:0] tlpHdr = {ILUPEU_TLP_HDR_WIDTH{1'b0}};
51// LPUXtrDataTLP LPUXtrTlpPkt;
52
53 //Payload arrays
54 bit [7:0] pyldByteAry[*];
55 bit [31:0] pyldDWAry[*];
56 bit [31:0] pyldDW;
57 integer length;
58 integer xtrLen = 0;
59 integer dataSpec = 0;
60
61 //
62 bit [7:0] pyldFirstByteValue = 0;
63 bit [63:0] tlpAddr = 0;
64 bit address_set = 0;
65 integer tlp_type = 0;
66 bit tlp_type_set = 0;
67 bit [7:0] IOSReqTag;
68
69
70 bit uniqueTagSet = 0;
71 static integer unique_tag_region = alloc(REGION, 0, 1);
72 static integer unique_tag_semaphore = alloc(SEMAPHORE, 0, 1, 1);
73
74 bit Trans_Direction;
75
76 task new ( ReportClass _Report,
77 CSRCollection _CSR,
78 ilupeuPodClass _Pod , //Xactors
79 ilupeuScenario _Scenario ); //Test Parameters
80
81 task GenRandomPCIEXtrTlp( bit _Trans_Direction,
82 integer _DataSpec );
83 task ConvertPcieTlp2Hdr();
84 task ConvertHdr2LpuXtrTlpPkt();
85 function bit[FNX_PCIE_XTR_REQ_TAG_WIDTH-1:0] GenUniqueTag();
86 task FreeUniqueTag(bit[FNX_PCIE_XTR_REQ_TAG_WIDTH-1:0] unique_tag);
87
88 //Moved from DMUXtr 11/17/04 to make full chip easier
89 function bit[31:0] nextPayloadDW( var integer DataSpec );
90
91}
92
93// class constructor
94task ilupeuTlpStrategyBase::new( ReportClass _Report,
95 CSRCollection _CSR,
96 ilupeuPodClass _Pod,
97 ilupeuScenario _Scenario )
98{
99 super.new( _Report,
100 _CSR,
101 _Pod,
102 _Scenario );
103
104
105 //FNXPCIEXtr Transaction used to access Denali registers
106 regTrans = new( Pod.FNXPCIEBldr );
107
108}
109
110
111task ilupeuTlpStrategyBase::GenRandomPCIEXtrTlp( bit _Trans_Direction,
112 integer _DataSpec ){
113//review - add a GenPCIEXtrTlp that all parameters can be passed in for
114
115 integer i,j, pyldByteValue;
116 bit [31:0] dataDW;
117
118
119 //Set the initial payload byte value
120 pyldByteValue = _DataSpec;
121
122 TlpTrans = new( Pod.FNXPCIEBldr );
123 //Set up the CTTransactionID
124 TlpTrans.SetID( ID );
125
126
127 //Get the handle to the transaction packet
128 TlpPkt = TlpTrans.MyPacket;
129
130 //Set the fields that are common to all TLP packets first
131 Trans_Direction = _Trans_Direction;
132
133 TlpPkt.PktType = FNX_PCIE_XTR_PKT_TYPE_TLP;
134
135 //Determine the TLP type from test parameters
136 //and set the header CmnFmt and CmnType fields
137 if (tlp_type_set) {
138 TlpPkt.Set( "CmnFmtType", tlp_type);
139 } else {
140 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){
141 randcase{
142 Scenario.EgrTlpMRd32Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRD_32 );
143 Scenario.EgrTlpMRd64Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRD_64 );
144 Scenario.EgrTlpMRd32LkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRDLK_32 );
145 Scenario.EgrTlpMRd64LkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRDLK_64 );
146 Scenario.EgrTlpMWr32Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MWR_32 );
147 Scenario.EgrTlpMWr64Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MWR_64 );
148 Scenario.EgrTlpIORdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_IORD );
149 Scenario.EgrTlpIOWrWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_IOWR );
150 Scenario.EgrTlpCfgRd0Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGRD0 );
151 Scenario.EgrTlpCfgWr0Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGWR0 );
152 Scenario.EgrTlpCfgRd1Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGRD1 );
153 Scenario.EgrTlpCfgWr1Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGWR1 );
154 Scenario.EgrTlpMsgINTxWt:{ TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
155 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
156 //Set up the TlpPkt.CmnType using MsgRouting
157 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
158 randcase{
159 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_A;
160 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_B;
161 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_C;
162 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_D;
163 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_A;
164 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_B;
165 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_C;
166 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_D;
167 }
168 }
169 Scenario.EgrTlpMsgPMWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
170 randcase{
171 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PM_ACTIVE_STATE_NAK;
172 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
173 }
174 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PM_PME;
175 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX;
176 }
177 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PME_TURN_OFF;
178 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
179 }
180 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PME_TO_ACK;
181 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_GNR_TO_ROOT_CMPLX;
182 }
183 }
184 //Set up the TlpPkt.CmnType using MsgRouting
185 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
186 }
187 Scenario.EgrTlpMsgErrSigWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
188 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX;
189 //Set up the TlpPkt.CmnType using MsgRouting
190 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
191 randcase{
192 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_COR;
193 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_NONFATAL;
194 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_FATAL;
195 }
196 }
197 Scenario.EgrTlpMsgUnLkWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
198 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
199 //Set up the TlpPkt.CmnType using MsgRouting
200 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
201 TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_LOCK_UNLOCK;
202 }
203 Scenario.EgrTlpMsgHtPlgWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
204 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
205 //Set up the TlpPkt.CmnType using MsgRouting
206 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
207 randcase{
208 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_ON;
209 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_OFF;
210 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_BLINK;
211 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_PRESSED;
212 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_ON;
213 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_OFF;
214 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_BLINK;
215 }
216 }
217 Scenario.EgrTlpMsgDSltPwrLmtWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSGD );
218 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
219 //Set up the TlpPkt.CmnType using MsgRouting
220 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
221 TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_SLOT_POWER_LIMIT;
222 }
223 Scenario.EgrTlpMsgVendorDefWt: { randcase{
224 10: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
225 10: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSGD );
226 }
227 randcase{
228 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX;
229 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ID;
230 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
231 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
232 }
233 //Set up the TlpPkt.CmnType using MsgRouting
234 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
235 randcase{
236 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_VD_TYPE0;
237 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_VD_TYPE1;
238 }
239 }
240 Scenario.EgrTlpCplWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPL );
241 Scenario.EgrTlpCplDWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLD );
242 Scenario.EgrTlpCplLkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLLK );
243 Scenario.EgrTlpCplDLkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLDLK );
244
245 }
246 }
247 else{ //ILUPEU_INGRESS_TRANS
248 randcase{
249 Scenario.IngrTlpMRd32Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRD_32 );
250 Scenario.IngrTlpMRd64Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRD_64 );
251 Scenario.IngrTlpMRd32LkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRDLK_32 );
252 Scenario.IngrTlpMRd64LkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MRDLK_64 );
253 Scenario.IngrTlpMWr32Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MWR_32 );
254 Scenario.IngrTlpMWr64Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MWR_64 );
255 Scenario.IngrTlpIORdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_IORD );
256 Scenario.IngrTlpIOWrWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_IOWR );
257 Scenario.IngrTlpCfgRd0Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGRD0 );
258 Scenario.IngrTlpCfgWr0Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGWR0 );
259 Scenario.IngrTlpCfgRd1Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGRD1 );
260 Scenario.IngrTlpCfgWr1Wt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CFGWR1 );
261 Scenario.IngrTlpMsgINTxWt:{ TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
262 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
263 //Set up the TlpPkt.CmnType using MsgRouting
264 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
265 randcase{
266 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_A;
267 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_B;
268 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_C;
269 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_ASSERT_D;
270 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_A;
271 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_B;
272 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_C;
273 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_INTX_DEASSERT_D;
274 }
275 }
276 Scenario.IngrTlpMsgPMWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
277 randcase{
278 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PM_ACTIVE_STATE_NAK;
279 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
280 }
281 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PM_PME;
282 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX;
283 }
284 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PME_TURN_OFF;
285 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
286 }
287 10:{ TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_PME_TO_ACK;
288 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_GNR_TO_ROOT_CMPLX;
289 }
290 }
291 //Set up the TlpPkt.CmnType using MsgRouting
292 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
293 }
294 Scenario.IngrTlpMsgErrSigWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
295 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX;
296 //Set up the TlpPkt.CmnType using MsgRouting
297 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
298 randcase{
299 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_COR;
300 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_NONFATAL;
301 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_ERR_FATAL;
302 }
303 }
304 Scenario.IngrTlpMsgUnLkWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
305 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
306 //Set up the TlpPkt.CmnType using MsgRouting
307 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
308 TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_LOCK_UNLOCK;
309 }
310 Scenario.IngrTlpMsgHtPlgWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
311 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
312 //Set up the TlpPkt.CmnType using MsgRouting
313 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
314 randcase{
315 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_ON;
316 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_OFF;
317 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_POWER_BLINK;
318 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_PRESSED;
319 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_ON;
320 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_OFF;
321 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_HP_ATTENTION_BLINK;
322 }
323 }
324 Scenario.IngrTlpMsgDSltPwrLmtWt: { TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSGD );
325 TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
326 //Set up the TlpPkt.CmnType using MsgRouting
327 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
328 TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_SLOT_POWER_LIMIT;
329 }
330 Scenario.IngrTlpMsgVendorDefWt: { randcase{
331 10: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSG );
332 10: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_MSGD );
333 }
334 randcase{
335 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_TO_ROOT_CMPLX; 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_ROUTED_BY_ID;
336 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_BCAST_FROM_ROOT_CMPLX;
337 10: TlpPkt.MsgRouting = FNX_PCIE_XTR_MSG_ROUTING_LOCAL;
338 }
339 //Set up the TlpPkt.CmnType using MsgRouting
340 TlpPkt.CmnType[FNX_PCIE_XTR_FMT_TYPE_MSG_ROUTING_SLC] = TlpPkt.MsgRouting;
341 randcase{
342 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_VD_TYPE0;
343 10: TlpPkt.MsgCode = FNX_PCIE_XTR_MSG_CODE_VD_TYPE1;
344 }
345 }
346 Scenario.IngrTlpCplWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPL );
347 Scenario.IngrTlpCplDWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLD );
348 Scenario.IngrTlpCplLkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLLK );
349 Scenario.IngrTlpCplDLkdWt: TlpPkt.Set( "CmnFmtType", FNX_PCIE_XTR_FMT_TYPE_CPLDLK );
350
351 }
352
353 }
354 }
355
356 //Randomize other Common Header fields
357 TlpPkt.CmnTC = 0; //Traffic Class - malformed packet error if not TC0 -Fire ASIC MAS pg1021
358 TlpPkt.CmnTD = 0; //TLP Digest - 1 indicates tlp digest - ecrc at end of tlp
359 if( Trans_Direction === ILUPEU_INGRESS_TRANS ){ //Denali strips off ECRC - review
360 TlpPkt.CmnTD = 0;
361 }
362 TlpPkt.CmnEP = 0; //urandom(); //Poisoned - review need to test
363 TlpPkt.CmnRO = 0; //Relaxed Ordering -Attribute[1] - Not suppported Fire ASIC MAS pg140
364 TlpPkt.CmnSnoop = 0; //No Snoop -Attribute[0] - Not suppported Fire ASIC MAS pg140]
365 //IO and Cfg packet types must set TC, RO,& Snoop to 0
366 if( (TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_IORD && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1) ||
367 TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] == FNX_PCIE_XTR_TYPE_MSG_FIXED ){ //MSG and MSGD have same bits set
368
369 TlpPkt.CmnTC = 0; //Traffic Class
370 TlpPkt.CmnRO = 0; //Relaxed Ordering -Attribute[1]
371 TlpPkt.CmnSnoop = 0; //No Snoop -Attribute[0]
372 }
373
374 //Set the length field based on Max payload size for either Egress or Ingress
375 //length is payload size in DW(4 bytes)
376 if( (Trans_Direction === ILUPEU_EGRESS_TRANS) && TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_DATA_SLC] ){
377
378 //Set length but don't go over MaxPayload size
379 length = RandUtil.Rand32(Scenario.EgrMinTlpPayloadLngth4Byt,
380 ((13'h80 << Scenario.denaliMaxPayload) < Scenario.EgrMaxTlpPayloadLngth4Byt) ?
381 (13'h80 << Scenario.denaliMaxPayload) : //Min MaxPayload value is 128Bytes
382 Scenario.EgrMaxTlpPayloadLngth4Byt );
383
384 }
385 else if( (Trans_Direction === ILUPEU_INGRESS_TRANS) && TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_DATA_SLC] ){
386
387 //Set length but don't go over MaxPayload size
388 length = RandUtil.Rand32(Scenario.IngrMinTlpPayloadLngth4Byt,
389 ((13'h80 << Scenario.ilupeuMaxPayload) < Scenario.IngrMaxTlpPayloadLngth4Byt) ?
390 (13'h80 << Scenario.ilupeuMaxPayload) : //Min MaxPayload value is 128Bytes
391 Scenario.IngrMaxTlpPayloadLngth4Byt );
392 }
393 //Reads can have random lengths
394 else if( ({TlpPkt.CmnFmt,TlpPkt.CmnType} === FNX_PCIE_XTR_FMT_TYPE_MRD_32) ||
395 ({TlpPkt.CmnFmt,TlpPkt.CmnType} === FNX_PCIE_XTR_FMT_TYPE_MRD_64) ||
396 ({TlpPkt.CmnFmt,TlpPkt.CmnType} === FNX_PCIE_XTR_FMT_TYPE_MRDLK_32) ||
397 ({TlpPkt.CmnFmt,TlpPkt.CmnType} === FNX_PCIE_XTR_FMT_TYPE_MRDLK_64) ){
398
399 length = urandom();
400 }
401 else{
402 length = 0;
403 }
404 //IO and Cfg packet types and MsgD's must set length = 1
405 if( (TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_IORD && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1) ||
406 ((TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED ) &&
407 TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_DATA_SLC]) ){ //MSG and MSGD have same bits set
408 length = 1;
409 }
410 TlpPkt.CmnLength = length;
411
412 //Set all header fields that are common to Memory, IO, and Cfg Tlps
413 if (address_set) {
414 TlpPkt.ReqBusNum = 0;
415 TlpPkt.ReqDeviceNum = 0;
416 TlpPkt.ReqFuncNum = 0;
417 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){
418 TlpPkt.ReqTag = IOSReqTag;
419 uniqueTagSet = 1'b1;
420 }
421 TlpPkt.BEFirstDW = 4'b1111;
422 TlpPkt.BELastDW = 4'b1111;
423 }
424 else if( !address_set && ( TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1) ){
425
426 TlpPkt.ReqBusNum = urandom();
427 TlpPkt.ReqDeviceNum = urandom();
428 TlpPkt.ReqFuncNum = urandom();
429 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){
430 TlpPkt.ReqTag = GenUniqueTag();
431 uniqueTagSet = 1'b1;
432 }
433 else{
434 TlpPkt.ReqTag = GenUniqueTag();
435 uniqueTagSet = 1'b1;
436 }
437
438
439 //Follow the Byte Enable rules in PCIE 2.2.5
440 if (address_set) {
441 TlpPkt.BEFirstDW = 4'b1111;
442 TlpPkt.BELastDW = 4'b1111;
443 }
444 else if( TlpPkt.CmnLength === 0 ){
445 TlpPkt.BEFirstDW = 0;
446 TlpPkt.BELastDW = 0;
447 }
448 else if( TlpPkt.CmnLength === 1 ){
449 TlpPkt.BEFirstDW = RandUtil.Rand32( 4'h1, 4'hf );
450 TlpPkt.BELastDW = 0;
451 }
452 else if( TlpPkt.CmnLength === 2 ){
453 TlpPkt.BEFirstDW = RandUtil.Rand32( 4'h1, 4'hf );
454 TlpPkt.BELastDW = RandUtil.Rand32( 4'h1, 4'hf );
455 }
456 else{
457 randcase{
458 1:{ TlpPkt.BEFirstDW = 4'b1111;
459 TlpPkt.BELastDW = 4'b1111;
460 }
461 0:{ TlpPkt.BEFirstDW = 4'b1000;
462 TlpPkt.BELastDW = 4'b0111;
463 }
464 0:{ TlpPkt.BEFirstDW = 4'b1100;
465 TlpPkt.BELastDW = 4'b0011;
466 }
467 0:{ TlpPkt.BEFirstDW = 4'b1110;
468 TlpPkt.BELastDW = 4'b0001;
469 }
470 }
471 }
472 } //End of common to Memory, IO, and Cfg Tlps
473
474 //Set address header fields for Memory, IO
475 //Not checking for 4K boundary crossing
476 if( TlpPkt.CmnType <= FNX_PCIE_XTR_FMT_TYPE_IOWR ){
477
478//#ifdef N2_FC
479 if (address_set) {
480 //
481 TlpPkt.AddrLower = tlpAddr[32:2];
482 } else {
483//#else
484 //TlpPkt.AddrLower = 30'h33220000; //review - urandom();
485 TlpPkt.AddrLower = urandom();
486 TlpPkt.AddrLower[7:0] = 8'h0;
487 }
488//#endif
489
490
491 //If its a 64bit address then set upper address also
492 if( TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_64BIT_SLC] ){
493//#ifdef N2_FC
494 if (address_set) {
495 //
496 TlpPkt.AddrUpper = tlpAddr[63:32];
497 } else {
498//#else
499 TlpPkt.AddrUpper = 32'h77665544; //review urandom();
500 }
501//#endif
502 }
503 }
504
505 //Set up DW3 fields for Configuration Requests
506 if( TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_CFGRD0 && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1 ){
507
508 TlpPkt.CfgBusNum = urandom();
509 TlpPkt.CfgDeviceNum = urandom();
510 TlpPkt.CfgFuncNum = urandom();
511 TlpPkt.CfgExtRegNum = urandom();
512 TlpPkt.CfgRegNum = urandom();
513 }
514
515 //Set up fields for Message Requests
516 if( TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED ){
517
518 TlpPkt.ReqBusNum = urandom();
519 TlpPkt.ReqDeviceNum = urandom();
520 TlpPkt.ReqFuncNum = urandom();
521 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){
522 TlpPkt.ReqTag = GenUniqueTag();
523 uniqueTagSet = 1'b1;
524 TlpPkt.MsgDW3 = urandom();
525 TlpPkt.MsgDW4 = urandom();
526 }
527 else{
528 TlpPkt.ReqTag = 0; //GenUniqueTag();
529 //uniqueTagSet = 1'b1;
530
531 //Denali sets the DW3 and DW4 fields to 0 if they are reserved, this only affects Ingress because
532 // the fields are set to 0 when they get transmitted
533 if( TlpPkt.MsgCode === FNX_PCIE_XTR_MSG_CODE_VD_TYPE0 || TlpPkt.MsgCode === FNX_PCIE_XTR_MSG_CODE_VD_TYPE1 ){
534 TlpPkt.MsgDW3 = 32'hffff;
535 TlpPkt.MsgDW4 = 0;
536 }
537 else{
538 TlpPkt.MsgDW3 = 0;
539 TlpPkt.MsgDW4 = 0;
540 }
541 }
542
543 }
544
545
546 //Set up fields for Completions - review CAN't be randmom anymore
547 if( TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_CPL && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CPLDLK ){
548
549 TlpPkt.CmplBusNum = urandom();
550 TlpPkt.CmplDeviceNum = urandom();
551 TlpPkt.CmplFuncNum = urandom();
552 TlpPkt.CmplStatus = urandom(); //review May need to limit to 0-4
553 TlpPkt.CmplBCM = urandom();
554 TlpPkt.CmplByteCount = urandom();
555 TlpPkt.CmplLowerAddr = urandom();
556 TlpPkt.ReqBusNum = urandom();
557 TlpPkt.ReqDeviceNum = urandom();
558 TlpPkt.ReqFuncNum = urandom();
559 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){
560 TlpPkt.ReqTag = GenUniqueTag();
561 uniqueTagSet = 1'b1;
562 }
563 else{
564 TlpPkt.ReqTag = GenUniqueTag();
565 uniqueTagSet = 1'b1;
566 }
567 }
568
569
570
571 //Set up the random payload if needed
572 if( TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_DATA_SLC] ){
573 if( TlpPkt.CmnLength === 0 ){
574 length = 1024;
575 }
576 else{
577 length = TlpPkt.CmnLength;
578 }
579
580 pyldByteAry = new[length*4];
581 //In order to use the DMUXtr env code -get a DW and then
582 // put it into a byte array byte 0 = DW[31:24]
583 for( i=0; i< length; i++){
584// MAQ: PEU This is hack to test PEU env. Need to put the correct data
585#ifdef N2_FC
586 dataDW = 8'hA5;
587#else
588 dataDW = this.nextPayloadDW( pyldByteValue );
589#endif
590 for( j=0; j<4; j++){
591 pyldByteAry[(i*4)+j] = dataDW[31-(j*8):24-(j*8)];
592 }
593 }
594 TlpPkt.SetPyld( pyldByteAry );
595 }
596
597 //Add TLP Digest
598 if( TlpPkt.CmnTD ){
599 TlpPkt.ECRC = urandom();
600 }
601
602 //Turn off Denali automatic tag generation
603 TlpPkt.GenTag = 0;
604
605 TlpPkt.PktDisplay( RTYP_DEBUG_3, "ilupeuTlpStrategyBase::GenRandomPCIEXtrTlp()" );
606
607} //End GenRandomPCIEXtrTlp()
608
609
610task ilupeuTlpStrategyBase::ConvertPcieTlp2Hdr(){
611
612 integer i;
613
614 //Use the TlpPkt to build up a 3 or 4 DW header plus a payload if needed
615 //Handle all the common fields first
616 tlpHdr[ILUPEU_TLP_HDR_FMT_BITS] = TlpPkt.CmnFmt;
617 tlpHdr[ILUPEU_TLP_HDR_TYPE_BITS] = TlpPkt.CmnType;
618 tlpHdr[ILUPEU_TLP_HDR_TC_BITS] = TlpPkt.CmnTC;
619 tlpHdr[ILUPEU_TLP_HDR_TD_BITS] = TlpPkt.CmnTD;
620 tlpHdr[ILUPEU_TLP_HDR_EP_BITS] = TlpPkt.CmnEP;
621 tlpHdr[ILUPEU_TLP_HDR_RO_BITS] = TlpPkt.CmnRO;
622 tlpHdr[ILUPEU_TLP_HDR_SNOOP_BITS] = TlpPkt.CmnSnoop;
623 tlpHdr[ILUPEU_TLP_HDR_LEN_BITS] = TlpPkt.CmnLength;
624
625
626 //Set all header fields that are common to Memory, IO, and Cfg and Msg TLP's
627 if( TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1 ||
628 TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED ){
629
630 tlpHdr[ILUPEU_TLP_HDR_REQ_BUS_NUM_BITS] = TlpPkt.ReqBusNum;
631 tlpHdr[ILUPEU_TLP_HDR_REQ_DEV_NUM_BITS] = TlpPkt.ReqDeviceNum;
632 tlpHdr[ILUPEU_TLP_HDR_REQ_FUNC_NUM_BITS] = TlpPkt.ReqFuncNum;
633 tlpHdr[ILUPEU_TLP_HDR_TAG_BITS] = TlpPkt.ReqTag;
634 if( TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED ){
635
636 tlpHdr[ILUPEU_TLP_HDR_MSG_CODE_BITS] = TlpPkt.MsgCode;
637 }
638 else{
639 tlpHdr[ILUPEU_TLP_HDR_LAST_DWBE_BITS] = TlpPkt.BELastDW;
640 tlpHdr[ILUPEU_TLP_HDR_FIRST_DWBE_BITS] = TlpPkt.BEFirstDW;
641 }
642 }
643
644
645 //Set address header fields for Memory, IO
646 //If this is a 64 bit address than assign both halves of the address
647 if( TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_IOWR ){
648 if( tlpHdr[ILUPEU_TLP_HDR_FMT_4DW_BITS] ){
649 tlpHdr[ILUPEU_TLP_HDR_ADDR64_UPPER_BITS] = TlpPkt.AddrUpper;
650 tlpHdr[ILUPEU_TLP_HDR_ADDR64_LOWER_BITS] = TlpPkt.AddrLower;
651 }
652 else{
653 tlpHdr[ILUPEU_TLP_HDR_ADDR32_BITS] = TlpPkt.AddrLower;
654 }
655 }
656
657 //Set up DW3 header fields for Configuration Requests
658 if( TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_CFGRD0 && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CFGWR1 ){
659
660 tlpHdr[ILUPEU_TLP_HDR_CFG_BUS_NUM_BITS] = TlpPkt.CfgBusNum;
661 tlpHdr[ILUPEU_TLP_HDR_CFG_DEV_NUM_BITS] = TlpPkt.CfgDeviceNum;
662 tlpHdr[ILUPEU_TLP_HDR_CFG_FUNC_NUM_BITS] = TlpPkt.CfgFuncNum;
663 tlpHdr[ILUPEU_TLP_HDR_CFG_EXT_REG_NUM_BITS] = TlpPkt.CfgExtRegNum;
664 tlpHdr[ILUPEU_TLP_HDR_CFG_REG_NUM_BITS] = TlpPkt.CfgRegNum;
665 }
666
667
668
669 //Set up DW3 & DW4 fields for Messages
670 if( TlpPkt.CmnType[FNX_PCIE_XTR_TYPE_MSG_FIXED_SLC] === FNX_PCIE_XTR_TYPE_MSG_FIXED ){
671
672 tlpHdr[ILUPEU_TLP_HDR_MSG_DW3_BITS] = TlpPkt.MsgDW3;
673 tlpHdr[ILUPEU_TLP_HDR_MSG_DW4_BITS] = TlpPkt.MsgDW4;
674 }
675
676
677 //Set up fields for Completions
678 if( TlpPkt.CmnType >= FNX_PCIE_XTR_TYPE_CPL && TlpPkt.CmnType <= FNX_PCIE_XTR_TYPE_CPLDLK ){
679
680 tlpHdr[ILUPEU_TLP_HDR_CPL_CPL_BUS_NUM_BITS] = TlpPkt.CmplBusNum;
681 tlpHdr[ILUPEU_TLP_HDR_CPL_CPL_DEV_NUM_BITS] = TlpPkt.CmplDeviceNum;
682 tlpHdr[ILUPEU_TLP_HDR_CPL_CPL_FUNC_NUM_BITS] = TlpPkt.CmplFuncNum;
683 tlpHdr[ILUPEU_TLP_HDR_CPL_STATUS_BITS] = TlpPkt.CmplStatus;
684 tlpHdr[ILUPEU_TLP_HDR_CPL_BCM_BITS] = TlpPkt.CmplBCM;
685 tlpHdr[ILUPEU_TLP_HDR_CPL_BYTECOUNT_BITS] = TlpPkt.CmplByteCount;
686 tlpHdr[ILUPEU_TLP_HDR_CPL_REQ_BUS_NUM_BITS] = TlpPkt.ReqBusNum;
687 tlpHdr[ILUPEU_TLP_HDR_CPL_REQ_DEV_NUM_BITS] = TlpPkt.ReqDeviceNum;
688 tlpHdr[ILUPEU_TLP_HDR_CPL_REQ_FUNC_NUM_BITS] = TlpPkt.ReqFuncNum;
689 tlpHdr[ILUPEU_TLP_HDR_CPL_TAG_BITS] = TlpPkt.ReqTag;
690 tlpHdr[ILUPEU_TLP_HDR_CPL_LOWADDR_BITS] = TlpPkt.CmplLowerAddr;
691 }
692
693
694/*
695DMUXtr payload specification
696 payloadByte = payload[7:0];
697 poisonedPayload = payload[15:8];
698 fillPayload = payload[16];
699 errPayload = payload[17];
700 errMask = payload[25:18];
701*/
702
703 //Convert the Byte Array Payload for Denali to a DW(4 byte) Array Payload
704 if( TlpPkt.CmnFmt[FNX_PCIE_XTR_FMT_DATA_SLC] ){
705 pyldDWAry = new[length];
706 //Denali swaps the data bits for a Cfg Write
707 if( (TlpPkt.CmnType === FNX_PCIE_XTR_TYPE_CFGWR0 || TlpPkt.CmnType === FNX_PCIE_XTR_TYPE_CFGWR1) &&
708 (Trans_Direction === ILUPEU_INGRESS_TRANS) ){
709 for( i=0; i < length; i++ ){
710 pyldDW[ILUPEU_DW_BYTE_0_BITS] = pyldByteAry[ (i*4)+3 ];
711 pyldDW[ILUPEU_DW_BYTE_1_BITS] = pyldByteAry[ (i*4)+2 ];
712 pyldDW[ILUPEU_DW_BYTE_2_BITS] = pyldByteAry[ (i*4)+1 ];
713 pyldDW[ILUPEU_DW_BYTE_3_BITS] = pyldByteAry[ (i*4)+0 ];
714
715 pyldDWAry[i] = pyldDW;
716 }
717 }
718 else{
719 for( i=0; i < length; i++ ){
720 pyldDW[ILUPEU_DW_BYTE_0_BITS] = pyldByteAry[ (i*4)+0 ]; //31:24
721 pyldDW[ILUPEU_DW_BYTE_1_BITS] = pyldByteAry[ (i*4)+1 ];
722 pyldDW[ILUPEU_DW_BYTE_2_BITS] = pyldByteAry[ (i*4)+2 ];
723 pyldDW[ILUPEU_DW_BYTE_3_BITS] = pyldByteAry[ (i*4)+3 ];
724
725 pyldDWAry[i] = pyldDW;
726 }
727 }
728 }
729
730 QuickReport( Report,
731 RTYP_DEBUG_3,
732 "%s ilupeuTlpStrategyBase::ConvertPcieTlp2Hdr() tlpHdr=%h ",ID.GetString(),tlpHdr );
733
734} //End ConvertPcieTlp2Hdr
735
736
737task ilupeuTlpStrategyBase::ConvertHdr2LpuXtrTlpPkt(){
738
739 integer i = 0;
740 integer j = 0;
741 integer hdrLen = 0;
742 integer dataLen = 0;
743 integer digestLen = 0;
744 integer LenAdjust = 0;
745
746/* review - Convert to DMU Xtr
747 //Now Convert the Header and Payload to LPUXtr packet
748 // Instantiate a new LPUXtr packet
749 LPUXtrTlpPkt = new( Pod.LPUXtrErrCntr, Pod.LPUXtrCfg );
750
751 // How big is the header and payload?
752 hdrLen = 3 + tlpHdr[ILUPEU_TLP_HDR_FMT_4DW_BITS];
753 if( tlpHdr[ILUPEU_TLP_HDR_FMT_DATA_BITS] ){
754 if( tlpHdr[ILUPEU_TLP_HDR_LEN_BITS] === 0 ){
755 dataLen = 1024;
756 }
757 else{
758 dataLen = tlpHdr[ILUPEU_TLP_HDR_LEN_BITS];
759 }
760 }
761 else{
762 dataLen = 0;
763 }
764
765 digestLen = tlpHdr[ILUPEU_TLP_HDR_TD_BITS];
766
767 // How big is the TLP that we'll give to the transactor?
768 xtrLen = hdrLen + dataLen + digestLen + LenAdjust;
769 if( xtrLen < 1 ){
770 xtrLen = 2;
771 }
772
773 // Insert the Header
774 LPUXtrTlpPkt._TLP[0] = tlpHdr[ILUPEU_TLP_HDR_DW0_BITS];
775 if( xtrLen > 1 ){
776 LPUXtrTlpPkt._TLP[1] = tlpHdr[ILUPEU_TLP_HDR_DW1_BITS];
777 }
778 if( xtrLen > 2 ){
779 LPUXtrTlpPkt._TLP[2] = tlpHdr[ILUPEU_TLP_HDR_DW2_BITS];
780 }
781 if( xtrLen > 3 && hdrLen === 4 ){
782 LPUXtrTlpPkt._TLP[3] = tlpHdr[ILUPEU_TLP_HDR_DW3_BITS];
783 }
784
785 // and insert the payload
786 for( i = hdrLen, j = 0; i < hdrLen+dataLen; i++, j++){
787 LPUXtrTlpPkt._TLP[i] = pyldDWAry[j];
788 }
789
790 if( digestLen ){
791 LPUXtrTlpPkt._TLP[i] = TlpPkt.ECRC;
792 i++;
793 }
794
795 // increase the payload length of the packet by LenAdjust if requested
796 for( ; i < xtrLen; i++ ){
797 LPUXtrTlpPkt._TLP[i] = urandom();
798 }
799
800 //Set any error or idle to 0
801 for( i=0; i<xtrLen; i++ ){
802 LPUXtrTlpPkt._badParity[i] = 0;
803 LPUXtrTlpPkt._idle[i] = 0;
804 LPUXtrTlpPkt._insertIdle[i] = 0;
805 }
806
807 //Set status to no error
808 LPUXtrTlpPkt._status = ILUPEUTLP_STATUS_NO_ERROR;
809 LPUXtrTlpPkt._abort = ILUPEUFALSE;
810*/
811
812}
813
814
815function bit[FNX_PCIE_XTR_REQ_TAG_WIDTH-1:0] ilupeuTlpStrategyBase::GenUniqueTag(){
816 integer loop_cnt = 10000;
817 bit[7:0] unique_tag;
818 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){//review - Only for PioMWr
819 unique_tag = RandUtil.Rand32( 0, 8'h0f );
820 unique_tag[4] = 1'b1;
821 }
822 else{
823 unique_tag = RandUtil.Rand32( 0, 8'hff );
824 }
825
826
827 semaphore_get( WAIT, unique_tag_semaphore, 1);
828 while( ! ( region_enter( NO_WAIT, unique_tag_region, unique_tag) ) && loop_cnt ) {
829 if( Trans_Direction === ILUPEU_EGRESS_TRANS ){//review - Only for PioMWr
830 unique_tag = RandUtil.Rand32( 0, 8'h0f );
831 unique_tag[4] = 1'b1;
832 }
833 else{
834 unique_tag = RandUtil.Rand32( 0, 8'hff );
835 }
836 loop_cnt--;
837 //Bail out of test if stuck in this loop too long
838 if( !loop_cnt ){
839 Report.report( RTYP_TEST_ERROR, "GenUniqueTag() stuck in loop for 10000 cycles\n " );
840 }
841 }
842 semaphore_put( unique_tag_semaphore, 1);
843
844printf(" :GenUniqueTag() unique_tag=%h \n",unique_tag );
845
846 GenUniqueTag = unique_tag;
847
848}
849
850task ilupeuTlpStrategyBase::FreeUniqueTag(bit[FNX_PCIE_XTR_REQ_TAG_WIDTH-1:0] unique_tag){
851
852 region_exit( unique_tag_region, unique_tag );
853
854}
855
856//
857function bit[31:0] ilupeuTlpStrategyBase::nextPayloadDW( var integer DataSpec )
858{
859 bit [7:0] dataByte;
860 bit [31:0] dataDW;
861 integer j;
862
863 dataByte = DataSpec;
864 dataDW = 32'b0;
865 for ( j=0; j<4; j++ )
866 {
867 dataDW = { dataDW[23:0], dataByte };
868 dataByte = dataByte + 1;
869 }
870
871 DataSpec = dataByte;
872
873 nextPayloadDW = dataDW;
874} /* end "nextPayloadDW" */
875
Full OpenSPARC design & verification tarball including full HDL.