Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / ios / vera / ras / include / ios_ras.if.vrhpal

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: ios_ras.if.vrhpal
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
// available with the language indicating that GPLv2 or any later version 
// may be used, or where a choice of which version of the GPL is applied is 
// otherwise unspecified. 
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
// CA 95054 USA or visit www.sun.com if you need additional information or 
// have any questions. 
// 
// ========== Copyright Header End ============================================
#ifndef INC__IOS_RAS_IF_VRH
#define INC__IOS_RAS_IF_VRH

#include "top_defines.vrh"

interface niu_sii_inj {
input		clk	CLOCK		verilog_node "`CPU.sii.iol2clk";
input		req		NSAMPLE 	#-3	verilog_node "`CPU.niu_sii_hdr_vld";
input	[127:0] data		NSAMPLE		#-3	verilog_node "`CPU.niu_sii_data";
input	[7:0]	parity		NSAMPLE		#-3	verilog_node "`CPU.niu_sii_parity";
//input		req	NSAMPLE	#-3	verilog_node "`TDS.niu_smx.req_sii.siireq.niu_sii_hdr_vld_n";
//input	[127:0] hdr	NSAMPLE	#-3	verilog_node "`TDS.niu_smx.req_sii.siireq.niu_hdr_data_n";
//input	[127:0] data	NSAMPLE	#-3	verilog_node "`TDS.niu_smx.req_sii.siireq.niu_sii_data_n";
//input	[7:0]	parity	NSAMPLE	#-3	verilog_node "`TDS.niu_smx.req_sii.siireq.niu_sii_parity_n";
}

interface sio_niu_inj {
input		clk	CLOCK		verilog_node "`CPU.sio.iol2clk";
input		req		NSAMPLE 	#-3	verilog_node "`CPU.sio_niu_hdr_vld";
input	[127:0] data		NSAMPLE		#-3	verilog_node "`CPU.sio_niu_data";
input	[7:0]	parity		NSAMPLE		#-3	verilog_node "`CPU.sio_niu_parity";
}

interface dmu_sii_inj {
input		clk	CLOCK		verilog_node "`CPU.sii.iol2clk";
input		req		NSAMPLE 	#-3	verilog_node "`CPU.dmu_sii_hdr_vld";
input [127:0]   data		NSAMPLE		#-3	verilog_node "`CPU.dmu_sii_data";
input [7:0]	parity		NSAMPLE		#-3	verilog_node "`CPU.dmu_sii_parity";
input		be_parity	NSAMPLE		#-3	verilog_node "`CPU.dmu_sii_be_parity";
input           wrack_vld       NSAMPLE        #-3      verilog_node "`CPU.dmu.sii_dmu_wrack_vld";
input [3:0]     wrack_tag       NSAMPLE        #-3      verilog_node "`CPU.dmu.sii_dmu_wrack_tag";
input           wrack_par       NSAMPLE        #-3      verilog_node "`CPU.dmu.sii_dmu_wrack_par";
}

interface sio_dmu_inj {
input		clk	CLOCK		verilog_node "`CPU.sio.iol2clk";
input		req		NSAMPLE 	#-3	verilog_node "`CPU.sio_dmu_hdr_vld";
input	[127:0] data		NSAMPLE		#-3	verilog_node "`CPU.sio_dmu_data";
input	[7:0]	parity		NSAMPLE		#-3	verilog_node "`CPU.sio_dmu_parity";
}

.for($b=0; $b<8; $b++) {
interface l2_${b}_sio_inj {
input		clk	CLOCK		verilog_node "`CPU.sio.l2clk";
input		ctag_vld	NSAMPLE 	#-3 	verilog_node "`SIO.l2b${b}_sio_ctag_vld";
input [31:0]	data		NSAMPLE 	#-3 	verilog_node "`SIO.l2b${b}_sio_data";
input [1:0]	parity		NSAMPLE 	#-3 	verilog_node "`SIO.l2b${b}_sio_parity";
input 		ue_err		NSAMPLE 	#-3 	verilog_node "`SIO.l2b${b}_sio_ue_err";
}

.}

interface sii_ncu_inj {
input		clk	CLOCK		verilog_node "`CPU.sii.iol2clk";
input           gnt     NSAMPLE      #-3      verilog_node "`CPU.ncu_sii_gnt";
input           req     NSAMPLE      #-3      verilog_node "`CPU.sii_ncu_req";
input   [31:0]  data    NSAMPLE      #-3      verilog_node "`CPU.sii_ncu_data";       
input   [1:0]   parity  NSAMPLE      #-3      verilog_node "`CPU.sii_ncu_dparity";    
}

interface dmu_ncu_inj {
input		clk	CLOCK		verilog_node "`CPU.ncu.iol2clk";
input           wrack_vld     NSAMPLE      #-3      verilog_node "`CPU.ncu.dmu_ncu_wrack_vld";
input [3:0]     wrack_tag     NSAMPLE      #-3      verilog_node "`CPU.ncu.dmu_ncu_wrack_tag";
input           wrack_par     NSAMPLE      #-3      verilog_node "`CPU.ncu.dmu_ncu_wrack_par";
input           mondo_ack     NSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_dmu_mondo_ack";
input           mondo_nack    NSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_dmu_mondo_nack";
input [5:0]     mondo_id      NSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_dmu_mondo_id";
input           mondo_id_par  NSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_dmu_mondo_id_par";
}

#ifndef GATESIM
interface ncu_ras_csr {
input		clk	CLOCK		verilog_node "`CPU.ncu.iol2clk";
input [42:0]    per     PSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasper_ff.d0_0.q";
input [42:0]    esr     PSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.rasesr_ff.d0_0.q";
input [58:0]    siisyn  PSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.siisyn_ff.d0_0.q";
input [60:0]    ncusyn  PSAMPLE      #-3      verilog_node "`CPU.ncu.ncu_scd_ctl.ncu_c2iscd_ctl.ncu_ctrl_ctl.ncusyn_ff.d0_0.q";
}
#endif

#endif