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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ios_ras_inj.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | task SetNiuSiiData15; | |
36 | input value; | |
37 | reg value; | |
38 | begin | |
39 | force `CPU.niu_sii_data[15] = value; | |
40 | end | |
41 | endtask | |
42 | ||
43 | task RelNiuSiiData15; | |
44 | begin | |
45 | release `CPU.niu_sii_data[15]; | |
46 | end | |
47 | endtask | |
48 | ||
49 | task SetNiuSiiDP0; | |
50 | input value; | |
51 | reg value; | |
52 | begin | |
53 | force `CPU.niu_sii_parity[0] = value; | |
54 | end | |
55 | endtask | |
56 | ||
57 | task RelNiuSiiDP0; | |
58 | begin | |
59 | release `CPU.niu_sii_parity[0]; | |
60 | end | |
61 | endtask | |
62 | ||
63 | task SetDmuSiiDP0; | |
64 | input value; | |
65 | reg value; | |
66 | begin | |
67 | force `CPU.dmu_sii_parity[0] = value; | |
68 | end | |
69 | endtask | |
70 | ||
71 | task RelDmuSiiDP0; | |
72 | begin | |
73 | release `CPU.dmu_sii_parity[0]; | |
74 | end | |
75 | endtask | |
76 | ||
77 | task SetDmuSiiBEP; | |
78 | input value; | |
79 | reg value; | |
80 | begin | |
81 | force `CPU.dmu_sii_be_parity = value; | |
82 | end | |
83 | endtask | |
84 | ||
85 | task RelDmuSiiBEP; | |
86 | begin | |
87 | release `CPU.dmu_sii_be_parity; | |
88 | end | |
89 | endtask | |
90 | ||
91 | task SetNiuSiiAP0; | |
92 | input value; | |
93 | reg value; | |
94 | begin | |
95 | force `CPU.niu_sii_data[83] = value; | |
96 | end | |
97 | endtask | |
98 | ||
99 | task RelNiuSiiAP0; | |
100 | begin | |
101 | release `CPU.niu_sii_data[83]; | |
102 | end | |
103 | endtask | |
104 | ||
105 | task SetNiuSiiCMDP; | |
106 | input value; | |
107 | reg value; | |
108 | begin | |
109 | force `CPU.niu_sii_data[62] = value; | |
110 | end | |
111 | endtask | |
112 | ||
113 | task RelNiuSiiCMDP; | |
114 | begin | |
115 | release `CPU.niu_sii_data[62]; | |
116 | end | |
117 | endtask | |
118 | ||
119 | task SetNiuSiiIOAE; | |
120 | begin | |
121 | force `CPU.niu_sii_data[81] = 1'b1; | |
122 | end | |
123 | endtask | |
124 | ||
125 | task RelNiuSiiIOAE; | |
126 | begin | |
127 | release `CPU.niu_sii_data[81]; | |
128 | end | |
129 | endtask | |
130 | ||
131 | task SetNiuSiiIOUE; | |
132 | begin | |
133 | force `CPU.niu_sii_data[80] = 1'b1; | |
134 | end | |
135 | endtask | |
136 | ||
137 | task RelNiuSiiIOUE; | |
138 | begin | |
139 | release `CPU.niu_sii_data[80]; | |
140 | end | |
141 | endtask | |
142 | ||
143 | task SetDmuSiiIOAE; | |
144 | begin | |
145 | force `CPU.dmu_sii_data[81] = 1'b1; | |
146 | end | |
147 | endtask | |
148 | ||
149 | task RelDmuSiiIOAE; | |
150 | begin | |
151 | release `CPU.dmu_sii_data[81]; | |
152 | end | |
153 | endtask | |
154 | ||
155 | task SetDmuSiiIOUE; | |
156 | begin | |
157 | force `CPU.dmu_sii_data[80] = 1'b1; | |
158 | end | |
159 | endtask | |
160 | ||
161 | task RelDmuSiiIOUE; | |
162 | begin | |
163 | release `CPU.dmu_sii_data[80]; | |
164 | end | |
165 | endtask | |
166 | ||
167 | task SetDmuSiiTOUT; | |
168 | begin | |
169 | force `CPU.dmu_sii_data[82] = 1'b1; | |
170 | end | |
171 | endtask | |
172 | ||
173 | task RelDmuSiiTOUT; | |
174 | begin | |
175 | release `CPU.dmu_sii_data[82]; | |
176 | end | |
177 | endtask | |
178 | ||
179 | task SetDmuSiiAP0; | |
180 | input value; | |
181 | reg value; | |
182 | begin | |
183 | force `CPU.dmu_sii_data[83] = value; | |
184 | end | |
185 | endtask | |
186 | ||
187 | task RelDmuSiiAP0; | |
188 | begin | |
189 | release `CPU.dmu_sii_data[83]; | |
190 | end | |
191 | endtask | |
192 | ||
193 | task SetDmuSiiCMDP; | |
194 | input value; | |
195 | reg value; | |
196 | begin | |
197 | force `CPU.dmu_sii_data[62] = value; | |
198 | end | |
199 | endtask | |
200 | ||
201 | task RelDmuSiiCMDP; | |
202 | begin | |
203 | release `CPU.dmu_sii_data[62]; | |
204 | end | |
205 | endtask | |
206 | ||
207 | task SetNiuSiiCECC0; | |
208 | input value; | |
209 | reg value; | |
210 | begin | |
211 | force `CPU.niu_sii_data[56] = value; | |
212 | end | |
213 | endtask | |
214 | ||
215 | task RelNiuSiiCECC0; | |
216 | begin | |
217 | release `CPU.niu_sii_data[56]; | |
218 | end | |
219 | endtask | |
220 | ||
221 | task SetDmuSiiCECC0; | |
222 | input value; | |
223 | reg value; | |
224 | begin | |
225 | force `CPU.dmu_sii_data[56] = value; | |
226 | end | |
227 | endtask | |
228 | ||
229 | task RelDmuSiiCECC0; | |
230 | begin | |
231 | release `CPU.dmu_sii_data[56]; | |
232 | end | |
233 | endtask | |
234 | ||
235 | task SetNiuSiiCECC1; | |
236 | input value; | |
237 | reg value; | |
238 | begin | |
239 | force `CPU.niu_sii_data[57] = value; | |
240 | end | |
241 | endtask | |
242 | ||
243 | task RelNiuSiiCECC1; | |
244 | begin | |
245 | release `CPU.niu_sii_data[57]; | |
246 | end | |
247 | endtask | |
248 | ||
249 | task SetDmuSiiCECC1; | |
250 | input value; | |
251 | reg value; | |
252 | begin | |
253 | force `CPU.dmu_sii_data[57] = value; | |
254 | end | |
255 | endtask | |
256 | ||
257 | task RelDmuSiiCECC1; | |
258 | begin | |
259 | release `CPU.dmu_sii_data[57]; | |
260 | end | |
261 | endtask | |
262 | ||
263 | task SetSioNiuDP0; | |
264 | input value; | |
265 | reg value; | |
266 | begin | |
267 | $dispmon ("IOS-RAS", 20, " force sio_niu_parity[0] = %1d", value); | |
268 | force `CPU.sio_niu_parity[0] = value; | |
269 | end | |
270 | endtask | |
271 | ||
272 | task RelSioNiuDP0; | |
273 | begin | |
274 | $dispmon ("IOS-RAS", 20, " release sio_niu_parity[0]"); | |
275 | release `CPU.sio_niu_parity[0]; | |
276 | end | |
277 | endtask | |
278 | ||
279 | task SetSioDmuDP0; | |
280 | input value; | |
281 | reg value; | |
282 | begin | |
283 | force `CPU.sio_dmu_parity[0] = value; | |
284 | end | |
285 | endtask | |
286 | ||
287 | task RelSioDmuDP0; | |
288 | begin | |
289 | release `CPU.sio_dmu_parity[0]; | |
290 | end | |
291 | endtask | |
292 | ||
293 | task SetSioNiuCECC0; | |
294 | input value; | |
295 | reg value; | |
296 | begin | |
297 | force `CPU.sio_niu_data[56] = value; | |
298 | end | |
299 | endtask | |
300 | ||
301 | task RelSioNiuCECC0; | |
302 | begin | |
303 | release `CPU.sio_niu_data[56]; | |
304 | end | |
305 | endtask | |
306 | ||
307 | task SetSioDmuCECC0; | |
308 | input value; | |
309 | reg value; | |
310 | begin | |
311 | force `CPU.sio_dmu_data[56] = value; | |
312 | end | |
313 | endtask | |
314 | ||
315 | task RelSioDmuCECC0; | |
316 | begin | |
317 | release `CPU.sio_dmu_data[56]; | |
318 | end | |
319 | endtask | |
320 | ||
321 | task SetSioNiuCECC1; | |
322 | input value; | |
323 | reg value; | |
324 | begin | |
325 | force `CPU.sio_niu_data[57] = value; | |
326 | end | |
327 | endtask | |
328 | ||
329 | task RelSioNiuCECC1; | |
330 | begin | |
331 | release `CPU.sio_niu_data[57]; | |
332 | end | |
333 | endtask | |
334 | ||
335 | task SetSioDmuCECC1; | |
336 | input value; | |
337 | reg value; | |
338 | begin | |
339 | force `CPU.sio_dmu_data[57] = value; | |
340 | end | |
341 | endtask | |
342 | ||
343 | task RelSioDmuCECC1; | |
344 | begin | |
345 | release `CPU.sio_dmu_data[57]; | |
346 | end | |
347 | endtask | |
348 | ||
349 | task SetL2SioDP0; | |
350 | input value; | |
351 | input bank; | |
352 | reg value; | |
353 | integer bank; | |
354 | begin | |
355 | case (bank) | |
356 | 0: force `SIO.l2b0_sio_parity[0] = value; | |
357 | 1: force `SIO.l2b1_sio_parity[0] = value; | |
358 | 2: force `SIO.l2b2_sio_parity[0] = value; | |
359 | 3: force `SIO.l2b3_sio_parity[0] = value; | |
360 | 4: force `SIO.l2b4_sio_parity[0] = value; | |
361 | 5: force `SIO.l2b5_sio_parity[0] = value; | |
362 | 6: force `SIO.l2b6_sio_parity[0] = value; | |
363 | 7: force `SIO.l2b7_sio_parity[0] = value; | |
364 | endcase | |
365 | end | |
366 | endtask | |
367 | ||
368 | task RelL2SioDP0; | |
369 | input bank; | |
370 | integer bank; | |
371 | begin | |
372 | case (bank) | |
373 | 0: release `SIO.l2b0_sio_parity[0]; | |
374 | 1: release `SIO.l2b1_sio_parity[0]; | |
375 | 2: release `SIO.l2b2_sio_parity[0]; | |
376 | 3: release `SIO.l2b3_sio_parity[0]; | |
377 | 4: release `SIO.l2b4_sio_parity[0]; | |
378 | 5: release `SIO.l2b5_sio_parity[0]; | |
379 | 6: release `SIO.l2b6_sio_parity[0]; | |
380 | 7: release `SIO.l2b7_sio_parity[0]; | |
381 | endcase | |
382 | end | |
383 | endtask | |
384 | ||
385 | task SetL2SioEBIT; | |
386 | input value; | |
387 | input bank; | |
388 | reg value; | |
389 | integer bank; | |
390 | begin | |
391 | case (bank) | |
392 | 0: force `SIO.l2b0_sio_data[21] = value; | |
393 | 1: force `SIO.l2b1_sio_data[21] = value; | |
394 | 2: force `SIO.l2b2_sio_data[21] = value; | |
395 | 3: force `SIO.l2b3_sio_data[21] = value; | |
396 | 4: force `SIO.l2b4_sio_data[21] = value; | |
397 | 5: force `SIO.l2b5_sio_data[21] = value; | |
398 | 6: force `SIO.l2b6_sio_data[21] = value; | |
399 | 7: force `SIO.l2b7_sio_data[21] = value; | |
400 | endcase | |
401 | end | |
402 | endtask | |
403 | ||
404 | task RelL2SioEBIT; | |
405 | input bank; | |
406 | integer bank; | |
407 | begin | |
408 | case (bank) | |
409 | 0: release `SIO.l2b0_sio_data[21]; | |
410 | 1: release `SIO.l2b1_sio_data[21]; | |
411 | 2: release `SIO.l2b2_sio_data[21]; | |
412 | 3: release `SIO.l2b3_sio_data[21]; | |
413 | 4: release `SIO.l2b4_sio_data[21]; | |
414 | 5: release `SIO.l2b5_sio_data[21]; | |
415 | 6: release `SIO.l2b6_sio_data[21]; | |
416 | 7: release `SIO.l2b7_sio_data[21]; | |
417 | endcase | |
418 | end | |
419 | endtask | |
420 | ||
421 | task SetL2SioCECC0; | |
422 | input value; | |
423 | input bank; | |
424 | reg value; | |
425 | integer bank; | |
426 | begin | |
427 | case (bank) | |
428 | 0: force `SIO.l2b0_sio_data[25] = value; | |
429 | 1: force `SIO.l2b1_sio_data[25] = value; | |
430 | 2: force `SIO.l2b2_sio_data[25] = value; | |
431 | 3: force `SIO.l2b3_sio_data[25] = value; | |
432 | 4: force `SIO.l2b4_sio_data[25] = value; | |
433 | 5: force `SIO.l2b5_sio_data[25] = value; | |
434 | 6: force `SIO.l2b6_sio_data[25] = value; | |
435 | 7: force `SIO.l2b7_sio_data[25] = value; | |
436 | endcase | |
437 | end | |
438 | endtask | |
439 | ||
440 | task SetL2SioCECC1; | |
441 | input value; | |
442 | input bank; | |
443 | reg value; | |
444 | integer bank; | |
445 | begin | |
446 | case (bank) | |
447 | 0: force `SIO.l2b0_sio_data[26] = value; | |
448 | 1: force `SIO.l2b1_sio_data[26] = value; | |
449 | 2: force `SIO.l2b2_sio_data[26] = value; | |
450 | 3: force `SIO.l2b3_sio_data[26] = value; | |
451 | 4: force `SIO.l2b4_sio_data[26] = value; | |
452 | 5: force `SIO.l2b5_sio_data[26] = value; | |
453 | 6: force `SIO.l2b6_sio_data[26] = value; | |
454 | 7: force `SIO.l2b7_sio_data[26] = value; | |
455 | endcase | |
456 | end | |
457 | endtask | |
458 | ||
459 | task RelL2SioCECC0; | |
460 | input bank; | |
461 | integer bank; | |
462 | begin | |
463 | case (bank) | |
464 | 0: release `SIO.l2b0_sio_data[25]; | |
465 | 1: release `SIO.l2b1_sio_data[25]; | |
466 | 2: release `SIO.l2b2_sio_data[25]; | |
467 | 3: release `SIO.l2b3_sio_data[25]; | |
468 | 4: release `SIO.l2b4_sio_data[25]; | |
469 | 5: release `SIO.l2b5_sio_data[25]; | |
470 | 6: release `SIO.l2b6_sio_data[25]; | |
471 | 7: release `SIO.l2b7_sio_data[25]; | |
472 | endcase | |
473 | end | |
474 | endtask | |
475 | ||
476 | task RelL2SioCECC1; | |
477 | input bank; | |
478 | integer bank; | |
479 | begin | |
480 | case (bank) | |
481 | 0: release `SIO.l2b0_sio_data[26]; | |
482 | 1: release `SIO.l2b1_sio_data[26]; | |
483 | 2: release `SIO.l2b2_sio_data[26]; | |
484 | 3: release `SIO.l2b3_sio_data[26]; | |
485 | 4: release `SIO.l2b4_sio_data[26]; | |
486 | 5: release `SIO.l2b5_sio_data[26]; | |
487 | 6: release `SIO.l2b6_sio_data[26]; | |
488 | 7: release `SIO.l2b7_sio_data[26]; | |
489 | endcase | |
490 | end | |
491 | endtask | |
492 | ||
493 | task SetSiiNcuDP0; | |
494 | input value; | |
495 | reg value; | |
496 | begin | |
497 | force `CPU.sii_ncu_dparity[0] = value; | |
498 | end | |
499 | endtask | |
500 | ||
501 | task RelSiiNcuDP0; | |
502 | begin | |
503 | release `CPU.sii_ncu_dparity[0]; | |
504 | end | |
505 | endtask | |
506 | ||
507 | task SetSiiNcuCECC0; | |
508 | input value; | |
509 | reg value; | |
510 | begin | |
511 | force `CPU.sii_ncu_data[16] = value; | |
512 | end | |
513 | endtask | |
514 | ||
515 | task RelSiiNcuCECC0; | |
516 | begin | |
517 | release `CPU.sii_ncu_data[16]; | |
518 | end | |
519 | endtask | |
520 | ||
521 | task SetSiiNcuCECC1; | |
522 | input value; | |
523 | reg value; | |
524 | begin | |
525 | force `CPU.sii_ncu_data[17] = value; | |
526 | end | |
527 | endtask | |
528 | ||
529 | task RelSiiNcuCECC1; | |
530 | begin | |
531 | release `CPU.sii_ncu_data[17]; | |
532 | end | |
533 | endtask | |
534 | ||
535 | task SetDmuNcuWRACKPAR; | |
536 | input value; | |
537 | reg value; | |
538 | begin | |
539 | force `CPU.dmu_ncu_wrack_par = value; | |
540 | end | |
541 | endtask | |
542 | ||
543 | task RelDmuNcuWRACKPAR; | |
544 | begin | |
545 | release `CPU.dmu_ncu_wrack_par; | |
546 | end | |
547 | endtask | |
548 | ||
549 | task SetNcuDmuMONDOPAR; | |
550 | input value; | |
551 | reg value; | |
552 | begin | |
553 | force `CPU.ncu_dmu_mondo_id_par = value; | |
554 | end | |
555 | endtask | |
556 | ||
557 | task RelNcuDmuMONDOPAR; | |
558 | begin | |
559 | release `CPU.ncu_dmu_mondo_id_par; | |
560 | end | |
561 | endtask | |
562 | ||
563 | task SetSiiDmuWRACKPAR; | |
564 | input value; | |
565 | reg value; | |
566 | begin | |
567 | force `CPU.sii_dmu_wrack_parity = value; | |
568 | end | |
569 | endtask | |
570 | ||
571 | task RelSiiDmuWRACKPAR; | |
572 | begin | |
573 | release `CPU.sii_dmu_wrack_parity; | |
574 | end | |
575 | endtask |