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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / mcu / ccu_pll_config.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ccu_pll_config.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
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15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
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20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
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34// ========== Copyright Header End ============================================
35`ifdef MCUSAT
36 `include "mcu_dispmonDefines.vh"
37`else
38 `include "defines.vh"
39 `include "dispmonDefines.vh"
40`endif
41
42module ccu_pll_config();
43
44
45reg [5:0] pll_div1;
46reg [5:0] pll_div2;
47reg [5:0] pll_div3;
48reg [6:0] pll_div4;
49
50integer sysclk;
51integer cmpclk;
52integer ioclk;
53integer drclk;
54
55reg [8*100:1] cmp_dr_ratio;
56
57//----------SYS-CMP-IO--DR-
58reg n2_clks_133_533_133_266;
59reg n2_clks_133_600_150_266;
60reg n2_clks_133_666_166_266;
61reg n2_clks_133_733_183_266;
62reg n2_clks_133_800_200_266;
63reg n2_clks_133_866_216_266;
64reg n2_clks_133_933_233_266;
65reg n2_clks_133_1000_250_266;
66reg n2_clks_133_1066_266_266;
67reg n2_clks_133_1133_283_266;
68reg n2_clks_133_1200_300_266;
69reg n2_clks_133_1266_316_266;
70reg n2_clks_133_1333_333_266;
71reg n2_clks_133_1400_350_266;
72
73reg n2_clks_166_666_166_333;
74reg n2_clks_166_750_187_333;
75reg n2_clks_166_833_208_333;
76reg n2_clks_166_916_229_333;
77reg n2_clks_166_1000_250_333;
78reg n2_clks_166_1083_270_333;
79reg n2_clks_166_1166_291_333;
80reg n2_clks_166_1250_312_333;
81reg n2_clks_166_1333_333_333;
82reg n2_clks_166_1416_354_333;
83reg n2_clks_166_1416_375_333;
84
85initial
86begin
87
88 //Initilize PLL DIVs
89
90 pll_div1 = 6'h0;
91 pll_div2 = 6'h0;
92 pll_div3 = 6'h0;
93 pll_div4 = 7'h0;
94
95 //Initilize clk setting regs
96
97 n2_clks_133_533_133_266 = 1'b0;
98 n2_clks_133_600_150_266 = 1'b0;
99 n2_clks_133_666_166_266 = 1'b0;
100 n2_clks_133_733_183_266 = 1'b0;
101 n2_clks_133_800_200_266 = 1'b0;
102 n2_clks_133_866_216_266 = 1'b0;
103 n2_clks_133_933_233_266 = 1'b0;
104 n2_clks_133_1000_250_266 = 1'b0;
105 n2_clks_133_1066_266_266 = 1'b0;
106 n2_clks_133_1133_283_266 = 1'b0;
107 n2_clks_133_1200_300_266 = 1'b0;
108 n2_clks_133_1266_316_266 = 1'b0;
109 n2_clks_133_1333_333_266 = 1'b0;
110 n2_clks_133_1400_350_266 = 1'b0;
111
112 n2_clks_166_666_166_333 = 1'b0;
113 n2_clks_166_750_187_333 = 1'b0;
114 n2_clks_166_833_208_333 = 1'b0;
115 n2_clks_166_916_229_333 = 1'b0;
116 n2_clks_166_1000_250_333 = 1'b0;
117 n2_clks_166_1083_270_333 = 1'b0;
118 n2_clks_166_1166_291_333 = 1'b0;
119 n2_clks_166_1250_312_333 = 1'b0;
120 n2_clks_166_1333_333_333 = 1'b0;
121 n2_clks_166_1416_354_333 = 1'b0;
122 n2_clks_166_1416_375_333 = 1'b0;
123
124 // --- SYS_CLK 133 ----
125
126 if (($test$plusargs("N2_CLKS_133_533_133_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_2.00")))))
127 n2_clks_133_533_133_266 = 1'b1;
128 else if (($test$plusargs("N2_CLKS_133_600_150_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_2.25")))))
129 n2_clks_133_600_150_266 = 1'b1;
130 else if (($test$plusargs("N2_CLKS_133_666_166_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_2.50")))))
131 n2_clks_133_666_166_266 = 1'b1;
132 else if (($test$plusargs("N2_CLKS_133_733_183_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_2.75")))))
133 n2_clks_133_733_183_266 = 1'b1;
134 else if (($test$plusargs("N2_CLKS_133_800_200_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_3.00")))))
135 n2_clks_133_800_200_266 = 1'b1;
136 else if (($test$plusargs("N2_CLKS_133_866_216_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_3.25")))))
137 n2_clks_133_866_216_266 = 1'b1;
138 else if (($test$plusargs("N2_CLKS_133_933_233_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_3.50")))))
139 n2_clks_133_933_233_266 = 1'b1;
140 else if (($test$plusargs("N2_CLKS_133_1000_250_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_3.75")))))
141 n2_clks_133_1000_250_266 = 1'b1;
142 else if (($test$plusargs("N2_CLKS_133_1066_266_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_4.00")))))
143 n2_clks_133_1066_266_266 = 1'b1;
144 else if (($test$plusargs("N2_CLKS_133_1133_283_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_4.25")))))
145 n2_clks_133_1133_283_266 = 1'b1;
146 else if (($test$plusargs("N2_CLKS_133_1200_300_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_4.50")))))
147 n2_clks_133_1200_300_266 = 1'b1;
148 else if (($test$plusargs("N2_CLKS_133_1266_316_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_4.75")))))
149 n2_clks_133_1266_316_266 = 1'b1;
150 else if (($test$plusargs("N2_CLKS_133_1333_333_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_5.00")))))
151 n2_clks_133_1333_333_266 = 1'b1;
152 else if (($test$plusargs("N2_CLKS_133_1400_350_266")) || (($test$plusargs("SYSCLK_133")) && (($test$plusargs("CMPDR_RATIO_5.25")))))
153 n2_clks_133_1400_350_266 = 1'b1;
154
155 // --- SYS_CLK 166 ----
156
157 else if (($test$plusargs("N2_CLKS_166_666_166_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_2.00")))))
158 n2_clks_166_666_166_333 = 1'b1;
159 else if (($test$plusargs("N2_CLKS_166_750_187_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_2.25")))))
160 n2_clks_166_750_187_333 = 1'b1;
161 else if (($test$plusargs("N2_CLKS_166_833_208_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_2.50")))))
162 n2_clks_166_833_208_333 = 1'b1;
163 else if (($test$plusargs("N2_CLKS_166_916_229_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_2.75")))))
164 n2_clks_166_916_229_333 = 1'b1;
165 else if (($test$plusargs("N2_CLKS_166_1000_250_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_3.00")))))
166 n2_clks_166_1000_250_333 = 1'b1;
167 else if (($test$plusargs("N2_CLKS_166_1083_270_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_3.25")))))
168 n2_clks_166_1083_270_333 = 1'b1;
169 else if (($test$plusargs("N2_CLKS_166_1166_291_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_3.50")))))
170 n2_clks_166_1166_291_333 = 1'b1;
171 else if (($test$plusargs("N2_CLKS_166_1250_312_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_3.75")))))
172 n2_clks_166_1250_312_333 = 1'b1;
173 else if (($test$plusargs("N2_CLKS_166_1333_333_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_4.00")))))
174 n2_clks_166_1333_333_333 = 1'b1;
175 else if (($test$plusargs("N2_CLKS_166_1416_354_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_4.25")))))
176 n2_clks_166_1416_354_333 = 1'b1;
177 else if (($test$plusargs("N2_CLKS_166_1416_375_333")) || (($test$plusargs("SYSCLK_166")) && (($test$plusargs("CMPDR_RATIO_4.50")))))
178 n2_clks_166_1416_375_333 = 1'b1;
179 else begin
180 `ifdef DDR2_533
181 n2_clks_133_1333_333_266 = 1'b1;
182 `else // DDR2_667
183 n2_clks_166_1333_333_333 = 1'b1; // Default
184 `endif
185 end
186
187 // --- SYS_CLK 133 ----
188
189 if (n2_clks_133_533_133_266) begin
190 pll_div1 = 6'h1;
191 pll_div2 = 6'h7;
192 pll_div3 = 6'h1;
193 pll_div4 = 7'h8;
194 sysclk = 133;
195 cmpclk = 533;
196 ioclk = 133;
197 drclk = 266;
198 cmp_dr_ratio = "2.00";
199 end
200
201 if (n2_clks_133_600_150_266) begin
202 pll_div1 = 6'h1;
203 pll_div2 = 6'h8;
204 pll_div3 = 6'h1;
205 pll_div4 = 7'h9;
206 sysclk = 133;
207 cmpclk = 600;
208 ioclk = 150;
209 drclk = 266;
210 cmp_dr_ratio = "2.25";
211 end
212
213 if (n2_clks_133_666_166_266) begin
214 pll_div1 = 6'h1;
215 pll_div2 = 6'h9;
216 pll_div3 = 6'h1;
217 pll_div4 = 7'ha;
218 sysclk = 133;
219 cmpclk = 666;
220 ioclk = 166;
221 drclk = 266;
222 cmp_dr_ratio = "2.50";
223 end
224
225 if (n2_clks_133_733_183_266) begin
226 pll_div1 = 6'h1;
227 pll_div2 = 6'ha;
228 pll_div3 = 6'h1;
229 pll_div4 = 7'hb;
230 sysclk = 133;
231 cmpclk = 733;
232 ioclk = 183;
233 drclk = 266;
234 cmp_dr_ratio = "2.75";
235 end
236
237 if (n2_clks_133_800_200_266) begin
238 pll_div1 = 6'h1;
239 pll_div2 = 6'hb;
240 pll_div3 = 6'h1;
241 pll_div4 = 7'hc;
242 sysclk = 133;
243 cmpclk = 800;
244 ioclk = 200;
245 drclk = 266;
246 cmp_dr_ratio = "3.00";
247 end
248
249 if (n2_clks_133_866_216_266) begin
250 pll_div1 = 6'h1;
251 pll_div2 = 6'hc;
252 pll_div3 = 6'h1;
253 pll_div4 = 7'hd;
254 sysclk = 133;
255 cmpclk = 866;
256 ioclk = 216;
257 drclk = 266;
258 cmp_dr_ratio = "3.25";
259 end
260
261 if (n2_clks_133_933_233_266) begin
262 pll_div1 = 6'h1;
263 pll_div2 = 6'hd;
264 pll_div3 = 6'h1;
265 pll_div4 = 7'he;
266 sysclk = 133;
267 cmpclk = 933;
268 ioclk = 233;
269 drclk = 266;
270 cmp_dr_ratio = "3.50";
271 end
272
273 if (n2_clks_133_1000_250_266) begin
274 pll_div1 = 6'h1;
275 pll_div2 = 6'he;
276 pll_div3 = 6'h1;
277 pll_div4 = 7'hf;
278 sysclk = 133;
279 cmpclk = 1000;
280 ioclk = 250;
281 drclk = 266;
282 cmp_dr_ratio = "3.75";
283 end
284
285 if (n2_clks_133_1066_266_266) begin
286 pll_div1 = 6'h1;
287 pll_div2 = 6'hf;
288 pll_div3 = 6'h1;
289 pll_div4 = 7'h10;
290 sysclk = 133;
291 cmpclk = 1066;
292 ioclk = 266;
293 drclk = 266;
294 cmp_dr_ratio = "4.00";
295 end
296
297 if (n2_clks_133_1133_283_266) begin
298 pll_div1 = 6'h1;
299 pll_div2 = 6'h10;
300 pll_div3 = 6'h1;
301 pll_div4 = 7'h11;
302 sysclk = 133;
303 cmpclk = 1133;
304 ioclk = 283;
305 drclk = 266;
306 cmp_dr_ratio = "4.25";
307 end
308
309 if (n2_clks_133_1200_300_266) begin
310 pll_div1 = 6'h1;
311 pll_div2 = 6'h11;
312 pll_div3 = 6'h1;
313 pll_div4 = 7'h12;
314 sysclk = 133;
315 cmpclk = 1200;
316 ioclk = 300;
317 drclk = 266;
318 cmp_dr_ratio = "4.50";
319 end
320
321 if (n2_clks_133_1266_316_266) begin
322 pll_div1 = 6'h1;
323 pll_div2 = 6'h12;
324 pll_div3 = 6'h1;
325 pll_div4 = 7'h13;
326 sysclk = 133;
327 cmpclk = 1266;
328 ioclk = 316;
329 drclk = 266;
330 cmp_dr_ratio = "4.75";
331 end
332
333 if (n2_clks_133_1333_333_266) begin
334 pll_div1 = 6'h1;
335 pll_div2 = 6'h13;
336 pll_div3 = 6'h1;
337 pll_div4 = 7'h14;
338 sysclk = 133;
339 cmpclk = 1333;
340 ioclk = 333;
341 drclk = 266;
342 cmp_dr_ratio = "5.00";
343 end
344
345 if (n2_clks_133_1400_350_266) begin
346 pll_div1 = 6'h1;
347 pll_div2 = 6'h14;
348 pll_div3 = 6'h1;
349 pll_div4 = 7'h15;
350 sysclk = 133;
351 cmpclk = 1400;
352 ioclk = 350;
353 drclk = 266;
354 cmp_dr_ratio = "5.25";
355 end
356
357 // --- SYS_CLK 166 ----
358
359 if (n2_clks_166_666_166_333) begin
360 pll_div1 = 6'h1;
361 pll_div2 = 6'h7;
362 pll_div3 = 6'h1;
363 pll_div4 = 7'h8;
364 sysclk = 166;
365 cmpclk = 666;
366 ioclk = 166;
367 drclk = 333;
368 cmp_dr_ratio = "2.00";
369 end
370
371 if (n2_clks_166_750_187_333) begin
372 pll_div1 = 6'h1;
373 pll_div2 = 6'h8;
374 pll_div3 = 6'h1;
375 pll_div4 = 7'h9;
376 sysclk = 166;
377 cmpclk = 750;
378 ioclk = 187;
379 drclk = 333;
380 cmp_dr_ratio = "2.25";
381 end
382
383 if (n2_clks_166_833_208_333) begin
384 pll_div1 = 6'h1;
385 pll_div2 = 6'h9;
386 pll_div3 = 6'h1;
387 pll_div4 = 7'ha;
388 sysclk = 166;
389 cmpclk = 833;
390 ioclk = 208;
391 drclk = 333;
392 cmp_dr_ratio = "2.50";
393 end
394
395 if (n2_clks_166_916_229_333) begin
396 pll_div1 = 6'h1;
397 pll_div2 = 6'ha;
398 pll_div3 = 6'h1;
399 pll_div4 = 7'hb;
400 sysclk = 166;
401 cmpclk = 916;
402 ioclk = 229;
403 drclk = 333;
404 cmp_dr_ratio = "2.75";
405 end
406
407 if (n2_clks_166_1000_250_333) begin
408 pll_div1 = 6'h1;
409 pll_div2 = 6'hb;
410 pll_div3 = 6'h1;
411 pll_div4 = 7'hc;
412 sysclk = 166;
413 cmpclk = 1000;
414 ioclk = 250;
415 drclk = 333;
416 cmp_dr_ratio = "3.00";
417 end
418
419 if (n2_clks_166_1083_270_333) begin
420 pll_div1 = 6'h1;
421 pll_div2 = 6'hc;
422 pll_div3 = 6'h1;
423 pll_div4 = 7'hd;
424 sysclk = 166;
425 cmpclk = 1083;
426 ioclk = 270;
427 drclk = 333;
428 cmp_dr_ratio = "3.25";
429 end
430
431 if (n2_clks_166_1166_291_333) begin
432 pll_div1 = 6'h1;
433 pll_div2 = 6'hd;
434 pll_div3 = 6'h1;
435 pll_div4 = 7'he;
436 sysclk = 166;
437 cmpclk = 1166;
438 ioclk = 291;
439 drclk = 333;
440 cmp_dr_ratio = "3.50";
441 end
442
443 if (n2_clks_166_1250_312_333) begin
444 pll_div1 = 6'h1;
445 pll_div2 = 6'he;
446 pll_div3 = 6'h1;
447 pll_div4 = 7'hf;
448 sysclk = 166;
449 cmpclk = 1250;
450 ioclk = 312;
451 drclk = 333;
452 cmp_dr_ratio = "3.75";
453 end
454
455 if (n2_clks_166_1333_333_333) begin
456 pll_div1 = 6'h1;
457 pll_div2 = 6'hf;
458 pll_div3 = 6'h1;
459 pll_div4 = 7'h10;
460 sysclk = 166;
461 cmpclk = 1333;
462 ioclk = 333;
463 drclk = 333;
464 cmp_dr_ratio = "4.00";
465 end
466
467 if (n2_clks_166_1416_354_333) begin
468 pll_div1 = 6'h1;
469 pll_div2 = 6'h10;
470 pll_div3 = 6'h1;
471 pll_div4 = 7'h11;
472 sysclk = 166;
473 cmpclk = 1416;
474 ioclk = 354;
475 drclk = 333;
476 cmp_dr_ratio = "4.25";
477 end
478
479 if (n2_clks_166_1416_375_333) begin
480 pll_div1 = 6'h1;
481 pll_div2 = 6'h11;
482 pll_div3 = 6'h1;
483 pll_div4 = 7'h12;
484 sysclk = 166;
485 cmpclk = 1416;
486 ioclk = 375;
487 drclk = 333;
488 cmp_dr_ratio = "4.50";
489 end
490
491#1;
492
493if ($test$plusargs("NO_CCU_CSR_SLAM")) begin
494 $display("CCU not forced\n");
495end
496else begin
497
498`ifdef CCU_GATE
499 force `CCU.pll_div1 = pll_div1;
500 force `CCU.pll_div2 = pll_div2;
501 force `CCU.pll_div3 = pll_div3;
502 force `CCU.pll_div4 = pll_div4;
503`else
504 force `CCU.csr_blk.pll_div1 = pll_div1;
505 force `CCU.csr_blk.pll_div2 = pll_div2;
506 force `CCU.csr_blk.pll_div3 = pll_div3;
507 force `CCU.csr_blk.pll_div4 = pll_div4;
508`endif // CCU_GATE
509
510 // --- DTM Mode ----
511
512 if ($test$plusargs("SLAM_VECTORS")) begin
513 pll_div1 = 6'h1;
514 pll_div2 = 6'h7;
515 pll_div3 = 6'h1;
516 pll_div4 = 6'h8;
517 wait (`CCU.cluster_arst_l == 1'b1);
518 if ($test$plusargs("CMPDR_RATIO_15")) begin
519 pll_div1 = 6'h0;
520 pll_div2 = 6'he;
521 pll_div3 = 6'h1;
522 pll_div4 = 6'h0;
523 sysclk = 104;
524 cmpclk = 1560;
525 ioclk = 104;
526 drclk = 104;
527 cmp_dr_ratio = "15.00";
528 end
529 else if ($test$plusargs("CMPDR_RATIO_11")) begin
530 pll_div1 = 6'h0;
531 pll_div2 = 6'ha;
532 pll_div3 = 6'h1;
533 pll_div4 = 6'h0;
534 sysclk = 104;
535 cmpclk = 1144;
536 ioclk = 104;
537 drclk = 104;
538 cmp_dr_ratio = "11.00";
539 end
540 else begin // if ($test$plusargs("CMPDR_RATIO_8"))
541 pll_div1 = 6'h0;
542 pll_div2 = 6'h7;
543 pll_div3 = 6'h1;
544 pll_div4 = 6'h0;
545 sysclk = 104;
546 cmpclk = 832;
547 ioclk = 104;
548 drclk = 104;
549 cmp_dr_ratio = "8.00";
550 end
551
552`ifdef CCU_GATE
553 force `CCU.pll_div1 = pll_div1;
554 force `CCU.pll_div2 = pll_div2;
555 force `CCU.pll_div3 = pll_div3;
556 force `CCU.pll_div4 = pll_div4;
557`else
558 force `CCU.csr_blk.pll_div1 = pll_div1;
559 force `CCU.csr_blk.pll_div2 = pll_div2;
560 force `CCU.csr_blk.pll_div3 = pll_div3;
561 force `CCU.csr_blk.pll_div4 = pll_div4;
562`endif // CCU_GATE
563
564 end
565
566end
567
568 `PR_ALWAYS("ccu_pll_config", `ALWAYS, "----------- CCU PLL CONFIGURATION -----------");
569 `PR_ALWAYS("ccu_pll_config", `ALWAYS, "PLL_DIV1 = %x PLL_DIV2 = %x PLL_DIV3 = %x PLL_DIV4 = %x", pll_div1, pll_div2, pll_div3, pll_div4);
570 `PR_ALWAYS("ccu_pll_config", `ALWAYS, "SYS_CLK = %0d MHz CMP_CLK = %0d MHz IO_CLK = %0d MHz DR_CLK = %0d MHz", sysclk, cmpclk, ioclk, drclk);
571 `PR_ALWAYS("ccu_pll_config", `ALWAYS, "CMP:DR RATIO = %s:1", cmp_dr_ratio);
572 `PR_ALWAYS("ccu_pll_config", `ALWAYS, "---------------------------------------------");
573
574end
575
576
577endmodule
Full OpenSPARC design & verification tarball including full HDL.