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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: crc_errinject_top.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module crc_errinject_top( | |
36 | fbdimm0a_tx_p_top, fbdimm0a_tx_n_top, fbdimm0a_rx_p_top, fbdimm0a_rx_n_top, | |
37 | fbdimm0b_tx_p_top, fbdimm0b_tx_n_top, fbdimm0b_rx_p_top, fbdimm0b_rx_n_top, | |
38 | fbdimm1a_tx_p_top, fbdimm1a_tx_n_top, fbdimm1a_rx_p_top, fbdimm1a_rx_n_top, | |
39 | fbdimm1b_tx_p_top, fbdimm1b_tx_n_top, fbdimm1b_rx_p_top, fbdimm1b_rx_n_top, | |
40 | fbdimm2a_tx_p_top, fbdimm2a_tx_n_top, fbdimm2a_rx_p_top, fbdimm2a_rx_n_top, | |
41 | fbdimm2b_tx_p_top, fbdimm2b_tx_n_top, fbdimm2b_rx_p_top, fbdimm2b_rx_n_top, | |
42 | fbdimm3a_tx_p_top, fbdimm3a_tx_n_top, fbdimm3a_rx_p_top, fbdimm3a_rx_n_top, | |
43 | fbdimm3b_tx_p_top, fbdimm3b_tx_n_top, fbdimm3b_rx_p_top, fbdimm3b_rx_n_top, | |
44 | fbd0a_tx_p_top, fbd0a_tx_n_top, fbd0a_rx_p_top, fbd0a_rx_n_top, | |
45 | fbd0b_tx_p_top, fbd0b_tx_n_top, fbd0b_rx_p_top, fbd0b_rx_n_top, | |
46 | fbd1a_tx_p_top, fbd1a_tx_n_top, fbd1a_rx_p_top, fbd1a_rx_n_top, | |
47 | fbd1b_tx_p_top, fbd1b_tx_n_top, fbd1b_rx_p_top, fbd1b_rx_n_top, | |
48 | fbd2a_tx_p_top, fbd2a_tx_n_top, fbd2a_rx_p_top, fbd2a_rx_n_top, | |
49 | fbd2b_tx_p_top, fbd2b_tx_n_top, fbd2b_rx_p_top, fbd2b_rx_n_top, | |
50 | fbd3a_tx_p_top, fbd3a_tx_n_top, fbd3a_rx_p_top, fbd3a_rx_n_top, | |
51 | fbd3b_tx_p_top, fbd3b_tx_n_top, fbd3b_rx_p_top, fbd3b_rx_n_top, | |
52 | sclk | |
53 | ); | |
54 | ||
55 | input [9:0] fbdimm0a_tx_p_top; | |
56 | input [9:0] fbdimm0a_tx_n_top; | |
57 | output [13:0] fbdimm0a_rx_p_top; | |
58 | output [13:0] fbdimm0a_rx_n_top; | |
59 | ||
60 | input [9:0] fbdimm0b_tx_p_top; | |
61 | input [9:0] fbdimm0b_tx_n_top; | |
62 | output [13:0] fbdimm0b_rx_p_top; | |
63 | output [13:0] fbdimm0b_rx_n_top; | |
64 | ||
65 | input [9:0] fbdimm1a_tx_p_top; | |
66 | input [9:0] fbdimm1a_tx_n_top; | |
67 | output [13:0] fbdimm1a_rx_p_top; | |
68 | output [13:0] fbdimm1a_rx_n_top; | |
69 | ||
70 | input [9:0] fbdimm1b_tx_p_top; | |
71 | input [9:0] fbdimm1b_tx_n_top; | |
72 | output [13:0] fbdimm1b_rx_p_top; | |
73 | output [13:0] fbdimm1b_rx_n_top; | |
74 | ||
75 | input [9:0] fbdimm2a_tx_p_top; | |
76 | input [9:0] fbdimm2a_tx_n_top; | |
77 | output [13:0] fbdimm2a_rx_p_top; | |
78 | output [13:0] fbdimm2a_rx_n_top; | |
79 | ||
80 | input [9:0] fbdimm2b_tx_p_top; | |
81 | input [9:0] fbdimm2b_tx_n_top; | |
82 | output [13:0] fbdimm2b_rx_p_top; | |
83 | output [13:0] fbdimm2b_rx_n_top; | |
84 | ||
85 | input [9:0] fbdimm3a_tx_p_top; | |
86 | input [9:0] fbdimm3a_tx_n_top; | |
87 | output [13:0] fbdimm3a_rx_p_top; | |
88 | output [13:0] fbdimm3a_rx_n_top; | |
89 | ||
90 | input [9:0] fbdimm3b_tx_p_top; | |
91 | input [9:0] fbdimm3b_tx_n_top; | |
92 | output [13:0] fbdimm3b_rx_p_top; | |
93 | output [13:0] fbdimm3b_rx_n_top; | |
94 | ||
95 | output [9:0] fbd0a_tx_p_top; | |
96 | output [9:0] fbd0a_tx_n_top; | |
97 | input [13:0] fbd0a_rx_p_top; | |
98 | input [13:0] fbd0a_rx_n_top; | |
99 | ||
100 | output [9:0] fbd0b_tx_p_top; | |
101 | output [9:0] fbd0b_tx_n_top; | |
102 | input [13:0] fbd0b_rx_p_top; | |
103 | input [13:0] fbd0b_rx_n_top; | |
104 | ||
105 | output [9:0] fbd1a_tx_p_top; | |
106 | output [9:0] fbd1a_tx_n_top; | |
107 | input [13:0] fbd1a_rx_p_top; | |
108 | input [13:0] fbd1a_rx_n_top; | |
109 | ||
110 | output [9:0] fbd1b_tx_p_top; | |
111 | output [9:0] fbd1b_tx_n_top; | |
112 | input [13:0] fbd1b_rx_p_top; | |
113 | input [13:0] fbd1b_rx_n_top; | |
114 | ||
115 | output [9:0] fbd2a_tx_p_top; | |
116 | output [9:0] fbd2a_tx_n_top; | |
117 | input [13:0] fbd2a_rx_p_top; | |
118 | input [13:0] fbd2a_rx_n_top; | |
119 | ||
120 | output [9:0] fbd2b_tx_p_top; | |
121 | output [9:0] fbd2b_tx_n_top; | |
122 | input [13:0] fbd2b_rx_p_top; | |
123 | input [13:0] fbd2b_rx_n_top; | |
124 | ||
125 | output [9:0] fbd3a_tx_p_top; | |
126 | output [9:0] fbd3a_tx_n_top; | |
127 | input [13:0] fbd3a_rx_p_top; | |
128 | input [13:0] fbd3a_rx_n_top; | |
129 | ||
130 | output [9:0] fbd3b_tx_p_top; | |
131 | output [9:0] fbd3b_tx_n_top; | |
132 | input [13:0] fbd3b_rx_p_top; | |
133 | input [13:0] fbd3b_rx_n_top; | |
134 | ||
135 | input sclk; | |
136 | reg train_seq_err_inj0,train_seq_err_inj1,train_seq_err_inj2,train_seq_err_inj3; | |
137 | ||
138 | /* | |
139 | wire init_done_0 = ~(`MCU0.fbdic.fbdic_l0_state) ; | |
140 | wire init_done_1 = ~(`MCU1.fbdic.fbdic_l0_state) ; | |
141 | wire init_done_2 = ~(`MCU2.fbdic.fbdic_l0_state) ; | |
142 | wire init_done_3 = ~(`MCU3.fbdic.fbdic_l0_state) ; | |
143 | */ | |
144 | ||
145 | ||
146 | initial | |
147 | begin | |
148 | ||
149 | train_seq_err_inj0 = 0; | |
150 | train_seq_err_inj1 = 0; | |
151 | train_seq_err_inj2 = 0; | |
152 | train_seq_err_inj3 = 0; | |
153 | ||
154 | if ($test$plusargs("MCU0_TRAINING_SEQ_ERR")) | |
155 | begin | |
156 | `PR_ALWAYS("crc_err", `ALWAYS, "MCU0: ENTERED INJECTION FOR TRAINING SEQUENCE"); | |
157 | train_seq_err_inj0 = 1; | |
158 | end | |
159 | else if ($test$plusargs("MCU1_TRAINING_SEQ_ERR")) | |
160 | begin | |
161 | `PR_ALWAYS("crc_err", `ALWAYS, " MCU1: ENTERED INJECTION FOR TRAINING SEQUENCE"); | |
162 | train_seq_err_inj1 = 1; | |
163 | end | |
164 | else if ($test$plusargs("MCU2_TRAINING_SEQ_ERR")) | |
165 | begin | |
166 | `PR_ALWAYS("crc_err", `ALWAYS, "MCU2: ENTERED INJECTION FOR TRAINING SEQUENCE"); | |
167 | train_seq_err_inj2 = 1; | |
168 | end | |
169 | else if ($test$plusargs("MCU3_TRAINING_SEQ_ERR")) | |
170 | begin | |
171 | `PR_ALWAYS("crc_err", `ALWAYS, " MCU3: ENTERED INJECTION FOR TRAINING SEQUENCE"); | |
172 | train_seq_err_inj3 = 1; | |
173 | end | |
174 | ||
175 | end // end of initial block | |
176 | ||
177 | `ifdef MCU_GATE | |
178 | wire init_done_0 = ~(train_seq_err_inj0 ? (1) : (`MCU0.fbdic__n15588)) ; | |
179 | wire init_done_1 = ~(train_seq_err_inj1 ? (1) : (`MCU1.fbdic__n15588)) ; | |
180 | wire init_done_2 = ~(train_seq_err_inj2 ? (1) : (`MCU2.fbdic__n15588)) ; | |
181 | wire init_done_3 = ~(train_seq_err_inj3 ? (1) : (`MCU3.fbdic__n15588)) ; | |
182 | `else | |
183 | wire init_done_0 = ~(train_seq_err_inj0 ? (1) : (`MCU0.fbdic.fbdic_l0_state)) ; | |
184 | wire init_done_1 = ~(train_seq_err_inj1 ? (1) : (`MCU1.fbdic.fbdic_l0_state)) ; | |
185 | wire init_done_2 = ~(train_seq_err_inj2 ? (1) : (`MCU2.fbdic.fbdic_l0_state)) ; | |
186 | wire init_done_3 = ~(train_seq_err_inj3 ? (1) : (`MCU3.fbdic.fbdic_l0_state)) ; | |
187 | `endif // mcu_gate | |
188 | ||
189 | ||
190 | ||
191 | ||
192 | //----------------------------------- | |
193 | // NB CRC Error Injectors | |
194 | //----------------------------------- | |
195 | ||
196 | nb_crc_error_injector nb_crc_errinj0a_p ( | |
197 | .pn_in (fbd0a_rx_p_top[13:0]), | |
198 | .pn_out (fbdimm0a_rx_p_top[13:0]), | |
199 | .init (init_done_0), | |
200 | .sclk (sclk) | |
201 | ); | |
202 | ||
203 | nb_crc_error_injector nb_crc_errinj0a_n ( | |
204 | .pn_in (fbd0a_rx_n_top[13:0]), | |
205 | .pn_out (fbdimm0a_rx_n_top[13:0]), | |
206 | .init (init_done_0), | |
207 | .sclk (sclk) | |
208 | ); | |
209 | ||
210 | nb_crc_error_injector nb_crc_errinj0b_p ( | |
211 | .pn_in (fbd0b_rx_p_top[13:0]), | |
212 | .pn_out (fbdimm0b_rx_p_top[13:0]), | |
213 | .init (init_done_0), | |
214 | .sclk (sclk) | |
215 | ); | |
216 | ||
217 | nb_crc_error_injector nb_crc_errinj0b_n ( | |
218 | .pn_in (fbd0b_rx_n_top[13:0]), | |
219 | .pn_out (fbdimm0b_rx_n_top[13:0]), | |
220 | .init (init_done_0), | |
221 | .sclk (sclk) | |
222 | ); | |
223 | ||
224 | nb_crc_error_injector nb_crc_errinj1a_p ( | |
225 | .pn_in (fbd1a_rx_p_top[13:0]), | |
226 | .pn_out (fbdimm1a_rx_p_top[13:0]), | |
227 | .init (init_done_1), | |
228 | .sclk (sclk) | |
229 | ); | |
230 | ||
231 | nb_crc_error_injector nb_crc_errinj1a_n ( | |
232 | .pn_in (fbd1a_rx_n_top[13:0]), | |
233 | .pn_out (fbdimm1a_rx_n_top[13:0]), | |
234 | .init (init_done_1), | |
235 | .sclk (sclk) | |
236 | ); | |
237 | ||
238 | nb_crc_error_injector nb_crc_errinj1b_p ( | |
239 | .pn_in (fbd1b_rx_p_top[13:0]), | |
240 | .pn_out (fbdimm1b_rx_p_top[13:0]), | |
241 | .init (init_done_1), | |
242 | .sclk (sclk) | |
243 | ); | |
244 | ||
245 | nb_crc_error_injector nb_crc_errinj1b_n ( | |
246 | .pn_in (fbd1b_rx_n_top[13:0]), | |
247 | .pn_out (fbdimm1b_rx_n_top[13:0]), | |
248 | .init (init_done_1), | |
249 | .sclk (sclk) | |
250 | ); | |
251 | ||
252 | nb_crc_error_injector nb_crc_errinj2a_p ( | |
253 | .pn_in (fbd2a_rx_p_top[13:0]), | |
254 | .pn_out (fbdimm2a_rx_p_top[13:0]), | |
255 | .init (init_done_2), | |
256 | .sclk (sclk) | |
257 | ); | |
258 | ||
259 | nb_crc_error_injector nb_crc_errinj2a_n ( | |
260 | .pn_in (fbd2a_rx_n_top[13:0]), | |
261 | .pn_out (fbdimm2a_rx_n_top[13:0]), | |
262 | .init (init_done_2), | |
263 | .sclk (sclk) | |
264 | ); | |
265 | ||
266 | nb_crc_error_injector nb_crc_errinj2b_p ( | |
267 | .pn_in (fbd2b_rx_p_top[13:0]), | |
268 | .pn_out (fbdimm2b_rx_p_top[13:0]), | |
269 | .init (init_done_2), | |
270 | .sclk (sclk) | |
271 | ); | |
272 | ||
273 | nb_crc_error_injector nb_crc_errinj2b_n ( | |
274 | .pn_in (fbd2b_rx_n_top[13:0]), | |
275 | .pn_out (fbdimm2b_rx_n_top[13:0]), | |
276 | .init (init_done_2), | |
277 | .sclk (sclk) | |
278 | ); | |
279 | ||
280 | nb_crc_error_injector nb_crc_errinj3a_p ( | |
281 | .pn_in (fbd3a_rx_p_top[13:0]), | |
282 | .pn_out (fbdimm3a_rx_p_top[13:0]), | |
283 | .init (init_done_3), | |
284 | .sclk (sclk) | |
285 | ); | |
286 | ||
287 | nb_crc_error_injector nb_crc_errinj3a_n ( | |
288 | .pn_in (fbd3a_rx_n_top[13:0]), | |
289 | .pn_out (fbdimm3a_rx_n_top[13:0]), | |
290 | .init (init_done_3), | |
291 | .sclk (sclk) | |
292 | ); | |
293 | ||
294 | nb_crc_error_injector nb_crc_errinj3b_p ( | |
295 | .pn_in (fbd3b_rx_p_top[13:0]), | |
296 | .pn_out (fbdimm3b_rx_p_top[13:0]), | |
297 | .init (init_done_3), | |
298 | .sclk (sclk) | |
299 | ); | |
300 | ||
301 | nb_crc_error_injector nb_crc_errinj3b_n ( | |
302 | .pn_in (fbd3b_rx_n_top[13:0]), | |
303 | .pn_out (fbdimm3b_rx_n_top[13:0]), | |
304 | .init (init_done_3), | |
305 | .sclk (sclk) | |
306 | ); | |
307 | ||
308 | //------------------------ | |
309 | // SB CRC Error Injectors | |
310 | //------------------------ | |
311 | ||
312 | sb_crc_error_injector sb_crc_errinj0a_p ( | |
313 | .ps_in (fbdimm0a_tx_p_top[9:0]), | |
314 | .ps_out (fbd0a_tx_p_top[9:0]), | |
315 | .init (init_done_0), | |
316 | .is_bar (1'b0), | |
317 | .link_clk (sclk) | |
318 | ); | |
319 | ||
320 | sb_crc_error_injector sb_crc_errinj0a_n ( | |
321 | .ps_in (fbdimm0a_tx_n_top[9:0]), | |
322 | .ps_out (fbd0a_tx_n_top[9:0]), | |
323 | .init (init_done_0), | |
324 | .is_bar (1'b1), | |
325 | .link_clk (sclk) | |
326 | ); | |
327 | ||
328 | sb_crc_error_injector sb_crc_errinj0b_p ( | |
329 | .ps_in (fbdimm0b_tx_p_top[9:0]), | |
330 | .ps_out (fbd0b_tx_p_top[9:0]), | |
331 | .init (init_done_0), | |
332 | .is_bar (1'b0), | |
333 | .link_clk (sclk) | |
334 | ); | |
335 | ||
336 | sb_crc_error_injector sb_crc_errinj0b_n ( | |
337 | .ps_in (fbdimm0b_tx_n_top[9:0]), | |
338 | .ps_out (fbd0b_tx_n_top[9:0]), | |
339 | .init (init_done_0), | |
340 | .is_bar (1'b1), | |
341 | .link_clk (sclk) | |
342 | ); | |
343 | ||
344 | sb_crc_error_injector sb_crc_errinj1a_p ( | |
345 | .ps_in (fbdimm1a_tx_p_top[9:0]), | |
346 | .ps_out (fbd1a_tx_p_top[9:0]), | |
347 | .init (init_done_1), | |
348 | .is_bar (1'b0), | |
349 | .link_clk (sclk) | |
350 | ); | |
351 | ||
352 | sb_crc_error_injector sb_crc_errinj1a_n ( | |
353 | .ps_in (fbdimm1a_tx_n_top[9:0]), | |
354 | .ps_out (fbd1a_tx_n_top[9:0]), | |
355 | .init (init_done_1), | |
356 | .is_bar (1'b1), | |
357 | .link_clk (sclk) | |
358 | ); | |
359 | ||
360 | sb_crc_error_injector sb_crc_errinj1b_p ( | |
361 | .ps_in (fbdimm1b_tx_p_top[9:0]), | |
362 | .ps_out (fbd1b_tx_p_top[9:0]), | |
363 | .init (init_done_1), | |
364 | .is_bar (1'b0), | |
365 | .link_clk (sclk) | |
366 | ); | |
367 | ||
368 | sb_crc_error_injector sb_crc_errinj1b_n ( | |
369 | .ps_in (fbdimm1b_tx_n_top[9:0]), | |
370 | .ps_out (fbd1b_tx_n_top[9:0]), | |
371 | .init (init_done_1), | |
372 | .is_bar (1'b1), | |
373 | .link_clk (sclk) | |
374 | ); | |
375 | ||
376 | sb_crc_error_injector sb_crc_errinj2a_p ( | |
377 | .ps_in (fbdimm2a_tx_p_top[9:0]), | |
378 | .ps_out (fbd2a_tx_p_top[9:0]), | |
379 | .init (init_done_2), | |
380 | .is_bar (1'b0), | |
381 | .link_clk (sclk) | |
382 | ); | |
383 | ||
384 | sb_crc_error_injector sb_crc_errinj2a_n ( | |
385 | .ps_in (fbdimm2a_tx_n_top[9:0]), | |
386 | .ps_out (fbd2a_tx_n_top[9:0]), | |
387 | .init (init_done_2), | |
388 | .is_bar (1'b1), | |
389 | .link_clk (sclk) | |
390 | ); | |
391 | ||
392 | sb_crc_error_injector sb_crc_errinj2b_p ( | |
393 | .ps_in (fbdimm2b_tx_p_top[9:0]), | |
394 | .ps_out (fbd2b_tx_p_top[9:0]), | |
395 | .init (init_done_2), | |
396 | .is_bar (1'b0), | |
397 | .link_clk (sclk) | |
398 | ); | |
399 | ||
400 | sb_crc_error_injector sb_crc_errinj2b_n ( | |
401 | .ps_in (fbdimm2b_tx_n_top[9:0]), | |
402 | .ps_out (fbd2b_tx_n_top[9:0]), | |
403 | .init (init_done_2), | |
404 | .is_bar (1'b1), | |
405 | .link_clk (sclk) | |
406 | ); | |
407 | ||
408 | sb_crc_error_injector sb_crc_errinj3a_p ( | |
409 | .ps_in (fbdimm3a_tx_p_top[9:0]), | |
410 | .ps_out (fbd3a_tx_p_top[9:0]), | |
411 | .init (init_done_3), | |
412 | .is_bar (1'b0), | |
413 | .link_clk (sclk) | |
414 | ); | |
415 | ||
416 | sb_crc_error_injector sb_crc_errinj3a_n ( | |
417 | .ps_in (fbdimm3a_tx_n_top[9:0]), | |
418 | .ps_out (fbd3a_tx_n_top[9:0]), | |
419 | .init (init_done_3), | |
420 | .is_bar (1'b1), | |
421 | .link_clk (sclk) | |
422 | ); | |
423 | ||
424 | sb_crc_error_injector sb_crc_errinj3b_p ( | |
425 | .ps_in (fbdimm3b_tx_p_top[9:0]), | |
426 | .ps_out (fbd3b_tx_p_top[9:0]), | |
427 | .init (init_done_3), | |
428 | .is_bar (1'b0), | |
429 | .link_clk (sclk) | |
430 | ); | |
431 | ||
432 | sb_crc_error_injector sb_crc_errinj3b_n ( | |
433 | .ps_in (fbdimm3b_tx_n_top[9:0]), | |
434 | .ps_out (fbd3b_tx_n_top[9:0]), | |
435 | .init (init_done_3), | |
436 | .is_bar (1'b1), | |
437 | .link_clk (sclk) | |
438 | ); | |
439 | ||
440 | endmodule |