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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / mcu / cross_module.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: cross_module.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`define TOP_MOD tb_top
39`define TOP_SHELL tb_top_shell
40`define CPU `TOP_MOD.cpu
41`define MCU0 `CPU.mcu0
42`define MCU1 `CPU.mcu1
43`define MCU2 `CPU.mcu2
44`define MCU3 `CPU.mcu3
45`define CCU `CPU.ccu
46
47`define MCU0_DRIF_CTL `MCU0.drif
48`define MCU0_UCB_CTL `MCU0.ucb
49`define MCU0_RDATA_CTL `MCU0.rdata
50`define MCU0_RDPCTL_CTL `MCU0.rdpctl
51`define MCU0_ADDRDP_DP `MCU0.addrdp
52`define MCU0_READDP_DP `MCU0.readdp
53`define MCU0_WRDP_DP `MCU0.wrdp
54`define MCU0_L2IF0_CTL `MCU0.l2if0
55`define MCU0_DRQ0_CTL `MCU0_DRIF_CTL.reqq.drq0
56`define MCU0_L2B0_ADR_Q `MCU0_ADDRDP_DP.l2b0_adr_queue
57`define MCU0_L2B0_ADRGEN_DP `MCU0_ADDRDP_DP.l2b0_adrgen_dp
58`define MCU0_L2IF1_CTL `MCU0.l2if1
59`define MCU0_DRQ1_CTL `MCU0_DRIF_CTL.reqq.drq1
60`define MCU0_L2B1_ADR_Q `MCU0_ADDRDP_DP.l2b1_adr_queue
61`define MCU0_L2B1_ADRGEN_DP `MCU0_ADDRDP_DP.l2b1_adrgen_dp
62`define MCU0_L2RDMX_DP `MCU0.l2rdmx
63
64`define MCU1_DRIF_CTL `MCU1.drif
65`define MCU1_UCB_CTL `MCU1.ucb
66`define MCU1_RDATA_CTL `MCU1.rdata
67`define MCU1_RDPCTL_CTL `MCU1.rdpctl
68`define MCU1_ADDRDP_DP `MCU1.addrdp
69`define MCU1_READDP_DP `MCU1.readdp
70`define MCU1_WRDP_DP `MCU1.wrdp
71`define MCU1_L2IF0_CTL `MCU1.l2if0
72`define MCU1_DRQ0_CTL `MCU1_DRIF_CTL.reqq.drq0
73`define MCU1_L2B0_ADR_Q `MCU1_ADDRDP_DP.l2b0_adr_queue
74`define MCU1_L2B0_ADRGEN_DP `MCU1_ADDRDP_DP.l2b0_adrgen_dp
75`define MCU1_L2IF1_CTL `MCU1.l2if1
76`define MCU1_DRQ1_CTL `MCU1_DRIF_CTL.reqq.drq1
77`define MCU1_L2B1_ADR_Q `MCU1_ADDRDP_DP.l2b1_adr_queue
78`define MCU1_L2B1_ADRGEN_DP `MCU1_ADDRDP_DP.l2b1_adrgen_dp
79`define MCU1_L2RDMX_DP `MCU1.l2rdmx
80
81`define MCU2_DRIF_CTL `MCU2.drif
82`define MCU2_UCB_CTL `MCU2.ucb
83`define MCU2_RDATA_CTL `MCU2.rdata
84`define MCU2_RDPCTL_CTL `MCU2.rdpctl
85`define MCU2_ADDRDP_DP `MCU2.addrdp
86`define MCU2_READDP_DP `MCU2.readdp
87`define MCU2_WRDP_DP `MCU2.wrdp
88`define MCU2_L2IF0_CTL `MCU2.l2if0
89`define MCU2_DRQ0_CTL `MCU2_DRIF_CTL.reqq.drq0
90`define MCU2_L2B0_ADR_Q `MCU2_ADDRDP_DP.l2b0_adr_queue
91`define MCU2_L2B0_ADRGEN_DP `MCU2_ADDRDP_DP.l2b0_adrgen_dp
92`define MCU2_L2IF1_CTL `MCU2.l2if1
93`define MCU2_DRQ1_CTL `MCU2_DRIF_CTL.reqq.drq1
94`define MCU2_L2B1_ADR_Q `MCU2_ADDRDP_DP.l2b1_adr_queue
95`define MCU2_L2B1_ADRGEN_DP `MCU2_ADDRDP_DP.l2b1_adrgen_dp
96`define MCU2_L2RDMX_DP `MCU2.l2rdmx
97
98`define MCU3_DRIF_CTL `MCU3.drif
99`define MCU3_UCB_CTL `MCU3.ucb
100`define MCU3_RDATA_CTL `MCU3.rdata
101`define MCU3_RDPCTL_CTL `MCU3.rdpctl
102`define MCU3_ADDRDP_DP `MCU3.addrdp
103`define MCU3_READDP_DP `MCU3.readdp
104`define MCU3_WRDP_DP `MCU3.wrdp
105`define MCU3_L2IF0_CTL `MCU3.l2if0
106`define MCU3_DRQ0_CTL `MCU3_DRIF_CTL.reqq.drq0
107`define MCU3_L2B0_ADR_Q `MCU3_ADDRDP_DP.l2b0_adr_queue
108`define MCU3_L2B0_ADRGEN_DP `MCU3_ADDRDP_DP.l2b0_adrgen_dp
109`define MCU3_L2IF1_CTL `MCU3.l2if1
110`define MCU3_DRQ1_CTL `MCU3_DRIF_CTL.reqq.drq1
111`define MCU3_L2B1_ADR_Q `MCU3_ADDRDP_DP.l2b1_adr_queue
112`define MCU3_L2B1_ADRGEN_DP `MCU3_ADDRDP_DP.l2b1_adrgen_dp
113`define MCU3_L2RDMX_DP `MCU3.l2rdmx
114
115`define FBD_CH_PATH0 `TOP_MOD.mcusat_fbdimm.fbdimm_mem0
116`define FBD_CH_PATH1 `TOP_MOD.mcusat_fbdimm.fbdimm_mem1
117`define FBD_CH_PATH2 `TOP_MOD.mcusat_fbdimm.fbdimm_mem2
118`define FBD_CH_PATH3 `TOP_MOD.mcusat_fbdimm.fbdimm_mem3
119`define FBD_CH_PATH4 `TOP_MOD.mcusat_fbdimm.fbdimm_mem4
120`define FBD_CH_PATH5 `TOP_MOD.mcusat_fbdimm.fbdimm_mem5
121`define FBD_CH_PATH6 `TOP_MOD.mcusat_fbdimm.fbdimm_mem6
122`define FBD_CH_PATH7 `TOP_MOD.mcusat_fbdimm.fbdimm_mem7
123
124`ifdef X8
125 `define DIMMPATH0 fbdimm0.fbdimm_DIMMx8
126 `define DIMMPATH1 fbdimm1.fbdimm_DIMMx8
127 `define DIMMPATH2 fbdimm2.fbdimm_DIMMx8
128 `define DIMMPATH3 fbdimm3.fbdimm_DIMMx8
129 `define DIMMPATH4 fbdimm4.fbdimm_DIMMx8
130 `define DIMMPATH5 fbdimm5.fbdimm_DIMMx8
131 `define DIMMPATH6 fbdimm6.fbdimm_DIMMx8
132 `define DIMMPATH7 fbdimm7.fbdimm_DIMMx8
133`else
134 `define DIMMPATH0 fbdimm0.fbdimm_DIMMx4
135 `define DIMMPATH1 fbdimm1.fbdimm_DIMMx4
136 `define DIMMPATH2 fbdimm2.fbdimm_DIMMx4
137 `define DIMMPATH3 fbdimm3.fbdimm_DIMMx4
138 `define DIMMPATH4 fbdimm4.fbdimm_DIMMx4
139 `define DIMMPATH5 fbdimm5.fbdimm_DIMMx4
140 `define DIMMPATH6 fbdimm6.fbdimm_DIMMx4
141 `define DIMMPATH7 fbdimm7.fbdimm_DIMMx4
142`endif
143
144`define ERR_INJ_DIMM0 fbdimm0.amb_dram_err_inj
145`define ERR_INJ_DIMM1 fbdimm1.amb_dram_err_inj
146`define ERR_INJ_DIMM2 fbdimm2.amb_dram_err_inj
147`define ERR_INJ_DIMM3 fbdimm3.amb_dram_err_inj
148`define ERR_INJ_DIMM4 fbdimm4.amb_dram_err_inj
149`define ERR_INJ_DIMM5 fbdimm5.amb_dram_err_inj
150`define ERR_INJ_DIMM6 fbdimm6.amb_dram_err_inj
151`define ERR_INJ_DIMM7 fbdimm7.amb_dram_err_inj
152
153`ifdef RANK_DIMM
154`else
155 `ifdef X8
156 `define RANK_DIMMPATH0 fbdimm0.fbdimm_DIMMx8_rank2
157 `define RANK_DIMMPATH1 fbdimm1.fbdimm_DIMMx8_rank2
158 `define RANK_DIMMPATH2 fbdimm2.fbdimm_DIMMx8_rank2
159 `define RANK_DIMMPATH3 fbdimm3.fbdimm_DIMMx8_rank2
160 `define RANK_DIMMPATH4 fbdimm4.fbdimm_DIMMx8_rank2
161 `define RANK_DIMMPATH5 fbdimm5.fbdimm_DIMMx8_rank2
162 `define RANK_DIMMPATH6 fbdimm6.fbdimm_DIMMx8_rank2
163 `define RANK_DIMMPATH7 fbdimm7.fbdimm_DIMMx8_rank2
164 `else
165 `define RANK_DIMMPATH0 fbdimm0.fbdimm_DIMMx4_rank2
166 `define RANK_DIMMPATH1 fbdimm1.fbdimm_DIMMx4_rank2
167 `define RANK_DIMMPATH2 fbdimm2.fbdimm_DIMMx4_rank2
168 `define RANK_DIMMPATH3 fbdimm3.fbdimm_DIMMx4_rank2
169 `define RANK_DIMMPATH4 fbdimm4.fbdimm_DIMMx4_rank2
170 `define RANK_DIMMPATH5 fbdimm5.fbdimm_DIMMx4_rank2
171 `define RANK_DIMMPATH6 fbdimm6.fbdimm_DIMMx4_rank2
172 `define RANK_DIMMPATH7 fbdimm7.fbdimm_DIMMx4_rank2
173 `endif
174`endif
175
176`ifdef MCU_GATE
177`define DRIF_PATH0 `MCU0
178`define DRIF_PATH1 `MCU1
179`define DRIF_PATH2 `MCU2
180`define DRIF_PATH3 `MCU3
181`define FBDIC_PATH0 `MCU0
182`define FBDIC_PATH1 `MCU1
183`define FBDIC_PATH2 `MCU2
184`define FBDIC_PATH3 `MCU3
185`else
186`define DRIF_PATH0 `MCU0.drif
187`define DRIF_PATH1 `MCU1.drif
188`define DRIF_PATH2 `MCU2.drif
189`define DRIF_PATH3 `MCU3.drif
190`define FBDIC_PATH0 `MCU0.fbdic
191`define FBDIC_PATH1 `MCU1.fbdic
192`define FBDIC_PATH2 `MCU2.fbdic
193`define FBDIC_PATH3 `MCU3.fbdic
194`endif
195
196
197`define DRAM_L2IF0 `MCU0.l2if0
198`define DRAM_L2IF1 `MCU0.l2if1
199`define DRAM_L2IF2 `MCU1.l2if0
200`define DRAM_L2IF3 `MCU1.l2if1
201`define DRAM_L2IF4 `MCU2.l2if0
202`define DRAM_L2IF5 `MCU2.l2if1
203`define DRAM_L2IF6 `MCU3.l2if0
204`define DRAM_L2IF7 `MCU3.l2if1
205
206`define REGISTERED_DIMMS
207`define MONITOR_SIGNAL 129
208`define REG_WRITE_BACK 126
209
210`define PLI_QUIT 1 /* None */
211`define PLI_SSTEP 2 /* %1 th id */
212`define PLI_READ_TH_REG 3 /* %1 th id, %2 win num, %3 reg num */
213`define PLI_READ_TH_CTL_REG 4 /* %1 th id, %2 reg num */
214`define PLI_READ_TH_FP_REG_I 5 /* %1 th id, %2 reg num */
215`define PLI_READ_TH_FP_REG_X 6 /* %1 th id, %2 reg num */
216`define PLI_RTL_DATA 7
217`define PLI_RTL_CYCLE 8
218`define PLI_WRITE_TH_XCC_REG 9
219`define PLI_RETRY 15
220`define PLI_WRITE_TH_REG_HI 10
221`define PLI_WRITE_TH_CTL_REG 12 /* %1 th id, %2 reg num, %3-%10 value */
222`define CMD_BUFSIZE 10240
223
224`define MONITOR_PATH `TOP_MOD.monitor
225`define MONITOR `TOP_MOD.monitor
226`define PC_CMP `TOP_MOD.monitor.pc_cmp
227`define SAS_SEND `TOP_MOD.sas_tasks.send_cmd
228`define SAS_DEF `TOP_MOD.sas_tasks.sas_def
229`define SAS_TASKS `TOP_MOD.sas_tasks
230
231`define SCPATH0 `CPU.sctag0
232`define SCPATH1 `CPU.sctag1
233`define SCPATH2 `CPU.sctag2
234`define SCPATH3 `CPU.sctag3
235`define SCPATH4 `CPU.sctag4
236`define SCPATH5 `CPU.sctag5
237`define SCPATH6 `CPU.sctag6
238`define SCPATH7 `CPU.sctag7
239
240`define SCDPATH0 `CPU.scdata0
241`define SCDPATH1 `CPU.scdata1
242`define SCDPATH2 `CPU.scdata2
243`define SCDPATH3 `CPU.scdata3
244
245`define DDR2_0IN_SIM_MON
246
247`ifdef DDR2_533
248 `define SYS_HALF_PERIOD 3750 // ps., 133Mhz == 7500ps
249`else
250 `define SYS_HALF_PERIOD 3000 // ps., 166Mhz == 6000ps
251`endif
252
253`ifdef DTM_ENABLED
254 `define SYS_HALF_PERIOD 4800 // ps., 104.57Mhz == 9600ps
255`endif
Full OpenSPARC design & verification tarball including full HDL.