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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / mcu / mcu_mem_config.v
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcu_mem_config.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
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28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35`ifdef MCUSAT
36 `include "mcu_dispmonDefines.vh"
37`else
38 `include "defines.vh"
39 `include "dispmonDefines.vh"
40`endif
41
42module mcu_mem_config ();
43
44reg chnl_type; // Dual Channel or Single Channel
45reg rank_addr; // RANK HI addr = 1, RANK LOW addr = 0
46reg [2:0] num_dimms; // DIMM NUMBERS: 1, 2, 4, 6, 8
47reg rank; // 1 RANK or 2 RANKS
48reg [1:0] dimm_size ;
49reg mcu_reg_slam_en;
50reg dram_part;
51
52reg [7:0] chnl_read_latency;
53reg [7:0] chnl_read_latency_gate;
54reg dtm_enabled,sys_enabled;
55
56initial
57begin
58`ifdef PALLADIUM
59`else
60 #1;
61`endif
62 if ($test$plusargs("SYS_SETTINGS"))
63begin
64 `PR_ALWAYS ("mcu_mem_config", `ALWAYS, "SIMULATION HAS SYSTEM SETTINGS ENABLED");
65
66 sys_enabled = 1'b1;
67end
68 else
69 sys_enabled = 1'b0;
70
71 if ($test$plusargs("DTM_ENABLED"))
72 dtm_enabled = 1'b1;
73 else
74 dtm_enabled = 1'b0;
75end
76
77initial
78begin // {
79
80`ifdef PALLADIUM
81`else
82 #1;
83`endif
84
85 if ($test$plusargs("NO_MCU_CSR_SLAM")) begin
86 `PR_INFO ("mcu_mem_config", `INFO, "MCU CSRs not slammed");
87 end
88 else begin
89
90 //----------------------------------------
91 // Disable MCU Timing Registers Slamming
92 //----------------------------------------
93
94 if ($test$plusargs("MCU_REG_DEFAULT_VAL"))
95 mcu_reg_slam_en = 1'b0;
96 else
97 mcu_reg_slam_en = 1'b1;
98
99 //----------------------------------------------------------
100 // DRAMs X8 PART
101 //----------------------------------------------------------
102
103`ifdef X8
104 if (mcu_reg_slam_en) begin
105 force `DRIF_PATH0.drif_cas_addr_bits[3:0] =4'ha;
106 force `DRIF_PATH1.drif_cas_addr_bits[3:0] =4'ha;
107 force `DRIF_PATH2.drif_cas_addr_bits[3:0] =4'ha;
108 force `DRIF_PATH3.drif_cas_addr_bits[3:0] =4'ha;
109 end
110`endif
111
112 //----------------------------------------------------------
113 // Memory Density Type : 256 Mb, 512 Mb, 1 Gb, 2 Gb
114 //----------------------------------------------------------
115
116 if ($test$plusargs("DIMM_SIZE_1G"))
117 begin // {
118`ifdef MCU_GATE
119 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_3_ =1'b0;
120 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_2_ =1'b0;
121 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_1_ =1'b0;
122 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_0_ =1'b1;
123
124 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_3_ =1'b0;
125 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_2_ =1'b0;
126 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_1_ =1'b0;
127 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_0_ =1'b1;
128
129 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_3_ =1'b0;
130 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_2_ =1'b0;
131 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_1_ =1'b0;
132 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_0_ =1'b1;
133
134 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_3_ =1'b0;
135 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_2_ =1'b0;
136 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_1_ =1'b0;
137 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_0_ =1'b1;
138`else
139 if (mcu_reg_slam_en) begin
140 force `DRIF_PATH0.drif_ras_addr_bits[3:0] =4'he;
141 force `DRIF_PATH1.drif_ras_addr_bits[3:0] =4'he;
142 force `DRIF_PATH2.drif_ras_addr_bits[3:0] =4'he;
143 force `DRIF_PATH3.drif_ras_addr_bits[3:0] =4'he;
144 end
145`endif // mcu_gate
146
147 dimm_size = 2'b10;
148 end // }
149 else if ($test$plusargs("DIMM_SIZE_512"))
150 begin // {
151`ifdef MCU_GATE
152 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_3_ =1'b0;
153 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_2_ =1'b0;
154 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_1_ =1'b0;
155 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_0_ =1'b1;
156
157 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_3_ =1'b0;
158 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_2_ =1'b0;
159 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_1_ =1'b0;
160 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_0_ =1'b1;
161
162 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_3_ =1'b0;
163 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_2_ =1'b0;
164 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_1_ =1'b0;
165 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_0_ =1'b1;
166
167 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_3_ =1'b0;
168 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_2_ =1'b0;
169 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_1_ =1'b0;
170 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_0_ =1'b1;
171
172 force `DRIF_PATH0.drif__inv_drif_eight_bank_mode = 1'b1;
173 force `DRIF_PATH1.drif__inv_drif_eight_bank_mode = 1'b1;
174 force `DRIF_PATH2.drif__inv_drif_eight_bank_mode = 1'b1;
175 force `DRIF_PATH3.drif__inv_drif_eight_bank_mode = 1'b1;
176`else
177 force `DRIF_PATH0.drif_ras_addr_bits[3:0] =4'he;
178 force `DRIF_PATH1.drif_ras_addr_bits[3:0] =4'he;
179 force `DRIF_PATH2.drif_ras_addr_bits[3:0] =4'he;
180 force `DRIF_PATH3.drif_ras_addr_bits[3:0] =4'he;
181
182 force `DRIF_PATH0.drif_eight_bank_mode = 1'b0;
183 force `DRIF_PATH1.drif_eight_bank_mode = 1'b0;
184 force `DRIF_PATH2.drif_eight_bank_mode = 1'b0;
185 force `DRIF_PATH3.drif_eight_bank_mode = 1'b0;
186`endif // mcu_gate
187
188 dimm_size = 2'b01;
189 end // }
190 else if ($test$plusargs("DIMM_SIZE_256"))
191 begin // {
192`ifdef MCU_GATE
193 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_3_ =1'b0;
194 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_2_ =1'b0;
195 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_1_ =1'b1;
196 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_0_ =1'b0;
197
198 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_3_ =1'b0;
199 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_2_ =1'b0;
200 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_1_ =1'b1;
201 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_0_ =1'b0;
202
203 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_3_ =1'b0;
204 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_2_ =1'b0;
205 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_1_ =1'b1;
206 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_0_ =1'b0;
207
208 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_3_ =1'b0;
209 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_2_ =1'b0;
210 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_1_ =1'b1;
211 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_0_ =1'b0;
212
213 force `DRIF_PATH0.drif__inv_drif_eight_bank_mode = 1'b1;
214 force `DRIF_PATH1.drif__inv_drif_eight_bank_mode = 1'b1;
215 force `DRIF_PATH2.drif__inv_drif_eight_bank_mode = 1'b1;
216 force `DRIF_PATH3.drif__inv_drif_eight_bank_mode = 1'b1;
217`else
218 force `DRIF_PATH0.drif_ras_addr_bits[3:0] =4'hd;
219 force `DRIF_PATH1.drif_ras_addr_bits[3:0] =4'hd;
220 force `DRIF_PATH2.drif_ras_addr_bits[3:0] =4'hd;
221 force `DRIF_PATH3.drif_ras_addr_bits[3:0] =4'hd;
222
223 force `DRIF_PATH0.drif_eight_bank_mode = 1'b0;
224 force `DRIF_PATH1.drif_eight_bank_mode = 1'b0;
225 force `DRIF_PATH2.drif_eight_bank_mode = 1'b0;
226 force `DRIF_PATH3.drif_eight_bank_mode = 1'b0;
227`endif // mcu_gate
228
229 dimm_size = 2'b00;
230 end // }
231 else
232 begin // {
233`ifdef X8
234 // use 1 GB for X8 if DIMM_SIZE_2G specified in diaglists
235`ifdef MCU_GATE
236 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_3_ =1'b0;
237 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_2_ =1'b0;
238 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_1_ =1'b0;
239 force `DRIF_PATH0.drif__inv_drif_ras_addr_bits_0_ =1'b1;
240
241 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_3_ =1'b0;
242 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_2_ =1'b0;
243 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_1_ =1'b0;
244 force `DRIF_PATH1.drif__inv_drif_ras_addr_bits_0_ =1'b1;
245
246 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_3_ =1'b0;
247 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_2_ =1'b0;
248 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_1_ =1'b0;
249 force `DRIF_PATH2.drif__inv_drif_ras_addr_bits_0_ =1'b1;
250
251 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_3_ =1'b0;
252 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_2_ =1'b0;
253 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_1_ =1'b0;
254 force `DRIF_PATH3.drif__inv_drif_ras_addr_bits_0_ =1'b1;
255`else
256 force `DRIF_PATH0.drif_ras_addr_bits[3:0] =4'he;
257 force `DRIF_PATH1.drif_ras_addr_bits[3:0] =4'he;
258 force `DRIF_PATH2.drif_ras_addr_bits[3:0] =4'he;
259 force `DRIF_PATH3.drif_ras_addr_bits[3:0] =4'he;
260`endif // mcu_gate
261`else
262 dimm_size = 2'b11; // use default = 2G b
263`endif
264 end // }
265
266 //------------------------------------
267 // MEMORY CONFIGURATION SETUP
268 //------------------------------------
269
270 if ($test$plusargs("DUAL_CHANNEL"))
271 chnl_type = 1'b1; // DUAL CHANNELS PER BRANCH
272 else if ($test$plusargs("SNG_CHANNEL"))
273 chnl_type = 1'b0; // SINGLE CHANNEL PER BRANCH
274 else
275 chnl_type = 1'b1; // DUAL CHANNELS PER BRANCH (Default)
276
277 if ($test$plusargs("RANK_LOW"))
278 rank_addr = 1'b0; // RANK LOW Address Select
279 else if ($test$plusargs("RANK_HIGH"))
280 rank_addr = 1'b1; // RANK HIGH Address Select
281 else
282 rank_addr = 1'b1; // RANK HIGH Address Select (Default)
283
284 if ($test$plusargs("1_FBDIMM")) // Number of DIMMS
285 num_dimms = 3'h1;
286 else if ($test$plusargs("2_FBDIMMS"))
287 num_dimms = 3'h2;
288 else if ($test$plusargs("3_FBDIMMS"))
289 num_dimms = 3'h3;
290 else if ($test$plusargs("4_FBDIMMS"))
291 num_dimms = 3'h4;
292 else if ($test$plusargs("5_FBDIMMS"))
293 num_dimms = 3'h5;
294 else if ($test$plusargs("6_FBDIMMS"))
295 num_dimms = 3'h6;
296 else if ($test$plusargs("7_FBDIMMS"))
297 num_dimms = 3'h7;
298 else if ($test$plusargs("8_FBDIMMS"))
299 num_dimms = 3'h0;
300 else
301 num_dimms = 3'h1; // Default 1 FBDIMM
302
303 if ($test$plusargs("STACK_DIMM"))
304 rank = 1'b1; // 2 RANKS
305 else
306 rank = 1'b0; // 1 RANK (Default)
307
308 if ($test$plusargs("X8"))
309 dram_part = 1;
310 else
311 dram_part = 0;
312
313
314 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "----- FBDIMM MEMORY CONFIGURATION ----- ");
315 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "CHANNEL TYPE [ Dual\(1\) / Single\(0\) ] = %b", chnl_type);
316 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "RANK ADDR SELECT TYPE [ High\(1\) / Low\(0\) ] = %b", rank_addr);
317 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "NUMBER OF FB-DIMMS/CHANNEL [ 001->1 010->2 100->4 000->8 ] = %b", num_dimms);
318 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "RANK SIDES [ Single Sided\(0\) / Double Sided\(1\) ] = %b", rank);
319 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "DIMM Size [ 00->256Mb 01->512Mb 10->1Gb 11->2Gb ] = %b",dimm_size);
320 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "DRAM PART [ X4\(0\) / X8\(1\) ] = %b", dram_part);
321 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "---------------------------------------- ");
322
323 //---------------------------------------------------------------
324 // CHANNEL TYPE
325 //---------------------------------------------------------------
326
327 if (chnl_type == 1'b0)
328 begin // {
329`ifdef MCU_GATE
330 force `DRIF_PATH0.drif__n32447 = 1'b1;
331 force `DRIF_PATH1.drif__n32447 = 1'b1;
332 force `DRIF_PATH2.drif__n32447 = 1'b1;
333 force `DRIF_PATH3.drif__n32447 = 1'b1;
334`else
335 force `DRIF_PATH0.drif_single_channel_mode = 1'b1;
336 force `DRIF_PATH1.drif_single_channel_mode = 1'b1;
337 force `DRIF_PATH2.drif_single_channel_mode = 1'b1;
338 force `DRIF_PATH3.drif_single_channel_mode = 1'b1;
339`endif // mcu_gate
340
341 end // }
342
343 //------------------------------------------------------------
344 // RANK HIGH / LOW
345 // NO. OF DIMMS
346 // SINGLE / DUAL RANK
347 //------------------------------------------------------------
348
349 if (mcu_reg_slam_en)
350 case ({rank_addr, num_dimms, rank})
351
352 //-----------------------------------------------
353 // RANK HIGH
354 //-----------------------------------------------
355
356 //-------------
357 // SINGLE RANK
358 //-------------
359
360 5'b1_001_0:
361 begin // {
362`ifdef MCU_GATE
363 force `DRIF_PATH0.drif__n32443 = 1'b0;
364 force `DRIF_PATH1.drif__n32443 = 1'b0;
365 force `DRIF_PATH2.drif__n32443 = 1'b0;
366 force `DRIF_PATH3.drif__n32443 = 1'b0;
367
368 force `DRIF_PATH0.drif__n32446 = 1'b0;
369 force `DRIF_PATH1.drif__n32446 = 1'b0;
370 force `DRIF_PATH2.drif__n32446 = 1'b0;
371 force `DRIF_PATH3.drif__n32446 = 1'b0;
372
373 force `DRIF_PATH0.drif__n32440 = 1'b0;
374 force `DRIF_PATH0.drif__n32441 = 1'b0;
375 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b0;
376
377 force `DRIF_PATH1.drif__n32440 = 1'b0;
378 force `DRIF_PATH1.drif__n32441 = 1'b0;
379 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b0;
380
381 force `DRIF_PATH2.drif__n32440 = 1'b0;
382 force `DRIF_PATH2.drif__n32441 = 1'b0;
383 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b0;
384
385 force `DRIF_PATH3.drif__n32440 = 1'b0;
386 force `DRIF_PATH3.drif__n32441 = 1'b0;
387 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b0;
388
389 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
390 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
391 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
392 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b0;
393
394 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
395 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
396 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
397 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b0;
398
399 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
400 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
401 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
402 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b0;
403
404 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
405 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
406 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
407 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b0;
408`else
409 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
410 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
411 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
412 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
413
414 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
415 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
416 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
417 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
418
419 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h1;
420 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h1;
421 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h1;
422 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h1;
423
424 force `FBDIC_PATH0.amb_id = 4'h0;
425 force `FBDIC_PATH1.amb_id = 4'h0;
426 force `FBDIC_PATH2.amb_id = 4'h0;
427 force `FBDIC_PATH3.amb_id = 4'h0;
428`endif // mcu_gate
429
430 end // }
431
432 5'b1_010_0:
433 begin // {
434`ifdef MCU_GATE
435 force `DRIF_PATH0.drif__n32443 = 1'b0;
436 force `DRIF_PATH1.drif__n32443 = 1'b0;
437 force `DRIF_PATH2.drif__n32443 = 1'b0;
438 force `DRIF_PATH3.drif__n32443 = 1'b0;
439
440 force `DRIF_PATH0.drif__n32446 = 1'b0;
441 force `DRIF_PATH1.drif__n32446 = 1'b0;
442 force `DRIF_PATH2.drif__n32446 = 1'b0;
443 force `DRIF_PATH3.drif__n32446 = 1'b0;
444
445 force `DRIF_PATH0.drif__n32440 = 1'b0;
446 force `DRIF_PATH0.drif__n32441 = 1'b1;
447 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
448
449 force `DRIF_PATH1.drif__n32440 = 1'b0;
450 force `DRIF_PATH1.drif__n32441 = 1'b1;
451 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
452
453 force `DRIF_PATH2.drif__n32440 = 1'b0;
454 force `DRIF_PATH2.drif__n32441 = 1'b1;
455 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
456
457 force `DRIF_PATH3.drif__n32440 = 1'b0;
458 force `DRIF_PATH3.drif__n32441 = 1'b1;
459 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
460
461 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
462 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
463 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
464 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
465
466 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
467 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
468 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
469 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
470
471 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
472 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
473 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
474 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
475
476 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
477 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
478 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
479 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
480`else
481 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
482 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
483 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
484 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
485
486 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
487 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
488 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
489 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
490
491 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h2;
492 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h2;
493 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h2;
494 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h2;
495
496 force `FBDIC_PATH0.amb_id = 4'h1;
497 force `FBDIC_PATH1.amb_id = 4'h1;
498 force `FBDIC_PATH2.amb_id = 4'h1;
499 force `FBDIC_PATH3.amb_id = 4'h1;
500`endif // mcu_gate
501
502 end // }
503
504 5'b1_100_0:
505 begin // {
506`ifdef MCU_GATE
507 force `DRIF_PATH0.drif__n32443 = 1'b0;
508 force `DRIF_PATH1.drif__n32443 = 1'b0;
509 force `DRIF_PATH2.drif__n32443 = 1'b0;
510 force `DRIF_PATH3.drif__n32443 = 1'b0;
511
512 force `DRIF_PATH0.drif__n32446 = 1'b0;
513 force `DRIF_PATH1.drif__n32446 = 1'b0;
514 force `DRIF_PATH2.drif__n32446 = 1'b0;
515 force `DRIF_PATH3.drif__n32446 = 1'b0;
516
517 force `DRIF_PATH0.drif__n32440 = 1'b1;
518 force `DRIF_PATH0.drif__n32441 = 1'b0;
519 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
520
521 force `DRIF_PATH1.drif__n32440 = 1'b1;
522 force `DRIF_PATH1.drif__n32441 = 1'b0;
523 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
524
525 force `DRIF_PATH2.drif__n32440 = 1'b1;
526 force `DRIF_PATH2.drif__n32441 = 1'b0;
527 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
528
529 force `DRIF_PATH3.drif__n32440 = 1'b1;
530 force `DRIF_PATH3.drif__n32441 = 1'b0;
531 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
532
533 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
534 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
535 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
536 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
537
538 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
539 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
540 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
541 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
542
543 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
544 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
545 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
546 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
547
548 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
549 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
550 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
551 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
552`else
553 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
554 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
555 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
556 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
557
558 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
559 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
560 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
561 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
562
563 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h4;
564 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h4;
565 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h4;
566 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h4;
567
568 force `FBDIC_PATH0.amb_id = 4'h3;
569 force `FBDIC_PATH1.amb_id = 4'h3;
570 force `FBDIC_PATH2.amb_id = 4'h3;
571 force `FBDIC_PATH3.amb_id = 4'h3;
572`endif // mcu_gate
573
574 end // }
575
576 5'b1_000_0:
577 begin // {
578`ifdef MCU_GATE
579 force `DRIF_PATH0.drif__n32443 = 1'b0;
580 force `DRIF_PATH1.drif__n32443 = 1'b0;
581 force `DRIF_PATH2.drif__n32443 = 1'b0;
582 force `DRIF_PATH3.drif__n32443 = 1'b0;
583
584 force `DRIF_PATH0.drif__n32446 = 1'b0;
585 force `DRIF_PATH1.drif__n32446 = 1'b0;
586 force `DRIF_PATH2.drif__n32446 = 1'b0;
587 force `DRIF_PATH3.drif__n32446 = 1'b0;
588
589 force `DRIF_PATH0.drif__n32440 = 1'b0; // 8 dimms
590 force `DRIF_PATH0.drif__n32441 = 1'b0;
591 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
592
593 force `DRIF_PATH1.drif__n32440 = 1'b0;
594 force `DRIF_PATH1.drif__n32441 = 1'b0;
595 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
596
597 force `DRIF_PATH2.drif__n32440 = 1'b0;
598 force `DRIF_PATH2.drif__n32441 = 1'b0;
599 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
600
601 force `DRIF_PATH3.drif__n32440 = 1'b0;
602 force `DRIF_PATH3.drif__n32441 = 1'b0;
603 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
604
605 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
606 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
607 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
608 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
609
610 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
611 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
612 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
613 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
614
615 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
616 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
617 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
618 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
619
620 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
621 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
622 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
623 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
624`else
625 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
626 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
627 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
628 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
629
630 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
631 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
632 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
633 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
634
635 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h0; // 8 dimms
636 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h0;
637 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h0;
638 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h0;
639
640 force `FBDIC_PATH0.amb_id = 4'h7;
641 force `FBDIC_PATH1.amb_id = 4'h7;
642 force `FBDIC_PATH2.amb_id = 4'h7;
643 force `FBDIC_PATH3.amb_id = 4'h7;
644`endif // mcu_gate
645
646 end // }
647
648
649 //------------
650 // DUAL RANKS
651 //------------
652
653 5'b1_001_1:
654 begin // {
655`ifdef MCU_GATE
656 force `DRIF_PATH0.drif__n32443 = 1'b0;
657 force `DRIF_PATH1.drif__n32443 = 1'b0;
658 force `DRIF_PATH2.drif__n32443 = 1'b0;
659 force `DRIF_PATH3.drif__n32443 = 1'b0;
660
661 force `DRIF_PATH0.drif__n32446 = 1'b1;
662 force `DRIF_PATH1.drif__n32446 = 1'b1;
663 force `DRIF_PATH2.drif__n32446 = 1'b1;
664 force `DRIF_PATH3.drif__n32446 = 1'b1;
665
666 force `DRIF_PATH0.drif__n32440 = 1'b0;
667 force `DRIF_PATH0.drif__n32441 = 1'b0;
668 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b0;
669
670 force `DRIF_PATH1.drif__n32440 = 1'b0;
671 force `DRIF_PATH1.drif__n32441 = 1'b0;
672 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b0;
673
674 force `DRIF_PATH2.drif__n32440 = 1'b0;
675 force `DRIF_PATH2.drif__n32441 = 1'b0;
676 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b0;
677
678 force `DRIF_PATH3.drif__n32440 = 1'b0;
679 force `DRIF_PATH3.drif__n32441 = 1'b0;
680 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b0;
681
682 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
683 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
684 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
685 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b0;
686
687 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
688 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
689 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
690 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b0;
691
692 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
693 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
694 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
695 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b0;
696
697 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
698 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
699 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
700 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b0;
701`else
702 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
703 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
704 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
705 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
706
707 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
708 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
709 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
710 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
711
712 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h1;
713 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h1;
714 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h1;
715 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h1;
716
717 force `FBDIC_PATH0.amb_id = 4'h0;
718 force `FBDIC_PATH1.amb_id = 4'h0;
719 force `FBDIC_PATH2.amb_id = 4'h0;
720 force `FBDIC_PATH3.amb_id = 4'h0;
721`endif // mcu_gate
722
723 end // }
724
725 5'b1_010_1:
726 begin // {
727`ifdef MCU_GATE
728 force `DRIF_PATH0.drif__n32443 = 1'b0;
729 force `DRIF_PATH1.drif__n32443 = 1'b0;
730 force `DRIF_PATH2.drif__n32443 = 1'b0;
731 force `DRIF_PATH3.drif__n32443 = 1'b0;
732
733 force `DRIF_PATH0.drif__n32446 = 1'b1;
734 force `DRIF_PATH1.drif__n32446 = 1'b1;
735 force `DRIF_PATH2.drif__n32446 = 1'b1;
736 force `DRIF_PATH3.drif__n32446 = 1'b1;
737
738 force `DRIF_PATH0.drif__n32440 = 1'b0;
739 force `DRIF_PATH0.drif__n32441 = 1'b1;
740 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
741
742 force `DRIF_PATH1.drif__n32440 = 1'b0;
743 force `DRIF_PATH1.drif__n32441 = 1'b1;
744 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
745
746 force `DRIF_PATH2.drif__n32440 = 1'b0;
747 force `DRIF_PATH2.drif__n32441 = 1'b1;
748 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
749
750 force `DRIF_PATH3.drif__n32440 = 1'b0;
751 force `DRIF_PATH3.drif__n32441 = 1'b1;
752 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
753
754 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
755 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
756 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
757 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
758
759 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
760 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
761 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
762 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
763
764 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
765 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
766 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
767 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
768
769 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
770 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
771 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
772 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
773`else
774 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
775 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
776 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
777 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
778
779 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
780 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
781 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
782 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
783
784 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h2;
785 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h2;
786 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h2;
787 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h2;
788
789 force `FBDIC_PATH0.amb_id = 4'h1;
790 force `FBDIC_PATH1.amb_id = 4'h1;
791 force `FBDIC_PATH2.amb_id = 4'h1;
792 force `FBDIC_PATH3.amb_id = 4'h1;
793`endif // mcu_gate
794
795 end // }
796
797 5'b1_100_1:
798 begin // {
799`ifdef MCU_GATE
800 force `DRIF_PATH0.drif__n32443 = 1'b0;
801 force `DRIF_PATH1.drif__n32443 = 1'b0;
802 force `DRIF_PATH2.drif__n32443 = 1'b0;
803 force `DRIF_PATH3.drif__n32443 = 1'b0;
804
805 force `DRIF_PATH0.drif__n32446 = 1'b1;
806 force `DRIF_PATH1.drif__n32446 = 1'b1;
807 force `DRIF_PATH2.drif__n32446 = 1'b1;
808 force `DRIF_PATH3.drif__n32446 = 1'b1;
809
810 force `DRIF_PATH0.drif__n32440 = 1'b1;
811 force `DRIF_PATH0.drif__n32441 = 1'b0;
812 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
813
814 force `DRIF_PATH1.drif__n32440 = 1'b1;
815 force `DRIF_PATH1.drif__n32441 = 1'b0;
816 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
817
818 force `DRIF_PATH2.drif__n32440 = 1'b1;
819 force `DRIF_PATH2.drif__n32441 = 1'b0;
820 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
821
822 force `DRIF_PATH3.drif__n32440 = 1'b1;
823 force `DRIF_PATH3.drif__n32441 = 1'b0;
824 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
825
826 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
827 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
828 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
829 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
830
831 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
832 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
833 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
834 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
835
836 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
837 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
838 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
839 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
840
841 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
842 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
843 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
844 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
845`else
846 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
847 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
848 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
849 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
850
851 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
852 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
853 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
854 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
855
856 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h4;
857 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h4;
858 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h4;
859 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h4;
860
861 force `FBDIC_PATH0.amb_id = 4'h3;
862 force `FBDIC_PATH1.amb_id = 4'h3;
863 force `FBDIC_PATH2.amb_id = 4'h3;
864 force `FBDIC_PATH3.amb_id = 4'h3;
865`endif // mcu_gate
866
867 end // }
868
869 5'b1_000_1:
870 begin // {
871`ifdef MCU_GATE
872 force `DRIF_PATH0.drif__n32443 = 1'b0;
873 force `DRIF_PATH1.drif__n32443 = 1'b0;
874 force `DRIF_PATH2.drif__n32443 = 1'b0;
875 force `DRIF_PATH3.drif__n32443 = 1'b0;
876
877 force `DRIF_PATH0.drif__n32446 = 1'b1;
878 force `DRIF_PATH1.drif__n32446 = 1'b1;
879 force `DRIF_PATH2.drif__n32446 = 1'b1;
880 force `DRIF_PATH3.drif__n32446 = 1'b1;
881
882 force `DRIF_PATH0.drif__n32440 = 1'b0; // 8 dimms
883 force `DRIF_PATH0.drif__n32441 = 1'b0;
884 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
885
886 force `DRIF_PATH1.drif__n32440 = 1'b0;
887 force `DRIF_PATH1.drif__n32441 = 1'b0;
888 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
889
890 force `DRIF_PATH2.drif__n32440 = 1'b0;
891 force `DRIF_PATH2.drif__n32441 = 1'b0;
892 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
893
894 force `DRIF_PATH3.drif__n32440 = 1'b0;
895 force `DRIF_PATH3.drif__n32441 = 1'b0;
896 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
897
898 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
899 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
900 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
901 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
902
903 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
904 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
905 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
906 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
907
908 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
909 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
910 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
911 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
912
913 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
914 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
915 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
916 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
917`else
918 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b0;
919 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b0;
920 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b0;
921 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b0;
922
923 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
924 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
925 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
926 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
927
928 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h0; // 8 dimms
929 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h0;
930 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h0;
931 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h0;
932
933 force `FBDIC_PATH0.amb_id = 4'h7;
934 force `FBDIC_PATH1.amb_id = 4'h7;
935 force `FBDIC_PATH2.amb_id = 4'h7;
936 force `FBDIC_PATH3.amb_id = 4'h7;
937`endif // mcu_gate
938
939 end // }
940
941 //---------------------------------------------------------------
942 // RANK LOW
943 //---------------------------------------------------------------
944
945 //--------------
946 // SINGLE RANK
947 //--------------
948
949 5'b0_001_0:
950 begin // {
951`ifdef MCU_GATE
952 force `DRIF_PATH0.drif__n32443 = 1'b1;
953 force `DRIF_PATH1.drif__n32443 = 1'b1;
954 force `DRIF_PATH2.drif__n32443 = 1'b1;
955 force `DRIF_PATH3.drif__n32443 = 1'b1;
956
957 force `DRIF_PATH0.drif__n32446 = 1'b0;
958 force `DRIF_PATH1.drif__n32446 = 1'b0;
959 force `DRIF_PATH2.drif__n32446 = 1'b0;
960 force `DRIF_PATH3.drif__n32446 = 1'b0;
961
962 force `DRIF_PATH0.drif__n32440 = 1'b0;
963 force `DRIF_PATH0.drif__n32441 = 1'b0;
964 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b0;
965
966 force `DRIF_PATH1.drif__n32440 = 1'b0;
967 force `DRIF_PATH1.drif__n32441 = 1'b0;
968 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b0;
969
970 force `DRIF_PATH2.drif__n32440 = 1'b0;
971 force `DRIF_PATH2.drif__n32441 = 1'b0;
972 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b0;
973
974 force `DRIF_PATH3.drif__n32440 = 1'b0;
975 force `DRIF_PATH3.drif__n32441 = 1'b0;
976 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b0;
977
978 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
979 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
980 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
981 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b0;
982
983 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
984 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
985 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
986 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b0;
987
988 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
989 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
990 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
991 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b0;
992
993 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
994 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
995 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
996 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b0;
997`else
998 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
999 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1000 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1001 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1002
1003 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
1004 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
1005 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
1006 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
1007
1008 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h1;
1009 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h1;
1010 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h1;
1011 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h1;
1012
1013 force `FBDIC_PATH0.amb_id = 4'h0;
1014 force `FBDIC_PATH1.amb_id = 4'h0;
1015 force `FBDIC_PATH2.amb_id = 4'h0;
1016 force `FBDIC_PATH3.amb_id = 4'h0;
1017`endif // mcu_gate
1018
1019 end // }
1020
1021 5'b0_010_0:
1022 begin // {
1023`ifdef MCU_GATE
1024 force `DRIF_PATH0.drif__n32443 = 1'b1;
1025 force `DRIF_PATH1.drif__n32443 = 1'b1;
1026 force `DRIF_PATH2.drif__n32443 = 1'b1;
1027 force `DRIF_PATH3.drif__n32443 = 1'b1;
1028
1029 force `DRIF_PATH0.drif__n32446 = 1'b0;
1030 force `DRIF_PATH1.drif__n32446 = 1'b0;
1031 force `DRIF_PATH2.drif__n32446 = 1'b0;
1032 force `DRIF_PATH3.drif__n32446 = 1'b0;
1033
1034 force `DRIF_PATH0.drif__n32440 = 1'b0;
1035 force `DRIF_PATH0.drif__n32441 = 1'b1;
1036 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1037
1038 force `DRIF_PATH1.drif__n32440 = 1'b0;
1039 force `DRIF_PATH1.drif__n32441 = 1'b1;
1040 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1041
1042 force `DRIF_PATH2.drif__n32440 = 1'b0;
1043 force `DRIF_PATH2.drif__n32441 = 1'b1;
1044 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1045
1046 force `DRIF_PATH3.drif__n32440 = 1'b0;
1047 force `DRIF_PATH3.drif__n32441 = 1'b1;
1048 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1049
1050 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1051 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
1052 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
1053 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1054
1055 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1056 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
1057 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
1058 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1059
1060 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1061 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
1062 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
1063 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1064
1065 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1066 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
1067 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
1068 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1069`else
1070 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1071 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1072 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1073 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1074
1075 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
1076 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
1077 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
1078 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
1079
1080 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h2;
1081 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h2;
1082 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h2;
1083 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h2;
1084
1085 force `FBDIC_PATH0.amb_id = 4'h1;
1086 force `FBDIC_PATH1.amb_id = 4'h1;
1087 force `FBDIC_PATH2.amb_id = 4'h1;
1088 force `FBDIC_PATH3.amb_id = 4'h1;
1089`endif // mcu_gate
1090
1091 end // }
1092
1093 5'b0_100_0:
1094 begin // {
1095`ifdef MCU_GATE
1096 force `DRIF_PATH0.drif__n32443 = 1'b1;
1097 force `DRIF_PATH1.drif__n32443 = 1'b1;
1098 force `DRIF_PATH2.drif__n32443 = 1'b1;
1099 force `DRIF_PATH3.drif__n32443 = 1'b1;
1100
1101 force `DRIF_PATH0.drif__n32446 = 1'b0;
1102 force `DRIF_PATH1.drif__n32446 = 1'b0;
1103 force `DRIF_PATH2.drif__n32446 = 1'b0;
1104 force `DRIF_PATH3.drif__n32446 = 1'b0;
1105
1106 force `DRIF_PATH0.drif__n32440 = 1'b1;
1107 force `DRIF_PATH0.drif__n32441 = 1'b0;
1108 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1109
1110 force `DRIF_PATH1.drif__n32440 = 1'b1;
1111 force `DRIF_PATH1.drif__n32441 = 1'b0;
1112 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1113
1114 force `DRIF_PATH2.drif__n32440 = 1'b1;
1115 force `DRIF_PATH2.drif__n32441 = 1'b0;
1116 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1117
1118 force `DRIF_PATH3.drif__n32440 = 1'b1;
1119 force `DRIF_PATH3.drif__n32441 = 1'b0;
1120 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1121
1122 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1123 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
1124 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
1125 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1126
1127 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1128 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
1129 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
1130 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1131
1132 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1133 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
1134 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
1135 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1136
1137 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1138 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
1139 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
1140 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1141`else
1142 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1143 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1144 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1145 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1146
1147 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
1148 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
1149 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
1150 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
1151
1152 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h4;
1153 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h4;
1154 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h4;
1155 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h4;
1156
1157 force `FBDIC_PATH0.amb_id = 4'h3;
1158 force `FBDIC_PATH1.amb_id = 4'h3;
1159 force `FBDIC_PATH2.amb_id = 4'h3;
1160 force `FBDIC_PATH3.amb_id = 4'h3;
1161`endif // mcu_gate
1162
1163 end // }
1164
1165 5'b0_110_0:
1166 begin // {
1167`ifdef MCU_GATE
1168 force `DRIF_PATH0.drif__n32443 = 1'b1;
1169 force `DRIF_PATH1.drif__n32443 = 1'b1;
1170 force `DRIF_PATH2.drif__n32443 = 1'b1;
1171 force `DRIF_PATH3.drif__n32443 = 1'b1;
1172
1173 force `DRIF_PATH0.drif__n32446 = 1'b0;
1174 force `DRIF_PATH1.drif__n32446 = 1'b0;
1175 force `DRIF_PATH2.drif__n32446 = 1'b0;
1176 force `DRIF_PATH3.drif__n32446 = 1'b0;
1177
1178 force `DRIF_PATH0.drif__n32440 = 1'b1;
1179 force `DRIF_PATH0.drif__n32441 = 1'b1;
1180 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1181
1182 force `DRIF_PATH1.drif__n32440 = 1'b1;
1183 force `DRIF_PATH1.drif__n32441 = 1'b1;
1184 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1185
1186 force `DRIF_PATH2.drif__n32440 = 1'b1;
1187 force `DRIF_PATH2.drif__n32441 = 1'b1;
1188 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1189
1190 force `DRIF_PATH3.drif__n32440 = 1'b1;
1191 force `DRIF_PATH3.drif__n32441 = 1'b1;
1192 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1193
1194 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1195 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
1196 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
1197 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1198
1199 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1200 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
1201 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
1202 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1203
1204 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1205 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
1206 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
1207 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1208
1209 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1210 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
1211 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
1212 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1213`else
1214 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1215 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1216 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1217 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1218
1219 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
1220 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
1221 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
1222 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
1223
1224 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h6;
1225 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h6;
1226 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h6;
1227 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h6;
1228
1229 force `FBDIC_PATH0.amb_id = 4'h5;
1230 force `FBDIC_PATH1.amb_id = 4'h5;
1231 force `FBDIC_PATH2.amb_id = 4'h5;
1232 force `FBDIC_PATH3.amb_id = 4'h5;
1233`endif // mcu_gate
1234
1235 end // }
1236
1237 5'b0_000_0:
1238 begin // {
1239`ifdef MCU_GATE
1240 force `DRIF_PATH0.drif__n32443 = 1'b1;
1241 force `DRIF_PATH1.drif__n32443 = 1'b1;
1242 force `DRIF_PATH2.drif__n32443 = 1'b1;
1243 force `DRIF_PATH3.drif__n32443 = 1'b1;
1244
1245 force `DRIF_PATH0.drif__n32446 = 1'b0;
1246 force `DRIF_PATH1.drif__n32446 = 1'b0;
1247 force `DRIF_PATH2.drif__n32446 = 1'b0;
1248 force `DRIF_PATH3.drif__n32446 = 1'b0;
1249
1250 force `DRIF_PATH0.drif__n32440 = 1'b0; // 8 dimms
1251 force `DRIF_PATH0.drif__n32441 = 1'b0;
1252 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1253
1254 force `DRIF_PATH1.drif__n32440 = 1'b0;
1255 force `DRIF_PATH1.drif__n32441 = 1'b0;
1256 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1257
1258 force `DRIF_PATH2.drif__n32440 = 1'b0;
1259 force `DRIF_PATH2.drif__n32441 = 1'b0;
1260 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1261
1262 force `DRIF_PATH3.drif__n32440 = 1'b0;
1263 force `DRIF_PATH3.drif__n32441 = 1'b0;
1264 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1265
1266 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1267 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
1268 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
1269 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1270
1271 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1272 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
1273 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
1274 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1275
1276 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1277 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
1278 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
1279 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1280
1281 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1282 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
1283 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
1284 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1285`else
1286 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1287 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1288 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1289 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1290
1291 force `DRIF_PATH0.drif_stacked_dimm = 1'b0;
1292 force `DRIF_PATH1.drif_stacked_dimm = 1'b0;
1293 force `DRIF_PATH2.drif_stacked_dimm = 1'b0;
1294 force `DRIF_PATH3.drif_stacked_dimm = 1'b0;
1295
1296 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h0; // 8 dimms
1297 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h0;
1298 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h0;
1299 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h0;
1300
1301 force `FBDIC_PATH0.amb_id = 4'h7;
1302 force `FBDIC_PATH1.amb_id = 4'h7;
1303 force `FBDIC_PATH2.amb_id = 4'h7;
1304 force `FBDIC_PATH3.amb_id = 4'h7;
1305`endif // mcu_gate
1306
1307 end // }
1308
1309
1310 //------------
1311 // DUAL RANKS
1312 //------------
1313
1314 5'b0_001_1:
1315 begin // {
1316`ifdef MCU_GATE
1317 force `DRIF_PATH0.drif__n32443 = 1'b1;
1318 force `DRIF_PATH1.drif__n32443 = 1'b1;
1319 force `DRIF_PATH2.drif__n32443 = 1'b1;
1320 force `DRIF_PATH3.drif__n32443 = 1'b1;
1321
1322 force `DRIF_PATH0.drif__n32446 = 1'b1;
1323 force `DRIF_PATH1.drif__n32446 = 1'b1;
1324 force `DRIF_PATH2.drif__n32446 = 1'b1;
1325 force `DRIF_PATH3.drif__n32446 = 1'b1;
1326
1327 force `DRIF_PATH0.drif__n32440 = 1'b0;
1328 force `DRIF_PATH0.drif__n32441 = 1'b0;
1329 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b0;
1330
1331 force `DRIF_PATH1.drif__n32440 = 1'b0;
1332 force `DRIF_PATH1.drif__n32441 = 1'b0;
1333 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b0;
1334
1335 force `DRIF_PATH2.drif__n32440 = 1'b0;
1336 force `DRIF_PATH2.drif__n32441 = 1'b0;
1337 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b0;
1338
1339 force `DRIF_PATH3.drif__n32440 = 1'b0;
1340 force `DRIF_PATH3.drif__n32441 = 1'b0;
1341 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b0;
1342
1343 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1344 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
1345 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
1346 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b0;
1347
1348 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1349 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
1350 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
1351 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b0;
1352
1353 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1354 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
1355 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
1356 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b0;
1357
1358 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1359 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
1360 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
1361 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b0;
1362`else
1363 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1364 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1365 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1366 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1367
1368 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
1369 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
1370 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
1371 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
1372
1373 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h1;
1374 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h1;
1375 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h1;
1376 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h1;
1377
1378 force `FBDIC_PATH0.amb_id = 4'h0;
1379 force `FBDIC_PATH1.amb_id = 4'h0;
1380 force `FBDIC_PATH2.amb_id = 4'h0;
1381 force `FBDIC_PATH3.amb_id = 4'h0;
1382`endif // mcu_gate
1383
1384 end // }
1385
1386 5'b0_010_1:
1387 begin // {
1388`ifdef MCU_GATE
1389 force `DRIF_PATH0.drif__n32443 = 1'b1;
1390 force `DRIF_PATH1.drif__n32443 = 1'b1;
1391 force `DRIF_PATH2.drif__n32443 = 1'b1;
1392 force `DRIF_PATH3.drif__n32443 = 1'b1;
1393
1394 force `DRIF_PATH0.drif__n32446 = 1'b1;
1395 force `DRIF_PATH1.drif__n32446 = 1'b1;
1396 force `DRIF_PATH2.drif__n32446 = 1'b1;
1397 force `DRIF_PATH3.drif__n32446 = 1'b1;
1398
1399 force `DRIF_PATH0.drif__n32440 = 1'b0;
1400 force `DRIF_PATH0.drif__n32441 = 1'b1;
1401 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1402
1403 force `DRIF_PATH1.drif__n32440 = 1'b0;
1404 force `DRIF_PATH1.drif__n32441 = 1'b1;
1405 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1406
1407 force `DRIF_PATH2.drif__n32440 = 1'b0;
1408 force `DRIF_PATH2.drif__n32441 = 1'b1;
1409 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1410
1411 force `DRIF_PATH3.drif__n32440 = 1'b0;
1412 force `DRIF_PATH3.drif__n32441 = 1'b1;
1413 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1414
1415 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1416 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
1417 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
1418 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1419
1420 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1421 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
1422 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
1423 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1424
1425 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1426 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
1427 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
1428 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1429
1430 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1431 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
1432 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
1433 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1434`else
1435 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1436 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1437 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1438 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1439
1440 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
1441 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
1442 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
1443 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
1444
1445 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h2;
1446 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h2;
1447 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h2;
1448 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h2;
1449
1450 force `FBDIC_PATH0.amb_id = 4'h1;
1451 force `FBDIC_PATH1.amb_id = 4'h1;
1452 force `FBDIC_PATH2.amb_id = 4'h1;
1453 force `FBDIC_PATH3.amb_id = 4'h1;
1454`endif // mcu_gate
1455
1456 end // }
1457
1458 5'b0_100_1:
1459 begin // {
1460`ifdef MCU_GATE
1461 force `DRIF_PATH0.drif__n32443 = 1'b1;
1462 force `DRIF_PATH1.drif__n32443 = 1'b1;
1463 force `DRIF_PATH2.drif__n32443 = 1'b1;
1464 force `DRIF_PATH3.drif__n32443 = 1'b1;
1465
1466 force `DRIF_PATH0.drif__n32446 = 1'b1;
1467 force `DRIF_PATH1.drif__n32446 = 1'b1;
1468 force `DRIF_PATH2.drif__n32446 = 1'b1;
1469 force `DRIF_PATH3.drif__n32446 = 1'b1;
1470
1471 force `DRIF_PATH0.drif__n32440 = 1'b1;
1472 force `DRIF_PATH0.drif__n32441 = 1'b0;
1473 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1474
1475 force `DRIF_PATH1.drif__n32440 = 1'b1;
1476 force `DRIF_PATH1.drif__n32441 = 1'b0;
1477 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1478
1479 force `DRIF_PATH2.drif__n32440 = 1'b1;
1480 force `DRIF_PATH2.drif__n32441 = 1'b0;
1481 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1482
1483 force `DRIF_PATH3.drif__n32440 = 1'b1;
1484 force `DRIF_PATH3.drif__n32441 = 1'b0;
1485 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1486
1487 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1488 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b0;
1489 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
1490 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1491
1492 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1493 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b0;
1494 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
1495 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1496
1497 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1498 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b0;
1499 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
1500 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1501
1502 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1503 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b0;
1504 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
1505 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1506`else
1507 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1508 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1509 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1510 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1511
1512 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
1513 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
1514 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
1515 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
1516
1517 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h4;
1518 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h4;
1519 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h4;
1520 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h4;
1521
1522 force `FBDIC_PATH0.amb_id = 4'h3;
1523 force `FBDIC_PATH1.amb_id = 4'h3;
1524 force `FBDIC_PATH2.amb_id = 4'h3;
1525 force `FBDIC_PATH3.amb_id = 4'h3;
1526`endif // mcu_gate
1527
1528 end // }
1529
1530 5'b0_110_0:
1531 begin // {
1532`ifdef MCU_GATE
1533 force `DRIF_PATH0.drif__n32443 = 1'b1;
1534 force `DRIF_PATH1.drif__n32443 = 1'b1;
1535 force `DRIF_PATH2.drif__n32443 = 1'b1;
1536 force `DRIF_PATH3.drif__n32443 = 1'b1;
1537
1538 force `DRIF_PATH0.drif__n32446 = 1'b1;
1539 force `DRIF_PATH1.drif__n32446 = 1'b1;
1540 force `DRIF_PATH2.drif__n32446 = 1'b1;
1541 force `DRIF_PATH3.drif__n32446 = 1'b1;
1542
1543 force `DRIF_PATH0.drif__n32440 = 1'b1;
1544 force `DRIF_PATH0.drif__n32441 = 1'b1;
1545 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1546
1547 force `DRIF_PATH1.drif__n32440 = 1'b1;
1548 force `DRIF_PATH1.drif__n32441 = 1'b1;
1549 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1550
1551 force `DRIF_PATH2.drif__n32440 = 1'b1;
1552 force `DRIF_PATH2.drif__n32441 = 1'b1;
1553 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1554
1555 force `DRIF_PATH3.drif__n32440 = 1'b1;
1556 force `DRIF_PATH3.drif__n32441 = 1'b1;
1557 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1558
1559 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1560 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
1561 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b0;
1562 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1563
1564 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1565 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
1566 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b0;
1567 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1568
1569 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1570 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
1571 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b0;
1572 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1573
1574 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1575 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
1576 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b0;
1577 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1578`else
1579 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1580 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1581 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1582 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1583
1584 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
1585 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
1586 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
1587 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
1588
1589 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h6;
1590 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h6;
1591 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h6;
1592 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h6;
1593
1594 force `FBDIC_PATH0.amb_id = 4'h5;
1595 force `FBDIC_PATH1.amb_id = 4'h5;
1596 force `FBDIC_PATH2.amb_id = 4'h5;
1597 force `FBDIC_PATH3.amb_id = 4'h5;
1598`endif // mcu_gate
1599
1600 end // }
1601
1602 5'b0_000_1:
1603 begin // {
1604`ifdef MCU_GATE
1605 force `DRIF_PATH0.drif__n32443 = 1'b1;
1606 force `DRIF_PATH1.drif__n32443 = 1'b1;
1607 force `DRIF_PATH2.drif__n32443 = 1'b1;
1608 force `DRIF_PATH3.drif__n32443 = 1'b1;
1609
1610 force `DRIF_PATH0.drif__n32446 = 1'b1;
1611 force `DRIF_PATH1.drif__n32446 = 1'b1;
1612 force `DRIF_PATH2.drif__n32446 = 1'b1;
1613 force `DRIF_PATH3.drif__n32446 = 1'b1;
1614
1615 force `DRIF_PATH0.drif__n32440 = 1'b0; // 8 dimms
1616 force `DRIF_PATH0.drif__n32441 = 1'b0;
1617 force `DRIF_PATH0.drif__inv_drif_dimms_present = 1'b1;
1618
1619 force `DRIF_PATH1.drif__n32440 = 1'b0;
1620 force `DRIF_PATH1.drif__n32441 = 1'b0;
1621 force `DRIF_PATH1.drif__inv_drif_dimms_present = 1'b1;
1622
1623 force `DRIF_PATH2.drif__n32440 = 1'b0;
1624 force `DRIF_PATH2.drif__n32441 = 1'b0;
1625 force `DRIF_PATH2.drif__inv_drif_dimms_present = 1'b1;
1626
1627 force `DRIF_PATH3.drif__n32440 = 1'b0;
1628 force `DRIF_PATH3.drif__n32441 = 1'b0;
1629 force `DRIF_PATH3.drif__inv_drif_dimms_present = 1'b1;
1630
1631 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_6_ = 1'b0;
1632 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_5_ = 1'b1;
1633 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_4_ = 1'b1;
1634 force `FBDIC_PATH0.fbdic__fbdic_fbd_state_3_ = 1'b1;
1635
1636 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_6_ = 1'b0;
1637 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_5_ = 1'b1;
1638 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_4_ = 1'b1;
1639 force `FBDIC_PATH1.fbdic__fbdic_fbd_state_3_ = 1'b1;
1640
1641 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_6_ = 1'b0;
1642 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_5_ = 1'b1;
1643 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_4_ = 1'b1;
1644 force `FBDIC_PATH2.fbdic__fbdic_fbd_state_3_ = 1'b1;
1645
1646 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_6_ = 1'b0;
1647 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_5_ = 1'b1;
1648 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_4_ = 1'b1;
1649 force `FBDIC_PATH3.fbdic__fbdic_fbd_state_3_ = 1'b1;
1650`else
1651 force `DRIF_PATH0.drif_addr_bank_low_sel = 1'b1;
1652 force `DRIF_PATH1.drif_addr_bank_low_sel = 1'b1;
1653 force `DRIF_PATH2.drif_addr_bank_low_sel = 1'b1;
1654 force `DRIF_PATH3.drif_addr_bank_low_sel = 1'b1;
1655
1656 force `DRIF_PATH0.drif_stacked_dimm = 1'b1;
1657 force `DRIF_PATH1.drif_stacked_dimm = 1'b1;
1658 force `DRIF_PATH2.drif_stacked_dimm = 1'b1;
1659 force `DRIF_PATH3.drif_stacked_dimm = 1'b1;
1660
1661 force `DRIF_PATH0.drif_dimms_present[2:0] = 3'h0; // 8 dimms
1662 force `DRIF_PATH1.drif_dimms_present[2:0] = 3'h0;
1663 force `DRIF_PATH2.drif_dimms_present[2:0] = 3'h0;
1664 force `DRIF_PATH3.drif_dimms_present[2:0] = 3'h0;
1665
1666 force `FBDIC_PATH0.amb_id = 4'h7;
1667 force `FBDIC_PATH1.amb_id = 4'h7;
1668 force `FBDIC_PATH2.amb_id = 4'h7;
1669 force `FBDIC_PATH3.amb_id = 4'h7;
1670`endif // mcu_gate
1671
1672 end // }
1673
1674 default:
1675 begin // {
1676 end // }
1677
1678 endcase
1679
1680end
1681
1682end // }
1683
1684initial
1685begin // {
1686
1687`ifdef PALLADIUM
1688`else
1689 #1;
1690`endif
1691
1692 if ($test$plusargs("NO_MCU_CSR_SLAM")) begin
1693 `PR_INFO ("mcu_mem_config", `INFO, "MCU CSRs not slammed");
1694 end
1695 else begin
1696
1697
1698`ifdef FLUSH_RESET
1699 @(posedge `TOP.flush_reset_complete);
1700 $display("FIRST flush reset done\n");
1701 if (dtm_enabled) begin
1702 @(posedge `TOP.flush_reset_complete);
1703 $display("SECOND flush reset done\n");
1704 end
1705`endif
1706
1707 //force `DRIF_PATH0.mcu_ddp_clk_enable = 1'b1;
1708 //force `DRIF_PATH1.mcu_ddp_clk_enable = 1'b1;
1709 //force `DRIF_PATH2.mcu_ddp_clk_enable = 1'b1;
1710 //force `DRIF_PATH3.mcu_ddp_clk_enable = 1'b1;
1711
1712 if (mcu_reg_slam_en && ~dtm_enabled) begin
1713 force `DRIF_PATH0.drif_cke_reg = 1'b1;
1714 force `DRIF_PATH1.drif_cke_reg = 1'b1;
1715 force `DRIF_PATH2.drif_cke_reg = 1'b1;
1716 force `DRIF_PATH3.drif_cke_reg = 1'b1;
1717 end
1718
1719 if ($test$plusargs("DRAM_SCRUB"))
1720 begin // {
1721`ifdef MCU_GATE
1722 force `DRIF_PATH0.drif__drif_data_scrub_enabled = 1'b1;
1723 force `DRIF_PATH1.drif__drif_data_scrub_enabled = 1'b1;
1724 force `DRIF_PATH2.drif__drif_data_scrub_enabled = 1'b1;
1725 force `DRIF_PATH3.drif__drif_data_scrub_enabled = 1'b1;
1726
1727 force {`DRIF_PATH0.drif__inv_drif_freq_scrub_11_,`DRIF_PATH0.drif__inv_drif_freq_scrub_10_,`DRIF_PATH0.drif__inv_drif_freq_scrub_9_,`DRIF_PATH0.drif__inv_drif_freq_scrub_8_,`DRIF_PATH0.drif__inv_drif_freq_scrub_7_,`DRIF_PATH0.drif__inv_drif_freq_scrub_6_,`DRIF_PATH0.drif__inv_drif_freq_scrub_5_,`DRIF_PATH0.drif__inv_drif_freq_scrub_4_,`DRIF_PATH0.drif__inv_drif_freq_scrub_3_,`DRIF_PATH0.drif__inv_drif_freq_scrub_2_,`DRIF_PATH0.drif__inv_drif_freq_scrub_1_,`DRIF_PATH0.drif__inv_drif_freq_scrub_0_} = 1'hfef;
1728
1729 force {`DRIF_PATH1.drif__inv_drif_freq_scrub_11_,`DRIF_PATH1.drif__inv_drif_freq_scrub_10_,`DRIF_PATH1.drif__inv_drif_freq_scrub_9_,`DRIF_PATH1.drif__inv_drif_freq_scrub_8_,`DRIF_PATH1.drif__inv_drif_freq_scrub_7_,`DRIF_PATH1.drif__inv_drif_freq_scrub_6_,`DRIF_PATH1.drif__inv_drif_freq_scrub_5_,`DRIF_PATH1.drif__inv_drif_freq_scrub_4_,`DRIF_PATH1.drif__inv_drif_freq_scrub_3_,`DRIF_PATH1.drif__inv_drif_freq_scrub_2_,`DRIF_PATH1.drif__inv_drif_freq_scrub_1_,`DRIF_PATH1.drif__inv_drif_freq_scrub_0_} = 1'hfef;
1730
1731 force {`DRIF_PATH2.drif__inv_drif_freq_scrub_11_,`DRIF_PATH2.drif__inv_drif_freq_scrub_10_,`DRIF_PATH2.drif__inv_drif_freq_scrub_9_,`DRIF_PATH2.drif__inv_drif_freq_scrub_8_,`DRIF_PATH2.drif__inv_drif_freq_scrub_7_,`DRIF_PATH2.drif__inv_drif_freq_scrub_6_,`DRIF_PATH2.drif__inv_drif_freq_scrub_5_,`DRIF_PATH2.drif__inv_drif_freq_scrub_4_,`DRIF_PATH2.drif__inv_drif_freq_scrub_3_,`DRIF_PATH2.drif__inv_drif_freq_scrub_2_,`DRIF_PATH2.drif__inv_drif_freq_scrub_1_,`DRIF_PATH2.drif__inv_drif_freq_scrub_0_} = 1'hfef;
1732
1733 force {`DRIF_PATH3.drif__inv_drif_freq_scrub_11_,`DRIF_PATH3.drif__inv_drif_freq_scrub_10_,`DRIF_PATH3.drif__inv_drif_freq_scrub_9_,`DRIF_PATH3.drif__inv_drif_freq_scrub_8_,`DRIF_PATH3.drif__inv_drif_freq_scrub_7_,`DRIF_PATH3.drif__inv_drif_freq_scrub_6_,`DRIF_PATH3.drif__inv_drif_freq_scrub_5_,`DRIF_PATH3.drif__inv_drif_freq_scrub_4_,`DRIF_PATH3.drif__inv_drif_freq_scrub_3_,`DRIF_PATH3.drif__inv_drif_freq_scrub_2_,`DRIF_PATH3.drif__inv_drif_freq_scrub_1_,`DRIF_PATH3.drif__inv_drif_freq_scrub_0_} = 1'hfef;
1734`else
1735 force `DRIF_PATH0.drif_data_scrub_enabled = 1'b1;
1736 force `DRIF_PATH1.drif_data_scrub_enabled = 1'b1;
1737 force `DRIF_PATH2.drif_data_scrub_enabled = 1'b1;
1738 force `DRIF_PATH3.drif_data_scrub_enabled = 1'b1;
1739
1740 force `DRIF_PATH0.drif_freq_scrub[11:0] =12'h10;
1741 force `DRIF_PATH1.drif_freq_scrub[11:0] =12'h10;
1742 force `DRIF_PATH2.drif_freq_scrub[11:0] =12'h10;
1743 force `DRIF_PATH3.drif_freq_scrub[11:0] =12'h10;
1744`endif // mcu_gate
1745 end // }
1746
1747 if ($test$plusargs("WARM_RESET"))
1748 begin // {
1749`ifdef MCU_GATE
1750 force `MCU0.fbdic__n15703 = 1'b1;
1751 force `MCU1.fbdic__n15703 = 1'b1;
1752 force `MCU2.fbdic__n15703 = 1'b1;
1753 force `MCU3.fbdic__n15703 = 1'b1;
1754`else
1755 force `MCU0.fbdic.fbdtm.rdpctl_kp_lnk_up = 1'b1;
1756 force `MCU1.fbdic.fbdtm.rdpctl_kp_lnk_up = 1'b1;
1757 force `MCU2.fbdic.fbdtm.rdpctl_kp_lnk_up = 1'b1;
1758 force `MCU3.fbdic.fbdtm.rdpctl_kp_lnk_up = 1'b1;
1759`endif // mcu_gate
1760 end // }
1761
1762`ifdef NEC_FBDIMM
1763 if (mcu_reg_slam_en) begin
1764 fork
1765 begin
1766`ifdef MCU_GATE
1767 force `DRIF_PATH0.drif__N2397 = 1'b0;
1768 wait (`FBDIC_PATH0.fbdic__n15588 == 1);
1769 wait (`FBDIC_PATH0.fbdic__n15588 == 0);
1770 wait (`FBDIC_PATH0.fbdic__n15588 == 1);
1771 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1772 force `DRIF_PATH0.drif__N2397 = 1'b1;
1773`else
1774 force `DRIF_PATH0.drif_init = 1'b1;
1775 wait (`FBDIC_PATH0.fbdic_l0_state == 1);
1776 wait (`FBDIC_PATH0.fbdic_l0_state == 0);
1777 wait (`FBDIC_PATH0.fbdic_l0_state == 1);
1778`ifdef X8
1779 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx8.U00.dram_init_done==1);
1780`else
1781 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1782`endif
1783 repeat (500) @ (posedge `DRIF_PATH0.drl2clk);
1784 force `DRIF_PATH0.drif_init = 1'b0;
1785`endif // mcu_gate
1786
1787 end
1788
1789 begin
1790`ifdef MCU_GATE
1791 force `DRIF_PATH1.drif__N2397 = 1'b0;
1792 wait (`FBDIC_PATH1.fbdic__n15588 == 1);
1793 wait (`FBDIC_PATH1.fbdic__n15588 == 0);
1794 wait (`FBDIC_PATH1.fbdic__n15588 == 1);
1795 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1796 force `DRIF_PATH1.drif__N23973 = 1'b1;
1797`else
1798 force `DRIF_PATH1.drif_init = 1'b1;
1799 wait (`FBDIC_PATH1.fbdic_l0_state == 1);
1800 wait (`FBDIC_PATH1.fbdic_l0_state == 0);
1801 wait (`FBDIC_PATH1.fbdic_l0_state == 1);
1802`ifdef X8
1803 wait (tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx8.U00.dram_init_done==1);
1804`else
1805 wait (tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1806`endif
1807 repeat (500) @ (posedge `DRIF_PATH1.drl2clk);
1808 force `DRIF_PATH1.drif_init = 1'b0;
1809`endif // mcu_gate
1810
1811 end
1812
1813 begin
1814`ifdef MCU_GATE
1815 force `DRIF_PATH2.drif__N2397 = 1'b0;
1816 wait (`FBDIC_PATH2.fbdic__n15588 == 1);
1817 wait (`FBDIC_PATH2.fbdic__n15588 == 0);
1818 wait (`FBDIC_PATH2.fbdic__n15588 == 1);
1819 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1820 force `DRIF_PATH2.drif__N2397 = 1'b1;
1821`else
1822 force `DRIF_PATH2.drif_init = 1'b1;
1823 wait (`FBDIC_PATH2.fbdic_l0_state == 1);
1824 wait (`FBDIC_PATH2.fbdic_l0_state == 0);
1825 wait (`FBDIC_PATH2.fbdic_l0_state == 1);
1826`ifdef X8
1827 wait (tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx8.U00.dram_init_done==1);
1828`else
1829 wait (tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1830`endif
1831 repeat (500) @ (posedge `DRIF_PATH2.drl2clk);
1832 force `DRIF_PATH2.drif_init = 1'b0;
1833`endif // mcu_gate
1834
1835 end
1836
1837 begin
1838`ifdef MCU_GATE
1839 force `DRIF_PATH3.drif__N2397 = 1'b0;
1840 wait (`FBDIC_PATH3.fbdic__n15588 == 1);
1841 wait (`FBDIC_PATH3.fbdic__n15588 == 0);
1842 wait (`FBDIC_PATH3.fbdic__n15588 == 1);
1843 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1844 force `DRIF_PATH3.drif__N2397 = 1'b1;
1845`else
1846 force `DRIF_PATH3.drif_init = 1'b1;
1847 wait (`FBDIC_PATH3.fbdic_l0_state == 1);
1848 wait (`FBDIC_PATH3.fbdic_l0_state == 0);
1849 wait (`FBDIC_PATH3.fbdic_l0_state == 1);
1850`ifdef X8
1851 wait (tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx8.U00.dram_init_done==1);
1852`else
1853 wait (tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1854`endif
1855 repeat (500) @ (posedge `DRIF_PATH3.drl2clk);
1856 force `DRIF_PATH3.drif_init = 1'b0;
1857`endif // mcu_gate
1858
1859 end
1860join
1861end
1862`else
1863`ifdef INPHI_FBDIMM
1864 if (mcu_reg_slam_en) begin
1865 fork
1866 begin
1867`ifdef MCU_GATE
1868 force `DRIF_PATH0.drif__N2397 = 1'b0;
1869 wait (`FBDIC_PATH0.fbdic__n15588 == 1);
1870 wait (`FBDIC_PATH0.fbdic__n15588 == 0);
1871 wait (`FBDIC_PATH0.fbdic__n15588 == 1);
1872 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1873 force `DRIF_PATH0.drif__N2397 = 1'b1;
1874`else
1875 force `DRIF_PATH0.drif_init = 1'b1;
1876 wait (`FBDIC_PATH0.fbdic_l0_state == 1);
1877 wait (`FBDIC_PATH0.fbdic_l0_state == 0);
1878 wait (`FBDIC_PATH0.fbdic_l0_state == 1);
1879 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1880 force `DRIF_PATH0.drif_init = 1'b0;
1881`endif // mcu_gate
1882
1883 end
1884
1885 begin
1886`ifdef MCU_GATE
1887 force `DRIF_PATH1.drif__N2397 = 1'b0;
1888 wait (`FBDIC_PATH1.fbdic__n15588 == 1);
1889 wait (`FBDIC_PATH1.fbdic__n15588 == 0);
1890 wait (`FBDIC_PATH1.fbdic__n15588 == 1);
1891 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1892 force `DRIF_PATH1.drif__N2397 = 1'b1;
1893`else
1894 force `DRIF_PATH1.drif_init = 1'b1;
1895 wait (`FBDIC_PATH1.fbdic_l0_state == 1);
1896 wait (`FBDIC_PATH1.fbdic_l0_state == 0);
1897 wait (`FBDIC_PATH1.fbdic_l0_state == 1);
1898 wait (tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1899 force `DRIF_PATH1.drif_init = 1'b0;
1900`endif // mcu_gate
1901
1902 end
1903 begin
1904`ifdef MCU_GATE
1905 force `DRIF_PATH2.drif__N2397 = 1'b0;
1906 wait (`FBDIC_PATH2.fbdic__n15588 == 1);
1907 wait (`FBDIC_PATH2.fbdic__n15588 == 0);
1908 wait (`FBDIC_PATH2.fbdic__n15588 == 1);
1909 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1910 force `DRIF_PATH2.drif__N2397 = 1'b1;
1911`else
1912 force `DRIF_PATH2.drif_init = 1'b1;
1913 wait (`FBDIC_PATH2.fbdic_l0_state == 1);
1914 wait (`FBDIC_PATH2.fbdic_l0_state == 0);
1915 wait (`FBDIC_PATH2.fbdic_l0_state == 1);
1916 wait (tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1917 force `DRIF_PATH2.drif_init = 1'b0;
1918`endif // mcu_gate
1919
1920 end
1921 begin
1922`ifdef MCU_GATE
1923 force `DRIF_PATH3.drif__N2397 = 1'b0;
1924 wait (`FBDIC_PATH3.fbdic__n15588 == 1);
1925 wait (`FBDIC_PATH3.fbdic__n15588 == 0);
1926 wait (`FBDIC_PATH3.fbdic__n15588 == 1);
1927 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1928 force `DRIF_PATH3.drif__N2397 = 1'b1;
1929`else
1930 force `DRIF_PATH3.drif_init = 1'b1;
1931 wait (`FBDIC_PATH3.fbdic_l0_state == 1);
1932 wait (`FBDIC_PATH3.fbdic_l0_state == 0);
1933 wait (`FBDIC_PATH3.fbdic_l0_state == 1);
1934 wait (tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1935 force `DRIF_PATH3.drif_init = 1'b0;
1936`endif // mcu_gate
1937
1938 end
1939join
1940 end
1941`else
1942`ifdef PALLADIUM
1943// NO_MCU_CSR_SLAM is set for FC1
1944`else
1945 if (mcu_reg_slam_en) begin
1946 fork
1947 begin
1948`ifdef MCU_GATE
1949 if (dtm_enabled)
1950 begin
1951 // do nothing 5/12/06*
1952 end
1953 else
1954 begin
1955 force `DRIF_PATH0.drif__N2397 = 1'b0;
1956 wait (`FBDIC_PATH0.fbdic__n15588 == 1);
1957 force `DRIF_PATH0.drif__N2397 = 1'b1;
1958 end
1959`else
1960 if (dtm_enabled)
1961 begin
1962 /* SV DTM Changes 04/25/06
1963 force `DRIF_PATH0.drif_init = 1'b1;
1964 `ifndef AXIS
1965 wait (tb_top.mcusat_fbdimm.fbdimm_mem0.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1966 `endif
1967 force `DRIF_PATH0.drif_init = 1'b0;
1968 END SV Changes */
1969 end
1970 else
1971 begin
1972 force `DRIF_PATH0.drif_init = 1'b1;
1973 wait (`FBDIC_PATH0.fbdic_l0_state == 1);
1974 force `DRIF_PATH0.drif_init = 1'b0;
1975 end
1976`endif // mcu_gate
1977
1978 end
1979
1980 begin
1981`ifdef MCU_GATE
1982 if (dtm_enabled)
1983 begin
1984 // do nothing 5/12/06*
1985 end
1986 else
1987 begin
1988 force `DRIF_PATH1.drif__N2397 = 1'b0;
1989 wait (`FBDIC_PATH1.fbdic__n15588 == 1);
1990 force `DRIF_PATH1.drif__N2397 = 1'b1;
1991 end
1992`else
1993 if (dtm_enabled)
1994 begin
1995 /* SV DTM Changes 04/25/06
1996 force `DRIF_PATH1.drif_init = 1'b1;
1997 `ifndef AXIS
1998 wait (tb_top.mcusat_fbdimm.fbdimm_mem2.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
1999 `endif
2000 force `DRIF_PATH1.drif_init = 1'b0;
2001 END SV changes */
2002
2003 end
2004 else
2005 begin
2006 force `DRIF_PATH1.drif_init = 1'b1;
2007 wait (`FBDIC_PATH1.fbdic_l0_state == 1);
2008 force `DRIF_PATH1.drif_init = 1'b0;
2009 end
2010`endif // mcu_gate
2011
2012 end
2013 begin
2014`ifdef MCU_GATE
2015 if (dtm_enabled)
2016 begin
2017 // do nothing 5/12/06*
2018 end
2019 else
2020 begin
2021 force `DRIF_PATH2.drif__N2397 = 1'b0;
2022 wait (`FBDIC_PATH2.fbdic__n15588 == 1);
2023 force `DRIF_PATH2.drif__N2397 = 1'b1;
2024 end
2025`else
2026 if (dtm_enabled)
2027 begin
2028 /* SV DTM Changes 04/25/06
2029 force `DRIF_PATH2.drif_init = 1'b1;
2030 `ifndef AXIS
2031 wait (tb_top.mcusat_fbdimm.fbdimm_mem4.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
2032 `endif
2033 force `DRIF_PATH2.drif_init = 1'b0;
2034 END SV Changes */
2035 end
2036 else
2037 begin
2038 force `DRIF_PATH2.drif_init = 1'b1;
2039 wait (`FBDIC_PATH2.fbdic_l0_state == 1);
2040 force `DRIF_PATH2.drif_init = 1'b0;
2041 end
2042`endif // mcu_gate
2043
2044 end
2045 begin
2046`ifdef MCU_GATE
2047 if (dtm_enabled)
2048 begin
2049 // do nothing 5/12/06*
2050 end
2051 else
2052 begin
2053 force `DRIF_PATH3.drif__N2397 = 1'b0;
2054 wait (`FBDIC_PATH3.fbdic__n15588 == 1);
2055 force `DRIF_PATH3.drif__N2397 = 1'b1;
2056 end
2057`else
2058 if (dtm_enabled)
2059 begin
2060 /* SV DTM Changes 04/25/06
2061 force `DRIF_PATH3.drif_init = 1'b1;
2062 `ifndef AXIS
2063 wait (tb_top.mcusat_fbdimm.fbdimm_mem6.fbdimm0.fbdimm_DIMMx4.U00.dram_init_done==1);
2064 `endif
2065 force `DRIF_PATH3.drif_init = 1'b0;
2066 END SV Changes */
2067 end
2068 else
2069 begin
2070 force `DRIF_PATH3.drif_init = 1'b1;
2071 wait (`FBDIC_PATH3.fbdic_l0_state == 1);
2072 force `DRIF_PATH3.drif_init = 1'b0;
2073 end
2074`endif // mcu_gate
2075
2076 end
2077
2078 join
2079 end // if (mcu_reg_slam_en)
2080
2081`endif // !`ifdef PALLADIUM
2082`endif // !`ifdef INPHI_FBDIMM
2083`endif // !`ifdef NEC_FBDIMM
2084
2085end
2086end // }
2087
2088//---- Program MCU DDR2 Timing Regs ------
2089
2090reg sng_channel;
2091reg [3:0] cas_latency;
2092reg [3:0] cas_latency_gate;
2093reg [3:0] additive_latency;
2094reg [3:0] additive_latency_gate;
2095reg [4:0] msb_drc;
2096reg [7:0] sync_train_interval;
2097reg [7:0] sync_train_interval_gate;
2098reg [7:0] cmd2datanxt;
2099reg [7:0] cmd2datacur;
2100
2101initial
2102begin
2103
2104`ifdef PALLADIUM
2105`else
2106 #1;
2107`endif
2108
2109 if ($test$plusargs("SNG_CHANNEL"))
2110 sng_channel = 1'b1;
2111 else
2112 sng_channel = 1'b0;
2113
2114 // default values
2115 cas_latency = 4'h3;
2116 additive_latency = 4'h3;
2117 sync_train_interval = 8'h2A; // default = 42;
2118
2119 if($value$plusargs("SET_CMD2DATA=%h",cmd2datanxt))
2120 cmd2datacur = cmd2datanxt;
2121 else begin
2122 cmd2datanxt = 8'h28; // default DLYFRMS [7:4] = 2 frames, DLYFRAC [3:0] = 8 UI
2123 cmd2datacur = 8'h28; // default DLYFRMS [7:4] = 2 frames, DLYFRAC [3:0] = 8 UI
2124 end
2125
2126 if(sng_channel)
2127 msb_drc = 5'h7;
2128 else
2129 msb_drc = 5'h6;
2130
2131 if ($test$plusargs("NO_MCU_CSR_SLAM")) begin
2132 `PR_INFO ("mcu_mem_config", `INFO, "MCU CSRs not slammed");
2133 end
2134 else begin
2135
2136 if (sng_channel) begin
2137`ifdef MCU_GATE
2138 force `MCU0.drif__n32447 = 1'b1;
2139 force `MCU1.drif__n32447 = 1'b1;
2140 force `MCU2.drif__n32447 = 1'b1;
2141 force `MCU3.drif__n32447 = 1'b1;
2142`else
2143 force `MCU0.drif.drif_single_channel_mode = 1'b1;
2144 force `MCU1.drif.drif_single_channel_mode = 1'b1;
2145 force `MCU2.drif.drif_single_channel_mode = 1'b1;
2146 force `MCU3.drif.drif_single_channel_mode = 1'b1;
2147`endif // mcu_gate
2148
2149 end
2150
2151 // Force cas_latency and additive latency; works only with idt amb
2152 `ifdef IDT_FBDIMM
2153
2154 if($value$plusargs("SET_CL=%d",cas_latency))
2155 begin
2156`ifdef MCU_GATE
2157 cas_latency_gate = cas_latency ^ 2'b11;
2158 force {`MCU0.drif__mode_reg_6_,`MCU0.drif__inv_mode_reg_5_,`MCU0.drif__inv_mode_reg_4_} = cas_latency_gate;
2159 force {`MCU1.drif__mode_reg_6_,`MCU1.drif__inv_mode_reg_5_,`MCU1.drif__inv_mode_reg_4_} = cas_latency_gate;
2160 force {`MCU2.drif__mode_reg_6_,`MCU2.drif__inv_mode_reg_5_,`MCU2.drif__inv_mode_reg_4_} = cas_latency_gate;
2161 force {`MCU3.drif__mode_reg_6_,`MCU3.drif__inv_mode_reg_5_,`MCU3.drif__inv_mode_reg_4_} = cas_latency_gate;
2162`else
2163 force `MCU0.drif.mode_reg[6:4] = cas_latency;
2164 force `MCU1.drif.mode_reg[6:4] = cas_latency;
2165 force `MCU2.drif.mode_reg[6:4] = cas_latency;
2166 force `MCU3.drif.mode_reg[6:4] = cas_latency;
2167`endif // mcu_gate
2168
2169 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** SET_CL *** : CL = %d", cas_latency);
2170 end // SET_CL
2171
2172 if($value$plusargs("SET_AL=%d",additive_latency))
2173 begin
2174`ifdef MCU_GATE
2175 additive_latency_gate = additive_latency ^ 2'b11;
2176 force {`MCU0.drif__ext_mode_reg1_5_,`MCU0.drif__inv_ext_mode_reg1_4_,`MCU0.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2177 force {`MCU1.drif__ext_mode_reg1_5_,`MCU1.drif__inv_ext_mode_reg1_4_,`MCU1.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2178 force {`MCU2.drif__ext_mode_reg1_5_,`MCU2.drif__inv_ext_mode_reg1_4_,`MCU2.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2179 force {`MCU3.drif__ext_mode_reg1_5_,`MCU3.drif__inv_ext_mode_reg1_4_,`MCU3.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2180`else
2181 force `MCU0.drif.ext_mode_reg1[5:3] = additive_latency;
2182 force `MCU1.drif.ext_mode_reg1[5:3] = additive_latency;
2183 force `MCU2.drif.ext_mode_reg1[5:3] = additive_latency;
2184 force `MCU3.drif.ext_mode_reg1[5:3] = additive_latency;
2185`endif // mcu_gate
2186
2187 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** SET_AL *** : AL = %d", additive_latency);
2188 end
2189
2190
2191 if($test$plusargs("RANDOM_PARAM"))
2192 begin
2193
2194 cmd2datanxt[7:4] = ({$random(`PARGS.seed)} % 9) + 1;
2195 if (cmd2datanxt[7:4] == 4'h1) cmd2datanxt[7:4] = 4'h2;
2196 if (cmd2datanxt[7:4] == 4'h8) cmd2datanxt[7:4] = 4'h9;
2197 cmd2datanxt[3:0] = 4'h0; // Do not randomize the UI delay
2198 cmd2datacur = cmd2datanxt;
2199
2200 cas_latency = ({$random(`PARGS.seed)} % 3) + 3;
2201 if(cas_latency == 4'h5)
2202 additive_latency = 4'h4;
2203 else
2204 additive_latency = ({$random(`PARGS.seed)} % 2) + 3;
2205
2206`ifdef MCU_GATE
2207 cas_latency_gate = cas_latency ^ 2'b11;
2208 additive_latency_gate = additive_latency ^ 2'b11;
2209 force {`MCU0.drif__mode_reg_6_,`MCU0.drif__inv_mode_reg_5_,`MCU0.drif__inv_mode_reg_4_} = cas_latenc_gatey;
2210 force {`MCU1.drif__mode_reg_6_,`MCU1.drif__inv_mode_reg_5_,`MCU1.drif__inv_mode_reg_4_} = cas_latency_gate;
2211 force {`MCU2.drif__mode_reg_6_,`MCU2.drif__inv_mode_reg_5_,`MCU2.drif__inv_mode_reg_4_} = cas_latency_gate;
2212 force {`MCU3.drif__mode_reg_6_,`MCU3.drif__inv_mode_reg_5_,`MCU3.drif__inv_mode_reg_4_} = cas_latency_gate;
2213
2214 force {`MCU0.drif__ext_mode_reg1_5_,`MCU0.drif__inv_ext_mode_reg1_4_,`MCU0.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2215 force {`MCU1.drif__ext_mode_reg1_5_,`MCU1.drif__inv_ext_mode_reg1_4_,`MCU1.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2216 force {`MCU2.drif__ext_mode_reg1_5_,`MCU2.drif__inv_ext_mode_reg1_4_,`MCU2.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2217 force {`MCU3.drif__ext_mode_reg1_5_,`MCU3.drif__inv_ext_mode_reg1_4_,`MCU3.drif__inv_ext_mode_reg1_3_} = additive_latency_gate;
2218
2219 sync_train_interval = ({$random(`PARGS.seed)} % 11) + 32;
2220 sync_train_interval_gate = sync_train_interval ^ 6'b101010;
2221 force {`MCU0.fbdic__fbdtm_fbdic_sync_frm_period_out_5_,`MCU0.fbdic__fbdic_sync_frm_period_4_,`MCU0.fbdic__fbdtm_fbdic_sync_frm_period_out_3_,`MCU0.fbdic__fbdic_sync_frm_period_2_,`MCU0.fbdic__fbdtm_fbdic_sync_frm_period_out_1_,`MCU0.fbdic__fbdic_sync_frm_period_0_} = sync_train_interval_gate[5:0];
2222 force {`MCU1.fbdic__fbdtm_fbdic_sync_frm_period_out_5_,`MCU1.fbdic__fbdic_sync_frm_period_4_,`MCU1.fbdic__fbdtm_fbdic_sync_frm_period_out_3_,`MCU1.fbdic__fbdic_sync_frm_period_2_,`MCU1.fbdic__fbdtm_fbdic_sync_frm_period_out_1_,`MCU1.fbdic__fbdic_sync_frm_period_0_} = sync_train_interval_gate[5:0];
2223 force {`MCU2.fbdic__fbdtm_fbdic_sync_frm_period_out_5_,`MCU2.fbdic__fbdic_sync_frm_period_4_,`MCU2.fbdic__fbdtm_fbdic_sync_frm_period_out_3_,`MCU2.fbdic__fbdic_sync_frm_period_2_,`MCU2.fbdic__fbdtm_fbdic_sync_frm_period_out_1_,`MCU2.fbdic__fbdic_sync_frm_period_0_} = sync_train_interval_gate[5:0];
2224 force {`MCU3.fbdic__fbdtm_fbdic_sync_frm_period_out_5_,`MCU3.fbdic__fbdic_sync_frm_period_4_,`MCU3.fbdic__fbdtm_fbdic_sync_frm_period_out_3_,`MCU3.fbdic__fbdic_sync_frm_period_2_,`MCU3.fbdic__fbdtm_fbdic_sync_frm_period_out_1_,`MCU3.fbdic__fbdic_sync_frm_period_0_} = sync_train_interval_gate[5:0];
2225
2226`else
2227 force `MCU0.drif.mode_reg[6:4] = cas_latency;
2228 force `MCU1.drif.mode_reg[6:4] = cas_latency;
2229 force `MCU2.drif.mode_reg[6:4] = cas_latency;
2230 force `MCU3.drif.mode_reg[6:4] = cas_latency;
2231
2232 force `MCU0.drif.ext_mode_reg1[5:3] = additive_latency;
2233 force `MCU1.drif.ext_mode_reg1[5:3] = additive_latency;
2234 force `MCU2.drif.ext_mode_reg1[5:3] = additive_latency;
2235 force `MCU3.drif.ext_mode_reg1[5:3] = additive_latency;
2236
2237 sync_train_interval = ({$random(`PARGS.seed)} % 11) + 32;
2238 force `MCU0.fbdic.fbdic_sync_frm_period[5:0] = sync_train_interval[5:0];
2239 force `MCU1.fbdic.fbdic_sync_frm_period[5:0] = sync_train_interval[5:0];
2240 force `MCU2.fbdic.fbdic_sync_frm_period[5:0] = sync_train_interval[5:0];
2241 force `MCU3.fbdic.fbdic_sync_frm_period[5:0] = sync_train_interval[5:0];
2242`endif // mcu_gate
2243
2244 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM *** : SYNC_TRAIN_INTERVAL = %d, AL = %d, CL = %d, CMD2DATANXT = %h", sync_train_interval, additive_latency, cas_latency, cmd2datanxt);
2245 end
2246 `endif // IDT_FBDIMM
2247
2248
2249
2250`ifdef DDR2_533 // Values computed based on dram_clk_period = 3.75ns (266 MHz)
2251 if (mcu_reg_slam_en) begin
2252`ifdef MCU_GATE
2253 force {`MCU0.drif__inv_ras_reg_1_,`MCU0.drif__ras_reg_2_,`MCU0.drif__ras_reg_1_,`MCU0.drif__inv_ras_reg_0_} = 4'h5;
2254 force {`MCU1.drif__inv_ras_reg_1_,`MCU1.drif__ras_reg_2_,`MCU1.drif__ras_reg_1_,`MCU1.drif__inv_ras_reg_0_} = 4'h5;
2255 force {`MCU2.drif__inv_ras_reg_1_,`MCU2.drif__ras_reg_2_,`MCU2.drif__ras_reg_1_,`MCU2.drif__inv_ras_reg_0_} = 4'h5;
2256 force {`MCU3.drif__inv_ras_reg_1_,`MCU3.drif__ras_reg_2_,`MCU3.drif__ras_reg_1_,`MCU3.drif__inv_ras_reg_0_} = 4'h5;
2257
2258 force {`MCU0.drif__rp_reg_3_,`MCU0.drif__rp_reg_2_,`MCU0.drif__inv_rp_reg_1_,`MCU0.drif__inv_rp_reg_0_} = 4'h0;
2259 force {`MCU1.drif__rp_reg_3_,`MCU1.drif__rp_reg_2_,`MCU1.drif__inv_rp_reg_1_,`MCU1.drif__inv_rp_reg_0_} = 4'h0;
2260 force {`MCU2.drif__rp_reg_3_,`MCU2.drif__rp_reg_2_,`MCU2.drif__inv_rp_reg_1_,`MCU2.drif__inv_rp_reg_0_} = 4'h0;
2261 force {`MCU3.drif__rp_reg_3_,`MCU3.drif__rp_reg_2_,`MCU3.drif__inv_rp_reg_1_,`MCU3.drif__inv_rp_reg_0_} = 4'h0;
2262
2263 force {`MCU0.drif__rtp_reg_2_,`MCU0.drif__inv_rtp_reg,`MCU0.drif__rtp_reg_0_} = 3'h0;
2264 force {`MCU1.drif__rtp_reg_2_,`MCU1.drif__inv_rtp_reg,`MCU1.drif__rtp_reg_0_} = 3'h0;
2265 force {`MCU2.drif__rtp_reg_2_,`MCU2.drif__inv_rtp_reg,`MCU2.drif__rtp_reg_0_} = 3'h0;
2266 force {`MCU3.drif__rtp_reg_2_,`MCU3.drif__inv_rtp_reg,`MCU3.drif__rtp_reg_0_} = 3'h0;
2267`else
2268if(sys_enabled) // For Settings same as the System
2269begin
2270 force `MCU0.drif.ras_reg = 4'hc;
2271 force `MCU1.drif.ras_reg = 4'hc;
2272 force `MCU2.drif.ras_reg = 4'hc;
2273 force `MCU3.drif.ras_reg = 4'hc;
2274
2275 force `MCU0.drif.rp_reg = 4'h5;
2276 force `MCU1.drif.rp_reg = 4'h5;
2277 force `MCU2.drif.rp_reg = 4'h5;
2278 force `MCU3.drif.rp_reg = 4'h5;
2279
2280 force `MCU0.drif.rtp_reg = 3'h2;
2281 force `MCU1.drif.rtp_reg = 3'h2;
2282 force `MCU2.drif.rtp_reg = 3'h2;
2283 force `MCU3.drif.rtp_reg = 3'h2;
2284
2285end
2286else
2287begin
2288 force `MCU0.drif.ras_reg = 4'hc;
2289 force `MCU1.drif.ras_reg = 4'hc;
2290 force `MCU2.drif.ras_reg = 4'hc;
2291 force `MCU3.drif.ras_reg = 4'hc;
2292
2293 force `MCU0.drif.rp_reg = 4'h3;
2294 force `MCU1.drif.rp_reg = 4'h3;
2295 force `MCU2.drif.rp_reg = 4'h3;
2296 force `MCU3.drif.rp_reg = 4'h3;
2297
2298 force `MCU0.drif.rtp_reg = 3'h2;
2299 force `MCU1.drif.rtp_reg = 3'h2;
2300 force `MCU2.drif.rtp_reg = 3'h2;
2301 force `MCU3.drif.rtp_reg = 3'h2;
2302end
2303`endif // mcu_gate
2304
2305 if (sng_channel) begin
2306`ifdef MCU_GATE
2307 force {`MCU0.drif__rc_reg_4_,`MCU0.drif__inv_rc_reg_3_,`MCU0.drif__inv_rc_reg_2_,`MCU0.drif__rc_reg_1_,`MCU0.drif__N3659 } = 5'h1d;
2308 force {`MCU1.drif__rc_reg_4_,`MCU1.drif__inv_rc_reg_3_,`MCU1.drif__inv_rc_reg_2_,`MCU1.drif__rc_reg_1_,`MCU1.drif__N3659 } = 5'h1d;
2309 force {`MCU2.drif__rc_reg_4_,`MCU2.drif__inv_rc_reg_3_,`MCU2.drif__inv_rc_reg_2_,`MCU2.drif__rc_reg_1_,`MCU2.drif__N3659 } = 5'h1d;
2310 force {`MCU3.drif__rc_reg_4_,`MCU3.drif__inv_rc_reg_3_,`MCU3.drif__inv_rc_reg_2_,`MCU3.drif__rc_reg_1_,`MCU3.drif__N3659 } = 5'h1d;
2311`else
2312 force `MCU0.drif.rc_reg = 5'h11; // System and TO 1.0/2.0 settings are same
2313 force `MCU1.drif.rc_reg = 5'h11;
2314 force `MCU2.drif.rc_reg = 5'h11;
2315 force `MCU3.drif.rc_reg = 5'h11;
2316`endif // mcu_gate
2317 end
2318 else begin // (DUAL_CHANNEL)
2319`ifdef MCU_GATE
2320 force {`MCU0.drif__rc_reg_4_,`MCU0.drif__inv_rc_reg_3_,`MCU0.drif__inv_rc_reg_2_,`MCU0.drif__rc_reg_1_,`MCU0.drif__N3659 } = 5'h3;
2321 force {`MCU1.drif__rc_reg_4_,`MCU1.drif__inv_rc_reg_3_,`MCU1.drif__inv_rc_reg_2_,`MCU1.drif__rc_reg_1_,`MCU1.drif__N3659 } = 5'h3;
2322 force {`MCU2.drif__rc_reg_4_,`MCU2.drif__inv_rc_reg_3_,`MCU2.drif__inv_rc_reg_2_,`MCU2.drif__rc_reg_1_,`MCU2.drif__N3659 } = 5'h3;
2323 force {`MCU3.drif__rc_reg_4_,`MCU3.drif__inv_rc_reg_3_,`MCU3.drif__inv_rc_reg_2_,`MCU3.drif__rc_reg_1_,`MCU3.drif__N3659 } = 5'h3;
2324`else
2325if(sys_enabled) // For Settings same as the System
2326begin
2327 force `MCU0.drif.rc_reg = 5'h11;
2328 force `MCU1.drif.rc_reg = 5'h11;
2329 force `MCU2.drif.rc_reg = 5'h11;
2330 force `MCU3.drif.rc_reg = 5'h11;
2331end
2332else
2333begin
2334 force `MCU0.drif.rc_reg = 5'hf;
2335 force `MCU1.drif.rc_reg = 5'hf;
2336 force `MCU2.drif.rc_reg = 5'hf;
2337 force `MCU3.drif.rc_reg = 5'hf;
2338end
2339`endif // mcu_gate
2340 end
2341
2342`ifdef MCU_GATE
2343 force {`MCU0.drif__rcd_reg_3_,`MCU0.drif__rcd_reg_2_,`MCU0.drif__inv_rcd_reg_1_,`MCU0.drif__inv_rcd_reg_0_} = 4'h0;
2344 force {`MCU1.drif__rcd_reg_3_,`MCU1.drif__rcd_reg_2_,`MCU1.drif__inv_rcd_reg_1_,`MCU1.drif__inv_rcd_reg_0_} = 4'h0;
2345 force {`MCU2.drif__rcd_reg_3_,`MCU2.drif__rcd_reg_2_,`MCU2.drif__inv_rcd_reg_1_,`MCU2.drif__inv_rcd_reg_0_} = 4'h0;
2346 force {`MCU3.drif__rcd_reg_3_,`MCU3.drif__rcd_reg_2_,`MCU3.drif__inv_rcd_reg_1_,`MCU3.drif__inv_rcd_reg_0_} = 4'h0;
2347
2348 force {`MCU0.drif__rfc_reg_reset_val_6_,`MCU0.drif__rfc_reg_reset_val_5_,`MCU0.drif__rfc_reg_reset_val_4_,`MCU0.drif__rfc_reg_reset_val_3_,`MCU0.drif__rfc_reg_reset_val_2_,`MCU0.drif__rfc_reg_reset_val_1_,`MCU0.drif__rfc_reg_reset_val_0_} = 7'h33;
2349 force {`MCU1.drif__rfc_reg_reset_val_6_,`MCU1.drif__rfc_reg_reset_val_5_,`MCU1.drif__rfc_reg_reset_val_4_,`MCU1.drif__rfc_reg_reset_val_3_,`MCU1.drif__rfc_reg_reset_val_2_,`MCU1.drif__rfc_reg_reset_val_1_,`MCU1.drif__rfc_reg_reset_val_0_} = 7'h33;
2350 force {`MCU2.drif__rfc_reg_reset_val_6_,`MCU2.drif__rfc_reg_reset_val_5_,`MCU2.drif__rfc_reg_reset_val_4_,`MCU2.drif__rfc_reg_reset_val_3_,`MCU2.drif__rfc_reg_reset_val_2_,`MCU2.drif__rfc_reg_reset_val_1_,`MCU2.drif__rfc_reg_reset_val_0_} = 7'h33;
2351 force {`MCU3.drif__rfc_reg_reset_val_6_,`MCU3.drif__rfc_reg_reset_val_5_,`MCU3.drif__rfc_reg_reset_val_4_,`MCU3.drif__rfc_reg_reset_val_3_,`MCU3.drif__rfc_reg_reset_val_2_,`MCU3.drif__rfc_reg_reset_val_1_,`MCU3.drif__rfc_reg_reset_val_0_} = 7'h33;
2352
2353 force {`MCU0.drif__wr_reg_3_,`MCU0.drif__wr_reg_2_,`MCU0.drif__inv_wr_reg_1_,`MCU0.drif__inv_wr_reg_0_} = 4'h7;
2354 force {`MCU1.drif__wr_reg_3_,`MCU1.drif__wr_reg_2_,`MCU1.drif__inv_wr_reg_1_,`MCU1.drif__inv_wr_reg_0_} = 4'h7;
2355 force {`MCU2.drif__wr_reg_3_,`MCU2.drif__wr_reg_2_,`MCU2.drif__inv_wr_reg_1_,`MCU2.drif__inv_wr_reg_0_} = 4'h7;
2356 force {`MCU3.drif__wr_reg_3_,`MCU3.drif__wr_reg_2_,`MCU3.drif__inv_wr_reg_1_,`MCU3.drif__inv_wr_reg_0_} = 4'h7;
2357
2358 force {`MCU0.drif__inv_iwtr_reg,`MCU0.drif__iwtr_reg_0_} = 2'h1;
2359 force {`MCU1.drif__inv_iwtr_reg,`MCU1.drif__iwtr_reg_0_} = 2'h1;
2360 force {`MCU2.drif__inv_iwtr_reg,`MCU2.drif__iwtr_reg_0_} = 2'h1;
2361 force {`MCU3.drif__inv_iwtr_reg,`MCU3.drif__iwtr_reg_0_} = 2'h1;
2362`else
2363if(sys_enabled) // For Settings same as the System
2364begin
2365 force `MCU0.drif.rcd_reg = 4'h4;
2366 force `MCU1.drif.rcd_reg = 4'h4;
2367 force `MCU2.drif.rcd_reg = 4'h4;
2368 force `MCU3.drif.rcd_reg = 4'h4;
2369
2370 force `MCU0.drif.rfc_reg = 7'h1c;
2371 force `MCU1.drif.rfc_reg = 7'h1c;
2372 force `MCU2.drif.rfc_reg = 7'h1c;
2373 force `MCU3.drif.rfc_reg = 7'h1c;
2374
2375 force `MCU0.drif.wr_reg = 4'h4;
2376 force `MCU1.drif.wr_reg = 4'h4;
2377 force `MCU2.drif.wr_reg = 4'h4;
2378 force `MCU3.drif.wr_reg = 4'h4;
2379
2380 force `MCU0.drif.iwtr_reg = 2'h2;
2381 force `MCU1.drif.iwtr_reg = 2'h2;
2382 force `MCU2.drif.iwtr_reg = 2'h2;
2383 force `MCU3.drif.iwtr_reg = 2'h2;
2384end
2385else
2386begin
2387 force `MCU0.drif.rcd_reg = 4'h3;
2388 force `MCU1.drif.rcd_reg = 4'h3;
2389 force `MCU2.drif.rcd_reg = 4'h3;
2390 force `MCU3.drif.rcd_reg = 4'h3;
2391
2392 force `MCU0.drif.rfc_reg = 7'h14;
2393 force `MCU1.drif.rfc_reg = 7'h14;
2394 force `MCU2.drif.rfc_reg = 7'h14;
2395 force `MCU3.drif.rfc_reg = 7'h14;
2396
2397 force `MCU0.drif.wr_reg = 4'h4;
2398 force `MCU1.drif.wr_reg = 4'h4;
2399 force `MCU2.drif.wr_reg = 4'h4;
2400 force `MCU3.drif.wr_reg = 4'h4;
2401
2402 force `MCU0.drif.iwtr_reg = 2'h3;
2403 force `MCU1.drif.iwtr_reg = 2'h3;
2404 force `MCU2.drif.iwtr_reg = 2'h3;
2405 force `MCU3.drif.iwtr_reg = 2'h3;
2406end
2407`endif // mcu_gate
2408
2409 if (sng_channel) begin
2410`ifdef MCU_GATE
2411 force {`MCU0.drif__rtw_dly_reg_3_,`MCU0.drif__rtw_dly_reg_2_,`MCU0.drif__rtw_dly_reg_1_,`MCU0.drif__rtw_reg_0_} = 4'h0;
2412 force {`MCU1.drif__rtw_dly_reg_3_,`MCU1.drif__rtw_dly_reg_2_,`MCU1.drif__rtw_dly_reg_1_,`MCU1.drif__rtw_reg_0_} = 4'h0;
2413 force {`MCU2.drif__rtw_dly_reg_3_,`MCU2.drif__rtw_dly_reg_2_,`MCU2.drif__rtw_dly_reg_1_,`MCU2.drif__rtw_reg_0_} = 4'h0;
2414 force {`MCU3.drif__rtw_dly_reg_3_,`MCU3.drif__rtw_dly_reg_2_,`MCU3.drif__rtw_dly_reg_1_,`MCU3.drif__rtw_reg_0_} = 4'h0;
2415`else
2416if(sys_enabled) // For Settings same as the System
2417begin
2418 force `MCU0.drif.rtw_dly_reg = 4'h1;
2419 force `MCU1.drif.rtw_dly_reg = 4'h1;
2420 force `MCU2.drif.rtw_dly_reg = 4'h1;
2421 force `MCU3.drif.rtw_dly_reg = 4'h1;
2422end
2423else
2424begin
2425
2426 force `MCU0.drif.rtw_reg = 4'h6;
2427 force `MCU1.drif.rtw_reg = 4'h6;
2428 force `MCU2.drif.rtw_reg = 4'h6;
2429 force `MCU3.drif.rtw_reg = 4'h6;
2430end
2431`endif // mcu_gate
2432 end
2433 else begin // (DUAL_CHANNEL)
2434`ifdef MCU_GATE
2435 force {`MCU0.drif__rtw_dly_reg_3_,`MCU0.drif__rtw_dly_reg_2_,`MCU0.drif__rtw_dly_reg_1_,`MCU0.drif__rtw_reg_0_} = 4'h0;
2436 force {`MCU1.drif__rtw_dly_reg_3_,`MCU1.drif__rtw_dly_reg_2_,`MCU1.drif__rtw_dly_reg_1_,`MCU1.drif__rtw_reg_0_} = 4'h0;
2437 force {`MCU2.drif__rtw_dly_reg_3_,`MCU2.drif__rtw_dly_reg_2_,`MCU2.drif__rtw_dly_reg_1_,`MCU2.drif__rtw_reg_0_} = 4'h0;
2438 force {`MCU3.drif__rtw_dly_reg_3_,`MCU3.drif__rtw_dly_reg_2_,`MCU3.drif__rtw_dly_reg_1_,`MCU3.drif__rtw_reg_0_} = 4'h0;
2439`else
2440if(sys_enabled) // For Settings same as the System
2441begin
2442 force `MCU0.drif.rtw_dly_reg = 4'h1;
2443 force `MCU1.drif.rtw_dly_reg = 4'h1;
2444 force `MCU2.drif.rtw_dly_reg = 4'h1;
2445 force `MCU3.drif.rtw_dly_reg = 4'h1;
2446end
2447else
2448begin
2449
2450 force `MCU0.drif.rtw_reg = 4'h4;
2451 force `MCU1.drif.rtw_reg = 4'h4;
2452 force `MCU2.drif.rtw_reg = 4'h4;
2453 force `MCU3.drif.rtw_reg = 4'h4;
2454end
2455`endif // mcu_gate
2456 end
2457
2458 if (sng_channel) begin
2459`ifdef MCU_GATE
2460 force {`MCU0.drif__rrd_reg_3_,`MCU0.drif__rrd_reg_2_,`MCU0.drif__inv_rrd_reg,`MCU0.drif__rrd_reg_0_} = 4'h7;
2461 force {`MCU1.drif__rrd_reg_3_,`MCU1.drif__rrd_reg_2_,`MCU1.drif__inv_rrd_reg,`MCU1.drif__rrd_reg_0_} = 4'h7;
2462 force {`MCU2.drif__rrd_reg_3_,`MCU2.drif__rrd_reg_2_,`MCU2.drif__inv_rrd_reg,`MCU2.drif__rrd_reg_0_} = 4'h7;
2463 force {`MCU3.drif__rrd_reg_3_,`MCU3.drif__rrd_reg_2_,`MCU3.drif__inv_rrd_reg,`MCU3.drif__rrd_reg_0_} = 4'h7;
2464`else
2465if(sys_enabled) // For Settings same as the System
2466begin
2467 force `MCU0.drif.rrd_reg = 4'h4;
2468 force `MCU1.drif.rrd_reg = 4'h4;
2469 force `MCU2.drif.rrd_reg = 4'h4;
2470 force `MCU3.drif.rrd_reg = 4'h4;
2471
2472end
2473else
2474begin
2475 force `MCU0.drif.rrd_reg = 4'h5;
2476 force `MCU1.drif.rrd_reg = 4'h5;
2477 force `MCU2.drif.rrd_reg = 4'h5;
2478 force `MCU3.drif.rrd_reg = 4'h5;
2479end
2480`endif // mcu_gate
2481 end
2482 else begin // (DUAL_CHANNEL)
2483`ifdef MCU_GATE
2484 force {`MCU0.drif__rrd_reg_3_,`MCU0.drif__rrd_reg_2_,`MCU0.drif__inv_rrd_reg,`MCU0.drif__rrd_reg_0_} = 4'h1;
2485 force {`MCU1.drif__rrd_reg_3_,`MCU1.drif__rrd_reg_2_,`MCU1.drif__inv_rrd_reg,`MCU1.drif__rrd_reg_0_} = 4'h1;
2486 force {`MCU2.drif__rrd_reg_3_,`MCU2.drif__rrd_reg_2_,`MCU2.drif__inv_rrd_reg,`MCU2.drif__rrd_reg_0_} = 4'h1;
2487 force {`MCU3.drif__rrd_reg_3_,`MCU3.drif__rrd_reg_2_,`MCU3.drif__inv_rrd_reg,`MCU3.drif__rrd_reg_0_} = 4'h1;
2488`else
2489if(sys_enabled) // For Settings same as the System
2490begin
2491 force `MCU0.drif.rrd_reg = 4'h2;
2492 force `MCU1.drif.rrd_reg = 4'h2;
2493 force `MCU2.drif.rrd_reg = 4'h2;
2494 force `MCU3.drif.rrd_reg = 4'h2;
2495
2496end
2497else
2498begin
2499
2500 force `MCU0.drif.rrd_reg = 4'h3;
2501 force `MCU1.drif.rrd_reg = 4'h3;
2502 force `MCU2.drif.rrd_reg = 4'h3;
2503 force `MCU3.drif.rrd_reg = 4'h3;
2504end
2505`endif // mcu_gate
2506 end
2507
2508`ifdef MCU_GATE
2509 force {`MCU0.drif__faw_reg_4_,`MCU0.drif__inv_faw_reg_1_,`MCU0.drif__faw_reg_2_,`MCU0.drif__inv_faw_reg_0_,`MCU0.drif__faw_reg_0_} = 5'h0;
2510 force {`MCU1.drif__faw_reg_4_,`MCU1.drif__inv_faw_reg_1_,`MCU1.drif__faw_reg_2_,`MCU1.drif__inv_faw_reg_0_,`MCU1.drif__faw_reg_0_} = 5'h0;
2511 force {`MCU2.drif__faw_reg_4_,`MCU2.drif__inv_faw_reg_1_,`MCU2.drif__faw_reg_2_,`MCU2.drif__inv_faw_reg_0_,`MCU2.drif__faw_reg_0_} = 5'h0;
2512 force {`MCU3.drif__faw_reg_4_,`MCU3.drif__inv_faw_reg_1_,`MCU3.drif__faw_reg_2_,`MCU3.drif__inv_faw_reg_0_,`MCU3.drif__faw_reg_0_} = 5'h0;
2513`else
2514 force `MCU0.drif.faw_reg = 5'ha;
2515 force `MCU1.drif.faw_reg = 5'ha;
2516 force `MCU2.drif.faw_reg = 5'ha;
2517 force `MCU3.drif.faw_reg = 5'ha;
2518`endif // mcu_gate
2519 end
2520
2521`else // DDR2_667 (Values computed based on dram_clk_period = 3ns (333.333 MHz))
2522 if (mcu_reg_slam_en) begin
2523
2524`ifdef NEC_FBDIMM
2525`ifdef MCU_GATE
2526 force {`MCU0.drif__drif_ref_freq_12_,`MCU0.drif__drif_ref_freq_out_11_,`MCU0.drif__drif_ref_freq_10_,`MCU0.drif__drif_ref_freq_9_,`MCU0.drif__drif_ref_freq_8_,`MCU0.drif__drif_ref_freq_7_,`MCU0.drif__drif_ref_freq_6_,`MCU0.drif__drif_ref_freq_out_5_,`MCU0.drif__drif_ref_freq_4_,`MCU0.drif__drif_ref_freq_3_,`MCU0.drif__drif_ref_freq_2_,`MCU0.drif__drif_ref_freq_1_,`MCU0.drif__drif_ref_freq_0_} = 13'h208;
2527 force {`MCU1.drif__drif_ref_freq_12_,`MCU1.drif__drif_ref_freq_out_11_,`MCU1.drif__drif_ref_freq_10_,`MCU1.drif__drif_ref_freq_9_,`MCU1.drif__drif_ref_freq_8_,`MCU1.drif__drif_ref_freq_7_,`MCU1.drif__drif_ref_freq_6_,`MCU1.drif__drif_ref_freq_out_5_,`MCU1.drif__drif_ref_freq_4_,`MCU1.drif__drif_ref_freq_3_,`MCU1.drif__drif_ref_freq_2_,`MCU1.drif__drif_ref_freq_1_,`MCU1.drif__drif_ref_freq_0_} = 13'h208;
2528 force {`MCU2.drif__drif_ref_freq_12_,`MCU2.drif__drif_ref_freq_out_11_,`MCU2.drif__drif_ref_freq_10_,`MCU2.drif__drif_ref_freq_9_,`MCU2.drif__drif_ref_freq_8_,`MCU2.drif__drif_ref_freq_7_,`MCU2.drif__drif_ref_freq_6_,`MCU2.drif__drif_ref_freq_out_5_,`MCU2.drif__drif_ref_freq_4_,`MCU2.drif__drif_ref_freq_3_,`MCU2.drif__drif_ref_freq_2_,`MCU2.drif__drif_ref_freq_1_,`MCU2.drif__drif_ref_freq_0_} = 13'h208;
2529 force {`MCU3.drif__drif_ref_freq_12_,`MCU3.drif__drif_ref_freq_out_11_,`MCU3.drif__drif_ref_freq_10_,`MCU3.drif__drif_ref_freq_9_,`MCU3.drif__drif_ref_freq_8_,`MCU3.drif__drif_ref_freq_7_,`MCU3.drif__drif_ref_freq_6_,`MCU3.drif__drif_ref_freq_out_5_,`MCU3.drif__drif_ref_freq_4_,`MCU3.drif__drif_ref_freq_3_,`MCU3.drif__drif_ref_freq_2_,`MCU3.drif__drif_ref_freq_1_,`MCU3.drif__drif_ref_freq_0_} = 13'h208;
2530`else
2531 force `MCU0.drif.drif_ref_freq = 13'ha28;
2532 force `MCU1.drif.drif_ref_freq = 13'ha28;
2533 force `MCU2.drif.drif_ref_freq = 13'ha28;
2534 force `MCU3.drif.drif_ref_freq = 13'ha28;
2535`endif // mcu_gate
2536`endif
2537
2538`ifdef MCU_GATE
2539 force {`MCU0.drif__inv_ras_reg_1_,`MCU0.drif__ras_reg_2_,`MCU0.drif__ras_reg_1_,`MCU0.drif__inv_ras_reg_0_} = 4'h6;
2540 force {`MCU1.drif__inv_ras_reg_1_,`MCU1.drif__ras_reg_2_,`MCU1.drif__ras_reg_1_,`MCU1.drif__inv_ras_reg_0_} = 4'h6;
2541 force {`MCU2.drif__inv_ras_reg_1_,`MCU2.drif__ras_reg_2_,`MCU2.drif__ras_reg_1_,`MCU2.drif__inv_ras_reg_0_} = 4'h6;
2542 force {`MCU3.drif__inv_ras_reg_1_,`MCU3.drif__ras_reg_2_,`MCU3.drif__ras_reg_1_,`MCU3.drif__inv_ras_reg_0_} = 4'h6;
2543
2544 force {`MCU0.drif__rp_reg_3_,`MCU0.drif__rp_reg_2_,`MCU0.drif__inv_rp_reg_1_,`MCU0.drif__inv_rp_reg_0_} = 4'h7;
2545 force {`MCU1.drif__rp_reg_3_,`MCU1.drif__rp_reg_2_,`MCU1.drif__inv_rp_reg_1_,`MCU1.drif__inv_rp_reg_0_} = 4'h7;
2546 force {`MCU2.drif__rp_reg_3_,`MCU2.drif__rp_reg_2_,`MCU2.drif__inv_rp_reg_1_,`MCU2.drif__inv_rp_reg_0_} = 4'h7;
2547 force {`MCU3.drif__rp_reg_3_,`MCU3.drif__rp_reg_2_,`MCU3.drif__inv_rp_reg_1_,`MCU3.drif__inv_rp_reg_0_} = 4'h7;
2548
2549 force {`MCU0.drif__rtp_reg_2_,`MCU0.drif__inv_rtp_reg,`MCU0.drif__rtp_reg_0_} = 3'h1;
2550 force {`MCU1.drif__rtp_reg_2_,`MCU1.drif__inv_rtp_reg,`MCU1.drif__rtp_reg_0_} = 3'h1;
2551 force {`MCU2.drif__rtp_reg_2_,`MCU2.drif__inv_rtp_reg,`MCU2.drif__rtp_reg_0_} = 3'h1;
2552 force {`MCU3.drif__rtp_reg_2_,`MCU3.drif__inv_rtp_reg,`MCU3.drif__rtp_reg_0_} = 3'h1;
2553`else
2554if(sys_enabled) // For Settings same as the System
2555begin
2556 force `MCU0.drif.ras_reg = 4'hf; // Same as sim before TO 2.0
2557 force `MCU1.drif.ras_reg = 4'hf;
2558 force `MCU2.drif.ras_reg = 4'hf;
2559 force `MCU3.drif.ras_reg = 4'hf;
2560
2561 force `MCU0.drif.rp_reg = 4'h5;
2562 force `MCU1.drif.rp_reg = 4'h5;
2563 force `MCU2.drif.rp_reg = 4'h5;
2564 force `MCU3.drif.rp_reg = 4'h5;
2565
2566 force `MCU0.drif.rtp_reg = 3'h3;// Same as sim before TO 2.0
2567 force `MCU1.drif.rtp_reg = 3'h3;
2568 force `MCU2.drif.rtp_reg = 3'h3;
2569 force `MCU3.drif.rtp_reg = 3'h3;
2570
2571end
2572else
2573begin
2574
2575 force `MCU0.drif.ras_reg = 4'hf;
2576 force `MCU1.drif.ras_reg = 4'hf;
2577 force `MCU2.drif.ras_reg = 4'hf;
2578 force `MCU3.drif.ras_reg = 4'hf;
2579
2580 force `MCU0.drif.rp_reg = 4'h4;
2581 force `MCU1.drif.rp_reg = 4'h4;
2582 force `MCU2.drif.rp_reg = 4'h4;
2583 force `MCU3.drif.rp_reg = 4'h4;
2584
2585 force `MCU0.drif.rtp_reg = 3'h3;
2586 force `MCU1.drif.rtp_reg = 3'h3;
2587 force `MCU2.drif.rtp_reg = 3'h3;
2588 force `MCU3.drif.rtp_reg = 3'h3;
2589end
2590`endif // mcu_gate
2591
2592 if (sng_channel) begin
2593`ifdef MCU_GATE
2594 force {`MCU0.drif__rc_reg_4_,`MCU0.drif__inv_rc_reg_3_,`MCU0.drif__inv_rc_reg_2_,`MCU0.drif__rc_reg_1_,`MCU0.drif__N3659 } = 5'h19;
2595 force {`MCU1.drif__rc_reg_4_,`MCU1.drif__inv_rc_reg_3_,`MCU1.drif__inv_rc_reg_2_,`MCU1.drif__rc_reg_1_,`MCU1.drif__N3659 } = 5'h19;
2596 force {`MCU2.drif__rc_reg_4_,`MCU2.drif__inv_rc_reg_3_,`MCU2.drif__inv_rc_reg_2_,`MCU2.drif__rc_reg_1_,`MCU2.drif__N3659 } = 5'h19;
2597 force {`MCU3.drif__rc_reg_4_,`MCU3.drif__inv_rc_reg_3_,`MCU3.drif__inv_rc_reg_2_,`MCU3.drif__rc_reg_1_,`MCU3.drif__N3659 } = 5'h19;
2598`else
2599if(sys_enabled)
2600begin
2601 force `MCU0.drif.rc_reg = 5'h14;
2602 force `MCU1.drif.rc_reg = 5'h14;
2603 force `MCU2.drif.rc_reg = 5'h14;
2604 force `MCU3.drif.rc_reg = 5'h14;
2605end
2606else
2607begin
2608 force `MCU0.drif.rc_reg = 5'h15;
2609 force `MCU1.drif.rc_reg = 5'h15;
2610 force `MCU2.drif.rc_reg = 5'h15;
2611 force `MCU3.drif.rc_reg = 5'h15;
2612end
2613`endif // mcu_gate
2614 end
2615 else begin // (DUAL_CHANNEL)
2616`ifdef MCU_GATE
2617 force {`MCU0.drif__rc_reg_4_,`MCU0.drif__inv_rc_reg_3_,`MCU0.drif__inv_rc_reg_2_,`MCU0.drif__rc_reg_1_,`MCU0.drif__N3659 } = 5'h1f;
2618 force {`MCU1.drif__rc_reg_4_,`MCU1.drif__inv_rc_reg_3_,`MCU1.drif__inv_rc_reg_2_,`MCU1.drif__rc_reg_1_,`MCU1.drif__N3659 } = 5'h1f;
2619 force {`MCU2.drif__rc_reg_4_,`MCU2.drif__inv_rc_reg_3_,`MCU2.drif__inv_rc_reg_2_,`MCU2.drif__rc_reg_1_,`MCU2.drif__N3659 } = 5'h1f;
2620 force {`MCU3.drif__rc_reg_4_,`MCU3.drif__inv_rc_reg_3_,`MCU3.drif__inv_rc_reg_2_,`MCU3.drif__rc_reg_1_,`MCU3.drif__N3659 } = 5'h1f;
2621`else
2622if(sys_enabled)
2623begin
2624 force `MCU0.drif.rc_reg = 5'h14;
2625 force `MCU1.drif.rc_reg = 5'h14;
2626 force `MCU2.drif.rc_reg = 5'h14;
2627 force `MCU3.drif.rc_reg = 5'h14;
2628end
2629else
2630begin
2631
2632 force `MCU0.drif.rc_reg = 5'h13;
2633 force `MCU1.drif.rc_reg = 5'h13;
2634 force `MCU2.drif.rc_reg = 5'h13;
2635 force `MCU3.drif.rc_reg = 5'h13;
2636end
2637`endif // mcu_gate
2638 end
2639
2640`ifdef MCU_GATE
2641 force {`MCU0.drif__rcd_reg_3_,`MCU0.drif__rcd_reg_2_,`MCU0.drif__inv_rcd_reg_1_,`MCU0.drif__inv_rcd_reg_0_} = 4'h7;
2642 force {`MCU1.drif__rcd_reg_3_,`MCU1.drif__rcd_reg_2_,`MCU1.drif__inv_rcd_reg_1_,`MCU1.drif__inv_rcd_reg_0_} = 4'h7;
2643 force {`MCU2.drif__rcd_reg_3_,`MCU2.drif__rcd_reg_2_,`MCU2.drif__inv_rcd_reg_1_,`MCU2.drif__inv_rcd_reg_0_} = 4'h7;
2644 force {`MCU3.drif__rcd_reg_3_,`MCU3.drif__rcd_reg_2_,`MCU3.drif__inv_rcd_reg_1_,`MCU3.drif__inv_rcd_reg_0_} = 4'h7;
2645
2646 force {`MCU0.drif__rfc_reg_reset_val_6_,`MCU0.drif__rfc_reg_reset_val_5_,`MCU0.drif__rfc_reg_reset_val_4_,`MCU0.drif__rfc_reg_reset_val_3_,`MCU0.drif__rfc_reg_reset_val_2_,`MCU0.drif__rfc_reg_reset_val_1_,`MCU0.drif__rfc_reg_reset_val_0_} = 7'h3e;
2647 force {`MCU1.drif__rfc_reg_reset_val_6_,`MCU1.drif__rfc_reg_reset_val_5_,`MCU1.drif__rfc_reg_reset_val_4_,`MCU1.drif__rfc_reg_reset_val_3_,`MCU1.drif__rfc_reg_reset_val_2_,`MCU1.drif__rfc_reg_reset_val_1_,`MCU1.drif__rfc_reg_reset_val_0_} = 7'h3e;
2648 force {`MCU2.drif__rfc_reg_reset_val_6_,`MCU2.drif__rfc_reg_reset_val_5_,`MCU2.drif__rfc_reg_reset_val_4_,`MCU2.drif__rfc_reg_reset_val_3_,`MCU2.drif__rfc_reg_reset_val_2_,`MCU2.drif__rfc_reg_reset_val_1_,`MCU2.drif__rfc_reg_reset_val_0_} = 7'h3e;
2649 force {`MCU3.drif__rfc_reg_reset_val_6_,`MCU3.drif__rfc_reg_reset_val_5_,`MCU3.drif__rfc_reg_reset_val_4_,`MCU3.drif__rfc_reg_reset_val_3_,`MCU3.drif__rfc_reg_reset_val_2_,`MCU3.drif__rfc_reg_reset_val_1_,`MCU3.drif__rfc_reg_reset_val_0_} = 7'h3e;
2650
2651 force {`MCU0.drif__wr_reg_3_,`MCU0.drif__wr_reg_2_,`MCU0.drif__inv_wr_reg_1_,`MCU0.drif__inv_wr_reg_0_} = 4'h6;
2652 force {`MCU1.drif__wr_reg_3_,`MCU1.drif__wr_reg_2_,`MCU1.drif__inv_wr_reg_1_,`MCU1.drif__inv_wr_reg_0_} = 4'h6;
2653 force {`MCU2.drif__wr_reg_3_,`MCU2.drif__wr_reg_2_,`MCU2.drif__inv_wr_reg_1_,`MCU2.drif__inv_wr_reg_0_} = 4'h6;
2654 force {`MCU3.drif__wr_reg_3_,`MCU3.drif__wr_reg_2_,`MCU3.drif__inv_wr_reg_1_,`MCU3.drif__inv_wr_reg_0_} = 4'h6;
2655
2656 force {`MCU0.drif__inv_iwtr_reg,`MCU0.drif__iwtr_reg_0_} = 2'h1;
2657 force {`MCU1.drif__inv_iwtr_reg,`MCU1.drif__iwtr_reg_0_} = 2'h1;
2658 force {`MCU2.drif__inv_iwtr_reg,`MCU2.drif__iwtr_reg_0_} = 2'h1;
2659 force {`MCU3.drif__inv_iwtr_reg,`MCU3.drif__iwtr_reg_0_} = 2'h1;
2660`else
2661if(sys_enabled) // For Settings same as the System
2662begin
2663 force `MCU0.drif.rcd_reg = 4'h5;
2664 force `MCU1.drif.rcd_reg = 4'h5;
2665 force `MCU2.drif.rcd_reg = 4'h5;
2666 force `MCU3.drif.rcd_reg = 4'h5;
2667
2668 force `MCU0.drif.rfc_reg = 7'h23;
2669 force `MCU1.drif.rfc_reg = 7'h23;
2670 force `MCU2.drif.rfc_reg = 7'h23;
2671 force `MCU3.drif.rfc_reg = 7'h23;
2672
2673 force `MCU0.drif.wr_reg = 4'h5;
2674 force `MCU1.drif.wr_reg = 4'h5;
2675 force `MCU2.drif.wr_reg = 4'h5;
2676 force `MCU3.drif.wr_reg = 4'h5;
2677
2678 force `MCU0.drif.iwtr_reg = 2'h3; // Same as simulation before TO 2.0
2679 force `MCU1.drif.iwtr_reg = 2'h3;
2680 force `MCU2.drif.iwtr_reg = 2'h3;
2681 force `MCU3.drif.iwtr_reg = 2'h3;
2682end
2683else
2684begin
2685
2686 force `MCU0.drif.rcd_reg = 4'h4;
2687 force `MCU1.drif.rcd_reg = 4'h4;
2688 force `MCU2.drif.rcd_reg = 4'h4;
2689 force `MCU3.drif.rcd_reg = 4'h4;
2690
2691 force `MCU0.drif.rfc_reg = 7'h19;
2692 force `MCU1.drif.rfc_reg = 7'h19;
2693 force `MCU2.drif.rfc_reg = 7'h19;
2694 force `MCU3.drif.rfc_reg = 7'h19;
2695
2696 force `MCU0.drif.wr_reg = 4'h5;
2697 force `MCU1.drif.wr_reg = 4'h5;
2698 force `MCU2.drif.wr_reg = 4'h5;
2699 force `MCU3.drif.wr_reg = 4'h5;
2700
2701 force `MCU0.drif.iwtr_reg = 2'h3;
2702 force `MCU1.drif.iwtr_reg = 2'h3;
2703 force `MCU2.drif.iwtr_reg = 2'h3;
2704 force `MCU3.drif.iwtr_reg = 2'h3;
2705end
2706`endif // mcu_gate
2707
2708 if (sng_channel) begin
2709`ifdef MCU_GATE
2710 force {`MCU0.drif__rtw_dly_reg_3_,`MCU0.drif__rtw_dly_reg_2_,`MCU0.drif__rtw_dly_reg_1_,`MCU0.drif__rtw_reg_0_} = 4'h0;
2711 force {`MCU1.drif__rtw_dly_reg_3_,`MCU1.drif__rtw_dly_reg_2_,`MCU1.drif__rtw_dly_reg_1_,`MCU1.drif__rtw_reg_0_} = 4'h0;
2712 force {`MCU2.drif__rtw_dly_reg_3_,`MCU2.drif__rtw_dly_reg_2_,`MCU2.drif__rtw_dly_reg_1_,`MCU2.drif__rtw_reg_0_} = 4'h0;
2713 force {`MCU3.drif__rtw_dly_reg_3_,`MCU3.drif__rtw_dly_reg_2_,`MCU3.drif__rtw_dly_reg_1_,`MCU3.drif__rtw_reg_0_} = 4'h0;
2714`else
2715if(sys_enabled) // For Settings same as the System
2716begin
2717 force `MCU0.drif.rtw_dly_reg = 4'h1;
2718 force `MCU1.drif.rtw_dly_reg = 4'h1;
2719 force `MCU2.drif.rtw_dly_reg = 4'h1;
2720 force `MCU3.drif.rtw_dly_reg = 4'h1;
2721end
2722else
2723begin
2724
2725 force `MCU0.drif.rtw_reg = 4'h6;
2726 force `MCU1.drif.rtw_reg = 4'h6;
2727 force `MCU2.drif.rtw_reg = 4'h6;
2728 force `MCU3.drif.rtw_reg = 4'h6;
2729end
2730`endif // mcu_gate
2731 end
2732 else begin // (DUAL_CHANNEL)
2733`ifdef MCU_GATE
2734 force {`MCU0.drif__rtw_dly_reg_3_,`MCU0.drif__rtw_dly_reg_2_,`MCU0.drif__rtw_dly_reg_1_,`MCU0.drif__rtw_reg_0_} = 4'h0;
2735 force {`MCU1.drif__rtw_dly_reg_3_,`MCU1.drif__rtw_dly_reg_2_,`MCU1.drif__rtw_dly_reg_1_,`MCU1.drif__rtw_reg_0_} = 4'h0;
2736 force {`MCU2.drif__rtw_dly_reg_3_,`MCU2.drif__rtw_dly_reg_2_,`MCU2.drif__rtw_dly_reg_1_,`MCU2.drif__rtw_reg_0_} = 4'h0;
2737 force {`MCU3.drif__rtw_dly_reg_3_,`MCU3.drif__rtw_dly_reg_2_,`MCU3.drif__rtw_dly_reg_1_,`MCU3.drif__rtw_reg_0_} = 4'h0;
2738`else
2739if(sys_enabled) // For Settings same as the System
2740begin
2741 force `MCU0.drif.rtw_dly_reg = 4'h1;
2742 force `MCU1.drif.rtw_dly_reg = 4'h1;
2743 force `MCU2.drif.rtw_dly_reg = 4'h1;
2744 force `MCU3.drif.rtw_dly_reg = 4'h1;
2745end
2746else
2747begin
2748 force `MCU0.drif.rtw_reg = 4'h4;
2749 force `MCU1.drif.rtw_reg = 4'h4;
2750 force `MCU2.drif.rtw_reg = 4'h4;
2751 force `MCU3.drif.rtw_reg = 4'h4;
2752end
2753
2754`endif // mcu_gate
2755/** This forces the output of the rtw reg equation, so removing it
2756`else
2757if(sys_enabled) // For Settings same as the System
2758begin
2759 force `MCU0.drif.rtw_reg = 4'h1;
2760 force `MCU1.drif.rtw_reg = 4'h1;
2761 force `MCU2.drif.rtw_reg = 4'h1;
2762 force `MCU3.drif.rtw_reg = 4'h1;
2763end
2764else
2765begin
2766 force `MCU0.drif.rtw_reg = 4'h4;
2767 force `MCU1.drif.rtw_reg = 4'h4;
2768 force `MCU2.drif.rtw_reg = 4'h4;
2769 force `MCU3.drif.rtw_reg = 4'h4;
2770end
2771`endif // mcu_gate
2772***/
2773 end
2774
2775 if (sng_channel) begin
2776`ifdef MCU_GATE
2777 force {`MCU0.drif__rrd_reg_3_,`MCU0.drif__rrd_reg_2_,`MCU0.drif__inv_rrd_reg,`MCU0.drif__rrd_reg_0_} = 4'h7;
2778 force {`MCU1.drif__rrd_reg_3_,`MCU1.drif__rrd_reg_2_,`MCU1.drif__inv_rrd_reg,`MCU1.drif__rrd_reg_0_} = 4'h7;
2779 force {`MCU2.drif__rrd_reg_3_,`MCU2.drif__rrd_reg_2_,`MCU2.drif__inv_rrd_reg,`MCU2.drif__rrd_reg_0_} = 4'h7;
2780 force {`MCU3.drif__rrd_reg_3_,`MCU3.drif__rrd_reg_2_,`MCU3.drif__inv_rrd_reg,`MCU3.drif__rrd_reg_0_} = 4'h7;
2781`else
2782if(sys_enabled) // For Settings same as the System
2783begin
2784 force `MCU0.drif.rrd_reg = 4'h5; // Same as sim pre TO 2.0
2785 force `MCU1.drif.rrd_reg = 4'h5;
2786 force `MCU2.drif.rrd_reg = 4'h5;
2787 force `MCU3.drif.rrd_reg = 4'h5;
2788
2789end
2790else
2791begin
2792
2793 force `MCU0.drif.rrd_reg = 4'h5;
2794 force `MCU1.drif.rrd_reg = 4'h5;
2795 force `MCU2.drif.rrd_reg = 4'h5;
2796 force `MCU3.drif.rrd_reg = 4'h5;
2797end
2798`endif // mcu_gate
2799 end
2800 else begin // (DUAL_CHANNEL)
2801`ifdef MCU_GATE
2802 force {`MCU0.drif__rrd_reg_3_,`MCU0.drif__rrd_reg_2_,`MCU0.drif__inv_rrd_reg,`MCU0.drif__rrd_reg_0_} = 4'h1;
2803 force {`MCU1.drif__rrd_reg_3_,`MCU1.drif__rrd_reg_2_,`MCU1.drif__inv_rrd_reg,`MCU1.drif__rrd_reg_0_} = 4'h1;
2804 force {`MCU2.drif__rrd_reg_3_,`MCU2.drif__rrd_reg_2_,`MCU2.drif__inv_rrd_reg,`MCU2.drif__rrd_reg_0_} = 4'h1;
2805 force {`MCU3.drif__rrd_reg_3_,`MCU3.drif__rrd_reg_2_,`MCU3.drif__inv_rrd_reg,`MCU3.drif__rrd_reg_0_} = 4'h1;
2806`else
2807if(sys_enabled) // For Settings same as the System
2808begin
2809 force `MCU0.drif.rrd_reg = 4'h3; // Same as sim pre TO 2.0
2810 force `MCU1.drif.rrd_reg = 4'h3;
2811 force `MCU2.drif.rrd_reg = 4'h3;
2812 force `MCU3.drif.rrd_reg = 4'h3;
2813
2814end
2815else
2816begin
2817 force `MCU0.drif.rrd_reg = 4'h3;
2818 force `MCU1.drif.rrd_reg = 4'h3;
2819 force `MCU2.drif.rrd_reg = 4'h3;
2820 force `MCU3.drif.rrd_reg = 4'h3;
2821end
2822`endif // mcu_gate
2823 end
2824
2825`ifdef MCU_GATE
2826 force {`MCU0.drif__faw_reg_4_,`MCU0.drif__inv_faw_reg_1_,`MCU0.drif__faw_reg_2_,`MCU0.drif__inv_faw_reg_0_,`MCU0.drif__faw_reg_0_} = 5'h7;
2827 force {`MCU1.drif__faw_reg_4_,`MCU1.drif__inv_faw_reg_1_,`MCU1.drif__faw_reg_2_,`MCU1.drif__inv_faw_reg_0_,`MCU1.drif__faw_reg_0_} = 5'h7;
2828 force {`MCU2.drif__faw_reg_4_,`MCU2.drif__inv_faw_reg_1_,`MCU2.drif__faw_reg_2_,`MCU2.drif__inv_faw_reg_0_,`MCU2.drif__faw_reg_0_} = 5'h7;
2829 force {`MCU3.drif__faw_reg_4_,`MCU3.drif__inv_faw_reg_1_,`MCU3.drif__faw_reg_2_,`MCU3.drif__inv_faw_reg_0_,`MCU3.drif__faw_reg_0_} = 5'h7;
2830`else
2831 force `MCU0.drif.faw_reg = 5'hd;
2832 force `MCU1.drif.faw_reg = 5'hd;
2833 force `MCU2.drif.faw_reg = 5'hd;
2834 force `MCU3.drif.faw_reg = 5'hd;
2835`endif // mcu_gate
2836 end
2837`endif
2838end // else: !if($test$plusargs("NO_MCU_CSR_SLAM"))
2839
2840
2841`ifdef IDT_FBDIMM
2842 if ($test$plusargs("NO_IDT_CSR_SLAM")) begin
2843 `PR_INFO ("mcu_mem_config", `INFO, "IDT CSRs not slammed");
2844 end
2845 else begin
2846
2847 // Set CL in idt_fbdimm
2848 `ifndef AXIS
2849 force `FBD_CH_PATH0.fbdimm0.CL = cas_latency[2:0];
2850 force `FBD_CH_PATH2.fbdimm0.CL = cas_latency[2:0];
2851 force `FBD_CH_PATH4.fbdimm0.CL = cas_latency[2:0];
2852 force `FBD_CH_PATH6.fbdimm0.CL = cas_latency[2:0];
2853
2854 `ifndef SNG_CHANNEL
2855 force `FBD_CH_PATH1.fbdimm0.CL = cas_latency[2:0];
2856 force `FBD_CH_PATH3.fbdimm0.CL = cas_latency[2:0];
2857 force `FBD_CH_PATH5.fbdimm0.CL = cas_latency[2:0];
2858 force `FBD_CH_PATH7.fbdimm0.CL = cas_latency[2:0];
2859 `endif
2860 `ifndef FBDIMM_NUM_1
2861 force `FBD_CH_PATH0.fbdimm1.CL = cas_latency[2:0];
2862 force `FBD_CH_PATH2.fbdimm1.CL = cas_latency[2:0];
2863 force `FBD_CH_PATH4.fbdimm1.CL = cas_latency[2:0];
2864 force `FBD_CH_PATH6.fbdimm1.CL = cas_latency[2:0];
2865
2866 `ifndef SNG_CHANNEL
2867 force `FBD_CH_PATH1.fbdimm1.CL = cas_latency[2:0];
2868 force `FBD_CH_PATH3.fbdimm1.CL = cas_latency[2:0];
2869 force `FBD_CH_PATH5.fbdimm1.CL = cas_latency[2:0];
2870 force `FBD_CH_PATH7.fbdimm1.CL = cas_latency[2:0];
2871 `endif
2872
2873 `ifndef FBDIMM_NUM_2
2874 force `FBD_CH_PATH0.fbdimm2.CL = cas_latency[2:0];
2875 force `FBD_CH_PATH2.fbdimm2.CL = cas_latency[2:0];
2876 force `FBD_CH_PATH4.fbdimm2.CL = cas_latency[2:0];
2877 force `FBD_CH_PATH6.fbdimm2.CL = cas_latency[2:0];
2878 force `FBD_CH_PATH0.fbdimm3.CL = cas_latency[2:0];
2879 force `FBD_CH_PATH2.fbdimm3.CL = cas_latency[2:0];
2880 force `FBD_CH_PATH4.fbdimm3.CL = cas_latency[2:0];
2881 force `FBD_CH_PATH6.fbdimm3.CL = cas_latency[2:0];
2882
2883 `ifndef SNG_CHANNEL
2884 force `FBD_CH_PATH1.fbdimm2.CL = cas_latency[2:0];
2885 force `FBD_CH_PATH3.fbdimm2.CL = cas_latency[2:0];
2886 force `FBD_CH_PATH5.fbdimm2.CL = cas_latency[2:0];
2887 force `FBD_CH_PATH7.fbdimm2.CL = cas_latency[2:0];
2888 force `FBD_CH_PATH1.fbdimm3.CL = cas_latency[2:0];
2889 force `FBD_CH_PATH3.fbdimm3.CL = cas_latency[2:0];
2890 force `FBD_CH_PATH5.fbdimm3.CL = cas_latency[2:0];
2891 force `FBD_CH_PATH7.fbdimm3.CL = cas_latency[2:0];
2892 `endif
2893
2894 `ifndef FBDIMM_NUM_4
2895 force `FBD_CH_PATH0.fbdimm4.CL = cas_latency[2:0];
2896 force `FBD_CH_PATH2.fbdimm4.CL = cas_latency[2:0];
2897 force `FBD_CH_PATH4.fbdimm4.CL = cas_latency[2:0];
2898 force `FBD_CH_PATH6.fbdimm4.CL = cas_latency[2:0];
2899 force `FBD_CH_PATH0.fbdimm5.CL = cas_latency[2:0];
2900 force `FBD_CH_PATH2.fbdimm5.CL = cas_latency[2:0];
2901 force `FBD_CH_PATH4.fbdimm5.CL = cas_latency[2:0];
2902 force `FBD_CH_PATH6.fbdimm5.CL = cas_latency[2:0];
2903 force `FBD_CH_PATH0.fbdimm6.CL = cas_latency[2:0];
2904 force `FBD_CH_PATH2.fbdimm6.CL = cas_latency[2:0];
2905 force `FBD_CH_PATH4.fbdimm6.CL = cas_latency[2:0];
2906 force `FBD_CH_PATH6.fbdimm6.CL = cas_latency[2:0];
2907 force `FBD_CH_PATH0.fbdimm7.CL = cas_latency[2:0];
2908 force `FBD_CH_PATH2.fbdimm7.CL = cas_latency[2:0];
2909 force `FBD_CH_PATH4.fbdimm7.CL = cas_latency[2:0];
2910 force `FBD_CH_PATH6.fbdimm7.CL = cas_latency[2:0];
2911
2912 `ifndef SNG_CHANNEL
2913 force `FBD_CH_PATH1.fbdimm4.CL = cas_latency[2:0];
2914 force `FBD_CH_PATH3.fbdimm4.CL = cas_latency[2:0];
2915 force `FBD_CH_PATH5.fbdimm4.CL = cas_latency[2:0];
2916 force `FBD_CH_PATH7.fbdimm4.CL = cas_latency[2:0];
2917 force `FBD_CH_PATH1.fbdimm5.CL = cas_latency[2:0];
2918 force `FBD_CH_PATH3.fbdimm5.CL = cas_latency[2:0];
2919 force `FBD_CH_PATH5.fbdimm5.CL = cas_latency[2:0];
2920 force `FBD_CH_PATH7.fbdimm5.CL = cas_latency[2:0];
2921 force `FBD_CH_PATH1.fbdimm6.CL = cas_latency[2:0];
2922 force `FBD_CH_PATH3.fbdimm6.CL = cas_latency[2:0];
2923 force `FBD_CH_PATH5.fbdimm6.CL = cas_latency[2:0];
2924 force `FBD_CH_PATH7.fbdimm6.CL = cas_latency[2:0];
2925 force `FBD_CH_PATH1.fbdimm7.CL = cas_latency[2:0];
2926 force `FBD_CH_PATH3.fbdimm7.CL = cas_latency[2:0];
2927 force `FBD_CH_PATH5.fbdimm7.CL = cas_latency[2:0];
2928 force `FBD_CH_PATH7.fbdimm7.CL = cas_latency[2:0];
2929 `endif
2930 `endif // num_4
2931 `endif // num_2
2932 `endif // num_1
2933 `endif // axis
2934
2935 // Set AL in idt_fbdimm
2936 `ifndef AXIS
2937 force `FBD_CH_PATH0.fbdimm0.AL = additive_latency[2:0];
2938 force `FBD_CH_PATH2.fbdimm0.AL = additive_latency[2:0];
2939 force `FBD_CH_PATH4.fbdimm0.AL = additive_latency[2:0];
2940 force `FBD_CH_PATH6.fbdimm0.AL = additive_latency[2:0];
2941
2942 `ifndef SNG_CHANNEL
2943 force `FBD_CH_PATH1.fbdimm0.AL = additive_latency[2:0];
2944 force `FBD_CH_PATH3.fbdimm0.AL = additive_latency[2:0];
2945 force `FBD_CH_PATH5.fbdimm0.AL = additive_latency[2:0];
2946 force `FBD_CH_PATH7.fbdimm0.AL = additive_latency[2:0];
2947 `endif
2948 `ifndef FBDIMM_NUM_1
2949 force `FBD_CH_PATH0.fbdimm1.AL = additive_latency[2:0];
2950 force `FBD_CH_PATH2.fbdimm1.AL = additive_latency[2:0];
2951 force `FBD_CH_PATH4.fbdimm1.AL = additive_latency[2:0];
2952 force `FBD_CH_PATH6.fbdimm1.AL = additive_latency[2:0];
2953
2954 `ifndef SNG_CHANNEL
2955 force `FBD_CH_PATH1.fbdimm1.AL = additive_latency[2:0];
2956 force `FBD_CH_PATH3.fbdimm1.AL = additive_latency[2:0];
2957 force `FBD_CH_PATH5.fbdimm1.AL = additive_latency[2:0];
2958 force `FBD_CH_PATH7.fbdimm1.AL = additive_latency[2:0];
2959 `endif
2960
2961 `ifndef FBDIMM_NUM_2
2962 force `FBD_CH_PATH0.fbdimm2.AL = additive_latency[2:0];
2963 force `FBD_CH_PATH2.fbdimm2.AL = additive_latency[2:0];
2964 force `FBD_CH_PATH4.fbdimm2.AL = additive_latency[2:0];
2965 force `FBD_CH_PATH6.fbdimm2.AL = additive_latency[2:0];
2966 force `FBD_CH_PATH0.fbdimm3.AL = additive_latency[2:0];
2967 force `FBD_CH_PATH2.fbdimm3.AL = additive_latency[2:0];
2968 force `FBD_CH_PATH4.fbdimm3.AL = additive_latency[2:0];
2969 force `FBD_CH_PATH6.fbdimm3.AL = additive_latency[2:0];
2970
2971 `ifndef SNG_CHANNEL
2972 force `FBD_CH_PATH1.fbdimm2.AL = additive_latency[2:0];
2973 force `FBD_CH_PATH3.fbdimm2.AL = additive_latency[2:0];
2974 force `FBD_CH_PATH5.fbdimm2.AL = additive_latency[2:0];
2975 force `FBD_CH_PATH7.fbdimm2.AL = additive_latency[2:0];
2976 force `FBD_CH_PATH1.fbdimm3.AL = additive_latency[2:0];
2977 force `FBD_CH_PATH3.fbdimm3.AL = additive_latency[2:0];
2978 force `FBD_CH_PATH5.fbdimm3.AL = additive_latency[2:0];
2979 force `FBD_CH_PATH7.fbdimm3.AL = additive_latency[2:0];
2980 `endif
2981
2982 `ifndef FBDIMM_NUM_4
2983 force `FBD_CH_PATH0.fbdimm4.AL = additive_latency[2:0];
2984 force `FBD_CH_PATH2.fbdimm4.AL = additive_latency[2:0];
2985 force `FBD_CH_PATH4.fbdimm4.AL = additive_latency[2:0];
2986 force `FBD_CH_PATH6.fbdimm4.AL = additive_latency[2:0];
2987 force `FBD_CH_PATH0.fbdimm5.AL = additive_latency[2:0];
2988 force `FBD_CH_PATH2.fbdimm5.AL = additive_latency[2:0];
2989 force `FBD_CH_PATH4.fbdimm5.AL = additive_latency[2:0];
2990 force `FBD_CH_PATH6.fbdimm5.AL = additive_latency[2:0];
2991 force `FBD_CH_PATH0.fbdimm6.AL = additive_latency[2:0];
2992 force `FBD_CH_PATH2.fbdimm6.AL = additive_latency[2:0];
2993 force `FBD_CH_PATH4.fbdimm6.AL = additive_latency[2:0];
2994 force `FBD_CH_PATH6.fbdimm6.AL = additive_latency[2:0];
2995 force `FBD_CH_PATH0.fbdimm7.AL = additive_latency[2:0];
2996 force `FBD_CH_PATH2.fbdimm7.AL = additive_latency[2:0];
2997 force `FBD_CH_PATH4.fbdimm7.AL = additive_latency[2:0];
2998 force `FBD_CH_PATH6.fbdimm7.AL = additive_latency[2:0];
2999
3000 `ifndef SNG_CHANNEL
3001 force `FBD_CH_PATH1.fbdimm4.AL = additive_latency[2:0];
3002 force `FBD_CH_PATH3.fbdimm4.AL = additive_latency[2:0];
3003 force `FBD_CH_PATH5.fbdimm4.AL = additive_latency[2:0];
3004 force `FBD_CH_PATH7.fbdimm4.AL = additive_latency[2:0];
3005 force `FBD_CH_PATH1.fbdimm5.AL = additive_latency[2:0];
3006 force `FBD_CH_PATH3.fbdimm5.AL = additive_latency[2:0];
3007 force `FBD_CH_PATH5.fbdimm5.AL = additive_latency[2:0];
3008 force `FBD_CH_PATH7.fbdimm5.AL = additive_latency[2:0];
3009 force `FBD_CH_PATH1.fbdimm6.AL = additive_latency[2:0];
3010 force `FBD_CH_PATH3.fbdimm6.AL = additive_latency[2:0];
3011 force `FBD_CH_PATH5.fbdimm6.AL = additive_latency[2:0];
3012 force `FBD_CH_PATH7.fbdimm6.AL = additive_latency[2:0];
3013 force `FBD_CH_PATH1.fbdimm7.AL = additive_latency[2:0];
3014 force `FBD_CH_PATH3.fbdimm7.AL = additive_latency[2:0];
3015 force `FBD_CH_PATH5.fbdimm7.AL = additive_latency[2:0];
3016 force `FBD_CH_PATH7.fbdimm7.AL = additive_latency[2:0];
3017 `endif
3018 `endif // num_4
3019 `endif // num_2
3020 `endif // num_1
3021 `endif // axis
3022
3023
3024 // Set AL and CL in DRC reg inside idt_fbidmm
3025 `ifndef AXIS
3026 force `FBD_CH_PATH0.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3027 force `FBD_CH_PATH2.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3028 force `FBD_CH_PATH4.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3029 force `FBD_CH_PATH6.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3030
3031 `ifndef SNG_CHANNEL
3032 force `FBD_CH_PATH1.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3033 force `FBD_CH_PATH3.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3034 force `FBD_CH_PATH5.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3035 force `FBD_CH_PATH7.fbdimm0.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3036 `endif
3037 `ifndef FBDIMM_NUM_1
3038 force `FBD_CH_PATH0.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3039 force `FBD_CH_PATH2.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3040 force `FBD_CH_PATH4.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3041 force `FBD_CH_PATH6.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3042
3043 `ifndef SNG_CHANNEL
3044 force `FBD_CH_PATH1.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3045 force `FBD_CH_PATH3.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3046 force `FBD_CH_PATH5.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3047 force `FBD_CH_PATH7.fbdimm1.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3048 `endif
3049
3050 `ifndef FBDIMM_NUM_2
3051 force `FBD_CH_PATH0.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3052 force `FBD_CH_PATH2.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3053 force `FBD_CH_PATH4.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3054 force `FBD_CH_PATH6.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3055 force `FBD_CH_PATH0.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3056 force `FBD_CH_PATH2.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3057 force `FBD_CH_PATH4.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3058 force `FBD_CH_PATH6.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3059
3060 `ifndef SNG_CHANNEL
3061 force `FBD_CH_PATH1.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3062 force `FBD_CH_PATH3.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3063 force `FBD_CH_PATH5.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3064 force `FBD_CH_PATH7.fbdimm2.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3065 force `FBD_CH_PATH1.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3066 force `FBD_CH_PATH3.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3067 force `FBD_CH_PATH5.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3068 force `FBD_CH_PATH7.fbdimm3.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3069 `endif
3070
3071 `ifndef FBDIMM_NUM_4
3072 force `FBD_CH_PATH0.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3073 force `FBD_CH_PATH2.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3074 force `FBD_CH_PATH4.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3075 force `FBD_CH_PATH6.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3076 force `FBD_CH_PATH0.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3077 force `FBD_CH_PATH2.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3078 force `FBD_CH_PATH4.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3079 force `FBD_CH_PATH6.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3080 force `FBD_CH_PATH0.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3081 force `FBD_CH_PATH2.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3082 force `FBD_CH_PATH4.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3083 force `FBD_CH_PATH6.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3084 force `FBD_CH_PATH0.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3085 force `FBD_CH_PATH2.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3086 force `FBD_CH_PATH4.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3087 force `FBD_CH_PATH6.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3088
3089 `ifndef SNG_CHANNEL
3090 force `FBD_CH_PATH1.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3091 force `FBD_CH_PATH3.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3092 force `FBD_CH_PATH5.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3093 force `FBD_CH_PATH7.fbdimm4.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3094 force `FBD_CH_PATH1.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3095 force `FBD_CH_PATH3.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3096 force `FBD_CH_PATH5.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3097 force `FBD_CH_PATH7.fbdimm5.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3098 force `FBD_CH_PATH1.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3099 force `FBD_CH_PATH3.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3100 force `FBD_CH_PATH5.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3101 force `FBD_CH_PATH7.fbdimm6.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3102 force `FBD_CH_PATH1.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3103 force `FBD_CH_PATH3.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3104 force `FBD_CH_PATH5.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3105 force `FBD_CH_PATH7.fbdimm7.idt_amb0.registers.reg37C = {msb_drc,additive_latency,cas_latency};
3106 `endif
3107 `endif // num_4
3108 `endif // num_2
3109 `endif // num_1
3110 `endif // axis
3111
3112 // Set sync_train_interval in DRC reg inside idt_fbidmm
3113 `ifndef AXIS
3114 force `FBD_CH_PATH0.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3115 force `FBD_CH_PATH2.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3116 force `FBD_CH_PATH4.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3117 force `FBD_CH_PATH6.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3118
3119 `ifndef SNG_CHANNEL
3120 force `FBD_CH_PATH1.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3121 force `FBD_CH_PATH3.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3122 force `FBD_CH_PATH5.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3123 force `FBD_CH_PATH7.fbdimm0.idt_amb0.registers.reg178 = sync_train_interval;
3124 `endif
3125 `ifndef FBDIMM_NUM_1
3126 force `FBD_CH_PATH0.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3127 force `FBD_CH_PATH2.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3128 force `FBD_CH_PATH4.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3129 force `FBD_CH_PATH6.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3130
3131 `ifndef SNG_CHANNEL
3132 force `FBD_CH_PATH1.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3133 force `FBD_CH_PATH3.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3134 force `FBD_CH_PATH5.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3135 force `FBD_CH_PATH7.fbdimm1.idt_amb0.registers.reg178 = sync_train_interval;
3136 `endif
3137
3138 `ifndef FBDIMM_NUM_2
3139 force `FBD_CH_PATH0.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3140 force `FBD_CH_PATH2.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3141 force `FBD_CH_PATH4.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3142 force `FBD_CH_PATH6.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3143 force `FBD_CH_PATH0.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3144 force `FBD_CH_PATH2.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3145 force `FBD_CH_PATH4.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3146 force `FBD_CH_PATH6.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3147
3148 `ifndef SNG_CHANNEL
3149 force `FBD_CH_PATH1.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3150 force `FBD_CH_PATH3.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3151 force `FBD_CH_PATH5.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3152 force `FBD_CH_PATH7.fbdimm2.idt_amb0.registers.reg178 = sync_train_interval;
3153 force `FBD_CH_PATH1.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3154 force `FBD_CH_PATH3.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3155 force `FBD_CH_PATH5.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3156 force `FBD_CH_PATH7.fbdimm3.idt_amb0.registers.reg178 = sync_train_interval;
3157 `endif
3158
3159 `ifndef FBDIMM_NUM_4
3160 force `FBD_CH_PATH0.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3161 force `FBD_CH_PATH2.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3162 force `FBD_CH_PATH4.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3163 force `FBD_CH_PATH6.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3164 force `FBD_CH_PATH0.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3165 force `FBD_CH_PATH2.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3166 force `FBD_CH_PATH4.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3167 force `FBD_CH_PATH6.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3168 force `FBD_CH_PATH0.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3169 force `FBD_CH_PATH2.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3170 force `FBD_CH_PATH4.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3171 force `FBD_CH_PATH6.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3172 force `FBD_CH_PATH0.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3173 force `FBD_CH_PATH2.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3174 force `FBD_CH_PATH4.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3175 force `FBD_CH_PATH6.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3176
3177 `ifndef SNG_CHANNEL
3178 force `FBD_CH_PATH1.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3179 force `FBD_CH_PATH3.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3180 force `FBD_CH_PATH5.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3181 force `FBD_CH_PATH7.fbdimm4.idt_amb0.registers.reg178 = sync_train_interval;
3182 force `FBD_CH_PATH1.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3183 force `FBD_CH_PATH3.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3184 force `FBD_CH_PATH5.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3185 force `FBD_CH_PATH7.fbdimm5.idt_amb0.registers.reg178 = sync_train_interval;
3186 force `FBD_CH_PATH1.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3187 force `FBD_CH_PATH3.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3188 force `FBD_CH_PATH5.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3189 force `FBD_CH_PATH7.fbdimm6.idt_amb0.registers.reg178 = sync_train_interval;
3190 force `FBD_CH_PATH1.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3191 force `FBD_CH_PATH3.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3192 force `FBD_CH_PATH5.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3193 force `FBD_CH_PATH7.fbdimm7.idt_amb0.registers.reg178 = sync_train_interval;
3194 `endif
3195 `endif // num_4
3196 `endif // num_2
3197 `endif // num_1
3198 `endif // axis
3199
3200 // Set cmd2datanxt in CMD2DATANXT reg (1E8) inside idt_fbidmm
3201 // Set cmd2datacur in CMD2DATACUR reg (1E9) inside idt_fbidmm
3202 `ifndef AXIS
3203 force `FBD_CH_PATH0.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3204 force `FBD_CH_PATH2.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3205 force `FBD_CH_PATH4.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3206 force `FBD_CH_PATH6.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3207
3208 `ifndef SNG_CHANNEL
3209 force `FBD_CH_PATH1.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3210 force `FBD_CH_PATH3.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3211 force `FBD_CH_PATH5.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3212 force `FBD_CH_PATH7.fbdimm0.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3213 `endif
3214 `ifndef FBDIMM_NUM_1
3215 force `FBD_CH_PATH0.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3216 force `FBD_CH_PATH2.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3217 force `FBD_CH_PATH4.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3218 force `FBD_CH_PATH6.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3219
3220 `ifndef SNG_CHANNEL
3221 force `FBD_CH_PATH1.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3222 force `FBD_CH_PATH3.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3223 force `FBD_CH_PATH5.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3224 force `FBD_CH_PATH7.fbdimm1.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3225 `endif
3226
3227 `ifndef FBDIMM_NUM_2
3228 force `FBD_CH_PATH0.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3229 force `FBD_CH_PATH2.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3230 force `FBD_CH_PATH4.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3231 force `FBD_CH_PATH6.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3232 force `FBD_CH_PATH0.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3233 force `FBD_CH_PATH2.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3234 force `FBD_CH_PATH4.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3235 force `FBD_CH_PATH6.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3236
3237 `ifndef SNG_CHANNEL
3238 force `FBD_CH_PATH1.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3239 force `FBD_CH_PATH3.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3240 force `FBD_CH_PATH5.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3241 force `FBD_CH_PATH7.fbdimm2.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3242 force `FBD_CH_PATH1.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3243 force `FBD_CH_PATH3.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3244 force `FBD_CH_PATH5.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3245 force `FBD_CH_PATH7.fbdimm3.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3246 `endif
3247
3248 `ifndef FBDIMM_NUM_4
3249 force `FBD_CH_PATH0.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3250 force `FBD_CH_PATH2.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3251 force `FBD_CH_PATH4.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3252 force `FBD_CH_PATH6.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3253 force `FBD_CH_PATH0.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3254 force `FBD_CH_PATH2.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3255 force `FBD_CH_PATH4.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3256 force `FBD_CH_PATH6.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3257 force `FBD_CH_PATH0.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3258 force `FBD_CH_PATH2.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3259 force `FBD_CH_PATH4.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3260 force `FBD_CH_PATH6.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3261 force `FBD_CH_PATH0.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3262 force `FBD_CH_PATH2.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3263 force `FBD_CH_PATH4.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3264 force `FBD_CH_PATH6.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3265
3266 `ifndef SNG_CHANNEL
3267 force `FBD_CH_PATH1.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3268 force `FBD_CH_PATH3.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3269 force `FBD_CH_PATH5.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3270 force `FBD_CH_PATH7.fbdimm4.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3271 force `FBD_CH_PATH1.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3272 force `FBD_CH_PATH3.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3273 force `FBD_CH_PATH5.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3274 force `FBD_CH_PATH7.fbdimm5.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3275 force `FBD_CH_PATH1.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3276 force `FBD_CH_PATH3.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3277 force `FBD_CH_PATH5.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3278 force `FBD_CH_PATH7.fbdimm6.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3279 force `FBD_CH_PATH1.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3280 force `FBD_CH_PATH3.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3281 force `FBD_CH_PATH5.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3282 force `FBD_CH_PATH7.fbdimm7.idt_amb0.registers.reg1E8 = {cmd2datacur,cmd2datanxt};
3283 `endif
3284 `endif // num_4
3285 `endif // num_2
3286 `endif // num_1
3287 `endif // axis
3288
3289 end // else: !if($test$plusargs("NO_IDT_CSR_SLAM"))
3290`endif // IDT_FBDIMM
3291
3292end // initial
3293
3294// ----- DTM Mode (Programming Channel Read Latency as no Polling State in DTM) ---
3295//The forces are applied after the first SSI sync has happened to model the behaviour
3296//during real world programming
3297always @ (negedge `CPU.SSI_SYNC_L)
3298if (dtm_enabled)
3299begin
3300repeat (200) @ (negedge `CPU.SSI_SCK);
3301`ifndef AXIS
3302 if (! $value$plusargs("set_channel_read_latency=%h", chnl_read_latency))
3303 chnl_read_latency = 8'h14 ;
3304
3305 if ($test$plusargs("NO_MCU_CSR_SLAM")) begin
3306 `PR_INFO ("mcu_mem_config", `INFO, "MCU CSRs not slammed");
3307 end
3308 else begin
3309`ifdef MCU_GATE
3310 chnl_read_latency_gate = chnl_read_latency ^ 8'hff;
3311
3312 // --- Set Channel Read latency in DTM mode ---
3313
3314 force {`MCU0.fbdic__inv_fbdic_rt_lat0_7_,`MCU0.fbdic__inv_fbdic_rt_lat0_6_,`MCU0.fbdic__inv_fbdic_rt_lat0_5_,`MCU0.fbdic__inv_fbdic_rt_lat0_4_,`MCU0.fbdic__inv_fbdic_rt_lat0_3_,`MCU0.fbdic__inv_fbdic_rt_lat0_2_,`MCU0.fbdic__inv_fbdic_rt_lat0_1_,`MCU0.fbdic__inv_fbdic_rt_lat0_0_} = chnl_read_latency_gate;
3315 force {`MCU1.fbdic__inv_fbdic_rt_lat0_7_,`MCU1.fbdic__inv_fbdic_rt_lat0_6_,`MCU1.fbdic__inv_fbdic_rt_lat0_5_,`MCU1.fbdic__inv_fbdic_rt_lat0_4_,`MCU1.fbdic__inv_fbdic_rt_lat0_3_,`MCU1.fbdic__inv_fbdic_rt_lat0_2_,`MCU1.fbdic__inv_fbdic_rt_lat0_1_,`MCU1.fbdic__inv_fbdic_rt_lat0_0_} = chnl_read_latency_gate;
3316 force {`MCU2.fbdic__inv_fbdic_rt_lat0_7_,`MCU2.fbdic__inv_fbdic_rt_lat0_6_,`MCU2.fbdic__inv_fbdic_rt_lat0_5_,`MCU2.fbdic__inv_fbdic_rt_lat0_4_,`MCU2.fbdic__inv_fbdic_rt_lat0_3_,`MCU2.fbdic__inv_fbdic_rt_lat0_2_,`MCU2.fbdic__inv_fbdic_rt_lat0_1_,`MCU2.fbdic__inv_fbdic_rt_lat0_0_} = chnl_read_latency_gate;
3317 force {`MCU3.fbdic__inv_fbdic_rt_lat0_7_,`MCU3.fbdic__inv_fbdic_rt_lat0_6_,`MCU3.fbdic__inv_fbdic_rt_lat0_5_,`MCU3.fbdic__inv_fbdic_rt_lat0_4_,`MCU3.fbdic__inv_fbdic_rt_lat0_3_,`MCU3.fbdic__inv_fbdic_rt_lat0_2_,`MCU3.fbdic__inv_fbdic_rt_lat0_1_,`MCU3.fbdic__inv_fbdic_rt_lat0_0_} = chnl_read_latency_gate;
3318
3319 force {`MCU0.fbdic__inv_fbdic_rt_lat1_7_,`MCU0.fbdic__inv_fbdic_rt_lat1_6_,`MCU0.fbdic__inv_fbdic_rt_lat1_5_,`MCU0.fbdic__inv_fbdic_rt_lat1_4_,`MCU0.fbdic__inv_fbdic_rt_lat1_3_,`MCU0.fbdic__inv_fbdic_rt_lat1_2_,`MCU0.fbdic__inv_fbdic_rt_lat1_1_,`MCU0.fbdic__inv_fbdic_rt_lat1_0_} = chnl_read_latency_gate;
3320 force {`MCU1.fbdic__inv_fbdic_rt_lat1_7_,`MCU1.fbdic__inv_fbdic_rt_lat1_6_,`MCU1.fbdic__inv_fbdic_rt_lat1_5_,`MCU1.fbdic__inv_fbdic_rt_lat1_4_,`MCU1.fbdic__inv_fbdic_rt_lat1_3_,`MCU1.fbdic__inv_fbdic_rt_lat1_2_,`MCU1.fbdic__inv_fbdic_rt_lat1_1_,`MCU1.fbdic__inv_fbdic_rt_lat1_0_} = chnl_read_latency_gate;
3321 force {`MCU2.fbdic__inv_fbdic_rt_lat1_7_,`MCU2.fbdic__inv_fbdic_rt_lat1_6_,`MCU2.fbdic__inv_fbdic_rt_lat1_5_,`MCU2.fbdic__inv_fbdic_rt_lat1_4_,`MCU2.fbdic__inv_fbdic_rt_lat1_3_,`MCU2.fbdic__inv_fbdic_rt_lat1_2_,`MCU2.fbdic__inv_fbdic_rt_lat1_1_,`MCU2.fbdic__inv_fbdic_rt_lat1_0_} = chnl_read_latency_gate;
3322 force {`MCU3.fbdic__inv_fbdic_rt_lat1_7_,`MCU3.fbdic__inv_fbdic_rt_lat1_6_,`MCU3.fbdic__inv_fbdic_rt_lat1_5_,`MCU3.fbdic__inv_fbdic_rt_lat1_4_,`MCU3.fbdic__inv_fbdic_rt_lat1_3_,`MCU3.fbdic__inv_fbdic_rt_lat1_2_,`MCU3.fbdic__inv_fbdic_rt_lat1_1_,`MCU3.fbdic__inv_fbdic_rt_lat1_0_} = chnl_read_latency_gate;
3323
3324 // --- Set Half Baud Rate in TI FSR ---
3325
3326 force {`MCU0.fbdic__n15679,`MCU0.fbdic__n15680} = 2'b1;
3327 force {`MCU1.fbdic__n15679,`MCU1.fbdic__n15680} = 2'b1;
3328 force {`MCU2.fbdic__n15679,`MCU2.fbdic__n15680} = 2'b1;
3329 force {`MCU3.fbdic__n15679,`MCU3.fbdic__n15680} = 2'b1;
3330`else
3331 // --- Set Channel Read latency in DTM mode ---
3332
3333 force `MCU0.fbdic.fbdic_rt_lat0 = chnl_read_latency;
3334 force `MCU1.fbdic.fbdic_rt_lat0 = chnl_read_latency;
3335 force `MCU2.fbdic.fbdic_rt_lat0 = chnl_read_latency;
3336 force `MCU3.fbdic.fbdic_rt_lat0 = chnl_read_latency;
3337
3338 force `MCU0.fbdic.fbdic_rt_lat1 = chnl_read_latency;
3339 force `MCU1.fbdic.fbdic_rt_lat1 = chnl_read_latency;
3340 force `MCU2.fbdic.fbdic_rt_lat1 = chnl_read_latency;
3341 force `MCU3.fbdic.fbdic_rt_lat1 = chnl_read_latency;
3342
3343 // --- Set Half Baud Rate in TI FSR ---
3344
3345 force `MCU0.fbdic.fbdic_sds_config[29:28] = 2'b1;
3346 force `MCU1.fbdic.fbdic_sds_config[29:28] = 2'b1;
3347 force `MCU2.fbdic.fbdic_sds_config[29:28] = 2'b1;
3348 force `MCU3.fbdic.fbdic_sds_config[29:28] = 2'b1;
3349`endif // mcu_gate
3350 end
3351`endif // ifndef AXIS
3352end
3353
3354
3355// ----- RANDOM_PARAM: Randomizing skew -----
3356
3357reg [9:0] random_deskew;
3358reg [1:0] random_deskew_ch; // randomize the skew on channels
3359
3360initial
3361begin
3362`ifdef PALLADIUM
3363`else
3364#1;
3365`endif
3366
3367 `ifndef NB_BITLANE_DESKEW
3368 if($test$plusargs("RANDOM_PARAM"))
3369 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "WARNING: Using RANDOM_PARAM +arg without building the model for NB_BITLANE_DESKEW ");
3370 `endif
3371
3372 `ifdef NB_BITLANE_DESKEW
3373
3374 if($test$plusargs("RANDOM_PARAM"))
3375 begin
3376
3377 // --- Added code for randomizing one of the channels for the skew
3378 random_deskew_ch = ({$random(`PARGS.seed)} % 4);
3379 if (random_deskew_ch==0)
3380 random_deskew_ch = 1;
3381 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_DESKEW_CH ***: random_deskew_ch = 0x%x", random_deskew_ch);
3382
3383 random_deskew = ({$random(`PARGS.seed)} % 60);
3384 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn0_deskew = 0x%x", random_deskew);
3385
3386 if (random_deskew_ch[0]) begin
3387 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn0_deskew = random_deskew;
3388 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn0_deskew = random_deskew;
3389 end
3390 if (random_deskew_ch[1]) begin
3391 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn0_deskew = random_deskew;
3392 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn0_deskew = random_deskew;
3393 end
3394 if (random_deskew_ch[0]) begin
3395 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn0_deskew = random_deskew;
3396 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn0_deskew = random_deskew;
3397 end
3398 if (random_deskew_ch[1]) begin
3399 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn0_deskew = random_deskew;
3400 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn0_deskew = random_deskew;
3401 end
3402 if (random_deskew_ch[0]) begin
3403 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn0_deskew = random_deskew;
3404 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn0_deskew = random_deskew;
3405 end
3406 if (random_deskew_ch[1]) begin
3407 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn0_deskew = random_deskew;
3408 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn0_deskew = random_deskew;
3409 end
3410 if (random_deskew_ch[0]) begin
3411 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn0_deskew = random_deskew;
3412 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn0_deskew = random_deskew;
3413 end
3414 if (random_deskew_ch[1]) begin
3415 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn0_deskew = random_deskew;
3416 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn0_deskew = random_deskew;
3417 end
3418
3419 random_deskew = ({$random(`PARGS.seed)} % 60);
3420 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn1_deskew = 0x%x", random_deskew);
3421
3422 if (random_deskew_ch[0]) begin
3423 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn1_deskew = random_deskew;
3424 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn1_deskew = random_deskew;
3425 end
3426 if (random_deskew_ch[1]) begin
3427 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn1_deskew = random_deskew;
3428 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn1_deskew = random_deskew;
3429 end
3430 if (random_deskew_ch[0]) begin
3431 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn1_deskew = random_deskew;
3432 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn1_deskew = random_deskew;
3433 end
3434 if (random_deskew_ch[1]) begin
3435 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn1_deskew = random_deskew;
3436 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn1_deskew = random_deskew;
3437 end
3438 if (random_deskew_ch[0]) begin
3439 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn1_deskew = random_deskew;
3440 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn1_deskew = random_deskew;
3441 end
3442 if (random_deskew_ch[1]) begin
3443 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn1_deskew = random_deskew;
3444 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn1_deskew = random_deskew;
3445 end
3446 if (random_deskew_ch[0]) begin
3447 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn1_deskew = random_deskew;
3448 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn1_deskew = random_deskew;
3449 end
3450 if (random_deskew_ch[1]) begin
3451 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn1_deskew = random_deskew;
3452 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn1_deskew = random_deskew;
3453 end
3454
3455 random_deskew = ({$random(`PARGS.seed)} % 60);
3456 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn2_deskew = 0x%x", random_deskew);
3457
3458 if (random_deskew_ch[0]) begin
3459 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn2_deskew = random_deskew;
3460 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn2_deskew = random_deskew;
3461 end
3462 if (random_deskew_ch[1]) begin
3463 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn2_deskew = random_deskew;
3464 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn2_deskew = random_deskew;
3465 end
3466 if (random_deskew_ch[0]) begin
3467 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn2_deskew = random_deskew;
3468 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn2_deskew = random_deskew;
3469 end
3470 if (random_deskew_ch[1]) begin
3471 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn2_deskew = random_deskew;
3472 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn2_deskew = random_deskew;
3473 end
3474 if (random_deskew_ch[0]) begin
3475 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn2_deskew = random_deskew;
3476 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn2_deskew = random_deskew;
3477 end
3478 if (random_deskew_ch[1]) begin
3479 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn2_deskew = random_deskew;
3480 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn2_deskew = random_deskew;
3481 end
3482 if (random_deskew_ch[0]) begin
3483 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn2_deskew = random_deskew;
3484 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn2_deskew = random_deskew;
3485 end
3486 if (random_deskew_ch[1]) begin
3487 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn2_deskew = random_deskew;
3488 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn2_deskew = random_deskew;
3489 end
3490
3491 random_deskew = ({$random(`PARGS.seed)} % 60);
3492 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn3_deskew = 0x%x", random_deskew);
3493
3494 if (random_deskew_ch[0]) begin
3495 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn3_deskew = random_deskew;
3496 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn3_deskew = random_deskew;
3497 end
3498 if (random_deskew_ch[1]) begin
3499 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn3_deskew = random_deskew;
3500 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn3_deskew = random_deskew;
3501 end
3502 if (random_deskew_ch[0]) begin
3503 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn3_deskew = random_deskew;
3504 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn3_deskew = random_deskew;
3505 end
3506 if (random_deskew_ch[1]) begin
3507 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn3_deskew = random_deskew;
3508 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn3_deskew = random_deskew;
3509 end
3510 if (random_deskew_ch[0]) begin
3511 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn3_deskew = random_deskew;
3512 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn3_deskew = random_deskew;
3513 end
3514 if (random_deskew_ch[1]) begin
3515 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn3_deskew = random_deskew;
3516 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn3_deskew = random_deskew;
3517 end
3518 if (random_deskew_ch[0]) begin
3519 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn3_deskew = random_deskew;
3520 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn3_deskew = random_deskew;
3521 end
3522 if (random_deskew_ch[1]) begin
3523 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn3_deskew = random_deskew;
3524 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn3_deskew = random_deskew;
3525 end
3526
3527 random_deskew = ({$random(`PARGS.seed)} % 60);
3528 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn4_deskew = 0x%x", random_deskew);
3529
3530 if (random_deskew_ch[0]) begin
3531 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn4_deskew = random_deskew;
3532 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn4_deskew = random_deskew;
3533 end
3534 if (random_deskew_ch[1]) begin
3535 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn4_deskew = random_deskew;
3536 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn4_deskew = random_deskew;
3537 end
3538 if (random_deskew_ch[0]) begin
3539 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn4_deskew = random_deskew;
3540 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn4_deskew = random_deskew;
3541 end
3542 if (random_deskew_ch[1]) begin
3543 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn4_deskew = random_deskew;
3544 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn4_deskew = random_deskew;
3545 end
3546 if (random_deskew_ch[0]) begin
3547 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn4_deskew = random_deskew;
3548 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn4_deskew = random_deskew;
3549 end
3550 if (random_deskew_ch[1]) begin
3551 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn4_deskew = random_deskew;
3552 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn4_deskew = random_deskew;
3553 end
3554 if (random_deskew_ch[0]) begin
3555 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn4_deskew = random_deskew;
3556 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn4_deskew = random_deskew;
3557 end
3558 if (random_deskew_ch[1]) begin
3559 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn4_deskew = random_deskew;
3560 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn4_deskew = random_deskew;
3561 end
3562
3563 random_deskew = ({$random(`PARGS.seed)} % 60);
3564 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn5_deskew = 0x%x", random_deskew);
3565
3566 if (random_deskew_ch[0]) begin
3567 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn5_deskew = random_deskew;
3568 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn5_deskew = random_deskew;
3569 end
3570 if (random_deskew_ch[1]) begin
3571 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn5_deskew = random_deskew;
3572 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn5_deskew = random_deskew;
3573 end
3574 if (random_deskew_ch[0]) begin
3575 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn5_deskew = random_deskew;
3576 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn5_deskew = random_deskew;
3577 end
3578 if (random_deskew_ch[1]) begin
3579 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn5_deskew = random_deskew;
3580 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn5_deskew = random_deskew;
3581 end
3582 if (random_deskew_ch[0]) begin
3583 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn5_deskew = random_deskew;
3584 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn5_deskew = random_deskew;
3585 end
3586 if (random_deskew_ch[1]) begin
3587 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn5_deskew = random_deskew;
3588 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn5_deskew = random_deskew;
3589 end
3590 if (random_deskew_ch[0]) begin
3591 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn5_deskew = random_deskew;
3592 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn5_deskew = random_deskew;
3593 end
3594 if (random_deskew_ch[1]) begin
3595 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn5_deskew = random_deskew;
3596 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn5_deskew = random_deskew;
3597 end
3598
3599 random_deskew = ({$random(`PARGS.seed)} % 60);
3600 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn6_deskew = 0x%x", random_deskew);
3601
3602 if (random_deskew_ch[0]) begin
3603 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn6_deskew = random_deskew;
3604 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn6_deskew = random_deskew;
3605 end
3606 if (random_deskew_ch[1]) begin
3607 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn6_deskew = random_deskew;
3608 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn6_deskew = random_deskew;
3609 end
3610 if (random_deskew_ch[0]) begin
3611 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn6_deskew = random_deskew;
3612 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn6_deskew = random_deskew;
3613 end
3614 if (random_deskew_ch[1]) begin
3615 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn6_deskew = random_deskew;
3616 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn6_deskew = random_deskew;
3617 end
3618 if (random_deskew_ch[0]) begin
3619 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn6_deskew = random_deskew;
3620 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn6_deskew = random_deskew;
3621 end
3622 if (random_deskew_ch[1]) begin
3623 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn6_deskew = random_deskew;
3624 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn6_deskew = random_deskew;
3625 end
3626 if (random_deskew_ch[0]) begin
3627 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn6_deskew = random_deskew;
3628 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn6_deskew = random_deskew;
3629 end
3630 if (random_deskew_ch[1]) begin
3631 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn6_deskew = random_deskew;
3632 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn6_deskew = random_deskew;
3633 end
3634
3635 random_deskew = ({$random(`PARGS.seed)} % 60);
3636 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn7_deskew = 0x%x", random_deskew);
3637
3638 if (random_deskew_ch[0]) begin
3639 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn7_deskew = random_deskew;
3640 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn7_deskew = random_deskew;
3641 end
3642 if (random_deskew_ch[1]) begin
3643 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn7_deskew = random_deskew;
3644 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn7_deskew = random_deskew;
3645 end
3646 if (random_deskew_ch[0]) begin
3647 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn7_deskew = random_deskew;
3648 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn7_deskew = random_deskew;
3649 end
3650 if (random_deskew_ch[1]) begin
3651 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn7_deskew = random_deskew;
3652 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn7_deskew = random_deskew;
3653 end
3654 if (random_deskew_ch[0]) begin
3655 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn7_deskew = random_deskew;
3656 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn7_deskew = random_deskew;
3657 end
3658 if (random_deskew_ch[1]) begin
3659 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn7_deskew = random_deskew;
3660 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn7_deskew = random_deskew;
3661 end
3662 if (random_deskew_ch[0]) begin
3663 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn7_deskew = random_deskew;
3664 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn7_deskew = random_deskew;
3665 end
3666 if (random_deskew_ch[1]) begin
3667 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn7_deskew = random_deskew;
3668 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn7_deskew = random_deskew;
3669 end
3670
3671 random_deskew = ({$random(`PARGS.seed)} % 60);
3672 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn8_deskew = 0x%x", random_deskew);
3673
3674 if (random_deskew_ch[0]) begin
3675 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn8_deskew = random_deskew;
3676 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn8_deskew = random_deskew;
3677 end
3678 if (random_deskew_ch[1]) begin
3679 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn8_deskew = random_deskew;
3680 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn8_deskew = random_deskew;
3681 end
3682 if (random_deskew_ch[0]) begin
3683 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn8_deskew = random_deskew;
3684 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn8_deskew = random_deskew;
3685 end
3686 if (random_deskew_ch[1]) begin
3687 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn8_deskew = random_deskew;
3688 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn8_deskew = random_deskew;
3689 end
3690 if (random_deskew_ch[0]) begin
3691 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn8_deskew = random_deskew;
3692 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn8_deskew = random_deskew;
3693 end
3694 if (random_deskew_ch[1]) begin
3695 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn8_deskew = random_deskew;
3696 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn8_deskew = random_deskew;
3697 end
3698 if (random_deskew_ch[0]) begin
3699 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn8_deskew = random_deskew;
3700 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn8_deskew = random_deskew;
3701 end
3702 if (random_deskew_ch[1]) begin
3703 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn8_deskew = random_deskew;
3704 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn8_deskew = random_deskew;
3705 end
3706
3707 random_deskew = ({$random(`PARGS.seed)} % 60);
3708 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn9_deskew = 0x%x", random_deskew);
3709
3710 if (random_deskew_ch[0]) begin
3711 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn9_deskew = random_deskew;
3712 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn9_deskew = random_deskew;
3713 end
3714 if (random_deskew_ch[1]) begin
3715 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn9_deskew = random_deskew;
3716 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn9_deskew = random_deskew;
3717 end
3718 if (random_deskew_ch[0]) begin
3719 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn9_deskew = random_deskew;
3720 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn9_deskew = random_deskew;
3721 end
3722 if (random_deskew_ch[1]) begin
3723 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn9_deskew = random_deskew;
3724 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn9_deskew = random_deskew;
3725 end
3726 if (random_deskew_ch[0]) begin
3727 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn9_deskew = random_deskew;
3728 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn9_deskew = random_deskew;
3729 end
3730 if (random_deskew_ch[1]) begin
3731 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn9_deskew = random_deskew;
3732 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn9_deskew = random_deskew;
3733 end
3734 if (random_deskew_ch[0]) begin
3735 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn9_deskew = random_deskew;
3736 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn9_deskew = random_deskew;
3737 end
3738 if (random_deskew_ch[1]) begin
3739 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn9_deskew = random_deskew;
3740 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn9_deskew = random_deskew;
3741 end
3742
3743 random_deskew = ({$random(`PARGS.seed)} % 60);
3744 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn10_deskew = 0x%x", random_deskew);
3745
3746 if (random_deskew_ch[0]) begin
3747 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn10_deskew = random_deskew;
3748 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn10_deskew = random_deskew;
3749 end
3750 if (random_deskew_ch[1]) begin
3751 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn10_deskew = random_deskew;
3752 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn10_deskew = random_deskew;
3753 end
3754 if (random_deskew_ch[0]) begin
3755 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn10_deskew = random_deskew;
3756 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn10_deskew = random_deskew;
3757 end
3758 if (random_deskew_ch[1]) begin
3759 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn10_deskew = random_deskew;
3760 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn10_deskew = random_deskew;
3761 end
3762 if (random_deskew_ch[0]) begin
3763 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn10_deskew = random_deskew;
3764 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn10_deskew = random_deskew;
3765 end
3766 if (random_deskew_ch[1]) begin
3767 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn10_deskew = random_deskew;
3768 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn10_deskew = random_deskew;
3769 end
3770 if (random_deskew_ch[0]) begin
3771 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn10_deskew = random_deskew;
3772 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn10_deskew = random_deskew;
3773 end
3774 if (random_deskew_ch[1]) begin
3775 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn10_deskew = random_deskew;
3776 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn10_deskew = random_deskew;
3777 end
3778
3779 random_deskew = ({$random(`PARGS.seed)} % 60);
3780 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn11_deskew = 0x%x", random_deskew);
3781
3782 if (random_deskew_ch[0]) begin
3783 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn11_deskew = random_deskew;
3784 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn11_deskew = random_deskew;
3785 end
3786 if (random_deskew_ch[1]) begin
3787 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn11_deskew = random_deskew;
3788 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn11_deskew = random_deskew;
3789 end
3790 if (random_deskew_ch[0]) begin
3791 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn11_deskew = random_deskew;
3792 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn11_deskew = random_deskew;
3793 end
3794 if (random_deskew_ch[1]) begin
3795 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn11_deskew = random_deskew;
3796 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn11_deskew = random_deskew;
3797 end
3798 if (random_deskew_ch[0]) begin
3799 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn11_deskew = random_deskew;
3800 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn11_deskew = random_deskew;
3801 end
3802 if (random_deskew_ch[1]) begin
3803 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn11_deskew = random_deskew;
3804 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn11_deskew = random_deskew;
3805 end
3806 if (random_deskew_ch[0]) begin
3807 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn11_deskew = random_deskew;
3808 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn11_deskew = random_deskew;
3809 end
3810 if (random_deskew_ch[1]) begin
3811 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn11_deskew = random_deskew;
3812 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn11_deskew = random_deskew;
3813 end
3814
3815 random_deskew = ({$random(`PARGS.seed)} % 60);
3816 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn12_deskew = 0x%x", random_deskew);
3817
3818 if (random_deskew_ch[0]) begin
3819 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn12_deskew = random_deskew;
3820 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn12_deskew = random_deskew;
3821 end
3822 if (random_deskew_ch[1]) begin
3823 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn12_deskew = random_deskew;
3824 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn12_deskew = random_deskew;
3825 end
3826 if (random_deskew_ch[0]) begin
3827 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn12_deskew = random_deskew;
3828 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn12_deskew = random_deskew;
3829 end
3830 if (random_deskew_ch[1]) begin
3831 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn12_deskew = random_deskew;
3832 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn12_deskew = random_deskew;
3833 end
3834 if (random_deskew_ch[0]) begin
3835 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn12_deskew = random_deskew;
3836 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn12_deskew = random_deskew;
3837 end
3838 if (random_deskew_ch[1]) begin
3839 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn12_deskew = random_deskew;
3840 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn12_deskew = random_deskew;
3841 end
3842 if (random_deskew_ch[0]) begin
3843 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn12_deskew = random_deskew;
3844 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn12_deskew = random_deskew;
3845 end
3846 if (random_deskew_ch[1]) begin
3847 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn12_deskew = random_deskew;
3848 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn12_deskew = random_deskew;
3849 end
3850
3851 random_deskew = ({$random(`PARGS.seed)} % 60);
3852 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "*** RANDOM_PARAM ***: pn13_deskew = 0x%x", random_deskew);
3853
3854 if (random_deskew_ch[0]) begin
3855 tb_top.nb_bitlane_deskew.nb_bitdskw0a_n.pn13_deskew = random_deskew;
3856 tb_top.nb_bitlane_deskew.nb_bitdskw0a_p.pn13_deskew = random_deskew;
3857 end
3858 if (random_deskew_ch[1]) begin
3859 tb_top.nb_bitlane_deskew.nb_bitdskw0b_n.pn13_deskew = random_deskew;
3860 tb_top.nb_bitlane_deskew.nb_bitdskw0b_p.pn13_deskew = random_deskew;
3861 end
3862 if (random_deskew_ch[0]) begin
3863 tb_top.nb_bitlane_deskew.nb_bitdskw1a_n.pn13_deskew = random_deskew;
3864 tb_top.nb_bitlane_deskew.nb_bitdskw1a_p.pn13_deskew = random_deskew;
3865 end
3866 if (random_deskew_ch[1]) begin
3867 tb_top.nb_bitlane_deskew.nb_bitdskw1b_n.pn13_deskew = random_deskew;
3868 tb_top.nb_bitlane_deskew.nb_bitdskw1b_p.pn13_deskew = random_deskew;
3869 end
3870 if (random_deskew_ch[0]) begin
3871 tb_top.nb_bitlane_deskew.nb_bitdskw2a_n.pn13_deskew = random_deskew;
3872 tb_top.nb_bitlane_deskew.nb_bitdskw2a_p.pn13_deskew = random_deskew;
3873 end
3874 if (random_deskew_ch[1]) begin
3875 tb_top.nb_bitlane_deskew.nb_bitdskw2b_n.pn13_deskew = random_deskew;
3876 tb_top.nb_bitlane_deskew.nb_bitdskw2b_p.pn13_deskew = random_deskew;
3877 end
3878 if (random_deskew_ch[0]) begin
3879 tb_top.nb_bitlane_deskew.nb_bitdskw3a_n.pn13_deskew = random_deskew;
3880 tb_top.nb_bitlane_deskew.nb_bitdskw3a_p.pn13_deskew = random_deskew;
3881 end
3882 if (random_deskew_ch[1]) begin
3883 tb_top.nb_bitlane_deskew.nb_bitdskw3b_n.pn13_deskew = random_deskew;
3884 tb_top.nb_bitlane_deskew.nb_bitdskw3b_p.pn13_deskew = random_deskew;
3885 end
3886
3887 end
3888 `endif
3889end
3890
3891`ifndef AXIS
3892// ----- Random scrub start addr -----
3893reg [39:0] scrub_addr;
3894reg [1:0] dimm_adjust;
3895reg [4:0] rank_adjust;
3896reg channel_adjust;
3897reg side_adjust;
3898reg [1:0] size_adjust;
3899
3900reg [2:0] dimm_num;
3901
3902
3903initial
3904begin
3905
3906 if ($test$plusargs("2_FBDIMMS")) begin
3907 dimm_adjust = 2'h2;
3908 dimm_num = $random(`PARGS.seed) & 1;
3909 end
3910 else if($test$plusargs("4_FBDIMMS")) begin
3911 dimm_adjust = 2'h1;
3912 dimm_num = $random(`PARGS.seed) % 4;
3913 end
3914 else if($test$plusargs("8_FBDIMMS")) begin
3915 dimm_adjust = 2'h0;
3916 dimm_num = $random(`PARGS.seed) % 8;
3917 end
3918 else begin
3919 dimm_adjust = 2'h3; // default 1_FBDIMM
3920 dimm_num = 0;
3921 end
3922
3923 if($test$plusargs("SNG_CHANNEL")) channel_adjust = 1'h1;
3924 else channel_adjust = 1'h0; // default DUAL_CHANNEL
3925
3926 if($test$plusargs("STACK_DIMM")) side_adjust = 1'h0;
3927 else side_adjust = 1'h1; // default RANK_DIMM
3928
3929 if ($test$plusargs("DIMM_SIZE_256")) size_adjust = 2'h3;
3930 else if($test$plusargs("DIMM_SIZE_512")) size_adjust = 2'h2;
3931 else if($test$plusargs("DIMM_SIZE_1G")) size_adjust = 2'h1;
3932 else size_adjust = 2'h0; // default DIMM_SIZE_2G
3933
3934
3935 if($test$plusargs("RANK_LOW")) rank_adjust = 5'h18 - size_adjust - channel_adjust;
3936 else rank_adjust = 0;
3937
3938 scrub_addr = (40'hffffffffff >> (1 + dimm_adjust + channel_adjust + side_adjust + size_adjust + rank_adjust));
3939 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "***** SCRUB INITIAL ADDR ***** : %0x", scrub_addr);
3940 scrub_addr = scrub_addr >> dimm_num;
3941 `PR_ALWAYS("mcu_mem_config", `ALWAYS, "***** SCRUB INITIAL ADDR ***** : %0x, %0x", scrub_addr, dimm_num);
3942end
3943
3944`ifdef MCU_GATE
3945always @(posedge `MCU0.drif__drif_data_scrub_enabled)
3946`else
3947always @(posedge `MCU0.drif.drif_data_scrub_enabled)
3948`endif // mcu_gate
3949begin
3950
3951 if($test$plusargs("RANDOM_ENV")) begin
3952`ifdef MCU_GATE
3953 force `MCU0.drif_scrub_addr[31:0] = scrub_addr[39:9];
3954 force `MCU1.drif_scrub_addr[31:0] = scrub_addr[39:9];
3955 force `MCU2.drif_scrub_addr[31:0] = scrub_addr[39:9];
3956 force `MCU3.drif_scrub_addr[31:0] = scrub_addr[39:9];
3957 @(posedge `MCU0.drl2clk);
3958 release `MCU0.drif_scrub_addr[31:0];
3959 release `MCU1.drif_scrub_addr[31:0];
3960 release `MCU2.drif_scrub_addr[31:0];
3961 release `MCU3.drif_scrub_addr[31:0];
3962`else
3963 force `MCU0.drif.drif_scrub_addr[31:0] = scrub_addr[39:9];
3964 force `MCU1.drif.drif_scrub_addr[31:0] = scrub_addr[39:9];
3965 force `MCU2.drif.drif_scrub_addr[31:0] = scrub_addr[39:9];
3966 force `MCU3.drif.drif_scrub_addr[31:0] = scrub_addr[39:9];
3967 @(posedge `MCU0.drl2clk);
3968 release `MCU0.drif.drif_scrub_addr[31:0];
3969 release `MCU1.drif.drif_scrub_addr[31:0];
3970 release `MCU2.drif.drif_scrub_addr[31:0];
3971 release `MCU3.drif.drif_scrub_addr[31:0];
3972`endif // mcu_gate
3973 end
3974end
3975`endif // `ifndef AXIS
3976
3977//---------------------------------------------
3978// Added random NB stuck at faults
3979//---------------------------------------------
3980
3981integer auto_fail_stuck_delay_rand;
3982integer auto_fail_stuck_delay;
3983integer local_tg_seed;
3984
3985`ifdef IDT_FBDIMM
3986initial
3987begin // {
3988 if ($test$plusargs("NB_LANE_FAILOVER_0"))
3989 begin // {
3990 if($value$plusargs("tg_seed=%d",local_tg_seed))
3991 begin
3992 $display("tg_seed value is=%d\n",local_tg_seed);
3993 auto_fail_stuck_delay_rand = $random(local_tg_seed);
3994 auto_fail_stuck_delay = (auto_fail_stuck_delay_rand % 500 + auto_fail_stuck_delay_rand % 1800 ) ;
3995 while(~((auto_fail_stuck_delay<2400) && (auto_fail_stuck_delay>999)) )
3996 begin
3997 auto_fail_stuck_delay_rand = $random(local_tg_seed);
3998 auto_fail_stuck_delay = (auto_fail_stuck_delay_rand % 500 + auto_fail_stuck_delay_rand % 1800 ) ;
3999 end
4000 end
4001 $display("NB lane 0 failover after delaytime=%d\n",auto_fail_stuck_delay);
4002 repeat (auto_fail_stuck_delay) @ (posedge `DRIF_PATH0.drl2clk);
4003
4004 if ($test$plusargs("NB_LANE_CH0_0")) begin // {
4005 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[0] = 1'b1;
4006 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[0] = 1'b1;
4007 $display("NB auto lane failover in channel 0, lane 0\n"); end // }
4008 if ($test$plusargs("NB_LANE_CH0_1")) begin // {
4009 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[1] = 1'b1;
4010 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[1] = 1'b1;
4011 $display("NB auto lane failover in channel 0, lane 1\n"); end // }
4012 if ($test$plusargs("NB_LANE_CH0_2")) begin // {
4013 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[2] = 1'b1;
4014 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[2] = 1'b1;
4015 $display("NB auto lane failover in channel 0, lane 2\n"); end // }
4016 if ($test$plusargs("NB_LANE_CH0_3")) begin // {
4017 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[3] = 1'b1;
4018 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[3] = 1'b1;
4019 $display("NB auto lane failover in channel 0, lane 3\n"); end // }
4020 if ($test$plusargs("NB_LANE_CH0_4")) begin // {
4021 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[4] = 1'b1;
4022 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[4] = 1'b1;
4023 $display("NB auto lane failover in channel 0, lane 4\n"); end // }
4024 if ($test$plusargs("NB_LANE_CH0_5")) begin // {
4025 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[5] = 1'b1;
4026 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[5] = 1'b1;
4027 $display("NB auto lane failover in channel 0, lane 5\n"); end // }
4028 if ($test$plusargs("NB_LANE_CH0_6")) begin // {
4029 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[6] = 1'b1;
4030 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[6] = 1'b1;
4031 $display("NB auto lane failover in channel 0, lane 6\n"); end // }
4032 if ($test$plusargs("NB_LANE_CH0_7")) begin // {
4033 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[7] = 1'b1;
4034 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[7] = 1'b1;
4035 $display("NB auto lane failover in channel 0, lane 7\n"); end // }
4036 if ($test$plusargs("NB_LANE_CH0_8")) begin // {
4037 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[8] = 1'b1;
4038 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[8] = 1'b1;
4039 $display("NB auto lane failover in channel 0, lane 8\n"); end // }
4040 if ($test$plusargs("NB_LANE_CH0_9")) begin // {
4041 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[9] = 1'b1;
4042 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[9] = 1'b1;
4043 $display("NB auto lane failover in channel 0, lane 9\n"); end // }
4044 if ($test$plusargs("NB_LANE_CH0_a")) begin // {
4045 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[10] = 1'b1;
4046 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[10] = 1'b1;
4047 $display("NB auto lane failover in channel 0, lane 10\n"); end // }
4048 if ($test$plusargs("NB_LANE_CH0_b")) begin // {
4049 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[11] = 1'b1;
4050 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[11] = 1'b1;
4051 $display("NB auto lane failover in channel 0, lane 11\n"); end // }
4052 if ($test$plusargs("NB_LANE_CH0_c")) begin // {
4053 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[12] = 1'b1;
4054 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[12] = 1'b1;
4055 $display("NB auto lane failover in channel 0, lane 12\n"); end // }
4056 if ($test$plusargs("NB_LANE_CH0_d")) begin // {
4057 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXP[13] = 1'b1;
4058 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem0.fbdimm0.NBTXN[13] = 1'b1;
4059 $display("NB auto lane failover in channel 0, lane 13\n"); end // }
4060 end // }
4061end // }
4062
4063`ifndef SNG_CHANNEL
4064initial
4065begin // {
4066
4067 if ($test$plusargs("NB_LANE_FAILOVER_1"))
4068 begin // {
4069 if($value$plusargs("tg_seed=%d",local_tg_seed))
4070 begin
4071 $display("tg_seed value is=%d\n",local_tg_seed);
4072 auto_fail_stuck_delay_rand = $random(local_tg_seed);
4073 auto_fail_stuck_delay = (auto_fail_stuck_delay_rand % 500 + auto_fail_stuck_delay_rand % 1800 ) ;
4074 while(~((auto_fail_stuck_delay<2400) && (auto_fail_stuck_delay>999)) )
4075 begin
4076 auto_fail_stuck_delay_rand = $random(local_tg_seed);
4077 auto_fail_stuck_delay = (auto_fail_stuck_delay_rand % 500 + auto_fail_stuck_delay_rand % 1800 ) ;
4078 end
4079 end
4080 $display("NB lane 1 failover after delaytime=%d\n",auto_fail_stuck_delay);
4081 repeat (auto_fail_stuck_delay) @ (posedge `DRIF_PATH0.drl2clk);
4082
4083 if ($test$plusargs("NB_LANE_CH1_0")) begin // {
4084 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[0] = 1'b1;
4085 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[0] = 1'b1;
4086 $display("NB auto lane failover in channel 1, lane 0\n"); end // }
4087 if ($test$plusargs("NB_LANE_CH1_1")) begin // {
4088 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[1] = 1'b1;
4089 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[1] = 1'b1;
4090 $display("NB auto lane failover in channel 1, lane 1\n"); end // }
4091 if ($test$plusargs("NB_LANE_CH1_2")) begin // {
4092 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[2] = 1'b1;
4093 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[2] = 1'b1;
4094 $display("NB auto lane failover in channel 1, lane 2\n"); end // }
4095 if ($test$plusargs("NB_LANE_CH1_3")) begin // {
4096 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[3] = 1'b1;
4097 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[3] = 1'b1;
4098 $display("NB auto lane failover in channel 1, lane 3\n"); end // }
4099 if ($test$plusargs("NB_LANE_CH1_4")) begin // {
4100 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[4] = 1'b1;
4101 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[4] = 1'b1;
4102 $display("NB auto lane failover in channel 1, lane 4\n"); end // }
4103 if ($test$plusargs("NB_LANE_CH1_5")) begin // {
4104 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[5] = 1'b1;
4105 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[5] = 1'b1;
4106 $display("NB auto lane failover in channel 1, lane 5\n"); end // }
4107 if ($test$plusargs("NB_LANE_CH1_6")) begin // {
4108 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[6] = 1'b1;
4109 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[6] = 1'b1;
4110 $display("NB auto lane failover in channel 1, lane 6\n"); end // }
4111 if ($test$plusargs("NB_LANE_CH1_7")) begin // {
4112 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[7] = 1'b1;
4113 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[7] = 1'b1;
4114 $display("NB auto lane failover in channel 1, lane 7\n"); end // }
4115 if ($test$plusargs("NB_LANE_CH1_8")) begin // {
4116 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[8] = 1'b1;
4117 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[8] = 1'b1;
4118 $display("NB auto lane failover in channel 1, lane 8\n"); end // }
4119 if ($test$plusargs("NB_LANE_CH1_9")) begin // {
4120 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[9] = 1'b1;
4121 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[9] = 1'b1;
4122 $display("NB auto lane failover in channel 1, lane 9\n"); end // }
4123 if ($test$plusargs("NB_LANE_CH1_a")) begin // {
4124 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[10] = 1'b1;
4125 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[10] = 1'b1;
4126 $display("NB auto lane failover in channel 1, lane 10\n"); end // }
4127 if ($test$plusargs("NB_LANE_CH1_b")) begin // {
4128 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[11] = 1'b1;
4129 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[11] = 1'b1;
4130 $display("NB auto lane failover in channel 1, lane 11\n"); end // }
4131 if ($test$plusargs("NB_LANE_CH1_c")) begin // {
4132 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[12] = 1'b1;
4133 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[12] = 1'b1;
4134 $display("NB auto lane failover in channel 1, lane 12\n"); end // }
4135 if ($test$plusargs("NB_LANE_CH1_d")) begin // {
4136 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXP[13] = 1'b1;
4137 force `TOP_MOD.mcusat_fbdimm.fbdimm_mem1.fbdimm0.NBTXN[13] = 1'b1;
4138 $display("NB auto lane failover in channel 1, lane 13\n"); end // }
4139 end // }
4140end // }
4141`endif // SNG_CHANNEL
4142`endif // IDT_FBDIMM
4143
4144
4145///////////////////////////////////////////////////////////////////////////////
4146//
4147// Detect stupid build arg vs run-arg errors, and fail with a meaningful msg.
4148//
4149///////////////////////////////////////////////////////////////////////////////
4150initial
4151begin // {
4152
4153`ifdef FBDIMM_NUM_1
4154 if ($test$plusargs("2_FBDIMMS"))
4155 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 2_FBDIMMS plusarg was specified.");
4156 else if ($test$plusargs("3_FBDIMMS"))
4157 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 3_FBDIMMS plusarg was specified.");
4158 else if ($test$plusargs("4_FBDIMMS"))
4159 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 4_FBDIMMS plusarg was specified.");
4160 else if ($test$plusargs("5_FBDIMMS"))
4161 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 5_FBDIMMS plusarg was specified.");
4162 else if ($test$plusargs("6_FBDIMMS"))
4163 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4164 else if ($test$plusargs("7_FBDIMMS"))
4165 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4166 else if ($test$plusargs("8_FBDIMMS"))
4167 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4168`else
4169 `ifdef FBDIMM_NUM_2
4170 if ($test$plusargs("3_FBDIMMS"))
4171 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 3_FBDIMMS plusarg was specified.");
4172 else if ($test$plusargs("4_FBDIMMS"))
4173 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 4_FBDIMMS plusarg was specified.");
4174 else if ($test$plusargs("5_FBDIMMS"))
4175 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 5_FBDIMMS plusarg was specified.");
4176 else if ($test$plusargs("6_FBDIMMS"))
4177 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4178 else if ($test$plusargs("7_FBDIMMS"))
4179 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4180 else if ($test$plusargs("8_FBDIMMS"))
4181 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 2 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4182 `else
4183 `ifdef FBDIMM_NUM_3
4184 if ($test$plusargs("4_FBDIMMS"))
4185 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 3 FBDIMM, but the 4_FBDIMMS plusarg was specified.");
4186 else if ($test$plusargs("5_FBDIMMS"))
4187 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 3 FBDIMM, but the 5_FBDIMMS plusarg was specified.");
4188 else if ($test$plusargs("6_FBDIMMS"))
4189 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 3 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4190 else if ($test$plusargs("7_FBDIMMS"))
4191 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 3 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4192 else if ($test$plusargs("8_FBDIMMS"))
4193 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 3 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4194 `else
4195 `ifdef FBDIMM_NUM_4
4196 if ($test$plusargs("5_FBDIMMS"))
4197 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 4 FBDIMM, but the 5_FBDIMMS plusarg was specified.");
4198 else if ($test$plusargs("6_FBDIMMS"))
4199 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 4 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4200 else if ($test$plusargs("7_FBDIMMS"))
4201 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 4 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4202 else if ($test$plusargs("8_FBDIMMS"))
4203 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 4 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4204 `else
4205 `ifdef FBDIMM_NUM_5
4206 if ($test$plusargs("6_FBDIMMS"))
4207 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 5 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4208 else if ($test$plusargs("7_FBDIMMS"))
4209 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 5 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4210 else if ($test$plusargs("8_FBDIMMS"))
4211 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 5 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4212 `else
4213 `ifdef FBDIMM_NUM_6
4214 if ($test$plusargs("7_FBDIMMS"))
4215 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 6 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4216 else if ($test$plusargs("8_FBDIMMS"))
4217 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 6 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4218 `else
4219 `ifdef FBDIMM_NUM_7
4220 if ($test$plusargs("8_FBDIMMS"))
4221 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 7 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4222 `else
4223 `ifdef FBDIMM_NUM_8
4224 // there are no build vs run-arg problems with FBDIMM_NUM_8
4225 `else
4226 // if a specific # of fbdimms is not specified, it defaults to 1
4227 if ($test$plusargs("2_FBDIMMS"))
4228 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 2_FBDIMMS plusarg was specified.");
4229 else if ($test$plusargs("3_FBDIMMS"))
4230 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 3_FBDIMMS plusarg was specified.");
4231 else if ($test$plusargs("4_FBDIMMS"))
4232 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 4_FBDIMMS plusarg was specified.");
4233 else if ($test$plusargs("5_FBDIMMS"))
4234 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 5_FBDIMMS plusarg was specified.");
4235 else if ($test$plusargs("6_FBDIMMS"))
4236 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 6_FBDIMMS plusarg was specified.");
4237 else if ($test$plusargs("7_FBDIMMS"))
4238 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 7_FBDIMMS plusarg was specified.");
4239 else if ($test$plusargs("8_FBDIMMS"))
4240 `PR_ERROR("mcu_mem_config", `ERROR, "The model was only built with 1 FBDIMM, but the 8_FBDIMMS plusarg was specified.");
4241 `endif
4242 `endif
4243 `endif
4244 `endif
4245 `endif
4246 `endif
4247 `endif
4248`endif
4249
4250end // }
4251
4252endmodule
Full OpenSPARC design & verification tarball including full HDL.