Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / niu / mac_sat / vera / include / nrx_xmac_drv_ports.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: nrx_xmac_drv_ports.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// ========== Copyright Header End ============================================
#define FIM_CK_IN_TIMING        PSAMPLE
#define FIM_CK_OUT_TIMING	PHOLD #0  
#define FIM_CK_CLK_TIMING	CLOCK

#ifdef IPP_CK_DIRECT_PORT

interface fim0_if {
  output       rx_req     FIM_CK_OUT_TIMING;
  input        rx_ack     FIM_CK_IN_TIMING;
  input [63:0] rx_data    FIM_CK_IN_TIMING;
  input [22:0] rx_stat    FIM_CK_IN_TIMING;
  input        rx_tag     FIM_CK_IN_TIMING;
  input        rx_ctrl    FIM_CK_IN_TIMING;
  input        clk        FIM_CK_CLK_TIMING;
   }



#else

interface fim0_if {
    output          rx_req          FIM_CK_OUT_TIMING verilog_node  "mac_core.nrx0.nrx_mac_req";
    input           rx_ack          FIM_CK_IN_TIMING verilog_node "mac_core.nrx0.mac_nrx_ack";
    input [63:0]    rx_data         FIM_CK_IN_TIMING verilog_node  "mac_core.nrx0.mac_nrx_data";
    input [22:0]    rx_stat         FIM_CK_IN_TIMING verilog_node  "mac_core.nrx0.mac_nrx_stat";
    input           rx_tag          FIM_CK_IN_TIMING verilog_node  "mac_core.nrx0.mac_nrx_tag";
    input           rx_ctrl         FIM_CK_IN_TIMING verilog_node  "mac_core.nrx0.mac_nrx_ctrl";
    input           clk             FIM_CK_CLK_TIMING verilog_node "mac_core.nrx0.core_clk";
  }


#endif

port fim_def {
	rx_req;
	rx_ack;
	rx_data;
        rx_stat; 
	rx_tag;
	rx_ctrl;
	clk;
   }

bind fim_def fim0 {
	rx_req		fim0_if.rx_req;
	rx_ack		fim0_if.rx_ack;
	rx_data		fim0_if.rx_data;
    	rx_stat     	fim0_if.rx_stat;
	rx_tag		fim0_if.rx_tag;
	rx_ctrl		fim0_if.rx_ctrl;
	clk		fim0_if.clk;
   }