projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / env / niu / mac_sat / vera / include / ntx_mac_drv_ports.vri
CommitLineData
86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ntx_mac_drv_ports.vri
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35#define OMF_CK_IN_TIMING PSAMPLE #-1
36#define OMF_CK_OUT_TIMING PHOLD #1
37#define OMF_CK_CLK_TIMING CLOCK
38#include "neptune_defines.vri"
39
40#ifdef NEPTUNE
41
42interface fom0_if {
43 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data0";
44 output [3:0] tx_stat OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_stat0";
45 output tx_abort OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_abort0";
46 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag0";
47 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req0";
48 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack0";
49 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_4ports.clk";
50}
51
52interface fom1_if {
53 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data1";
54 output [3:0] tx_stat OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_stat1";
55 output tx_abort OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_abort1";
56 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag1";
57 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req1";
58 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack1";
59 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_4ports.clk";
60}
61
62interface fom2_if {
63 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data2";
64 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag2";
65 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req2";
66 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack2";
67 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_4ports.clk";
68}
69interface fom3_if {
70 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data3";
71 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag3";
72 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req3";
73 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack3";
74 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_4ports.clk";
75}
76
77#else
78
79interface fom0_if {
80 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data0";
81 output [3:0] tx_stat OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_stat0";
82 output tx_abort OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_abort0";
83 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag0";
84 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req0";
85 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack0";
86 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
87}
88
89interface fom1_if {
90 output [63:0] tx_data OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_data1";
91 output [3:0] tx_stat OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_stat1";
92 output tx_abort OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_abort1";
93 output tx_tag OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_tag1";
94 input tx_mac_req OMF_CK_IN_TIMING verilog_node MAC_DUV_PATH.mac_txc_req1";
95 output tx_ack OMF_CK_OUT_TIMING verilog_node MAC_DUV_PATH.txc_mac_ack1";
96 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
97}
98
99#endif
100
101#ifdef NEPTUNE
102interface id_if {
103 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_4ports.clk";
104}
105
106#else
107
108interface id_if {
109 input clk OMF_CK_CLK_TIMING verilog_node MAC_DUV_PATH.mac_core.mac_2ports.niu_clk";
110}
111
112#endif
113
114port xfom_def {
115 tx_data;
116 tx_stat;
117 tx_abort;
118 tx_tag;
119 tx_mac_req;
120 tx_ack;
121 clk;
122 }
123
124port fom_def {
125 tx_data;
126 tx_tag;
127 tx_mac_req;
128 tx_ack;
129 clk;
130 }
131
132
133port id_def {
134 // init_done;
135 clk;
136 }
137
138bind id_def init {
139
140 // init_done id_if.init_done;
141 clk id_if.clk;
142
143}
144
145#ifdef NEPTUNE
146bind xfom_def fom0 {
147 tx_data fom0_if.tx_data;
148 tx_stat fom0_if.tx_stat;
149 tx_abort fom0_if.tx_abort;
150 tx_tag fom0_if.tx_tag;
151 tx_mac_req fom0_if.tx_mac_req;
152 tx_ack fom0_if.tx_ack;
153 clk fom0_if.clk;
154 }
155
156bind xfom_def fom1 {
157 tx_data fom1_if.tx_data;
158 tx_stat fom1_if.tx_stat;
159 tx_abort fom1_if.tx_abort;
160 tx_tag fom1_if.tx_tag;
161 tx_mac_req fom1_if.tx_mac_req;
162 tx_ack fom1_if.tx_ack;
163 clk fom1_if.clk;
164 }
165
166bind fom_def fom2 {
167 tx_data fom2_if.tx_data;
168 tx_tag fom2_if.tx_tag;
169 tx_mac_req fom2_if.tx_mac_req;
170 tx_ack fom2_if.tx_ack;
171 clk fom2_if.clk;
172 }
173
174
175bind fom_def fom3 {
176 tx_data fom3_if.tx_data;
177 tx_tag fom3_if.tx_tag;
178 tx_mac_req fom3_if.tx_mac_req;
179 tx_ack fom3_if.tx_ack;
180 clk fom3_if.clk;
181 }
182
183#else
184
185bind xfom_def fom0 {
186 tx_data fom0_if.tx_data;
187 tx_stat fom0_if.tx_stat;
188 tx_abort fom0_if.tx_abort;
189 tx_tag fom0_if.tx_tag;
190 tx_mac_req fom0_if.tx_mac_req;
191 tx_ack fom0_if.tx_ack;
192 clk fom0_if.clk;
193 }
194
195bind xfom_def fom1 {
196 tx_data fom1_if.tx_data;
197 tx_stat fom1_if.tx_stat;
198 tx_abort fom1_if.tx_abort;
199 tx_tag fom1_if.tx_tag;
200 tx_mac_req fom1_if.tx_mac_req;
201 tx_ack fom1_if.tx_ack;
202 clk fom1_if.clk;
203 }
204
205#endif
Full OpenSPARC design & verification tarball including full HDL.