Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / verif / env / niu / rxc_sat / vera / include / rxc_dmc_chkr_ports.vri

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: rxc_dmc_chkr_ports.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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#include "rxc_defines.vri"
#define	RXC_CK_IN_TIMING PSAMPLE #-1
#define RXC_CK_CLK_TIMING  CLOCK

interface dmc_rxc_port0_if{
  input	[127:0]	rxc_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data0";
  input		rxc_dmc_sop		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data0[128]";
  input		rxc_dmc_eop		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data0[129]";
  input		rxc_dmc_ful_pkt		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_ful_pkt0";
  input		rxc_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_dat_emp0";
  input		rxc_dmc_err		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_dat_err0";
  input		rxc_dmc_ack		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_dat_ack0";
  input	 	rxc_clk		        RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.clk";
  input		dmc_rxc_req		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.dmc_rxc_dat_req0";
}
interface dmc_rxc_port1_if{
  input	[127:0]	rxc_dmc_pkt_data	RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data1";
  input		rxc_dmc_sop		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data1[128]";
  input		rxc_dmc_eop		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_data1[129]";
  input		rxc_dmc_pkt_rdy		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_ful_pkt1";
  input		rxc_dmc_empty		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_ful_emp1";
  input		rxc_dmc_ack		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.rxc_dmc_dat_ack1";
  input	 	rxc_clk		        RXC_CK_CLK_TIMING verilog_node RXC_DUV_PATH.clk";
  input		dmc_rxc_req		RXC_CK_IN_TIMING verilog_node RXC_DUV_PATH.dmc_rxc_dat_req1";
}

port dmc_rxc_port{
  rxc_dmc_pkt_data;
  rxc_dmc_sop;
  rxc_dmc_eop;
  rxc_dmc_pkt_rdy;
  rxc_dmc_empty;
  rxc_dmc_ack;
  dmc_rxc_req;
  rxc_clk;
}
bind dmc_rxc_port dmc_rxc_drv0{
	rxc_dmc_pkt_data	dmc_rxc_port0_if.rxc_dmc_pkt_data;
	rxc_dmc_sop		dmc_rxc_port0_if.rxc_dmc_sop;
	rxc_dmc_eop		dmc_rxc_port0_if.rxc_dmc_eop;
	rxc_dmc_pkt_rdy		dmc_rxc_port0_if.rxc_dmc_pkt_rdy;
	rxc_dmc_empty		dmc_rxc_port0_if.rxc_dmc_empty;
	rxc_dmc_ack		dmc_rxc_port0_if.rxc_dmc_ack;
	dmc_rxc_req		dmc_rxc_port0_if.dmc_rxc_req;
	rxc_clk		        dmc_rxc_port0_if.rxc_clk;
}
bind dmc_rxc_port dmc_rxc_drv1{
	rxc_dmc_pkt_data	dmc_rxc_port1_if.rxc_dmc_pkt_data;
	rxc_dmc_sop		dmc_rxc_port1_if.rxc_dmc_sop;
	rxc_dmc_eop		dmc_rxc_port1_if.rxc_dmc_eop;
	rxc_dmc_pkt_rdy		dmc_rxc_port1_if.rxc_dmc_pkt_rdy;
	rxc_dmc_empty		dmc_rxc_port1_if.rxc_dmc_empty;
	rxc_dmc_ack		dmc_rxc_port1_if.rxc_dmc_ack;
	dmc_rxc_req		dmc_rxc_port1_if.dmc_rxc_req;
	rxc_clk		        dmc_rxc_port0_if.rxc_clk;
}